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7e1543c2 PB |
1 | /* |
2 | * ARM AMBA PrimeCell PL031 RTC | |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery | |
5 | * | |
6 | * This file is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
6b620ca3 PB |
10 | * Contributions after 2012-01-13 are licensed under the terms of the |
11 | * GNU GPL, version 2 or (at your option) any later version. | |
7e1543c2 PB |
12 | */ |
13 | ||
8ef94f0b | 14 | #include "qemu/osdep.h" |
b0de99f3 | 15 | #include "hw/timer/pl031.h" |
83c9f4ca | 16 | #include "hw/sysbus.h" |
1de7afc9 | 17 | #include "qemu/timer.h" |
9c17d615 | 18 | #include "sysemu/sysemu.h" |
f348b6d1 | 19 | #include "qemu/cutils.h" |
03dd024f | 20 | #include "qemu/log.h" |
0b8fa32f | 21 | #include "qemu/module.h" |
dd849ef2 | 22 | #include "trace.h" |
7e1543c2 PB |
23 | |
24 | #define RTC_DR 0x00 /* Data read register */ | |
25 | #define RTC_MR 0x04 /* Match register */ | |
26 | #define RTC_LR 0x08 /* Data load register */ | |
27 | #define RTC_CR 0x0c /* Control register */ | |
28 | #define RTC_IMSC 0x10 /* Interrupt mask and set register */ | |
29 | #define RTC_RIS 0x14 /* Raw interrupt status register */ | |
30 | #define RTC_MIS 0x18 /* Masked interrupt status register */ | |
31 | #define RTC_ICR 0x1c /* Interrupt clear register */ | |
32 | ||
7e1543c2 PB |
33 | static const unsigned char pl031_id[] = { |
34 | 0x31, 0x10, 0x14, 0x00, /* Device ID */ | |
35 | 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ | |
36 | }; | |
37 | ||
b91f0dfd | 38 | static void pl031_update(PL031State *s) |
7e1543c2 | 39 | { |
dd849ef2 PM |
40 | uint32_t flags = s->is & s->im; |
41 | ||
42 | trace_pl031_irq_state(flags); | |
43 | qemu_set_irq(s->irq, flags); | |
7e1543c2 PB |
44 | } |
45 | ||
46 | static void pl031_interrupt(void * opaque) | |
47 | { | |
b91f0dfd | 48 | PL031State *s = (PL031State *)opaque; |
7e1543c2 | 49 | |
13a16f1d | 50 | s->is = 1; |
dd849ef2 | 51 | trace_pl031_alarm_raised(); |
7e1543c2 PB |
52 | pl031_update(s); |
53 | } | |
54 | ||
b91f0dfd | 55 | static uint32_t pl031_get_count(PL031State *s) |
7e1543c2 | 56 | { |
884f17c2 | 57 | int64_t now = qemu_clock_get_ns(rtc_clock); |
73bcb24d | 58 | return s->tick_offset + now / NANOSECONDS_PER_SECOND; |
7e1543c2 PB |
59 | } |
60 | ||
b91f0dfd | 61 | static void pl031_set_alarm(PL031State *s) |
7e1543c2 | 62 | { |
7e1543c2 PB |
63 | uint32_t ticks; |
64 | ||
7e1543c2 PB |
65 | /* The timer wraps around. This subtraction also wraps in the same way, |
66 | and gives correct results when alarm < now_ticks. */ | |
b0f26631 | 67 | ticks = s->mr - pl031_get_count(s); |
dd849ef2 | 68 | trace_pl031_set_alarm(ticks); |
7e1543c2 | 69 | if (ticks == 0) { |
bc72ad67 | 70 | timer_del(s->timer); |
7e1543c2 PB |
71 | pl031_interrupt(s); |
72 | } else { | |
884f17c2 | 73 | int64_t now = qemu_clock_get_ns(rtc_clock); |
73bcb24d | 74 | timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND); |
7e1543c2 PB |
75 | } |
76 | } | |
77 | ||
a8170e5e | 78 | static uint64_t pl031_read(void *opaque, hwaddr offset, |
9edbe481 | 79 | unsigned size) |
7e1543c2 | 80 | { |
b91f0dfd | 81 | PL031State *s = (PL031State *)opaque; |
dd849ef2 | 82 | uint64_t r; |
7e1543c2 PB |
83 | |
84 | switch (offset) { | |
85 | case RTC_DR: | |
dd849ef2 PM |
86 | r = pl031_get_count(s); |
87 | break; | |
7e1543c2 | 88 | case RTC_MR: |
dd849ef2 PM |
89 | r = s->mr; |
90 | break; | |
7e1543c2 | 91 | case RTC_IMSC: |
dd849ef2 PM |
92 | r = s->im; |
93 | break; | |
7e1543c2 | 94 | case RTC_RIS: |
dd849ef2 PM |
95 | r = s->is; |
96 | break; | |
7e1543c2 | 97 | case RTC_LR: |
dd849ef2 PM |
98 | r = s->lr; |
99 | break; | |
7e1543c2 PB |
100 | case RTC_CR: |
101 | /* RTC is permanently enabled. */ | |
dd849ef2 PM |
102 | r = 1; |
103 | break; | |
7e1543c2 | 104 | case RTC_MIS: |
dd849ef2 PM |
105 | r = s->is & s->im; |
106 | break; | |
107 | case 0xfe0 ... 0xfff: | |
108 | r = pl031_id[(offset - 0xfe0) >> 2]; | |
109 | break; | |
7e1543c2 | 110 | case RTC_ICR: |
a5089c05 PM |
111 | qemu_log_mask(LOG_GUEST_ERROR, |
112 | "pl031: read of write-only register at offset 0x%x\n", | |
113 | (int)offset); | |
dd849ef2 | 114 | r = 0; |
7e1543c2 PB |
115 | break; |
116 | default: | |
a5089c05 PM |
117 | qemu_log_mask(LOG_GUEST_ERROR, |
118 | "pl031_read: Bad offset 0x%x\n", (int)offset); | |
dd849ef2 | 119 | r = 0; |
7e1543c2 PB |
120 | break; |
121 | } | |
122 | ||
dd849ef2 PM |
123 | trace_pl031_read(offset, r); |
124 | return r; | |
7e1543c2 PB |
125 | } |
126 | ||
a8170e5e | 127 | static void pl031_write(void * opaque, hwaddr offset, |
9edbe481 | 128 | uint64_t value, unsigned size) |
7e1543c2 | 129 | { |
b91f0dfd | 130 | PL031State *s = (PL031State *)opaque; |
7e1543c2 | 131 | |
dd849ef2 | 132 | trace_pl031_write(offset, value); |
7e1543c2 PB |
133 | |
134 | switch (offset) { | |
135 | case RTC_LR: | |
136 | s->tick_offset += value - pl031_get_count(s); | |
137 | pl031_set_alarm(s); | |
138 | break; | |
139 | case RTC_MR: | |
140 | s->mr = value; | |
141 | pl031_set_alarm(s); | |
142 | break; | |
143 | case RTC_IMSC: | |
144 | s->im = value & 1; | |
7e1543c2 PB |
145 | pl031_update(s); |
146 | break; | |
147 | case RTC_ICR: | |
ff2712ba | 148 | /* The PL031 documentation (DDI0224B) states that the interrupt is |
7e1543c2 PB |
149 | cleared when bit 0 of the written value is set. However the |
150 | arm926e documentation (DDI0287B) states that the interrupt is | |
151 | cleared when any value is written. */ | |
7e1543c2 PB |
152 | s->is = 0; |
153 | pl031_update(s); | |
154 | break; | |
155 | case RTC_CR: | |
156 | /* Written value is ignored. */ | |
157 | break; | |
158 | ||
159 | case RTC_DR: | |
160 | case RTC_MIS: | |
161 | case RTC_RIS: | |
a5089c05 PM |
162 | qemu_log_mask(LOG_GUEST_ERROR, |
163 | "pl031: write to read-only register at offset 0x%x\n", | |
164 | (int)offset); | |
7e1543c2 PB |
165 | break; |
166 | ||
167 | default: | |
a5089c05 PM |
168 | qemu_log_mask(LOG_GUEST_ERROR, |
169 | "pl031_write: Bad offset 0x%x\n", (int)offset); | |
7e1543c2 PB |
170 | break; |
171 | } | |
172 | } | |
173 | ||
9edbe481 AK |
174 | static const MemoryRegionOps pl031_ops = { |
175 | .read = pl031_read, | |
176 | .write = pl031_write, | |
177 | .endianness = DEVICE_NATIVE_ENDIAN, | |
7e1543c2 PB |
178 | }; |
179 | ||
81dcc494 | 180 | static void pl031_init(Object *obj) |
7e1543c2 | 181 | { |
81dcc494 XZ |
182 | PL031State *s = PL031(obj); |
183 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
f6503059 | 184 | struct tm tm; |
7e1543c2 | 185 | |
81dcc494 | 186 | memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000); |
750ecd44 | 187 | sysbus_init_mmio(dev, &s->iomem); |
7e1543c2 | 188 | |
a63bdb31 | 189 | sysbus_init_irq(dev, &s->irq); |
f6503059 | 190 | qemu_get_timedate(&tm, 0); |
884f17c2 | 191 | s->tick_offset = mktimegm(&tm) - |
73bcb24d | 192 | qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; |
7e1543c2 | 193 | |
884f17c2 | 194 | s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s); |
7e1543c2 | 195 | } |
a63bdb31 | 196 | |
44b1ff31 | 197 | static int pl031_pre_save(void *opaque) |
b0f26631 | 198 | { |
b91f0dfd | 199 | PL031State *s = opaque; |
b0f26631 PB |
200 | |
201 | /* tick_offset is base_time - rtc_clock base time. Instead, we want to | |
bc72ad67 AB |
202 | * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */ |
203 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
73bcb24d | 204 | s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND; |
44b1ff31 DDAG |
205 | |
206 | return 0; | |
b0f26631 PB |
207 | } |
208 | ||
ac204b8f PB |
209 | static int pl031_post_load(void *opaque, int version_id) |
210 | { | |
b91f0dfd | 211 | PL031State *s = opaque; |
ac204b8f | 212 | |
bc72ad67 | 213 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
73bcb24d | 214 | s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND; |
ac204b8f PB |
215 | pl031_set_alarm(s); |
216 | return 0; | |
217 | } | |
218 | ||
219 | static const VMStateDescription vmstate_pl031 = { | |
220 | .name = "pl031", | |
221 | .version_id = 1, | |
222 | .minimum_version_id = 1, | |
b0f26631 | 223 | .pre_save = pl031_pre_save, |
ac204b8f PB |
224 | .post_load = pl031_post_load, |
225 | .fields = (VMStateField[]) { | |
b91f0dfd AF |
226 | VMSTATE_UINT32(tick_offset_vmstate, PL031State), |
227 | VMSTATE_UINT32(mr, PL031State), | |
228 | VMSTATE_UINT32(lr, PL031State), | |
229 | VMSTATE_UINT32(cr, PL031State), | |
230 | VMSTATE_UINT32(im, PL031State), | |
231 | VMSTATE_UINT32(is, PL031State), | |
ac204b8f PB |
232 | VMSTATE_END_OF_LIST() |
233 | } | |
234 | }; | |
235 | ||
999e12bb AL |
236 | static void pl031_class_init(ObjectClass *klass, void *data) |
237 | { | |
39bffca2 | 238 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 239 | |
39bffca2 | 240 | dc->vmsd = &vmstate_pl031; |
999e12bb AL |
241 | } |
242 | ||
8c43a6f0 | 243 | static const TypeInfo pl031_info = { |
d3b80049 | 244 | .name = TYPE_PL031, |
39bffca2 | 245 | .parent = TYPE_SYS_BUS_DEVICE, |
b91f0dfd | 246 | .instance_size = sizeof(PL031State), |
81dcc494 | 247 | .instance_init = pl031_init, |
39bffca2 | 248 | .class_init = pl031_class_init, |
0dc5595c PM |
249 | }; |
250 | ||
83f7d43a | 251 | static void pl031_register_types(void) |
a63bdb31 | 252 | { |
39bffca2 | 253 | type_register_static(&pl031_info); |
a63bdb31 PB |
254 | } |
255 | ||
83f7d43a | 256 | type_init(pl031_register_types) |