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7e1543c2 PB |
1 | /* |
2 | * ARM AMBA PrimeCell PL031 RTC | |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery | |
5 | * | |
6 | * This file is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
6b620ca3 PB |
10 | * Contributions after 2012-01-13 are licensed under the terms of the |
11 | * GNU GPL, version 2 or (at your option) any later version. | |
7e1543c2 PB |
12 | */ |
13 | ||
8ef94f0b | 14 | #include "qemu/osdep.h" |
b0de99f3 | 15 | #include "hw/timer/pl031.h" |
83c9f4ca | 16 | #include "hw/sysbus.h" |
1de7afc9 | 17 | #include "qemu/timer.h" |
9c17d615 | 18 | #include "sysemu/sysemu.h" |
f348b6d1 | 19 | #include "qemu/cutils.h" |
03dd024f | 20 | #include "qemu/log.h" |
7e1543c2 PB |
21 | |
22 | //#define DEBUG_PL031 | |
23 | ||
24 | #ifdef DEBUG_PL031 | |
001faf32 BS |
25 | #define DPRINTF(fmt, ...) \ |
26 | do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0) | |
7e1543c2 | 27 | #else |
001faf32 | 28 | #define DPRINTF(fmt, ...) do {} while(0) |
7e1543c2 PB |
29 | #endif |
30 | ||
31 | #define RTC_DR 0x00 /* Data read register */ | |
32 | #define RTC_MR 0x04 /* Match register */ | |
33 | #define RTC_LR 0x08 /* Data load register */ | |
34 | #define RTC_CR 0x0c /* Control register */ | |
35 | #define RTC_IMSC 0x10 /* Interrupt mask and set register */ | |
36 | #define RTC_RIS 0x14 /* Raw interrupt status register */ | |
37 | #define RTC_MIS 0x18 /* Masked interrupt status register */ | |
38 | #define RTC_ICR 0x1c /* Interrupt clear register */ | |
39 | ||
7e1543c2 PB |
40 | static const unsigned char pl031_id[] = { |
41 | 0x31, 0x10, 0x14, 0x00, /* Device ID */ | |
42 | 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ | |
43 | }; | |
44 | ||
b91f0dfd | 45 | static void pl031_update(PL031State *s) |
7e1543c2 PB |
46 | { |
47 | qemu_set_irq(s->irq, s->is & s->im); | |
48 | } | |
49 | ||
50 | static void pl031_interrupt(void * opaque) | |
51 | { | |
b91f0dfd | 52 | PL031State *s = (PL031State *)opaque; |
7e1543c2 | 53 | |
13a16f1d | 54 | s->is = 1; |
7e1543c2 PB |
55 | DPRINTF("Alarm raised\n"); |
56 | pl031_update(s); | |
57 | } | |
58 | ||
b91f0dfd | 59 | static uint32_t pl031_get_count(PL031State *s) |
7e1543c2 | 60 | { |
884f17c2 | 61 | int64_t now = qemu_clock_get_ns(rtc_clock); |
73bcb24d | 62 | return s->tick_offset + now / NANOSECONDS_PER_SECOND; |
7e1543c2 PB |
63 | } |
64 | ||
b91f0dfd | 65 | static void pl031_set_alarm(PL031State *s) |
7e1543c2 | 66 | { |
7e1543c2 PB |
67 | uint32_t ticks; |
68 | ||
7e1543c2 PB |
69 | /* The timer wraps around. This subtraction also wraps in the same way, |
70 | and gives correct results when alarm < now_ticks. */ | |
b0f26631 | 71 | ticks = s->mr - pl031_get_count(s); |
7e1543c2 PB |
72 | DPRINTF("Alarm set in %ud ticks\n", ticks); |
73 | if (ticks == 0) { | |
bc72ad67 | 74 | timer_del(s->timer); |
7e1543c2 PB |
75 | pl031_interrupt(s); |
76 | } else { | |
884f17c2 | 77 | int64_t now = qemu_clock_get_ns(rtc_clock); |
73bcb24d | 78 | timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND); |
7e1543c2 PB |
79 | } |
80 | } | |
81 | ||
a8170e5e | 82 | static uint64_t pl031_read(void *opaque, hwaddr offset, |
9edbe481 | 83 | unsigned size) |
7e1543c2 | 84 | { |
b91f0dfd | 85 | PL031State *s = (PL031State *)opaque; |
7e1543c2 | 86 | |
7e1543c2 PB |
87 | if (offset >= 0xfe0 && offset < 0x1000) |
88 | return pl031_id[(offset - 0xfe0) >> 2]; | |
89 | ||
90 | switch (offset) { | |
91 | case RTC_DR: | |
92 | return pl031_get_count(s); | |
93 | case RTC_MR: | |
94 | return s->mr; | |
95 | case RTC_IMSC: | |
96 | return s->im; | |
97 | case RTC_RIS: | |
98 | return s->is; | |
99 | case RTC_LR: | |
100 | return s->lr; | |
101 | case RTC_CR: | |
102 | /* RTC is permanently enabled. */ | |
103 | return 1; | |
104 | case RTC_MIS: | |
105 | return s->is & s->im; | |
106 | case RTC_ICR: | |
a5089c05 PM |
107 | qemu_log_mask(LOG_GUEST_ERROR, |
108 | "pl031: read of write-only register at offset 0x%x\n", | |
109 | (int)offset); | |
7e1543c2 PB |
110 | break; |
111 | default: | |
a5089c05 PM |
112 | qemu_log_mask(LOG_GUEST_ERROR, |
113 | "pl031_read: Bad offset 0x%x\n", (int)offset); | |
7e1543c2 PB |
114 | break; |
115 | } | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
a8170e5e | 120 | static void pl031_write(void * opaque, hwaddr offset, |
9edbe481 | 121 | uint64_t value, unsigned size) |
7e1543c2 | 122 | { |
b91f0dfd | 123 | PL031State *s = (PL031State *)opaque; |
7e1543c2 | 124 | |
7e1543c2 PB |
125 | |
126 | switch (offset) { | |
127 | case RTC_LR: | |
128 | s->tick_offset += value - pl031_get_count(s); | |
129 | pl031_set_alarm(s); | |
130 | break; | |
131 | case RTC_MR: | |
132 | s->mr = value; | |
133 | pl031_set_alarm(s); | |
134 | break; | |
135 | case RTC_IMSC: | |
136 | s->im = value & 1; | |
137 | DPRINTF("Interrupt mask %d\n", s->im); | |
138 | pl031_update(s); | |
139 | break; | |
140 | case RTC_ICR: | |
ff2712ba | 141 | /* The PL031 documentation (DDI0224B) states that the interrupt is |
7e1543c2 PB |
142 | cleared when bit 0 of the written value is set. However the |
143 | arm926e documentation (DDI0287B) states that the interrupt is | |
144 | cleared when any value is written. */ | |
145 | DPRINTF("Interrupt cleared"); | |
146 | s->is = 0; | |
147 | pl031_update(s); | |
148 | break; | |
149 | case RTC_CR: | |
150 | /* Written value is ignored. */ | |
151 | break; | |
152 | ||
153 | case RTC_DR: | |
154 | case RTC_MIS: | |
155 | case RTC_RIS: | |
a5089c05 PM |
156 | qemu_log_mask(LOG_GUEST_ERROR, |
157 | "pl031: write to read-only register at offset 0x%x\n", | |
158 | (int)offset); | |
7e1543c2 PB |
159 | break; |
160 | ||
161 | default: | |
a5089c05 PM |
162 | qemu_log_mask(LOG_GUEST_ERROR, |
163 | "pl031_write: Bad offset 0x%x\n", (int)offset); | |
7e1543c2 PB |
164 | break; |
165 | } | |
166 | } | |
167 | ||
9edbe481 AK |
168 | static const MemoryRegionOps pl031_ops = { |
169 | .read = pl031_read, | |
170 | .write = pl031_write, | |
171 | .endianness = DEVICE_NATIVE_ENDIAN, | |
7e1543c2 PB |
172 | }; |
173 | ||
81dcc494 | 174 | static void pl031_init(Object *obj) |
7e1543c2 | 175 | { |
81dcc494 XZ |
176 | PL031State *s = PL031(obj); |
177 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
f6503059 | 178 | struct tm tm; |
7e1543c2 | 179 | |
81dcc494 | 180 | memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000); |
750ecd44 | 181 | sysbus_init_mmio(dev, &s->iomem); |
7e1543c2 | 182 | |
a63bdb31 | 183 | sysbus_init_irq(dev, &s->irq); |
f6503059 | 184 | qemu_get_timedate(&tm, 0); |
884f17c2 | 185 | s->tick_offset = mktimegm(&tm) - |
73bcb24d | 186 | qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; |
7e1543c2 | 187 | |
884f17c2 | 188 | s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s); |
7e1543c2 | 189 | } |
a63bdb31 | 190 | |
44b1ff31 | 191 | static int pl031_pre_save(void *opaque) |
b0f26631 | 192 | { |
b91f0dfd | 193 | PL031State *s = opaque; |
b0f26631 PB |
194 | |
195 | /* tick_offset is base_time - rtc_clock base time. Instead, we want to | |
bc72ad67 AB |
196 | * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility. */ |
197 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
73bcb24d | 198 | s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND; |
44b1ff31 DDAG |
199 | |
200 | return 0; | |
b0f26631 PB |
201 | } |
202 | ||
ac204b8f PB |
203 | static int pl031_post_load(void *opaque, int version_id) |
204 | { | |
b91f0dfd | 205 | PL031State *s = opaque; |
ac204b8f | 206 | |
bc72ad67 | 207 | int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
73bcb24d | 208 | s->tick_offset = s->tick_offset_vmstate - delta / NANOSECONDS_PER_SECOND; |
ac204b8f PB |
209 | pl031_set_alarm(s); |
210 | return 0; | |
211 | } | |
212 | ||
213 | static const VMStateDescription vmstate_pl031 = { | |
214 | .name = "pl031", | |
215 | .version_id = 1, | |
216 | .minimum_version_id = 1, | |
b0f26631 | 217 | .pre_save = pl031_pre_save, |
ac204b8f PB |
218 | .post_load = pl031_post_load, |
219 | .fields = (VMStateField[]) { | |
b91f0dfd AF |
220 | VMSTATE_UINT32(tick_offset_vmstate, PL031State), |
221 | VMSTATE_UINT32(mr, PL031State), | |
222 | VMSTATE_UINT32(lr, PL031State), | |
223 | VMSTATE_UINT32(cr, PL031State), | |
224 | VMSTATE_UINT32(im, PL031State), | |
225 | VMSTATE_UINT32(is, PL031State), | |
ac204b8f PB |
226 | VMSTATE_END_OF_LIST() |
227 | } | |
228 | }; | |
229 | ||
999e12bb AL |
230 | static void pl031_class_init(ObjectClass *klass, void *data) |
231 | { | |
39bffca2 | 232 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 233 | |
39bffca2 | 234 | dc->vmsd = &vmstate_pl031; |
999e12bb AL |
235 | } |
236 | ||
8c43a6f0 | 237 | static const TypeInfo pl031_info = { |
d3b80049 | 238 | .name = TYPE_PL031, |
39bffca2 | 239 | .parent = TYPE_SYS_BUS_DEVICE, |
b91f0dfd | 240 | .instance_size = sizeof(PL031State), |
81dcc494 | 241 | .instance_init = pl031_init, |
39bffca2 | 242 | .class_init = pl031_class_init, |
0dc5595c PM |
243 | }; |
244 | ||
83f7d43a | 245 | static void pl031_register_types(void) |
a63bdb31 | 246 | { |
39bffca2 | 247 | type_register_static(&pl031_info); |
a63bdb31 PB |
248 | } |
249 | ||
83f7d43a | 250 | type_init(pl031_register_types) |