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Commit | Line | Data |
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56d07a90 GX |
1 | /* |
2 | * OSTimer device simulation in PKUnity SoC | |
3 | * | |
4 | * Copyright (C) 2010-2012 Guan Xuetao | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation, or any later version. | |
9 | * See the COPYING file in the top-level directory. | |
10 | */ | |
0b8fa32f | 11 | |
5af98cc5 | 12 | #include "qemu/osdep.h" |
83c9f4ca PB |
13 | #include "hw/sysbus.h" |
14 | #include "hw/ptimer.h" | |
6a1751b7 | 15 | #include "qemu/main-loop.h" |
0b8fa32f | 16 | #include "qemu/module.h" |
56d07a90 GX |
17 | |
18 | #undef DEBUG_PUV3 | |
0d09e41a | 19 | #include "hw/unicore32/puv3.h" |
56d07a90 | 20 | |
9c9610b8 AF |
21 | #define TYPE_PUV3_OST "puv3_ost" |
22 | #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST) | |
23 | ||
56d07a90 | 24 | /* puv3 ostimer implementation. */ |
9c9610b8 AF |
25 | typedef struct PUV3OSTState { |
26 | SysBusDevice parent_obj; | |
27 | ||
56d07a90 GX |
28 | MemoryRegion iomem; |
29 | QEMUBH *bh; | |
30 | qemu_irq irq; | |
31 | ptimer_state *ptimer; | |
32 | ||
33 | uint32_t reg_OSMR0; | |
34 | uint32_t reg_OSCR; | |
35 | uint32_t reg_OSSR; | |
36 | uint32_t reg_OIER; | |
37 | } PUV3OSTState; | |
38 | ||
a8170e5e | 39 | static uint64_t puv3_ost_read(void *opaque, hwaddr offset, |
56d07a90 GX |
40 | unsigned size) |
41 | { | |
42 | PUV3OSTState *s = opaque; | |
43 | uint32_t ret = 0; | |
44 | ||
45 | switch (offset) { | |
46 | case 0x10: /* Counter Register */ | |
47 | ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer); | |
48 | break; | |
49 | case 0x14: /* Status Register */ | |
50 | ret = s->reg_OSSR; | |
51 | break; | |
52 | case 0x1c: /* Interrupt Enable Register */ | |
53 | ret = s->reg_OIER; | |
54 | break; | |
55 | default: | |
56 | DPRINTF("Bad offset %x\n", (int)offset); | |
57 | } | |
58 | DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); | |
59 | return ret; | |
60 | } | |
61 | ||
a8170e5e | 62 | static void puv3_ost_write(void *opaque, hwaddr offset, |
56d07a90 GX |
63 | uint64_t value, unsigned size) |
64 | { | |
65 | PUV3OSTState *s = opaque; | |
66 | ||
67 | DPRINTF("offset 0x%x, value 0x%x\n", offset, value); | |
68 | switch (offset) { | |
69 | case 0x00: /* Match Register 0 */ | |
70 | s->reg_OSMR0 = value; | |
71 | if (s->reg_OSMR0 > s->reg_OSCR) { | |
72 | ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR); | |
73 | } else { | |
74 | ptimer_set_count(s->ptimer, s->reg_OSMR0 + | |
75 | (0xffffffff - s->reg_OSCR)); | |
76 | } | |
77 | ptimer_run(s->ptimer, 2); | |
78 | break; | |
79 | case 0x14: /* Status Register */ | |
80 | assert(value == 0); | |
81 | if (s->reg_OSSR) { | |
82 | s->reg_OSSR = value; | |
83 | qemu_irq_lower(s->irq); | |
84 | } | |
85 | break; | |
86 | case 0x1c: /* Interrupt Enable Register */ | |
87 | s->reg_OIER = value; | |
88 | break; | |
89 | default: | |
90 | DPRINTF("Bad offset %x\n", (int)offset); | |
91 | } | |
92 | } | |
93 | ||
94 | static const MemoryRegionOps puv3_ost_ops = { | |
95 | .read = puv3_ost_read, | |
96 | .write = puv3_ost_write, | |
97 | .impl = { | |
98 | .min_access_size = 4, | |
99 | .max_access_size = 4, | |
100 | }, | |
101 | .endianness = DEVICE_NATIVE_ENDIAN, | |
102 | }; | |
103 | ||
104 | static void puv3_ost_tick(void *opaque) | |
105 | { | |
106 | PUV3OSTState *s = opaque; | |
107 | ||
108 | DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n", | |
109 | s->reg_OSCR, s->reg_OSMR0); | |
110 | ||
111 | s->reg_OSCR = s->reg_OSMR0; | |
112 | if (s->reg_OIER) { | |
113 | s->reg_OSSR = 1; | |
114 | qemu_irq_raise(s->irq); | |
115 | } | |
116 | } | |
117 | ||
30735a2b | 118 | static void puv3_ost_realize(DeviceState *dev, Error **errp) |
56d07a90 | 119 | { |
9c9610b8 | 120 | PUV3OSTState *s = PUV3_OST(dev); |
30735a2b | 121 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
56d07a90 GX |
122 | |
123 | s->reg_OIER = 0; | |
124 | s->reg_OSSR = 0; | |
125 | s->reg_OSMR0 = 0; | |
126 | s->reg_OSCR = 0; | |
127 | ||
30735a2b | 128 | sysbus_init_irq(sbd, &s->irq); |
56d07a90 GX |
129 | |
130 | s->bh = qemu_bh_new(puv3_ost_tick, s); | |
e7ea81c3 | 131 | s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); |
56d07a90 GX |
132 | ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); |
133 | ||
853dca12 | 134 | memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost", |
56d07a90 | 135 | PUV3_REGS_OFFSET); |
30735a2b | 136 | sysbus_init_mmio(sbd, &s->iomem); |
56d07a90 GX |
137 | } |
138 | ||
139 | static void puv3_ost_class_init(ObjectClass *klass, void *data) | |
140 | { | |
30735a2b | 141 | DeviceClass *dc = DEVICE_CLASS(klass); |
56d07a90 | 142 | |
30735a2b | 143 | dc->realize = puv3_ost_realize; |
56d07a90 GX |
144 | } |
145 | ||
146 | static const TypeInfo puv3_ost_info = { | |
9c9610b8 | 147 | .name = TYPE_PUV3_OST, |
56d07a90 GX |
148 | .parent = TYPE_SYS_BUS_DEVICE, |
149 | .instance_size = sizeof(PUV3OSTState), | |
150 | .class_init = puv3_ost_class_init, | |
151 | }; | |
152 | ||
153 | static void puv3_ost_register_type(void) | |
154 | { | |
155 | type_register_static(&puv3_ost_info); | |
156 | } | |
157 | ||
158 | type_init(puv3_ost_register_type) |