[mirror_qemu.git] / hw / timer / sh_timer.c

/*
 * SuperH Timer modules.
 *
 * Copyright (c) 2007 Magnus Damm
 * Based on arm_timer.c by Paul Brook
 * Copyright (c) 2005-2006 CodeSourcery.
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sh4/sh.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"
#include "hw/ptimer.h"

//#define DEBUG_TIMER

#define TIMER_TCR_TPSC          (7 << 0)
#define TIMER_TCR_CKEG          (3 << 3)
#define TIMER_TCR_UNIE          (1 << 5)
#define TIMER_TCR_ICPE          (3 << 6)
#define TIMER_TCR_UNF           (1 << 8)
#define TIMER_TCR_ICPF          (1 << 9)
#define TIMER_TCR_RESERVED      (0x3f << 10)

#define TIMER_FEAT_CAPT   (1 << 0)
#define TIMER_FEAT_EXTCLK (1 << 1)

#define OFFSET_TCOR   0
#define OFFSET_TCNT   1
#define OFFSET_TCR    2
#define OFFSET_TCPR   3

typedef struct {
    ptimer_state *timer;
    uint32_t tcnt;
    uint32_t tcor;
    uint32_t tcr;
    uint32_t tcpr;
    int freq;
    int int_level;
    int old_level;
    int feat;
    int enabled;
    qemu_irq irq;
} sh_timer_state;

/* Check all active timers, and schedule the next timer interrupt. */

static void sh_timer_update(sh_timer_state *s)
{
    int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);

    if (new_level != s->old_level)
      qemu_set_irq (s->irq, new_level);

    s->old_level = s->int_level;
    s->int_level = new_level;
}

static uint32_t sh_timer_read(void *opaque, hwaddr offset)
{
    sh_timer_state *s = (sh_timer_state *)opaque;

    switch (offset >> 2) {
    case OFFSET_TCOR:
        return s->tcor;
    case OFFSET_TCNT:
        return ptimer_get_count(s->timer);
    case OFFSET_TCR:
        return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
    case OFFSET_TCPR:
        if (s->feat & TIMER_FEAT_CAPT)
            return s->tcpr;
        /* fall through */
    default:
        hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void sh_timer_write(void *opaque, hwaddr offset,
                            uint32_t value)
{
    sh_timer_state *s = (sh_timer_state *)opaque;
    int freq;

    switch (offset >> 2) {
    case OFFSET_TCOR:
        s->tcor = value;
        ptimer_set_limit(s->timer, s->tcor, 0);
        break;
    case OFFSET_TCNT:
        s->tcnt = value;
        ptimer_set_count(s->timer, s->tcnt);
        break;
    case OFFSET_TCR:
        if (s->enabled) {
            /* Pause the timer if it is running.  This may cause some
               inaccuracy dure to rounding, but avoids a whole lot of other
               messyness.  */
            ptimer_stop(s->timer);
        }
        freq = s->freq;
        /* ??? Need to recalculate expiry time after changing divisor.  */
        switch (value & TIMER_TCR_TPSC) {
        case 0: freq >>= 2; break;
        case 1: freq >>= 4; break;
        case 2: freq >>= 6; break;
        case 3: freq >>= 8; break;
        case 4: freq >>= 10; break;
	case 6:
	case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
	default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
        }
        switch ((value & TIMER_TCR_CKEG) >> 3) {
	case 0: break;
        case 1:
        case 2:
        case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
	default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
        }
        switch ((value & TIMER_TCR_ICPE) >> 6) {
	case 0: break;
        case 2:
        case 3: if (s->feat & TIMER_FEAT_CAPT) break;
	default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
        }
	if ((value & TIMER_TCR_UNF) == 0)
            s->int_level = 0;

	value &= ~TIMER_TCR_UNF;

	if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
            hw_error("sh_timer_write: Reserved ICPF value\n");

	value &= ~TIMER_TCR_ICPF; /* capture not supported */

	if (value & TIMER_TCR_RESERVED)
            hw_error("sh_timer_write: Reserved TCR bits set\n");
        s->tcr = value;
        ptimer_set_limit(s->timer, s->tcor, 0);
        ptimer_set_freq(s->timer, freq);
        if (s->enabled) {
            /* Restart the timer if still enabled.  */
            ptimer_run(s->timer, 0);
        }
        break;
    case OFFSET_TCPR:
        if (s->feat & TIMER_FEAT_CAPT) {
            s->tcpr = value;
	    break;
	}
    default:
        hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
    }
    sh_timer_update(s);
}

static void sh_timer_start_stop(void *opaque, int enable)
{
    sh_timer_state *s = (sh_timer_state *)opaque;

#ifdef DEBUG_TIMER
    printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
#endif

    if (s->enabled && !enable) {
        ptimer_stop(s->timer);
    }
    if (!s->enabled && enable) {
        ptimer_run(s->timer, 0);
    }
    s->enabled = !!enable;

#ifdef DEBUG_TIMER
    printf("sh_timer_start_stop done %d\n", s->enabled);
#endif
}

static void sh_timer_tick(void *opaque)
{
    sh_timer_state *s = (sh_timer_state *)opaque;
    s->int_level = s->enabled;
    sh_timer_update(s);
}

static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
{
    sh_timer_state *s;
    QEMUBH *bh;

    s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
    s->freq = freq;
    s->feat = feat;
    s->tcor = 0xffffffff;
    s->tcnt = 0xffffffff;
    s->tcpr = 0xdeadbeef;
    s->tcr = 0;
    s->enabled = 0;
    s->irq = irq;

    bh = qemu_bh_new(sh_timer_tick, s);
    s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);

    sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
    sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
    sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
    sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
    /* ??? Save/restore.  */
    return s;
}

typedef struct {
    MemoryRegion iomem;
    MemoryRegion iomem_p4;
    MemoryRegion iomem_a7;
    void *timer[3];
    int level[3];
    uint32_t tocr;
    uint32_t tstr;
    int feat;
} tmu012_state;

static uint64_t tmu012_read(void *opaque, hwaddr offset,
                            unsigned size)
{
    tmu012_state *s = (tmu012_state *)opaque;

#ifdef DEBUG_TIMER
    printf("tmu012_read 0x%lx\n", (unsigned long) offset);
#endif

    if (offset >= 0x20) {
        if (!(s->feat & TMU012_FEAT_3CHAN))
	    hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
        return sh_timer_read(s->timer[2], offset - 0x20);
    }

    if (offset >= 0x14)
        return sh_timer_read(s->timer[1], offset - 0x14);

    if (offset >= 0x08)
        return sh_timer_read(s->timer[0], offset - 0x08);

    if (offset == 4)
        return s->tstr;

    if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
        return s->tocr;

    hw_error("tmu012_write: Bad offset %x\n", (int)offset);
    return 0;
}

static void tmu012_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    tmu012_state *s = (tmu012_state *)opaque;

#ifdef DEBUG_TIMER
    printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
#endif

    if (offset >= 0x20) {
        if (!(s->feat & TMU012_FEAT_3CHAN))
	    hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
        sh_timer_write(s->timer[2], offset - 0x20, value);
	return;
    }

    if (offset >= 0x14) {
        sh_timer_write(s->timer[1], offset - 0x14, value);
	return;
    }

    if (offset >= 0x08) {
        sh_timer_write(s->timer[0], offset - 0x08, value);
	return;
    }

    if (offset == 4) {
        sh_timer_start_stop(s->timer[0], value & (1 << 0));
        sh_timer_start_stop(s->timer[1], value & (1 << 1));
        if (s->feat & TMU012_FEAT_3CHAN)
            sh_timer_start_stop(s->timer[2], value & (1 << 2));
	else
            if (value & (1 << 2))
                hw_error("tmu012_write: Bad channel\n");

	s->tstr = value;
	return;
    }

    if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
        s->tocr = value & (1 << 0);
    }
}

static const MemoryRegionOps tmu012_ops = {
    .read = tmu012_read,
    .write = tmu012_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void tmu012_init(MemoryRegion *sysmem, hwaddr base,
                 int feat, uint32_t freq,
		 qemu_irq ch0_irq, qemu_irq ch1_irq,
		 qemu_irq ch2_irq0, qemu_irq ch2_irq1)
{
    tmu012_state *s;
    int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;

    s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
    s->feat = feat;
    s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
    s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
    if (feat & TMU012_FEAT_3CHAN)
        s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
				    ch2_irq0); /* ch2_irq1 not supported */

    memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
                          "timer", 0x100000000ULL);

    memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
                             &s->iomem, 0, 0x1000);
    memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);

    memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
                             &s->iomem, 0, 0x1000);
    memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
    /* ??? Save/restore.  */
}
Commit	Line	Data
cd1a3f68 TS	1	/*
	2	* SuperH Timer modules.
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	* Based on arm_timer.c by Paul Brook
	6	* Copyright (c) 2005-2006 CodeSourcery.
	7	*
8e31bf38	8	* This code is licensed under the GPL.
cd1a3f68 TS	9	*/
cd1a3f68 TS	10
282bc81e	11	#include "qemu/osdep.h"
83c9f4ca	12	#include "hw/hw.h"
0d09e41a	13	#include "hw/sh4/sh.h"
1de7afc9	14	#include "qemu/timer.h"
6a1751b7	15	#include "qemu/main-loop.h"
83c9f4ca	16	#include "hw/ptimer.h"
cd1a3f68 TS	17
	18	//#define DEBUG_TIMER
	19
	20	#define TIMER_TCR_TPSC (7 << 0)
	21	#define TIMER_TCR_CKEG (3 << 3)
	22	#define TIMER_TCR_UNIE (1 << 5)
	23	#define TIMER_TCR_ICPE (3 << 6)
	24	#define TIMER_TCR_UNF (1 << 8)
	25	#define TIMER_TCR_ICPF (1 << 9)
	26	#define TIMER_TCR_RESERVED (0x3f << 10)
	27
	28	#define TIMER_FEAT_CAPT (1 << 0)
	29	#define TIMER_FEAT_EXTCLK (1 << 1)
	30
e7786f27 AJ	31	#define OFFSET_TCOR 0
	32	#define OFFSET_TCNT 1
	33	#define OFFSET_TCR 2
	34	#define OFFSET_TCPR 3
	35
cd1a3f68 TS	36	typedef struct {
	37	ptimer_state *timer;
	38	uint32_t tcnt;
	39	uint32_t tcor;
	40	uint32_t tcr;
	41	uint32_t tcpr;
	42	int freq;
	43	int int_level;
703243a0	44	int old_level;
cd1a3f68 TS	45	int feat;
cd1a3f68 TS	46	int enabled;
96e2fc41	47	qemu_irq irq;
cd1a3f68 TS	48	} sh_timer_state;
	49
	50	/* Check all active timers, and schedule the next timer interrupt. */
	51
	52	static void sh_timer_update(sh_timer_state *s)
	53	{
703243a0 AZ	54	int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
	55
	56	if (new_level != s->old_level)
96e2fc41	57	qemu_set_irq (s->irq, new_level);
703243a0 AZ	58
	59	s->old_level = s->int_level;
	60	s->int_level = new_level;
cd1a3f68 TS	61	}
cd1a3f68 TS	62
a8170e5e	63	static uint32_t sh_timer_read(void *opaque, hwaddr offset)
cd1a3f68 TS	64	{
	65	sh_timer_state s = (sh_timer_state )opaque;
	66
	67	switch (offset >> 2) {
e7786f27	68	case OFFSET_TCOR:
cd1a3f68	69	return s->tcor;
e7786f27	70	case OFFSET_TCNT:
cd1a3f68	71	return ptimer_get_count(s->timer);
e7786f27	72	case OFFSET_TCR:
cd1a3f68	73	return s->tcr \| (s->int_level ? TIMER_TCR_UNF : 0);
e7786f27	74	case OFFSET_TCPR:
cd1a3f68 TS	75	if (s->feat & TIMER_FEAT_CAPT)
cd1a3f68 TS	76	return s->tcpr;
edd7541b	77	/* fall through */
cd1a3f68	78	default:
2ac71179	79	hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
cd1a3f68 TS	80	return 0;
	81	}
	82	}
	83
a8170e5e	84	static void sh_timer_write(void *opaque, hwaddr offset,
cd1a3f68 TS	85	uint32_t value)
	86	{
	87	sh_timer_state s = (sh_timer_state )opaque;
	88	int freq;
	89
	90	switch (offset >> 2) {
e7786f27	91	case OFFSET_TCOR:
cd1a3f68 TS	92	s->tcor = value;
	93	ptimer_set_limit(s->timer, s->tcor, 0);
	94	break;
e7786f27	95	case OFFSET_TCNT:
cd1a3f68 TS	96	s->tcnt = value;
	97	ptimer_set_count(s->timer, s->tcnt);
	98	break;
e7786f27	99	case OFFSET_TCR:
cd1a3f68 TS	100	if (s->enabled) {
	101	/* Pause the timer if it is running. This may cause some
	102	inaccuracy dure to rounding, but avoids a whole lot of other
	103	messyness. */
	104	ptimer_stop(s->timer);
	105	}
	106	freq = s->freq;
	107	/* ??? Need to recalculate expiry time after changing divisor. */
	108	switch (value & TIMER_TCR_TPSC) {
	109	case 0: freq >>= 2; break;
	110	case 1: freq >>= 4; break;
	111	case 2: freq >>= 6; break;
	112	case 3: freq >>= 8; break;
	113	case 4: freq >>= 10; break;
	114	case 6:
	115	case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
2ac71179	116	default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
cd1a3f68 TS	117	}
	118	switch ((value & TIMER_TCR_CKEG) >> 3) {
	119	case 0: break;
	120	case 1:
	121	case 2:
	122	case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
2ac71179	123	default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
cd1a3f68 TS	124	}
	125	switch ((value & TIMER_TCR_ICPE) >> 6) {
	126	case 0: break;
	127	case 2:
	128	case 3: if (s->feat & TIMER_FEAT_CAPT) break;
2ac71179	129	default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
cd1a3f68 TS	130	}
	131	if ((value & TIMER_TCR_UNF) == 0)
	132	s->int_level = 0;
	133
	134	value &= ~TIMER_TCR_UNF;
	135
	136	if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
2ac71179	137	hw_error("sh_timer_write: Reserved ICPF value\n");
cd1a3f68 TS	138
	139	value &= ~TIMER_TCR_ICPF; /* capture not supported */
	140
	141	if (value & TIMER_TCR_RESERVED)
2ac71179	142	hw_error("sh_timer_write: Reserved TCR bits set\n");
cd1a3f68 TS	143	s->tcr = value;
	144	ptimer_set_limit(s->timer, s->tcor, 0);
	145	ptimer_set_freq(s->timer, freq);
	146	if (s->enabled) {
	147	/* Restart the timer if still enabled. */
	148	ptimer_run(s->timer, 0);
	149	}
	150	break;
e7786f27	151	case OFFSET_TCPR:
cd1a3f68 TS	152	if (s->feat & TIMER_FEAT_CAPT) {
	153	s->tcpr = value;
	154	break;
	155	}
	156	default:
2ac71179	157	hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
cd1a3f68 TS	158	}
	159	sh_timer_update(s);
	160	}
	161
	162	static void sh_timer_start_stop(void *opaque, int enable)
	163	{
	164	sh_timer_state s = (sh_timer_state )opaque;
	165
	166	#ifdef DEBUG_TIMER
	167	printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
	168	#endif
	169
	170	if (s->enabled && !enable) {
	171	ptimer_stop(s->timer);
	172	}
	173	if (!s->enabled && enable) {
	174	ptimer_run(s->timer, 0);
	175	}
	176	s->enabled = !!enable;
	177
	178	#ifdef DEBUG_TIMER
	179	printf("sh_timer_start_stop done %d\n", s->enabled);
	180	#endif
	181	}
	182
	183	static void sh_timer_tick(void *opaque)
	184	{
	185	sh_timer_state s = (sh_timer_state )opaque;
	186	s->int_level = s->enabled;
	187	sh_timer_update(s);
	188	}
	189
96e2fc41	190	static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
cd1a3f68 TS	191	{
	192	sh_timer_state *s;
	193	QEMUBH *bh;
	194
7267c094	195	s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
cd1a3f68 TS	196	s->freq = freq;
	197	s->feat = feat;
	198	s->tcor = 0xffffffff;
	199	s->tcnt = 0xffffffff;
	200	s->tcpr = 0xdeadbeef;
e7786f27	201	s->tcr = 0;
cd1a3f68	202	s->enabled = 0;
703243a0	203	s->irq = irq;
cd1a3f68 TS	204
cd1a3f68 TS	205	bh = qemu_bh_new(sh_timer_tick, s);
e7ea81c3	206	s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
e7786f27 AJ	207
	208	sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
	209	sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
	210	sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
	211	sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
cd1a3f68 TS	212	/* ??? Save/restore. */
	213	return s;
	214	}
	215
	216	typedef struct {
89e29451 BC	217	MemoryRegion iomem;
	218	MemoryRegion iomem_p4;
	219	MemoryRegion iomem_a7;
cd1a3f68 TS	220	void *timer[3];
	221	int level[3];
	222	uint32_t tocr;
	223	uint32_t tstr;
cd1a3f68 TS	224	int feat;
	225	} tmu012_state;
	226
a8170e5e	227	static uint64_t tmu012_read(void *opaque, hwaddr offset,
89e29451	228	unsigned size)
cd1a3f68 TS	229	{
	230	tmu012_state s = (tmu012_state )opaque;
	231
	232	#ifdef DEBUG_TIMER
	233	printf("tmu012_read 0x%lx\n", (unsigned long) offset);
	234	#endif
cd1a3f68 TS	235
	236	if (offset >= 0x20) {
	237	if (!(s->feat & TMU012_FEAT_3CHAN))
2ac71179	238	hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
cd1a3f68 TS	239	return sh_timer_read(s->timer[2], offset - 0x20);
	240	}
	241
	242	if (offset >= 0x14)
	243	return sh_timer_read(s->timer[1], offset - 0x14);
	244
	245	if (offset >= 0x08)
	246	return sh_timer_read(s->timer[0], offset - 0x08);
	247
	248	if (offset == 4)
	249	return s->tstr;
	250
	251	if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
	252	return s->tocr;
	253
2ac71179	254	hw_error("tmu012_write: Bad offset %x\n", (int)offset);
cd1a3f68 TS	255	return 0;
	256	}
	257
a8170e5e	258	static void tmu012_write(void *opaque, hwaddr offset,
89e29451	259	uint64_t value, unsigned size)
cd1a3f68 TS	260	{
	261	tmu012_state s = (tmu012_state )opaque;
	262
	263	#ifdef DEBUG_TIMER
	264	printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
	265	#endif
cd1a3f68 TS	266
	267	if (offset >= 0x20) {
	268	if (!(s->feat & TMU012_FEAT_3CHAN))
2ac71179	269	hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
cd1a3f68 TS	270	sh_timer_write(s->timer[2], offset - 0x20, value);
	271	return;
	272	}
	273
	274	if (offset >= 0x14) {
	275	sh_timer_write(s->timer[1], offset - 0x14, value);
	276	return;
	277	}
	278
	279	if (offset >= 0x08) {
	280	sh_timer_write(s->timer[0], offset - 0x08, value);
	281	return;
	282	}
	283
	284	if (offset == 4) {
	285	sh_timer_start_stop(s->timer[0], value & (1 << 0));
	286	sh_timer_start_stop(s->timer[1], value & (1 << 1));
	287	if (s->feat & TMU012_FEAT_3CHAN)
	288	sh_timer_start_stop(s->timer[2], value & (1 << 2));
	289	else
	290	if (value & (1 << 2))
2ac71179	291	hw_error("tmu012_write: Bad channel\n");
cd1a3f68 TS	292
	293	s->tstr = value;
	294	return;
	295	}
	296
	297	if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
	298	s->tocr = value & (1 << 0);
	299	}
	300	}
	301
89e29451 BC	302	static const MemoryRegionOps tmu012_ops = {
	303	.read = tmu012_read,
	304	.write = tmu012_write,
	305	.endianness = DEVICE_NATIVE_ENDIAN,
cd1a3f68 TS	306	};
cd1a3f68 TS	307
a8170e5e	308	void tmu012_init(MemoryRegion *sysmem, hwaddr base,
89e29451	309	int feat, uint32_t freq,
96e2fc41 AJ	310	qemu_irq ch0_irq, qemu_irq ch1_irq,
96e2fc41 AJ	311	qemu_irq ch2_irq0, qemu_irq ch2_irq1)
cd1a3f68	312	{
cd1a3f68 TS	313	tmu012_state *s;
	314	int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
	315
7267c094	316	s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
cd1a3f68	317	s->feat = feat;
703243a0 AZ	318	s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
703243a0 AZ	319	s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
cd1a3f68	320	if (feat & TMU012_FEAT_3CHAN)
703243a0 AZ	321	s->timer[2] = sh_timer_init(freq, timer_feat \| TIMER_FEAT_CAPT,
703243a0 AZ	322	ch2_irq0); /* ch2_irq1 not supported */
89e29451	323
2c9b15ca	324	memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
89e29451 BC	325	"timer", 0x100000000ULL);
89e29451 BC	326
2c9b15ca	327	memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
89e29451 BC	328	&s->iomem, 0, 0x1000);
	329	memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
	330
2c9b15ca	331	memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
89e29451 BC	332	&s->iomem, 0, 0x1000);
89e29451 BC	333	memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
cd1a3f68 TS	334	/* ??? Save/restore. */
cd1a3f68 TS	335	}