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Commit | Line | Data |
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e80cfcfc FB |
1 | /* |
2 | * QEMU Sparc SLAVIO timer controller emulation | |
3 | * | |
66321a11 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
e80cfcfc FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c70c59ee | 24 | |
282bc81e | 25 | #include "qemu/osdep.h" |
1de7afc9 | 26 | #include "qemu/timer.h" |
64552b6b | 27 | #include "hw/irq.h" |
83c9f4ca | 28 | #include "hw/ptimer.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
97bf4851 | 32 | #include "trace.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
db1015e9 | 34 | #include "qom/object.h" |
66321a11 | 35 | |
e80cfcfc FB |
36 | /* |
37 | * Registers of hardware timer in sun4m. | |
38 | * | |
39 | * This is the timer/counter part of chip STP2001 (Slave I/O), also | |
40 | * produced as NCR89C105. See | |
41 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt | |
5fafdf24 | 42 | * |
e80cfcfc FB |
43 | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 |
44 | * are zero. Bit 31 is 1 when count has been reached. | |
45 | * | |
ba3c64fb FB |
46 | * Per-CPU timers interrupt local CPU, system timer uses normal |
47 | * interrupt routing. | |
48 | * | |
e80cfcfc FB |
49 | */ |
50 | ||
81732d19 BS |
51 | #define MAX_CPUS 16 |
52 | ||
7204ff9c | 53 | typedef struct CPUTimerState { |
d7edfd27 | 54 | qemu_irq irq; |
8d05ea8a BS |
55 | ptimer_state *timer; |
56 | uint32_t count, counthigh, reached; | |
f90074f4 | 57 | /* processor only */ |
ead4cf04 | 58 | uint32_t run; |
f90074f4 | 59 | uint64_t limit; |
7204ff9c BS |
60 | } CPUTimerState; |
61 | ||
c275471e | 62 | #define TYPE_SLAVIO_TIMER "slavio_timer" |
8063396b | 63 | OBJECT_DECLARE_SIMPLE_TYPE(SLAVIO_TIMERState, SLAVIO_TIMER) |
c275471e | 64 | |
db1015e9 | 65 | struct SLAVIO_TIMERState { |
c275471e AF |
66 | SysBusDevice parent_obj; |
67 | ||
7204ff9c | 68 | uint32_t num_cpus; |
7204ff9c | 69 | uint32_t cputimer_mode; |
f90074f4 | 70 | CPUTimerState cputimer[MAX_CPUS + 1]; |
db1015e9 | 71 | }; |
e80cfcfc | 72 | |
7204ff9c | 73 | typedef struct TimerContext { |
a3d12d07 | 74 | MemoryRegion iomem; |
7204ff9c BS |
75 | SLAVIO_TIMERState *s; |
76 | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ | |
77 | } TimerContext; | |
78 | ||
115646b6 | 79 | #define SYS_TIMER_SIZE 0x14 |
81732d19 | 80 | #define CPU_TIMER_SIZE 0x10 |
e80cfcfc | 81 | |
d2c38b24 BS |
82 | #define TIMER_LIMIT 0 |
83 | #define TIMER_COUNTER 1 | |
84 | #define TIMER_COUNTER_NORST 2 | |
85 | #define TIMER_STATUS 3 | |
86 | #define TIMER_MODE 4 | |
87 | ||
88 | #define TIMER_COUNT_MASK32 0xfffffe00 | |
89 | #define TIMER_LIMIT_MASK32 0x7fffffff | |
90 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL | |
91 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL | |
92 | #define TIMER_REACHED 0x80000000 | |
93 | #define TIMER_PERIOD 500ULL // 500ns | |
68fb89a2 BS |
94 | #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) |
95 | #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) | |
d2c38b24 | 96 | |
7204ff9c | 97 | static int slavio_timer_is_user(TimerContext *tc) |
115646b6 | 98 | { |
7204ff9c BS |
99 | SLAVIO_TIMERState *s = tc->s; |
100 | unsigned int timer_index = tc->timer_index; | |
101 | ||
102 | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); | |
115646b6 BS |
103 | } |
104 | ||
e80cfcfc | 105 | // Update count, set irq, update expire_time |
8d05ea8a | 106 | // Convert from ptimer countdown units |
7204ff9c | 107 | static void slavio_timer_get_out(CPUTimerState *t) |
e80cfcfc | 108 | { |
bd7e2875 | 109 | uint64_t count, limit; |
e80cfcfc | 110 | |
7204ff9c | 111 | if (t->limit == 0) { /* free-run system or processor counter */ |
bd7e2875 | 112 | limit = TIMER_MAX_COUNT32; |
7204ff9c BS |
113 | } else { |
114 | limit = t->limit; | |
115 | } | |
9ebec28b BS |
116 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
117 | ||
97bf4851 | 118 | trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
7204ff9c BS |
119 | t->count = count & TIMER_COUNT_MASK32; |
120 | t->counthigh = count >> 32; | |
e80cfcfc FB |
121 | } |
122 | ||
123 | // timer callback | |
124 | static void slavio_timer_irq(void *opaque) | |
125 | { | |
7204ff9c BS |
126 | TimerContext *tc = opaque; |
127 | SLAVIO_TIMERState *s = tc->s; | |
128 | CPUTimerState *t = &s->cputimer[tc->timer_index]; | |
129 | ||
130 | slavio_timer_get_out(t); | |
97bf4851 | 131 | trace_slavio_timer_irq(t->counthigh, t->count); |
68fb89a2 BS |
132 | /* if limit is 0 (free-run), there will be no match */ |
133 | if (t->limit != 0) { | |
134 | t->reached = TIMER_REACHED; | |
135 | } | |
452efba6 BS |
136 | /* there is no interrupt if user timer or free-run */ |
137 | if (!slavio_timer_is_user(tc) && t->limit != 0) { | |
7204ff9c BS |
138 | qemu_irq_raise(t->irq); |
139 | } | |
e80cfcfc FB |
140 | } |
141 | ||
a8170e5e | 142 | static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr, |
a3d12d07 | 143 | unsigned size) |
e80cfcfc | 144 | { |
7204ff9c BS |
145 | TimerContext *tc = opaque; |
146 | SLAVIO_TIMERState *s = tc->s; | |
8d05ea8a | 147 | uint32_t saddr, ret; |
7204ff9c BS |
148 | unsigned int timer_index = tc->timer_index; |
149 | CPUTimerState *t = &s->cputimer[timer_index]; | |
e80cfcfc | 150 | |
e64d7d59 | 151 | saddr = addr >> 2; |
e80cfcfc | 152 | switch (saddr) { |
d2c38b24 | 153 | case TIMER_LIMIT: |
f930d07e BS |
154 | // read limit (system counter mode) or read most signifying |
155 | // part of counter (user mode) | |
7204ff9c | 156 | if (slavio_timer_is_user(tc)) { |
115646b6 | 157 | // read user timer MSW |
7204ff9c BS |
158 | slavio_timer_get_out(t); |
159 | ret = t->counthigh | t->reached; | |
115646b6 BS |
160 | } else { |
161 | // read limit | |
f930d07e | 162 | // clear irq |
7204ff9c BS |
163 | qemu_irq_lower(t->irq); |
164 | t->reached = 0; | |
165 | ret = t->limit & TIMER_LIMIT_MASK32; | |
f930d07e | 166 | } |
8d05ea8a | 167 | break; |
d2c38b24 | 168 | case TIMER_COUNTER: |
f930d07e BS |
169 | // read counter and reached bit (system mode) or read lsbits |
170 | // of counter (user mode) | |
7204ff9c BS |
171 | slavio_timer_get_out(t); |
172 | if (slavio_timer_is_user(tc)) { // read user timer LSW | |
173 | ret = t->count & TIMER_MAX_COUNT64; | |
174 | } else { // read limit | |
175 | ret = (t->count & TIMER_MAX_COUNT32) | | |
176 | t->reached; | |
177 | } | |
8d05ea8a | 178 | break; |
d2c38b24 | 179 | case TIMER_STATUS: |
115646b6 | 180 | // only available in processor counter/timer |
f930d07e | 181 | // read start/stop status |
7204ff9c | 182 | if (timer_index > 0) { |
ead4cf04 | 183 | ret = t->run; |
7204ff9c BS |
184 | } else { |
185 | ret = 0; | |
186 | } | |
8d05ea8a | 187 | break; |
d2c38b24 | 188 | case TIMER_MODE: |
115646b6 | 189 | // only available in system counter |
f930d07e | 190 | // read user/system mode |
7204ff9c | 191 | ret = s->cputimer_mode; |
8d05ea8a | 192 | break; |
e80cfcfc | 193 | default: |
97bf4851 | 194 | trace_slavio_timer_mem_readl_invalid(addr); |
8d05ea8a BS |
195 | ret = 0; |
196 | break; | |
e80cfcfc | 197 | } |
97bf4851 | 198 | trace_slavio_timer_mem_readl(addr, ret); |
8d05ea8a | 199 | return ret; |
e80cfcfc FB |
200 | } |
201 | ||
a8170e5e | 202 | static void slavio_timer_mem_writel(void *opaque, hwaddr addr, |
a3d12d07 | 203 | uint64_t val, unsigned size) |
e80cfcfc | 204 | { |
7204ff9c BS |
205 | TimerContext *tc = opaque; |
206 | SLAVIO_TIMERState *s = tc->s; | |
e80cfcfc | 207 | uint32_t saddr; |
7204ff9c BS |
208 | unsigned int timer_index = tc->timer_index; |
209 | CPUTimerState *t = &s->cputimer[timer_index]; | |
e80cfcfc | 210 | |
97bf4851 | 211 | trace_slavio_timer_mem_writel(addr, val); |
e64d7d59 | 212 | saddr = addr >> 2; |
e80cfcfc | 213 | switch (saddr) { |
d2c38b24 | 214 | case TIMER_LIMIT: |
2ee62f32 | 215 | ptimer_transaction_begin(t->timer); |
7204ff9c | 216 | if (slavio_timer_is_user(tc)) { |
e1cb9502 BS |
217 | uint64_t count; |
218 | ||
115646b6 | 219 | // set user counter MSW, reset counter |
7204ff9c BS |
220 | t->limit = TIMER_MAX_COUNT64; |
221 | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); | |
222 | t->reached = 0; | |
223 | count = ((uint64_t)t->counthigh << 32) | t->count; | |
97bf4851 | 224 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
9ebec28b | 225 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
115646b6 BS |
226 | } else { |
227 | // set limit, reset counter | |
7204ff9c BS |
228 | qemu_irq_lower(t->irq); |
229 | t->limit = val & TIMER_MAX_COUNT32; | |
5e347892 PM |
230 | if (t->limit == 0) { /* free-run */ |
231 | ptimer_set_limit(t->timer, | |
232 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); | |
233 | } else { | |
234 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); | |
85e3023e | 235 | } |
81732d19 | 236 | } |
2ee62f32 | 237 | ptimer_transaction_commit(t->timer); |
115646b6 | 238 | break; |
d2c38b24 | 239 | case TIMER_COUNTER: |
7204ff9c | 240 | if (slavio_timer_is_user(tc)) { |
e1cb9502 BS |
241 | uint64_t count; |
242 | ||
115646b6 | 243 | // set user counter LSW, reset counter |
7204ff9c BS |
244 | t->limit = TIMER_MAX_COUNT64; |
245 | t->count = val & TIMER_MAX_COUNT64; | |
246 | t->reached = 0; | |
247 | count = ((uint64_t)t->counthigh) << 32 | t->count; | |
97bf4851 | 248 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
2ee62f32 | 249 | ptimer_transaction_begin(t->timer); |
9ebec28b | 250 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
2ee62f32 | 251 | ptimer_transaction_commit(t->timer); |
97bf4851 BS |
252 | } else { |
253 | trace_slavio_timer_mem_writel_counter_invalid(); | |
254 | } | |
115646b6 | 255 | break; |
d2c38b24 | 256 | case TIMER_COUNTER_NORST: |
f930d07e | 257 | // set limit without resetting counter |
7204ff9c | 258 | t->limit = val & TIMER_MAX_COUNT32; |
2ee62f32 | 259 | ptimer_transaction_begin(t->timer); |
9ebec28b BS |
260 | if (t->limit == 0) { /* free-run */ |
261 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); | |
262 | } else { | |
263 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); | |
85e3023e | 264 | } |
2ee62f32 | 265 | ptimer_transaction_commit(t->timer); |
f930d07e | 266 | break; |
d2c38b24 | 267 | case TIMER_STATUS: |
2ee62f32 | 268 | ptimer_transaction_begin(t->timer); |
7204ff9c | 269 | if (slavio_timer_is_user(tc)) { |
115646b6 | 270 | // start/stop user counter |
ead4cf04 | 271 | if (val & 1) { |
97bf4851 | 272 | trace_slavio_timer_mem_writel_status_start(timer_index); |
9ebec28b | 273 | ptimer_run(t->timer, 0); |
ead4cf04 | 274 | } else { |
97bf4851 | 275 | trace_slavio_timer_mem_writel_status_stop(timer_index); |
9ebec28b | 276 | ptimer_stop(t->timer); |
f930d07e BS |
277 | } |
278 | } | |
ead4cf04 | 279 | t->run = val & 1; |
2ee62f32 | 280 | ptimer_transaction_commit(t->timer); |
f930d07e | 281 | break; |
d2c38b24 | 282 | case TIMER_MODE: |
7204ff9c | 283 | if (timer_index == 0) { |
81732d19 BS |
284 | unsigned int i; |
285 | ||
7204ff9c | 286 | for (i = 0; i < s->num_cpus; i++) { |
67e42751 | 287 | unsigned int processor = 1 << i; |
7204ff9c | 288 | CPUTimerState *curr_timer = &s->cputimer[i + 1]; |
67e42751 | 289 | |
2ee62f32 | 290 | ptimer_transaction_begin(curr_timer->timer); |
67e42751 | 291 | // check for a change in timer mode for this processor |
7204ff9c | 292 | if ((val & processor) != (s->cputimer_mode & processor)) { |
67e42751 | 293 | if (val & processor) { // counter -> user timer |
7204ff9c | 294 | qemu_irq_lower(curr_timer->irq); |
67e42751 | 295 | // counters are always running |
ead4cf04 MCA |
296 | if (!curr_timer->run) { |
297 | ptimer_stop(curr_timer->timer); | |
298 | } | |
67e42751 | 299 | // user timer limit is always the same |
7204ff9c BS |
300 | curr_timer->limit = TIMER_MAX_COUNT64; |
301 | ptimer_set_limit(curr_timer->timer, | |
302 | LIMIT_TO_PERIODS(curr_timer->limit), | |
77f193da | 303 | 1); |
67e42751 BS |
304 | // set this processors user timer bit in config |
305 | // register | |
7204ff9c | 306 | s->cputimer_mode |= processor; |
97bf4851 | 307 | trace_slavio_timer_mem_writel_mode_user(timer_index); |
67e42751 | 308 | } else { // user timer -> counter |
67e42751 | 309 | // start the counter |
7204ff9c | 310 | ptimer_run(curr_timer->timer, 0); |
67e42751 BS |
311 | // clear this processors user timer bit in config |
312 | // register | |
7204ff9c | 313 | s->cputimer_mode &= ~processor; |
97bf4851 | 314 | trace_slavio_timer_mem_writel_mode_counter(timer_index); |
67e42751 | 315 | } |
115646b6 | 316 | } |
2ee62f32 | 317 | ptimer_transaction_commit(curr_timer->timer); |
81732d19 | 318 | } |
7204ff9c | 319 | } else { |
97bf4851 | 320 | trace_slavio_timer_mem_writel_mode_invalid(); |
7204ff9c | 321 | } |
f930d07e | 322 | break; |
e80cfcfc | 323 | default: |
97bf4851 | 324 | trace_slavio_timer_mem_writel_invalid(addr); |
f930d07e | 325 | break; |
e80cfcfc FB |
326 | } |
327 | } | |
328 | ||
a3d12d07 BC |
329 | static const MemoryRegionOps slavio_timer_mem_ops = { |
330 | .read = slavio_timer_mem_readl, | |
331 | .write = slavio_timer_mem_writel, | |
332 | .endianness = DEVICE_NATIVE_ENDIAN, | |
333 | .valid = { | |
62a9b228 PMD |
334 | .min_access_size = 4, |
335 | .max_access_size = 8, | |
336 | }, | |
337 | .impl = { | |
a3d12d07 BC |
338 | .min_access_size = 4, |
339 | .max_access_size = 4, | |
340 | }, | |
e80cfcfc FB |
341 | }; |
342 | ||
f4b19cd0 BS |
343 | static const VMStateDescription vmstate_timer = { |
344 | .name ="timer", | |
345 | .version_id = 3, | |
346 | .minimum_version_id = 3, | |
35d08458 | 347 | .fields = (VMStateField[]) { |
f4b19cd0 BS |
348 | VMSTATE_UINT64(limit, CPUTimerState), |
349 | VMSTATE_UINT32(count, CPUTimerState), | |
350 | VMSTATE_UINT32(counthigh, CPUTimerState), | |
351 | VMSTATE_UINT32(reached, CPUTimerState), | |
ead4cf04 | 352 | VMSTATE_UINT32(run , CPUTimerState), |
f4b19cd0 BS |
353 | VMSTATE_PTIMER(timer, CPUTimerState), |
354 | VMSTATE_END_OF_LIST() | |
7204ff9c | 355 | } |
f4b19cd0 | 356 | }; |
e80cfcfc | 357 | |
f4b19cd0 BS |
358 | static const VMStateDescription vmstate_slavio_timer = { |
359 | .name ="slavio_timer", | |
360 | .version_id = 3, | |
361 | .minimum_version_id = 3, | |
35d08458 | 362 | .fields = (VMStateField[]) { |
f4b19cd0 BS |
363 | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, |
364 | vmstate_timer, CPUTimerState), | |
365 | VMSTATE_END_OF_LIST() | |
7204ff9c | 366 | } |
f4b19cd0 | 367 | }; |
e80cfcfc | 368 | |
0e0bfeea | 369 | static void slavio_timer_reset(DeviceState *d) |
e80cfcfc | 370 | { |
c275471e | 371 | SLAVIO_TIMERState *s = SLAVIO_TIMER(d); |
7204ff9c BS |
372 | unsigned int i; |
373 | CPUTimerState *curr_timer; | |
374 | ||
375 | for (i = 0; i <= MAX_CPUS; i++) { | |
376 | curr_timer = &s->cputimer[i]; | |
377 | curr_timer->limit = 0; | |
378 | curr_timer->count = 0; | |
379 | curr_timer->reached = 0; | |
5933e8a9 | 380 | if (i <= s->num_cpus) { |
2ee62f32 | 381 | ptimer_transaction_begin(curr_timer->timer); |
7204ff9c BS |
382 | ptimer_set_limit(curr_timer->timer, |
383 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); | |
384 | ptimer_run(curr_timer->timer, 0); | |
ead4cf04 | 385 | curr_timer->run = 1; |
2ee62f32 | 386 | ptimer_transaction_commit(curr_timer->timer); |
7204ff9c | 387 | } |
85e3023e | 388 | } |
7204ff9c | 389 | s->cputimer_mode = 0; |
e80cfcfc FB |
390 | } |
391 | ||
4410b94c | 392 | static void slavio_timer_init(Object *obj) |
c70c59ee | 393 | { |
4410b94c XZ |
394 | SLAVIO_TIMERState *s = SLAVIO_TIMER(obj); |
395 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
7204ff9c BS |
396 | unsigned int i; |
397 | TimerContext *tc; | |
e80cfcfc | 398 | |
7204ff9c | 399 | for (i = 0; i <= MAX_CPUS; i++) { |
a3d12d07 BC |
400 | uint64_t size; |
401 | char timer_name[20]; | |
402 | ||
7267c094 | 403 | tc = g_malloc0(sizeof(TimerContext)); |
7204ff9c BS |
404 | tc->s = s; |
405 | tc->timer_index = i; | |
c70c59ee | 406 | |
2ee62f32 PM |
407 | s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc, |
408 | PTIMER_POLICY_DEFAULT); | |
409 | ptimer_transaction_begin(s->cputimer[i].timer); | |
7204ff9c | 410 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
2ee62f32 | 411 | ptimer_transaction_commit(s->cputimer[i].timer); |
e80cfcfc | 412 | |
a3d12d07 BC |
413 | size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; |
414 | snprintf(timer_name, sizeof(timer_name), "timer-%i", i); | |
4410b94c | 415 | memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc, |
a3d12d07 | 416 | timer_name, size); |
750ecd44 | 417 | sysbus_init_mmio(dev, &tc->iomem); |
7204ff9c BS |
418 | |
419 | sysbus_init_irq(dev, &s->cputimer[i].irq); | |
c70c59ee | 420 | } |
81732d19 BS |
421 | } |
422 | ||
999e12bb AL |
423 | static Property slavio_timer_properties[] = { |
424 | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), | |
425 | DEFINE_PROP_END_OF_LIST(), | |
426 | }; | |
427 | ||
428 | static void slavio_timer_class_init(ObjectClass *klass, void *data) | |
429 | { | |
39bffca2 | 430 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 431 | |
39bffca2 AL |
432 | dc->reset = slavio_timer_reset; |
433 | dc->vmsd = &vmstate_slavio_timer; | |
4f67d30b | 434 | device_class_set_props(dc, slavio_timer_properties); |
999e12bb AL |
435 | } |
436 | ||
8c43a6f0 | 437 | static const TypeInfo slavio_timer_info = { |
c275471e | 438 | .name = TYPE_SLAVIO_TIMER, |
39bffca2 AL |
439 | .parent = TYPE_SYS_BUS_DEVICE, |
440 | .instance_size = sizeof(SLAVIO_TIMERState), | |
4410b94c | 441 | .instance_init = slavio_timer_init, |
39bffca2 | 442 | .class_init = slavio_timer_class_init, |
c70c59ee BS |
443 | }; |
444 | ||
83f7d43a | 445 | static void slavio_timer_register_types(void) |
c70c59ee | 446 | { |
39bffca2 | 447 | type_register_static(&slavio_timer_info); |
c70c59ee BS |
448 | } |
449 | ||
83f7d43a | 450 | type_init(slavio_timer_register_types) |