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spapr_pci: Fix broken naming of PCI bus
[mirror_qemu.git] / hw / timer / twl92230.c
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7e7c5e4c
AZ		 1/*
2 * TI TWL92230C energy-management companion device for the OMAP24xx.
3 * Aka. Menelaus (N4200 MENELAUS1_V2.2)
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 20 */
21
282bc81e 22#include "qemu/osdep.h"
83c9f4ca 23#include "hw/hw.h"
1de7afc9 24#include "qemu/timer.h"
0d09e41a 25#include "hw/i2c/i2c.h"
9c17d615 26#include "sysemu/sysemu.h"
28ecbaee 27#include "ui/console.h"
f348b6d1 28#include "qemu/bcd.h"
7e7c5e4c
AZ		 29
30#define VERBOSE 1
31
dd37dfa9
AF		 32#define TYPE_TWL92230 "twl92230"
33#define TWL92230(obj) OBJECT_CHECK(MenelausState, (obj), TYPE_TWL92230)
34
35typedef struct MenelausState {
36 I2CSlave parent_obj;
7e7c5e4c
AZ		 37
38 int firstbyte;
39 uint8_t reg;
40
41 uint8_t vcore[5];
42 uint8_t dcdc[3];
43 uint8_t ldo[8];
44 uint8_t sleep[2];
45 uint8_t osc;
46 uint8_t detect;
47 uint16_t mask;
48 uint16_t status;
49 uint8_t dir;
50 uint8_t inputs;
51 uint8_t outputs;
52 uint8_t bbsms;
53 uint8_t pull[4];
54 uint8_t mmc_ctrl[3];
55 uint8_t mmc_debounce;
56 struct {
57 uint8_t ctrl;
58 uint16_t comp;
b0f74c87 59 QEMUTimer *hz_tm;
7e7c5e4c
AZ		 60 int64_t next;
61 struct tm tm;
62 struct tm new;
63 struct tm alm;
aec454d2
AZ		 64 int sec_offset;
65 int alm_sec;
66 int next_comp;
7e7c5e4c 67 } rtc;
f0495f56 68 uint16_t rtc_next_vmstate;
d3356811 69 qemu_irq out[4];
b53d44e5 70 uint8_t pwrbtn_state;
bc24a225 71} MenelausState;
7e7c5e4c 72
bc24a225 73static inline void menelaus_update(MenelausState *s)
7e7c5e4c 74{
d3356811 75 qemu_set_irq(s->out[3], s->status & ~s->mask);
7e7c5e4c
AZ		 76}
77
bc24a225 78static inline void menelaus_rtc_start(MenelausState *s)
7e7c5e4c 79{
884f17c2 80 s->rtc.next += qemu_clock_get_ms(rtc_clock);
bc72ad67 81 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 82}
83
bc24a225 84static inline void menelaus_rtc_stop(MenelausState *s)
7e7c5e4c 85{
bc72ad67 86 timer_del(s->rtc.hz_tm);
884f17c2 87 s->rtc.next -= qemu_clock_get_ms(rtc_clock);
7e7c5e4c
AZ		 88 if (s->rtc.next < 1)
89 s->rtc.next = 1;
90}
91
bc24a225 92static void menelaus_rtc_update(MenelausState *s)
7e7c5e4c 93{
aec454d2 94 qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
7e7c5e4c
AZ		 95}
96
bc24a225 97static void menelaus_alm_update(MenelausState *s)
7e7c5e4c
AZ		 98{
99 if ((s->rtc.ctrl & 3) == 3)
aec454d2 100 s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
7e7c5e4c
AZ		 101}
102
103static void menelaus_rtc_hz(void *opaque)
104{
bc24a225 105 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 106
aec454d2
AZ		 107 s->rtc.next_comp --;
108 s->rtc.alm_sec --;
7e7c5e4c 109 s->rtc.next += 1000;
bc72ad67 110 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 111 if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
112 menelaus_rtc_update(s);
113 if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
114 s->status |= 1 << 8; /* RTCTMR */
115 else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
116 s->status |= 1 << 8; /* RTCTMR */
117 else if (!s->rtc.tm.tm_hour)
118 s->status |= 1 << 8; /* RTCTMR */
119 } else
120 s->status |= 1 << 8; /* RTCTMR */
121 if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
aec454d2 122 if (s->rtc.alm_sec == 0)
7e7c5e4c
AZ		 123 s->status |= 1 << 9; /* RTCALM */
124 /* TODO: wake-up */
125 }
aec454d2 126 if (s->rtc.next_comp <= 0) {
7e7c5e4c 127 s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
aec454d2 128 s->rtc.next_comp = 3600;
7e7c5e4c
AZ		 129 }
130 menelaus_update(s);
131}
132
9e07bdf8 133static void menelaus_reset(I2CSlave *i2c)
7e7c5e4c 134{
dd37dfa9
AF		 135 MenelausState *s = TWL92230(i2c);
136
7e7c5e4c
AZ		 137 s->reg = 0x00;
138
139 s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
140 s->vcore[1] = 0x05;
141 s->vcore[2] = 0x02;
142 s->vcore[3] = 0x0c;
143 s->vcore[4] = 0x03;
144 s->dcdc[0] = 0x33; /* Depends on wiring */
145 s->dcdc[1] = 0x03;
146 s->dcdc[2] = 0x00;
147 s->ldo[0] = 0x95;
148 s->ldo[1] = 0x7e;
149 s->ldo[2] = 0x00;
150 s->ldo[3] = 0x00; /* Depends on wiring */
151 s->ldo[4] = 0x03; /* Depends on wiring */
152 s->ldo[5] = 0x00;
153 s->ldo[6] = 0x00;
154 s->ldo[7] = 0x00;
155 s->sleep[0] = 0x00;
156 s->sleep[1] = 0x00;
157 s->osc = 0x01;
158 s->detect = 0x09;
159 s->mask = 0x0fff;
160 s->status = 0;
161 s->dir = 0x07;
162 s->outputs = 0x00;
163 s->bbsms = 0x00;
164 s->pull[0] = 0x00;
165 s->pull[1] = 0x00;
166 s->pull[2] = 0x00;
167 s->pull[3] = 0x00;
168 s->mmc_ctrl[0] = 0x03;
169 s->mmc_ctrl[1] = 0xc0;
170 s->mmc_ctrl[2] = 0x00;
171 s->mmc_debounce = 0x05;
172
7e7c5e4c
AZ		 173 if (s->rtc.ctrl & 1)
174 menelaus_rtc_stop(s);
175 s->rtc.ctrl = 0x00;
176 s->rtc.comp = 0x0000;
177 s->rtc.next = 1000;
aec454d2
AZ		 178 s->rtc.sec_offset = 0;
179 s->rtc.next_comp = 1800;
180 s->rtc.alm_sec = 1800;
7e7c5e4c
AZ		 181 s->rtc.alm.tm_sec = 0x00;
182 s->rtc.alm.tm_min = 0x00;
183 s->rtc.alm.tm_hour = 0x00;
184 s->rtc.alm.tm_mday = 0x01;
185 s->rtc.alm.tm_mon = 0x00;
186 s->rtc.alm.tm_year = 2004;
187 menelaus_update(s);
188}
189
7e7c5e4c
AZ		 190static void menelaus_gpio_set(void *opaque, int line, int level)
191{
bc24a225 192 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 193
dd4427a6
PB		 194 if (line < 3) {
195 /* No interrupt generated */
196 s->inputs &= ~(1 << line);
197 s->inputs |= level << line;
198 return;
199 }
7e7c5e4c
AZ		 200
201 if (!s->pwrbtn_state && level) {
202 s->status |= 1 << 11; /* PSHBTN */
203 menelaus_update(s);
204 }
205 s->pwrbtn_state = level;
206}
207
208#define MENELAUS_REV 0x01
209#define MENELAUS_VCORE_CTRL1 0x02
210#define MENELAUS_VCORE_CTRL2 0x03
211#define MENELAUS_VCORE_CTRL3 0x04
212#define MENELAUS_VCORE_CTRL4 0x05
213#define MENELAUS_VCORE_CTRL5 0x06
214#define MENELAUS_DCDC_CTRL1 0x07
215#define MENELAUS_DCDC_CTRL2 0x08
216#define MENELAUS_DCDC_CTRL3 0x09
217#define MENELAUS_LDO_CTRL1 0x0a
218#define MENELAUS_LDO_CTRL2 0x0b
219#define MENELAUS_LDO_CTRL3 0x0c
220#define MENELAUS_LDO_CTRL4 0x0d
221#define MENELAUS_LDO_CTRL5 0x0e
222#define MENELAUS_LDO_CTRL6 0x0f
223#define MENELAUS_LDO_CTRL7 0x10
224#define MENELAUS_LDO_CTRL8 0x11
225#define MENELAUS_SLEEP_CTRL1 0x12
226#define MENELAUS_SLEEP_CTRL2 0x13
227#define MENELAUS_DEVICE_OFF 0x14
228#define MENELAUS_OSC_CTRL 0x15
229#define MENELAUS_DETECT_CTRL 0x16
230#define MENELAUS_INT_MASK1 0x17
231#define MENELAUS_INT_MASK2 0x18
232#define MENELAUS_INT_STATUS1 0x19
233#define MENELAUS_INT_STATUS2 0x1a
234#define MENELAUS_INT_ACK1 0x1b
235#define MENELAUS_INT_ACK2 0x1c
236#define MENELAUS_GPIO_CTRL 0x1d
237#define MENELAUS_GPIO_IN 0x1e
238#define MENELAUS_GPIO_OUT 0x1f
239#define MENELAUS_BBSMS 0x20
240#define MENELAUS_RTC_CTRL 0x21
241#define MENELAUS_RTC_UPDATE 0x22
242#define MENELAUS_RTC_SEC 0x23
243#define MENELAUS_RTC_MIN 0x24
244#define MENELAUS_RTC_HR 0x25
245#define MENELAUS_RTC_DAY 0x26
246#define MENELAUS_RTC_MON 0x27
247#define MENELAUS_RTC_YR 0x28
248#define MENELAUS_RTC_WKDAY 0x29
249#define MENELAUS_RTC_AL_SEC 0x2a
250#define MENELAUS_RTC_AL_MIN 0x2b
251#define MENELAUS_RTC_AL_HR 0x2c
252#define MENELAUS_RTC_AL_DAY 0x2d
253#define MENELAUS_RTC_AL_MON 0x2e
254#define MENELAUS_RTC_AL_YR 0x2f
255#define MENELAUS_RTC_COMP_MSB 0x30
256#define MENELAUS_RTC_COMP_LSB 0x31
257#define MENELAUS_S1_PULL_EN 0x32
258#define MENELAUS_S1_PULL_DIR 0x33
259#define MENELAUS_S2_PULL_EN 0x34
260#define MENELAUS_S2_PULL_DIR 0x35
261#define MENELAUS_MCT_CTRL1 0x36
262#define MENELAUS_MCT_CTRL2 0x37
263#define MENELAUS_MCT_CTRL3 0x38
264#define MENELAUS_MCT_PIN_ST 0x39
265#define MENELAUS_DEBOUNCE1 0x3a
266
267static uint8_t menelaus_read(void *opaque, uint8_t addr)
268{
bc24a225 269 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 270 int reg = 0;
271
272 switch (addr) {
273 case MENELAUS_REV:
274 return 0x22;
275
276 case MENELAUS_VCORE_CTRL5: reg ++;
277 case MENELAUS_VCORE_CTRL4: reg ++;
278 case MENELAUS_VCORE_CTRL3: reg ++;
279 case MENELAUS_VCORE_CTRL2: reg ++;
280 case MENELAUS_VCORE_CTRL1:
281 return s->vcore[reg];
282
283 case MENELAUS_DCDC_CTRL3: reg ++;
284 case MENELAUS_DCDC_CTRL2: reg ++;
285 case MENELAUS_DCDC_CTRL1:
286 return s->dcdc[reg];
287
288 case MENELAUS_LDO_CTRL8: reg ++;
289 case MENELAUS_LDO_CTRL7: reg ++;
290 case MENELAUS_LDO_CTRL6: reg ++;
291 case MENELAUS_LDO_CTRL5: reg ++;
292 case MENELAUS_LDO_CTRL4: reg ++;
293 case MENELAUS_LDO_CTRL3: reg ++;
294 case MENELAUS_LDO_CTRL2: reg ++;
295 case MENELAUS_LDO_CTRL1:
296 return s->ldo[reg];
297
298 case MENELAUS_SLEEP_CTRL2: reg ++;
299 case MENELAUS_SLEEP_CTRL1:
300 return s->sleep[reg];
301
302 case MENELAUS_DEVICE_OFF:
303 return 0;
304
305 case MENELAUS_OSC_CTRL:
306 return s->osc | (1 << 7); /* CLK32K_GOOD */
307
308 case MENELAUS_DETECT_CTRL:
309 return s->detect;
310
311 case MENELAUS_INT_MASK1:
312 return (s->mask >> 0) & 0xff;
313 case MENELAUS_INT_MASK2:
314 return (s->mask >> 8) & 0xff;
315
316 case MENELAUS_INT_STATUS1:
317 return (s->status >> 0) & 0xff;
318 case MENELAUS_INT_STATUS2:
319 return (s->status >> 8) & 0xff;
320
321 case MENELAUS_INT_ACK1:
322 case MENELAUS_INT_ACK2:
323 return 0;
324
325 case MENELAUS_GPIO_CTRL:
326 return s->dir;
327 case MENELAUS_GPIO_IN:
328 return s->inputs | (~s->dir & s->outputs);
329 case MENELAUS_GPIO_OUT:
330 return s->outputs;
331
332 case MENELAUS_BBSMS:
333 return s->bbsms;
334
335 case MENELAUS_RTC_CTRL:
336 return s->rtc.ctrl;
337 case MENELAUS_RTC_UPDATE:
338 return 0x00;
339 case MENELAUS_RTC_SEC:
340 menelaus_rtc_update(s);
341 return to_bcd(s->rtc.tm.tm_sec);
342 case MENELAUS_RTC_MIN:
343 menelaus_rtc_update(s);
344 return to_bcd(s->rtc.tm.tm_min);
345 case MENELAUS_RTC_HR:
346 menelaus_rtc_update(s);
347 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
348 return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
349 (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
350 else
351 return to_bcd(s->rtc.tm.tm_hour);
352 case MENELAUS_RTC_DAY:
353 menelaus_rtc_update(s);
354 return to_bcd(s->rtc.tm.tm_mday);
355 case MENELAUS_RTC_MON:
356 menelaus_rtc_update(s);
357 return to_bcd(s->rtc.tm.tm_mon + 1);
358 case MENELAUS_RTC_YR:
359 menelaus_rtc_update(s);
360 return to_bcd(s->rtc.tm.tm_year - 2000);
361 case MENELAUS_RTC_WKDAY:
362 menelaus_rtc_update(s);
363 return to_bcd(s->rtc.tm.tm_wday);
364 case MENELAUS_RTC_AL_SEC:
365 return to_bcd(s->rtc.alm.tm_sec);
366 case MENELAUS_RTC_AL_MIN:
367 return to_bcd(s->rtc.alm.tm_min);
368 case MENELAUS_RTC_AL_HR:
369 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
370 return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
371 (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
372 else
373 return to_bcd(s->rtc.alm.tm_hour);
374 case MENELAUS_RTC_AL_DAY:
375 return to_bcd(s->rtc.alm.tm_mday);
376 case MENELAUS_RTC_AL_MON:
377 return to_bcd(s->rtc.alm.tm_mon + 1);
378 case MENELAUS_RTC_AL_YR:
379 return to_bcd(s->rtc.alm.tm_year - 2000);
380 case MENELAUS_RTC_COMP_MSB:
381 return (s->rtc.comp >> 8) & 0xff;
382 case MENELAUS_RTC_COMP_LSB:
383 return (s->rtc.comp >> 0) & 0xff;
384
385 case MENELAUS_S1_PULL_EN:
386 return s->pull[0];
387 case MENELAUS_S1_PULL_DIR:
388 return s->pull[1];
389 case MENELAUS_S2_PULL_EN:
390 return s->pull[2];
391 case MENELAUS_S2_PULL_DIR:
392 return s->pull[3];
393
394 case MENELAUS_MCT_CTRL3: reg ++;
395 case MENELAUS_MCT_CTRL2: reg ++;
396 case MENELAUS_MCT_CTRL1:
397 return s->mmc_ctrl[reg];
398 case MENELAUS_MCT_PIN_ST:
399 /* TODO: return the real Card Detect */
400 return 0;
401 case MENELAUS_DEBOUNCE1:
402 return s->mmc_debounce;
403
404 default:
405#ifdef VERBOSE
a89f364a 406 printf("%s: unknown register %02x\n", __func__, addr);
7e7c5e4c
AZ		 407#endif
408 break;
409 }
410 return 0;
411}
412
413static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
414{
bc24a225 415 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 416 int line;
417 int reg = 0;
418 struct tm tm;
419
420 switch (addr) {
421 case MENELAUS_VCORE_CTRL1:
422 s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
423 break;
424 case MENELAUS_VCORE_CTRL2:
425 s->vcore[1] = value;
426 break;
427 case MENELAUS_VCORE_CTRL3:
428 s->vcore[2] = MIN(value & 0x1f, 0x12);
429 break;
430 case MENELAUS_VCORE_CTRL4:
431 s->vcore[3] = MIN(value & 0x1f, 0x12);
432 break;
433 case MENELAUS_VCORE_CTRL5:
434 s->vcore[4] = value & 3;
435 /* XXX
436 * auto set to 3 on M_Active, nRESWARM
437 * auto set to 0 on M_WaitOn, M_Backup
438 */
439 break;
440
441 case MENELAUS_DCDC_CTRL1:
442 s->dcdc[0] = value & 0x3f;
443 break;
444 case MENELAUS_DCDC_CTRL2:
445 s->dcdc[1] = value & 0x07;
446 /* XXX
447 * auto set to 3 on M_Active, nRESWARM
448 * auto set to 0 on M_WaitOn, M_Backup
449 */
450 break;
451 case MENELAUS_DCDC_CTRL3:
452 s->dcdc[2] = value & 0x07;
453 break;
454
455 case MENELAUS_LDO_CTRL1:
456 s->ldo[0] = value;
457 break;
458 case MENELAUS_LDO_CTRL2:
459 s->ldo[1] = value & 0x7f;
460 /* XXX
461 * auto set to 0x7e on M_WaitOn, M_Backup
462 */
463 break;
464 case MENELAUS_LDO_CTRL3:
465 s->ldo[2] = value & 3;
466 /* XXX
467 * auto set to 3 on M_Active, nRESWARM
468 * auto set to 0 on M_WaitOn, M_Backup
469 */
470 break;
471 case MENELAUS_LDO_CTRL4:
472 s->ldo[3] = value & 3;
473 /* XXX
474 * auto set to 3 on M_Active, nRESWARM
475 * auto set to 0 on M_WaitOn, M_Backup
476 */
477 break;
478 case MENELAUS_LDO_CTRL5:
479 s->ldo[4] = value & 3;
480 /* XXX
481 * auto set to 3 on M_Active, nRESWARM
482 * auto set to 0 on M_WaitOn, M_Backup
483 */
484 break;
485 case MENELAUS_LDO_CTRL6:
486 s->ldo[5] = value & 3;
487 break;
488 case MENELAUS_LDO_CTRL7:
489 s->ldo[6] = value & 3;
490 break;
491 case MENELAUS_LDO_CTRL8:
492 s->ldo[7] = value & 3;
493 break;
494
495 case MENELAUS_SLEEP_CTRL2: reg ++;
496 case MENELAUS_SLEEP_CTRL1:
497 s->sleep[reg] = value;
498 break;
499
500 case MENELAUS_DEVICE_OFF:
dd37dfa9
AF		 501 if (value & 1) {
502 menelaus_reset(I2C_SLAVE(s));
503 }
7e7c5e4c
AZ		 504 break;
505
506 case MENELAUS_OSC_CTRL:
507 s->osc = value & 7;
508 break;
509
510 case MENELAUS_DETECT_CTRL:
511 s->detect = value & 0x7f;
512 break;
513
514 case MENELAUS_INT_MASK1:
515 s->mask &= 0xf00;
516 s->mask |= value << 0;
517 menelaus_update(s);
518 break;
519 case MENELAUS_INT_MASK2:
520 s->mask &= 0x0ff;
521 s->mask |= value << 8;
522 menelaus_update(s);
523 break;
524
525 case MENELAUS_INT_ACK1:
526 s->status &= ~(((uint16_t) value) << 0);
527 menelaus_update(s);
528 break;
529 case MENELAUS_INT_ACK2:
530 s->status &= ~(((uint16_t) value) << 8);
531 menelaus_update(s);
532 break;
533
534 case MENELAUS_GPIO_CTRL:
d3356811
PB		 535 for (line = 0; line < 3; line ++) {
536 if (((s->dir ^ value) >> line) & 1) {
537 qemu_set_irq(s->out[line],
538 ((s->outputs & ~s->dir) >> line) & 1);
539 }
540 }
7e7c5e4c
AZ		 541 s->dir = value & 0x67;
542 break;
543 case MENELAUS_GPIO_OUT:
d3356811
PB		 544 for (line = 0; line < 3; line ++) {
545 if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
546 qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
547 }
548 }
7e7c5e4c
AZ		 549 s->outputs = value & 0x07;
550 break;
551
552 case MENELAUS_BBSMS:
553 s->bbsms = 0x0d;
554 break;
555
556 case MENELAUS_RTC_CTRL:
557 if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
558 if (value & 1)
559 menelaus_rtc_start(s);
560 else
561 menelaus_rtc_stop(s);
562 }
563 s->rtc.ctrl = value & 0x1f;
564 menelaus_alm_update(s);
565 break;
566 case MENELAUS_RTC_UPDATE:
567 menelaus_rtc_update(s);
568 memcpy(&tm, &s->rtc.tm, sizeof(tm));
569 switch (value & 0xf) {
570 case 0:
571 break;
572 case 1:
573 tm.tm_sec = s->rtc.new.tm_sec;
574 break;
575 case 2:
576 tm.tm_min = s->rtc.new.tm_min;
577 break;
578 case 3:
579 if (s->rtc.new.tm_hour > 23)
580 goto rtc_badness;
581 tm.tm_hour = s->rtc.new.tm_hour;
582 break;
583 case 4:
584 if (s->rtc.new.tm_mday < 1)
585 goto rtc_badness;
586 /* TODO check range */
587 tm.tm_mday = s->rtc.new.tm_mday;
588 break;
589 case 5:
590 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
591 goto rtc_badness;
592 tm.tm_mon = s->rtc.new.tm_mon;
593 break;
594 case 6:
595 tm.tm_year = s->rtc.new.tm_year;
596 break;
597 case 7:
598 /* TODO set .tm_mday instead */
599 tm.tm_wday = s->rtc.new.tm_wday;
600 break;
601 case 8:
602 if (s->rtc.new.tm_hour > 23)
603 goto rtc_badness;
604 if (s->rtc.new.tm_mday < 1)
605 goto rtc_badness;
606 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
607 goto rtc_badness;
608 tm.tm_sec = s->rtc.new.tm_sec;
609 tm.tm_min = s->rtc.new.tm_min;
610 tm.tm_hour = s->rtc.new.tm_hour;
611 tm.tm_mday = s->rtc.new.tm_mday;
612 tm.tm_mon = s->rtc.new.tm_mon;
613 tm.tm_year = s->rtc.new.tm_year;
614 break;
615 rtc_badness:
616 default:
617 fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
a89f364a 618 __func__, value);
7e7c5e4c
AZ		 619 s->status |= 1 << 10; /* RTCERR */
620 menelaus_update(s);
621 }
aec454d2 622 s->rtc.sec_offset = qemu_timedate_diff(&tm);
7e7c5e4c
AZ		 623 break;
624 case MENELAUS_RTC_SEC:
625 s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
626 break;
627 case MENELAUS_RTC_MIN:
628 s->rtc.tm.tm_min = from_bcd(value & 0x7f);
629 break;
630 case MENELAUS_RTC_HR:
631 s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
632 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
633 from_bcd(value & 0x3f);
634 break;
635 case MENELAUS_RTC_DAY:
636 s->rtc.tm.tm_mday = from_bcd(value);
637 break;
638 case MENELAUS_RTC_MON:
639 s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
640 break;
641 case MENELAUS_RTC_YR:
642 s->rtc.tm.tm_year = 2000 + from_bcd(value);
643 break;
644 case MENELAUS_RTC_WKDAY:
645 s->rtc.tm.tm_mday = from_bcd(value);
646 break;
647 case MENELAUS_RTC_AL_SEC:
648 s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
649 menelaus_alm_update(s);
650 break;
651 case MENELAUS_RTC_AL_MIN:
652 s->rtc.alm.tm_min = from_bcd(value & 0x7f);
653 menelaus_alm_update(s);
654 break;
655 case MENELAUS_RTC_AL_HR:
656 s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
657 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
658 from_bcd(value & 0x3f);
659 menelaus_alm_update(s);
660 break;
661 case MENELAUS_RTC_AL_DAY:
662 s->rtc.alm.tm_mday = from_bcd(value);
663 menelaus_alm_update(s);
664 break;
665 case MENELAUS_RTC_AL_MON:
666 s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
667 menelaus_alm_update(s);
668 break;
669 case MENELAUS_RTC_AL_YR:
670 s->rtc.alm.tm_year = 2000 + from_bcd(value);
671 menelaus_alm_update(s);
672 break;
673 case MENELAUS_RTC_COMP_MSB:
674 s->rtc.comp &= 0xff;
675 s->rtc.comp |= value << 8;
676 break;
677 case MENELAUS_RTC_COMP_LSB:
678 s->rtc.comp &= 0xff << 8;
679 s->rtc.comp |= value;
680 break;
681
682 case MENELAUS_S1_PULL_EN:
683 s->pull[0] = value;
684 break;
685 case MENELAUS_S1_PULL_DIR:
686 s->pull[1] = value & 0x1f;
687 break;
688 case MENELAUS_S2_PULL_EN:
689 s->pull[2] = value;
690 break;
691 case MENELAUS_S2_PULL_DIR:
692 s->pull[3] = value & 0x1f;
693 break;
694
695 case MENELAUS_MCT_CTRL1:
696 s->mmc_ctrl[0] = value & 0x7f;
697 break;
698 case MENELAUS_MCT_CTRL2:
699 s->mmc_ctrl[1] = value;
700 /* TODO update Card Detect interrupts */
701 break;
702 case MENELAUS_MCT_CTRL3:
703 s->mmc_ctrl[2] = value & 0xf;
704 break;
705 case MENELAUS_DEBOUNCE1:
706 s->mmc_debounce = value & 0x3f;
707 break;
708
709 default:
710#ifdef VERBOSE
a89f364a 711 printf("%s: unknown register %02x\n", __func__, addr);
7e7c5e4c
AZ		 712#endif
713 }
714}
715
d307c28c 716static int menelaus_event(I2CSlave *i2c, enum i2c_event event)
7e7c5e4c 717{
dd37dfa9 718 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 719
720 if (event == I2C_START_SEND)
721 s->firstbyte = 1;
d307c28c
CM		 722
723 return 0;
7e7c5e4c
AZ		 724}
725
9e07bdf8 726static int menelaus_tx(I2CSlave *i2c, uint8_t data)
7e7c5e4c 727{
dd37dfa9
AF		 728 MenelausState *s = TWL92230(i2c);
729
7e7c5e4c
AZ		 730 /* Interpret register address byte */
731 if (s->firstbyte) {
732 s->reg = data;
733 s->firstbyte = 0;
734 } else
735 menelaus_write(s, s->reg ++, data);
736
737 return 0;
738}
739
2ac4c5f4 740static uint8_t menelaus_rx(I2CSlave *i2c)
7e7c5e4c 741{
dd37dfa9 742 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 743
744 return menelaus_read(s, s->reg ++);
745}
746
f0495f56
JQ		 747/* Save restore 32 bit int as uint16_t
748 This is a Big hack, but it is how the old state did it.
749 Or we broke compatibility in the state, or we can't use struct tm
750 */
7e7c5e4c 751
2c21ee76 752static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
03fee66f 753 const VMStateField *field)
f0495f56
JQ		 754{
755 int *v = pv;
756 *v = qemu_get_be16(f);
757 return 0;
7e7c5e4c
AZ		 758}
759
2c21ee76 760static int put_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
03fee66f 761 const VMStateField *field, QJSON *vmdesc)
7e7c5e4c 762{
f0495f56
JQ		 763 int *v = pv;
764 qemu_put_be16(f, *v);
2c21ee76
JD		 765
766 return 0;
f0495f56 767}
7e7c5e4c 768
d05ac8fa 769static const VMStateInfo vmstate_hack_int32_as_uint16 = {
f0495f56
JQ		 770 .name = "int32_as_uint16",
771 .get = get_int32_as_uint16,
772 .put = put_int32_as_uint16,
773};
7e7c5e4c 774
f0495f56
JQ		 775#define VMSTATE_UINT16_HACK(_f, _s) \
776 VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
777
778
779static const VMStateDescription vmstate_menelaus_tm = {
780 .name = "menelaus_tm",
781 .version_id = 0,
782 .minimum_version_id = 0,
8f1e884b 783 .fields = (VMStateField[]) {
f0495f56
JQ		 784 VMSTATE_UINT16_HACK(tm_sec, struct tm),
785 VMSTATE_UINT16_HACK(tm_min, struct tm),
786 VMSTATE_UINT16_HACK(tm_hour, struct tm),
787 VMSTATE_UINT16_HACK(tm_mday, struct tm),
788 VMSTATE_UINT16_HACK(tm_min, struct tm),
789 VMSTATE_UINT16_HACK(tm_year, struct tm),
790 VMSTATE_END_OF_LIST()
791 }
792};
7e7c5e4c 793
44b1ff31 794static int menelaus_pre_save(void *opaque)
7e7c5e4c 795{
f0495f56
JQ		 796 MenelausState *s = opaque;
797 /* Should be <= 1000 */
884f17c2 798 s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
44b1ff31
DDAG		 799
800 return 0;
f0495f56 801}
7e7c5e4c 802
f0495f56
JQ		 803static int menelaus_post_load(void *opaque, int version_id)
804{
805 MenelausState *s = opaque;
7e7c5e4c
AZ		 806
807 if (s->rtc.ctrl & 1) /* RTC_EN */
808 menelaus_rtc_stop(s);
f0495f56
JQ		 809
810 s->rtc.next = s->rtc_next_vmstate;
811
7e7c5e4c
AZ		 812 menelaus_alm_update(s);
813 menelaus_update(s);
814 if (s->rtc.ctrl & 1) /* RTC_EN */
815 menelaus_rtc_start(s);
7e7c5e4c
AZ		 816 return 0;
817}
818
f0495f56
JQ		 819static const VMStateDescription vmstate_menelaus = {
820 .name = "menelaus",
821 .version_id = 0,
822 .minimum_version_id = 0,
f0495f56
JQ		 823 .pre_save = menelaus_pre_save,
824 .post_load = menelaus_post_load,
8f1e884b 825 .fields = (VMStateField[]) {
f0495f56
JQ		 826 VMSTATE_INT32(firstbyte, MenelausState),
827 VMSTATE_UINT8(reg, MenelausState),
828 VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
829 VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
830 VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
831 VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
832 VMSTATE_UINT8(osc, MenelausState),
833 VMSTATE_UINT8(detect, MenelausState),
834 VMSTATE_UINT16(mask, MenelausState),
835 VMSTATE_UINT16(status, MenelausState),
836 VMSTATE_UINT8(dir, MenelausState),
837 VMSTATE_UINT8(inputs, MenelausState),
838 VMSTATE_UINT8(outputs, MenelausState),
839 VMSTATE_UINT8(bbsms, MenelausState),
840 VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
841 VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
842 VMSTATE_UINT8(mmc_debounce, MenelausState),
843 VMSTATE_UINT8(rtc.ctrl, MenelausState),
844 VMSTATE_UINT16(rtc.comp, MenelausState),
845 VMSTATE_UINT16(rtc_next_vmstate, MenelausState),
846 VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
847 struct tm),
848 VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
849 struct tm),
850 VMSTATE_UINT8(pwrbtn_state, MenelausState),
dd37dfa9 851 VMSTATE_I2C_SLAVE(parent_obj, MenelausState),
f0495f56
JQ		 852 VMSTATE_END_OF_LIST()
853 }
854};
855
c8c9e103 856static void twl92230_realize(DeviceState *dev, Error **errp)
7e7c5e4c 857{
c8c9e103 858 MenelausState *s = TWL92230(dev);
7e7c5e4c 859
884f17c2 860 s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
d3356811 861 /* Three output pins plus one interrupt pin. */
dd37dfa9 862 qdev_init_gpio_out(dev, s->out, 4);
dd4427a6
PB		 863
864 /* Three input pins plus one power-button pin. */
dd37dfa9 865 qdev_init_gpio_in(dev, menelaus_gpio_set, 4);
7e7c5e4c 866
c8c9e103 867 menelaus_reset(I2C_SLAVE(dev));
7e7c5e4c
AZ		 868}
869
b5ea9327
AL		 870static void twl92230_class_init(ObjectClass *klass, void *data)
871{
39bffca2 872 DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327
AL		 873 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
874
c8c9e103 875 dc->realize = twl92230_realize;
b5ea9327
AL		 876 sc->event = menelaus_event;
877 sc->recv = menelaus_rx;
878 sc->send = menelaus_tx;
39bffca2 879 dc->vmsd = &vmstate_menelaus;
b5ea9327
AL		 880}
881
8c43a6f0 882static const TypeInfo twl92230_info = {
dd37dfa9 883 .name = TYPE_TWL92230,
39bffca2
AL		 884 .parent = TYPE_I2C_SLAVE,
885 .instance_size = sizeof(MenelausState),
886 .class_init = twl92230_class_init,
d3356811 887};
7e7c5e4c 888
83f7d43a 889static void twl92230_register_types(void)
7e7c5e4c 890{
39bffca2 891 type_register_static(&twl92230_info);
7e7c5e4c 892}
d3356811 893
83f7d43a 894type_init(twl92230_register_types)
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