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Include qemu/module.h where needed, drop it from qemu-common.h
[mirror_qemu.git] / hw / timer / twl92230.c
CommitLineData
7e7c5e4c
AZ		 1/*
2 * TI TWL92230C energy-management companion device for the OMAP24xx.
3 * Aka. Menelaus (N4200 MENELAUS1_V2.2)
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 20 */
21
282bc81e 22#include "qemu/osdep.h"
83c9f4ca 23#include "hw/hw.h"
1de7afc9 24#include "qemu/timer.h"
0d09e41a 25#include "hw/i2c/i2c.h"
9c17d615 26#include "sysemu/sysemu.h"
28ecbaee 27#include "ui/console.h"
f348b6d1 28#include "qemu/bcd.h"
0b8fa32f 29#include "qemu/module.h"
7e7c5e4c
AZ		 30
31#define VERBOSE 1
32
dd37dfa9
AF		 33#define TYPE_TWL92230 "twl92230"
34#define TWL92230(obj) OBJECT_CHECK(MenelausState, (obj), TYPE_TWL92230)
35
36typedef struct MenelausState {
37 I2CSlave parent_obj;
7e7c5e4c
AZ		 38
39 int firstbyte;
40 uint8_t reg;
41
42 uint8_t vcore[5];
43 uint8_t dcdc[3];
44 uint8_t ldo[8];
45 uint8_t sleep[2];
46 uint8_t osc;
47 uint8_t detect;
48 uint16_t mask;
49 uint16_t status;
50 uint8_t dir;
51 uint8_t inputs;
52 uint8_t outputs;
53 uint8_t bbsms;
54 uint8_t pull[4];
55 uint8_t mmc_ctrl[3];
56 uint8_t mmc_debounce;
57 struct {
58 uint8_t ctrl;
59 uint16_t comp;
b0f74c87 60 QEMUTimer *hz_tm;
7e7c5e4c
AZ		 61 int64_t next;
62 struct tm tm;
63 struct tm new;
64 struct tm alm;
aec454d2
AZ		 65 int sec_offset;
66 int alm_sec;
67 int next_comp;
7e7c5e4c 68 } rtc;
f0495f56 69 uint16_t rtc_next_vmstate;
d3356811 70 qemu_irq out[4];
b53d44e5 71 uint8_t pwrbtn_state;
bc24a225 72} MenelausState;
7e7c5e4c 73
bc24a225 74static inline void menelaus_update(MenelausState *s)
7e7c5e4c 75{
d3356811 76 qemu_set_irq(s->out[3], s->status & ~s->mask);
7e7c5e4c
AZ		 77}
78
bc24a225 79static inline void menelaus_rtc_start(MenelausState *s)
7e7c5e4c 80{
884f17c2 81 s->rtc.next += qemu_clock_get_ms(rtc_clock);
bc72ad67 82 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 83}
84
bc24a225 85static inline void menelaus_rtc_stop(MenelausState *s)
7e7c5e4c 86{
bc72ad67 87 timer_del(s->rtc.hz_tm);
884f17c2 88 s->rtc.next -= qemu_clock_get_ms(rtc_clock);
7e7c5e4c
AZ		 89 if (s->rtc.next < 1)
90 s->rtc.next = 1;
91}
92
bc24a225 93static void menelaus_rtc_update(MenelausState *s)
7e7c5e4c 94{
aec454d2 95 qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
7e7c5e4c
AZ		 96}
97
bc24a225 98static void menelaus_alm_update(MenelausState *s)
7e7c5e4c
AZ		 99{
100 if ((s->rtc.ctrl & 3) == 3)
aec454d2 101 s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
7e7c5e4c
AZ		 102}
103
104static void menelaus_rtc_hz(void *opaque)
105{
bc24a225 106 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 107
aec454d2
AZ		 108 s->rtc.next_comp --;
109 s->rtc.alm_sec --;
7e7c5e4c 110 s->rtc.next += 1000;
bc72ad67 111 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 112 if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
113 menelaus_rtc_update(s);
114 if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
115 s->status |= 1 << 8; /* RTCTMR */
116 else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
117 s->status |= 1 << 8; /* RTCTMR */
118 else if (!s->rtc.tm.tm_hour)
119 s->status |= 1 << 8; /* RTCTMR */
120 } else
121 s->status |= 1 << 8; /* RTCTMR */
122 if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
aec454d2 123 if (s->rtc.alm_sec == 0)
7e7c5e4c
AZ		 124 s->status |= 1 << 9; /* RTCALM */
125 /* TODO: wake-up */
126 }
aec454d2 127 if (s->rtc.next_comp <= 0) {
7e7c5e4c 128 s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
aec454d2 129 s->rtc.next_comp = 3600;
7e7c5e4c
AZ		 130 }
131 menelaus_update(s);
132}
133
9e07bdf8 134static void menelaus_reset(I2CSlave *i2c)
7e7c5e4c 135{
dd37dfa9
AF		 136 MenelausState *s = TWL92230(i2c);
137
7e7c5e4c
AZ		 138 s->reg = 0x00;
139
140 s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
141 s->vcore[1] = 0x05;
142 s->vcore[2] = 0x02;
143 s->vcore[3] = 0x0c;
144 s->vcore[4] = 0x03;
145 s->dcdc[0] = 0x33; /* Depends on wiring */
146 s->dcdc[1] = 0x03;
147 s->dcdc[2] = 0x00;
148 s->ldo[0] = 0x95;
149 s->ldo[1] = 0x7e;
150 s->ldo[2] = 0x00;
151 s->ldo[3] = 0x00; /* Depends on wiring */
152 s->ldo[4] = 0x03; /* Depends on wiring */
153 s->ldo[5] = 0x00;
154 s->ldo[6] = 0x00;
155 s->ldo[7] = 0x00;
156 s->sleep[0] = 0x00;
157 s->sleep[1] = 0x00;
158 s->osc = 0x01;
159 s->detect = 0x09;
160 s->mask = 0x0fff;
161 s->status = 0;
162 s->dir = 0x07;
163 s->outputs = 0x00;
164 s->bbsms = 0x00;
165 s->pull[0] = 0x00;
166 s->pull[1] = 0x00;
167 s->pull[2] = 0x00;
168 s->pull[3] = 0x00;
169 s->mmc_ctrl[0] = 0x03;
170 s->mmc_ctrl[1] = 0xc0;
171 s->mmc_ctrl[2] = 0x00;
172 s->mmc_debounce = 0x05;
173
7e7c5e4c
AZ		 174 if (s->rtc.ctrl & 1)
175 menelaus_rtc_stop(s);
176 s->rtc.ctrl = 0x00;
177 s->rtc.comp = 0x0000;
178 s->rtc.next = 1000;
aec454d2
AZ		 179 s->rtc.sec_offset = 0;
180 s->rtc.next_comp = 1800;
181 s->rtc.alm_sec = 1800;
7e7c5e4c
AZ		 182 s->rtc.alm.tm_sec = 0x00;
183 s->rtc.alm.tm_min = 0x00;
184 s->rtc.alm.tm_hour = 0x00;
185 s->rtc.alm.tm_mday = 0x01;
186 s->rtc.alm.tm_mon = 0x00;
187 s->rtc.alm.tm_year = 2004;
188 menelaus_update(s);
189}
190
7e7c5e4c
AZ		 191static void menelaus_gpio_set(void *opaque, int line, int level)
192{
bc24a225 193 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 194
dd4427a6
PB		 195 if (line < 3) {
196 /* No interrupt generated */
197 s->inputs &= ~(1 << line);
198 s->inputs |= level << line;
199 return;
200 }
7e7c5e4c
AZ		 201
202 if (!s->pwrbtn_state && level) {
203 s->status |= 1 << 11; /* PSHBTN */
204 menelaus_update(s);
205 }
206 s->pwrbtn_state = level;
207}
208
209#define MENELAUS_REV 0x01
210#define MENELAUS_VCORE_CTRL1 0x02
211#define MENELAUS_VCORE_CTRL2 0x03
212#define MENELAUS_VCORE_CTRL3 0x04
213#define MENELAUS_VCORE_CTRL4 0x05
214#define MENELAUS_VCORE_CTRL5 0x06
215#define MENELAUS_DCDC_CTRL1 0x07
216#define MENELAUS_DCDC_CTRL2 0x08
217#define MENELAUS_DCDC_CTRL3 0x09
218#define MENELAUS_LDO_CTRL1 0x0a
219#define MENELAUS_LDO_CTRL2 0x0b
220#define MENELAUS_LDO_CTRL3 0x0c
221#define MENELAUS_LDO_CTRL4 0x0d
222#define MENELAUS_LDO_CTRL5 0x0e
223#define MENELAUS_LDO_CTRL6 0x0f
224#define MENELAUS_LDO_CTRL7 0x10
225#define MENELAUS_LDO_CTRL8 0x11
226#define MENELAUS_SLEEP_CTRL1 0x12
227#define MENELAUS_SLEEP_CTRL2 0x13
228#define MENELAUS_DEVICE_OFF 0x14
229#define MENELAUS_OSC_CTRL 0x15
230#define MENELAUS_DETECT_CTRL 0x16
231#define MENELAUS_INT_MASK1 0x17
232#define MENELAUS_INT_MASK2 0x18
233#define MENELAUS_INT_STATUS1 0x19
234#define MENELAUS_INT_STATUS2 0x1a
235#define MENELAUS_INT_ACK1 0x1b
236#define MENELAUS_INT_ACK2 0x1c
237#define MENELAUS_GPIO_CTRL 0x1d
238#define MENELAUS_GPIO_IN 0x1e
239#define MENELAUS_GPIO_OUT 0x1f
240#define MENELAUS_BBSMS 0x20
241#define MENELAUS_RTC_CTRL 0x21
242#define MENELAUS_RTC_UPDATE 0x22
243#define MENELAUS_RTC_SEC 0x23
244#define MENELAUS_RTC_MIN 0x24
245#define MENELAUS_RTC_HR 0x25
246#define MENELAUS_RTC_DAY 0x26
247#define MENELAUS_RTC_MON 0x27
248#define MENELAUS_RTC_YR 0x28
249#define MENELAUS_RTC_WKDAY 0x29
250#define MENELAUS_RTC_AL_SEC 0x2a
251#define MENELAUS_RTC_AL_MIN 0x2b
252#define MENELAUS_RTC_AL_HR 0x2c
253#define MENELAUS_RTC_AL_DAY 0x2d
254#define MENELAUS_RTC_AL_MON 0x2e
255#define MENELAUS_RTC_AL_YR 0x2f
256#define MENELAUS_RTC_COMP_MSB 0x30
257#define MENELAUS_RTC_COMP_LSB 0x31
258#define MENELAUS_S1_PULL_EN 0x32
259#define MENELAUS_S1_PULL_DIR 0x33
260#define MENELAUS_S2_PULL_EN 0x34
261#define MENELAUS_S2_PULL_DIR 0x35
262#define MENELAUS_MCT_CTRL1 0x36
263#define MENELAUS_MCT_CTRL2 0x37
264#define MENELAUS_MCT_CTRL3 0x38
265#define MENELAUS_MCT_PIN_ST 0x39
266#define MENELAUS_DEBOUNCE1 0x3a
267
268static uint8_t menelaus_read(void *opaque, uint8_t addr)
269{
bc24a225 270 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 271 int reg = 0;
272
273 switch (addr) {
274 case MENELAUS_REV:
275 return 0x22;
276
277 case MENELAUS_VCORE_CTRL5: reg ++;
278 case MENELAUS_VCORE_CTRL4: reg ++;
279 case MENELAUS_VCORE_CTRL3: reg ++;
280 case MENELAUS_VCORE_CTRL2: reg ++;
281 case MENELAUS_VCORE_CTRL1:
282 return s->vcore[reg];
283
284 case MENELAUS_DCDC_CTRL3: reg ++;
285 case MENELAUS_DCDC_CTRL2: reg ++;
286 case MENELAUS_DCDC_CTRL1:
287 return s->dcdc[reg];
288
289 case MENELAUS_LDO_CTRL8: reg ++;
290 case MENELAUS_LDO_CTRL7: reg ++;
291 case MENELAUS_LDO_CTRL6: reg ++;
292 case MENELAUS_LDO_CTRL5: reg ++;
293 case MENELAUS_LDO_CTRL4: reg ++;
294 case MENELAUS_LDO_CTRL3: reg ++;
295 case MENELAUS_LDO_CTRL2: reg ++;
296 case MENELAUS_LDO_CTRL1:
297 return s->ldo[reg];
298
299 case MENELAUS_SLEEP_CTRL2: reg ++;
300 case MENELAUS_SLEEP_CTRL1:
301 return s->sleep[reg];
302
303 case MENELAUS_DEVICE_OFF:
304 return 0;
305
306 case MENELAUS_OSC_CTRL:
307 return s->osc | (1 << 7); /* CLK32K_GOOD */
308
309 case MENELAUS_DETECT_CTRL:
310 return s->detect;
311
312 case MENELAUS_INT_MASK1:
313 return (s->mask >> 0) & 0xff;
314 case MENELAUS_INT_MASK2:
315 return (s->mask >> 8) & 0xff;
316
317 case MENELAUS_INT_STATUS1:
318 return (s->status >> 0) & 0xff;
319 case MENELAUS_INT_STATUS2:
320 return (s->status >> 8) & 0xff;
321
322 case MENELAUS_INT_ACK1:
323 case MENELAUS_INT_ACK2:
324 return 0;
325
326 case MENELAUS_GPIO_CTRL:
327 return s->dir;
328 case MENELAUS_GPIO_IN:
329 return s->inputs | (~s->dir & s->outputs);
330 case MENELAUS_GPIO_OUT:
331 return s->outputs;
332
333 case MENELAUS_BBSMS:
334 return s->bbsms;
335
336 case MENELAUS_RTC_CTRL:
337 return s->rtc.ctrl;
338 case MENELAUS_RTC_UPDATE:
339 return 0x00;
340 case MENELAUS_RTC_SEC:
341 menelaus_rtc_update(s);
342 return to_bcd(s->rtc.tm.tm_sec);
343 case MENELAUS_RTC_MIN:
344 menelaus_rtc_update(s);
345 return to_bcd(s->rtc.tm.tm_min);
346 case MENELAUS_RTC_HR:
347 menelaus_rtc_update(s);
348 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
349 return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
350 (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
351 else
352 return to_bcd(s->rtc.tm.tm_hour);
353 case MENELAUS_RTC_DAY:
354 menelaus_rtc_update(s);
355 return to_bcd(s->rtc.tm.tm_mday);
356 case MENELAUS_RTC_MON:
357 menelaus_rtc_update(s);
358 return to_bcd(s->rtc.tm.tm_mon + 1);
359 case MENELAUS_RTC_YR:
360 menelaus_rtc_update(s);
361 return to_bcd(s->rtc.tm.tm_year - 2000);
362 case MENELAUS_RTC_WKDAY:
363 menelaus_rtc_update(s);
364 return to_bcd(s->rtc.tm.tm_wday);
365 case MENELAUS_RTC_AL_SEC:
366 return to_bcd(s->rtc.alm.tm_sec);
367 case MENELAUS_RTC_AL_MIN:
368 return to_bcd(s->rtc.alm.tm_min);
369 case MENELAUS_RTC_AL_HR:
370 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
371 return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
372 (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
373 else
374 return to_bcd(s->rtc.alm.tm_hour);
375 case MENELAUS_RTC_AL_DAY:
376 return to_bcd(s->rtc.alm.tm_mday);
377 case MENELAUS_RTC_AL_MON:
378 return to_bcd(s->rtc.alm.tm_mon + 1);
379 case MENELAUS_RTC_AL_YR:
380 return to_bcd(s->rtc.alm.tm_year - 2000);
381 case MENELAUS_RTC_COMP_MSB:
382 return (s->rtc.comp >> 8) & 0xff;
383 case MENELAUS_RTC_COMP_LSB:
384 return (s->rtc.comp >> 0) & 0xff;
385
386 case MENELAUS_S1_PULL_EN:
387 return s->pull[0];
388 case MENELAUS_S1_PULL_DIR:
389 return s->pull[1];
390 case MENELAUS_S2_PULL_EN:
391 return s->pull[2];
392 case MENELAUS_S2_PULL_DIR:
393 return s->pull[3];
394
395 case MENELAUS_MCT_CTRL3: reg ++;
396 case MENELAUS_MCT_CTRL2: reg ++;
397 case MENELAUS_MCT_CTRL1:
398 return s->mmc_ctrl[reg];
399 case MENELAUS_MCT_PIN_ST:
400 /* TODO: return the real Card Detect */
401 return 0;
402 case MENELAUS_DEBOUNCE1:
403 return s->mmc_debounce;
404
405 default:
406#ifdef VERBOSE
a89f364a 407 printf("%s: unknown register %02x\n", __func__, addr);
7e7c5e4c
AZ		 408#endif
409 break;
410 }
411 return 0;
412}
413
414static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
415{
bc24a225 416 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 417 int line;
418 int reg = 0;
419 struct tm tm;
420
421 switch (addr) {
422 case MENELAUS_VCORE_CTRL1:
423 s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
424 break;
425 case MENELAUS_VCORE_CTRL2:
426 s->vcore[1] = value;
427 break;
428 case MENELAUS_VCORE_CTRL3:
429 s->vcore[2] = MIN(value & 0x1f, 0x12);
430 break;
431 case MENELAUS_VCORE_CTRL4:
432 s->vcore[3] = MIN(value & 0x1f, 0x12);
433 break;
434 case MENELAUS_VCORE_CTRL5:
435 s->vcore[4] = value & 3;
436 /* XXX
437 * auto set to 3 on M_Active, nRESWARM
438 * auto set to 0 on M_WaitOn, M_Backup
439 */
440 break;
441
442 case MENELAUS_DCDC_CTRL1:
443 s->dcdc[0] = value & 0x3f;
444 break;
445 case MENELAUS_DCDC_CTRL2:
446 s->dcdc[1] = value & 0x07;
447 /* XXX
448 * auto set to 3 on M_Active, nRESWARM
449 * auto set to 0 on M_WaitOn, M_Backup
450 */
451 break;
452 case MENELAUS_DCDC_CTRL3:
453 s->dcdc[2] = value & 0x07;
454 break;
455
456 case MENELAUS_LDO_CTRL1:
457 s->ldo[0] = value;
458 break;
459 case MENELAUS_LDO_CTRL2:
460 s->ldo[1] = value & 0x7f;
461 /* XXX
462 * auto set to 0x7e on M_WaitOn, M_Backup
463 */
464 break;
465 case MENELAUS_LDO_CTRL3:
466 s->ldo[2] = value & 3;
467 /* XXX
468 * auto set to 3 on M_Active, nRESWARM
469 * auto set to 0 on M_WaitOn, M_Backup
470 */
471 break;
472 case MENELAUS_LDO_CTRL4:
473 s->ldo[3] = value & 3;
474 /* XXX
475 * auto set to 3 on M_Active, nRESWARM
476 * auto set to 0 on M_WaitOn, M_Backup
477 */
478 break;
479 case MENELAUS_LDO_CTRL5:
480 s->ldo[4] = value & 3;
481 /* XXX
482 * auto set to 3 on M_Active, nRESWARM
483 * auto set to 0 on M_WaitOn, M_Backup
484 */
485 break;
486 case MENELAUS_LDO_CTRL6:
487 s->ldo[5] = value & 3;
488 break;
489 case MENELAUS_LDO_CTRL7:
490 s->ldo[6] = value & 3;
491 break;
492 case MENELAUS_LDO_CTRL8:
493 s->ldo[7] = value & 3;
494 break;
495
496 case MENELAUS_SLEEP_CTRL2: reg ++;
497 case MENELAUS_SLEEP_CTRL1:
498 s->sleep[reg] = value;
499 break;
500
501 case MENELAUS_DEVICE_OFF:
dd37dfa9
AF		 502 if (value & 1) {
503 menelaus_reset(I2C_SLAVE(s));
504 }
7e7c5e4c
AZ		 505 break;
506
507 case MENELAUS_OSC_CTRL:
508 s->osc = value & 7;
509 break;
510
511 case MENELAUS_DETECT_CTRL:
512 s->detect = value & 0x7f;
513 break;
514
515 case MENELAUS_INT_MASK1:
516 s->mask &= 0xf00;
517 s->mask |= value << 0;
518 menelaus_update(s);
519 break;
520 case MENELAUS_INT_MASK2:
521 s->mask &= 0x0ff;
522 s->mask |= value << 8;
523 menelaus_update(s);
524 break;
525
526 case MENELAUS_INT_ACK1:
527 s->status &= ~(((uint16_t) value) << 0);
528 menelaus_update(s);
529 break;
530 case MENELAUS_INT_ACK2:
531 s->status &= ~(((uint16_t) value) << 8);
532 menelaus_update(s);
533 break;
534
535 case MENELAUS_GPIO_CTRL:
d3356811
PB		 536 for (line = 0; line < 3; line ++) {
537 if (((s->dir ^ value) >> line) & 1) {
538 qemu_set_irq(s->out[line],
539 ((s->outputs & ~s->dir) >> line) & 1);
540 }
541 }
7e7c5e4c
AZ		 542 s->dir = value & 0x67;
543 break;
544 case MENELAUS_GPIO_OUT:
d3356811
PB		 545 for (line = 0; line < 3; line ++) {
546 if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
547 qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
548 }
549 }
7e7c5e4c
AZ		 550 s->outputs = value & 0x07;
551 break;
552
553 case MENELAUS_BBSMS:
554 s->bbsms = 0x0d;
555 break;
556
557 case MENELAUS_RTC_CTRL:
558 if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
559 if (value & 1)
560 menelaus_rtc_start(s);
561 else
562 menelaus_rtc_stop(s);
563 }
564 s->rtc.ctrl = value & 0x1f;
565 menelaus_alm_update(s);
566 break;
567 case MENELAUS_RTC_UPDATE:
568 menelaus_rtc_update(s);
569 memcpy(&tm, &s->rtc.tm, sizeof(tm));
570 switch (value & 0xf) {
571 case 0:
572 break;
573 case 1:
574 tm.tm_sec = s->rtc.new.tm_sec;
575 break;
576 case 2:
577 tm.tm_min = s->rtc.new.tm_min;
578 break;
579 case 3:
580 if (s->rtc.new.tm_hour > 23)
581 goto rtc_badness;
582 tm.tm_hour = s->rtc.new.tm_hour;
583 break;
584 case 4:
585 if (s->rtc.new.tm_mday < 1)
586 goto rtc_badness;
587 /* TODO check range */
588 tm.tm_mday = s->rtc.new.tm_mday;
589 break;
590 case 5:
591 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
592 goto rtc_badness;
593 tm.tm_mon = s->rtc.new.tm_mon;
594 break;
595 case 6:
596 tm.tm_year = s->rtc.new.tm_year;
597 break;
598 case 7:
599 /* TODO set .tm_mday instead */
600 tm.tm_wday = s->rtc.new.tm_wday;
601 break;
602 case 8:
603 if (s->rtc.new.tm_hour > 23)
604 goto rtc_badness;
605 if (s->rtc.new.tm_mday < 1)
606 goto rtc_badness;
607 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
608 goto rtc_badness;
609 tm.tm_sec = s->rtc.new.tm_sec;
610 tm.tm_min = s->rtc.new.tm_min;
611 tm.tm_hour = s->rtc.new.tm_hour;
612 tm.tm_mday = s->rtc.new.tm_mday;
613 tm.tm_mon = s->rtc.new.tm_mon;
614 tm.tm_year = s->rtc.new.tm_year;
615 break;
616 rtc_badness:
617 default:
618 fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
a89f364a 619 __func__, value);
7e7c5e4c
AZ		 620 s->status |= 1 << 10; /* RTCERR */
621 menelaus_update(s);
622 }
aec454d2 623 s->rtc.sec_offset = qemu_timedate_diff(&tm);
7e7c5e4c
AZ		 624 break;
625 case MENELAUS_RTC_SEC:
626 s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
627 break;
628 case MENELAUS_RTC_MIN:
629 s->rtc.tm.tm_min = from_bcd(value & 0x7f);
630 break;
631 case MENELAUS_RTC_HR:
632 s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
633 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
634 from_bcd(value & 0x3f);
635 break;
636 case MENELAUS_RTC_DAY:
637 s->rtc.tm.tm_mday = from_bcd(value);
638 break;
639 case MENELAUS_RTC_MON:
640 s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
641 break;
642 case MENELAUS_RTC_YR:
643 s->rtc.tm.tm_year = 2000 + from_bcd(value);
644 break;
645 case MENELAUS_RTC_WKDAY:
646 s->rtc.tm.tm_mday = from_bcd(value);
647 break;
648 case MENELAUS_RTC_AL_SEC:
649 s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
650 menelaus_alm_update(s);
651 break;
652 case MENELAUS_RTC_AL_MIN:
653 s->rtc.alm.tm_min = from_bcd(value & 0x7f);
654 menelaus_alm_update(s);
655 break;
656 case MENELAUS_RTC_AL_HR:
657 s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
658 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
659 from_bcd(value & 0x3f);
660 menelaus_alm_update(s);
661 break;
662 case MENELAUS_RTC_AL_DAY:
663 s->rtc.alm.tm_mday = from_bcd(value);
664 menelaus_alm_update(s);
665 break;
666 case MENELAUS_RTC_AL_MON:
667 s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
668 menelaus_alm_update(s);
669 break;
670 case MENELAUS_RTC_AL_YR:
671 s->rtc.alm.tm_year = 2000 + from_bcd(value);
672 menelaus_alm_update(s);
673 break;
674 case MENELAUS_RTC_COMP_MSB:
675 s->rtc.comp &= 0xff;
676 s->rtc.comp |= value << 8;
677 break;
678 case MENELAUS_RTC_COMP_LSB:
679 s->rtc.comp &= 0xff << 8;
680 s->rtc.comp |= value;
681 break;
682
683 case MENELAUS_S1_PULL_EN:
684 s->pull[0] = value;
685 break;
686 case MENELAUS_S1_PULL_DIR:
687 s->pull[1] = value & 0x1f;
688 break;
689 case MENELAUS_S2_PULL_EN:
690 s->pull[2] = value;
691 break;
692 case MENELAUS_S2_PULL_DIR:
693 s->pull[3] = value & 0x1f;
694 break;
695
696 case MENELAUS_MCT_CTRL1:
697 s->mmc_ctrl[0] = value & 0x7f;
698 break;
699 case MENELAUS_MCT_CTRL2:
700 s->mmc_ctrl[1] = value;
701 /* TODO update Card Detect interrupts */
702 break;
703 case MENELAUS_MCT_CTRL3:
704 s->mmc_ctrl[2] = value & 0xf;
705 break;
706 case MENELAUS_DEBOUNCE1:
707 s->mmc_debounce = value & 0x3f;
708 break;
709
710 default:
711#ifdef VERBOSE
a89f364a 712 printf("%s: unknown register %02x\n", __func__, addr);
7e7c5e4c
AZ		 713#endif
714 }
715}
716
d307c28c 717static int menelaus_event(I2CSlave *i2c, enum i2c_event event)
7e7c5e4c 718{
dd37dfa9 719 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 720
721 if (event == I2C_START_SEND)
722 s->firstbyte = 1;
d307c28c
CM		 723
724 return 0;
7e7c5e4c
AZ		 725}
726
9e07bdf8 727static int menelaus_tx(I2CSlave *i2c, uint8_t data)
7e7c5e4c 728{
dd37dfa9
AF		 729 MenelausState *s = TWL92230(i2c);
730
7e7c5e4c
AZ		 731 /* Interpret register address byte */
732 if (s->firstbyte) {
733 s->reg = data;
734 s->firstbyte = 0;
735 } else
736 menelaus_write(s, s->reg ++, data);
737
738 return 0;
739}
740
2ac4c5f4 741static uint8_t menelaus_rx(I2CSlave *i2c)
7e7c5e4c 742{
dd37dfa9 743 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 744
745 return menelaus_read(s, s->reg ++);
746}
747
f0495f56
JQ		 748/* Save restore 32 bit int as uint16_t
749 This is a Big hack, but it is how the old state did it.
750 Or we broke compatibility in the state, or we can't use struct tm
751 */
7e7c5e4c 752
2c21ee76 753static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
03fee66f 754 const VMStateField *field)
f0495f56
JQ		 755{
756 int *v = pv;
757 *v = qemu_get_be16(f);
758 return 0;
7e7c5e4c
AZ		 759}
760
2c21ee76 761static int put_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
03fee66f 762 const VMStateField *field, QJSON *vmdesc)
7e7c5e4c 763{
f0495f56
JQ		 764 int *v = pv;
765 qemu_put_be16(f, *v);
2c21ee76
JD		 766
767 return 0;
f0495f56 768}
7e7c5e4c 769
d05ac8fa 770static const VMStateInfo vmstate_hack_int32_as_uint16 = {
f0495f56
JQ		 771 .name = "int32_as_uint16",
772 .get = get_int32_as_uint16,
773 .put = put_int32_as_uint16,
774};
7e7c5e4c 775
f0495f56
JQ		 776#define VMSTATE_UINT16_HACK(_f, _s) \
777 VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
778
779
780static const VMStateDescription vmstate_menelaus_tm = {
781 .name = "menelaus_tm",
782 .version_id = 0,
783 .minimum_version_id = 0,
8f1e884b 784 .fields = (VMStateField[]) {
f0495f56
JQ		 785 VMSTATE_UINT16_HACK(tm_sec, struct tm),
786 VMSTATE_UINT16_HACK(tm_min, struct tm),
787 VMSTATE_UINT16_HACK(tm_hour, struct tm),
788 VMSTATE_UINT16_HACK(tm_mday, struct tm),
789 VMSTATE_UINT16_HACK(tm_min, struct tm),
790 VMSTATE_UINT16_HACK(tm_year, struct tm),
791 VMSTATE_END_OF_LIST()
792 }
793};
7e7c5e4c 794
44b1ff31 795static int menelaus_pre_save(void *opaque)
7e7c5e4c 796{
f0495f56
JQ		 797 MenelausState *s = opaque;
798 /* Should be <= 1000 */
884f17c2 799 s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
44b1ff31
DDAG		 800
801 return 0;
f0495f56 802}
7e7c5e4c 803
f0495f56
JQ		 804static int menelaus_post_load(void *opaque, int version_id)
805{
806 MenelausState *s = opaque;
7e7c5e4c
AZ		 807
808 if (s->rtc.ctrl & 1) /* RTC_EN */
809 menelaus_rtc_stop(s);
f0495f56
JQ		 810
811 s->rtc.next = s->rtc_next_vmstate;
812
7e7c5e4c
AZ		 813 menelaus_alm_update(s);
814 menelaus_update(s);
815 if (s->rtc.ctrl & 1) /* RTC_EN */
816 menelaus_rtc_start(s);
7e7c5e4c
AZ		 817 return 0;
818}
819
f0495f56
JQ		 820static const VMStateDescription vmstate_menelaus = {
821 .name = "menelaus",
822 .version_id = 0,
823 .minimum_version_id = 0,
f0495f56
JQ		 824 .pre_save = menelaus_pre_save,
825 .post_load = menelaus_post_load,
8f1e884b 826 .fields = (VMStateField[]) {
f0495f56
JQ		 827 VMSTATE_INT32(firstbyte, MenelausState),
828 VMSTATE_UINT8(reg, MenelausState),
829 VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
830 VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
831 VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
832 VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
833 VMSTATE_UINT8(osc, MenelausState),
834 VMSTATE_UINT8(detect, MenelausState),
835 VMSTATE_UINT16(mask, MenelausState),
836 VMSTATE_UINT16(status, MenelausState),
837 VMSTATE_UINT8(dir, MenelausState),
838 VMSTATE_UINT8(inputs, MenelausState),
839 VMSTATE_UINT8(outputs, MenelausState),
840 VMSTATE_UINT8(bbsms, MenelausState),
841 VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
842 VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
843 VMSTATE_UINT8(mmc_debounce, MenelausState),
844 VMSTATE_UINT8(rtc.ctrl, MenelausState),
845 VMSTATE_UINT16(rtc.comp, MenelausState),
846 VMSTATE_UINT16(rtc_next_vmstate, MenelausState),
847 VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
848 struct tm),
849 VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
850 struct tm),
851 VMSTATE_UINT8(pwrbtn_state, MenelausState),
dd37dfa9 852 VMSTATE_I2C_SLAVE(parent_obj, MenelausState),
f0495f56
JQ		 853 VMSTATE_END_OF_LIST()
854 }
855};
856
c8c9e103 857static void twl92230_realize(DeviceState *dev, Error **errp)
7e7c5e4c 858{
c8c9e103 859 MenelausState *s = TWL92230(dev);
7e7c5e4c 860
884f17c2 861 s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
d3356811 862 /* Three output pins plus one interrupt pin. */
dd37dfa9 863 qdev_init_gpio_out(dev, s->out, 4);
dd4427a6
PB		 864
865 /* Three input pins plus one power-button pin. */
dd37dfa9 866 qdev_init_gpio_in(dev, menelaus_gpio_set, 4);
7e7c5e4c 867
c8c9e103 868 menelaus_reset(I2C_SLAVE(dev));
7e7c5e4c
AZ		 869}
870
b5ea9327
AL		 871static void twl92230_class_init(ObjectClass *klass, void *data)
872{
39bffca2 873 DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327
AL		 874 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
875
c8c9e103 876 dc->realize = twl92230_realize;
b5ea9327
AL		 877 sc->event = menelaus_event;
878 sc->recv = menelaus_rx;
879 sc->send = menelaus_tx;
39bffca2 880 dc->vmsd = &vmstate_menelaus;
b5ea9327
AL		 881}
882
8c43a6f0 883static const TypeInfo twl92230_info = {
dd37dfa9 884 .name = TYPE_TWL92230,
39bffca2
AL		 885 .parent = TYPE_I2C_SLAVE,
886 .instance_size = sizeof(MenelausState),
887 .class_init = twl92230_class_init,
d3356811 888};
7e7c5e4c 889
83f7d43a 890static void twl92230_register_types(void)
7e7c5e4c 891{
39bffca2 892 type_register_static(&twl92230_info);
7e7c5e4c 893}
d3356811 894
83f7d43a 895type_init(twl92230_register_types)
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