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7e7c5e4c
AZ		 1/*
2 * TI TWL92230C energy-management companion device for the OMAP24xx.
3 * Aka. Menelaus (N4200 MENELAUS1_V2.2)
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 20 */
21
282bc81e 22#include "qemu/osdep.h"
a8d25326 23#include "qemu-common.h"
83c9f4ca 24#include "hw/hw.h"
1de7afc9 25#include "qemu/timer.h"
0d09e41a 26#include "hw/i2c/i2c.h"
64552b6b 27#include "hw/irq.h"
ca77ee28 28#include "migration/qemu-file-types.h"
d6454270 29#include "migration/vmstate.h"
9c17d615 30#include "sysemu/sysemu.h"
28ecbaee 31#include "ui/console.h"
f348b6d1 32#include "qemu/bcd.h"
0b8fa32f 33#include "qemu/module.h"
7e7c5e4c
AZ		 34
35#define VERBOSE 1
36
dd37dfa9
AF		 37#define TYPE_TWL92230 "twl92230"
38#define TWL92230(obj) OBJECT_CHECK(MenelausState, (obj), TYPE_TWL92230)
39
40typedef struct MenelausState {
41 I2CSlave parent_obj;
7e7c5e4c
AZ		 42
43 int firstbyte;
44 uint8_t reg;
45
46 uint8_t vcore[5];
47 uint8_t dcdc[3];
48 uint8_t ldo[8];
49 uint8_t sleep[2];
50 uint8_t osc;
51 uint8_t detect;
52 uint16_t mask;
53 uint16_t status;
54 uint8_t dir;
55 uint8_t inputs;
56 uint8_t outputs;
57 uint8_t bbsms;
58 uint8_t pull[4];
59 uint8_t mmc_ctrl[3];
60 uint8_t mmc_debounce;
61 struct {
62 uint8_t ctrl;
63 uint16_t comp;
b0f74c87 64 QEMUTimer *hz_tm;
7e7c5e4c
AZ		 65 int64_t next;
66 struct tm tm;
67 struct tm new;
68 struct tm alm;
aec454d2
AZ		 69 int sec_offset;
70 int alm_sec;
71 int next_comp;
7e7c5e4c 72 } rtc;
f0495f56 73 uint16_t rtc_next_vmstate;
d3356811 74 qemu_irq out[4];
b53d44e5 75 uint8_t pwrbtn_state;
bc24a225 76} MenelausState;
7e7c5e4c 77
bc24a225 78static inline void menelaus_update(MenelausState *s)
7e7c5e4c 79{
d3356811 80 qemu_set_irq(s->out[3], s->status & ~s->mask);
7e7c5e4c
AZ		 81}
82
bc24a225 83static inline void menelaus_rtc_start(MenelausState *s)
7e7c5e4c 84{
884f17c2 85 s->rtc.next += qemu_clock_get_ms(rtc_clock);
bc72ad67 86 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 87}
88
bc24a225 89static inline void menelaus_rtc_stop(MenelausState *s)
7e7c5e4c 90{
bc72ad67 91 timer_del(s->rtc.hz_tm);
884f17c2 92 s->rtc.next -= qemu_clock_get_ms(rtc_clock);
7e7c5e4c
AZ		 93 if (s->rtc.next < 1)
94 s->rtc.next = 1;
95}
96
bc24a225 97static void menelaus_rtc_update(MenelausState *s)
7e7c5e4c 98{
aec454d2 99 qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset);
7e7c5e4c
AZ		 100}
101
bc24a225 102static void menelaus_alm_update(MenelausState *s)
7e7c5e4c
AZ		 103{
104 if ((s->rtc.ctrl & 3) == 3)
aec454d2 105 s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset;
7e7c5e4c
AZ		 106}
107
108static void menelaus_rtc_hz(void *opaque)
109{
bc24a225 110 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 111
aec454d2
AZ		 112 s->rtc.next_comp --;
113 s->rtc.alm_sec --;
7e7c5e4c 114 s->rtc.next += 1000;
bc72ad67 115 timer_mod(s->rtc.hz_tm, s->rtc.next);
7e7c5e4c
AZ		 116 if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */
117 menelaus_rtc_update(s);
118 if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec)
119 s->status |= 1 << 8; /* RTCTMR */
120 else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min)
121 s->status |= 1 << 8; /* RTCTMR */
122 else if (!s->rtc.tm.tm_hour)
123 s->status |= 1 << 8; /* RTCTMR */
124 } else
125 s->status |= 1 << 8; /* RTCTMR */
126 if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */
aec454d2 127 if (s->rtc.alm_sec == 0)
7e7c5e4c
AZ		 128 s->status |= 1 << 9; /* RTCALM */
129 /* TODO: wake-up */
130 }
aec454d2 131 if (s->rtc.next_comp <= 0) {
7e7c5e4c 132 s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000);
aec454d2 133 s->rtc.next_comp = 3600;
7e7c5e4c
AZ		 134 }
135 menelaus_update(s);
136}
137
9e07bdf8 138static void menelaus_reset(I2CSlave *i2c)
7e7c5e4c 139{
dd37dfa9
AF		 140 MenelausState *s = TWL92230(i2c);
141
7e7c5e4c
AZ		 142 s->reg = 0x00;
143
144 s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */
145 s->vcore[1] = 0x05;
146 s->vcore[2] = 0x02;
147 s->vcore[3] = 0x0c;
148 s->vcore[4] = 0x03;
149 s->dcdc[0] = 0x33; /* Depends on wiring */
150 s->dcdc[1] = 0x03;
151 s->dcdc[2] = 0x00;
152 s->ldo[0] = 0x95;
153 s->ldo[1] = 0x7e;
154 s->ldo[2] = 0x00;
155 s->ldo[3] = 0x00; /* Depends on wiring */
156 s->ldo[4] = 0x03; /* Depends on wiring */
157 s->ldo[5] = 0x00;
158 s->ldo[6] = 0x00;
159 s->ldo[7] = 0x00;
160 s->sleep[0] = 0x00;
161 s->sleep[1] = 0x00;
162 s->osc = 0x01;
163 s->detect = 0x09;
164 s->mask = 0x0fff;
165 s->status = 0;
166 s->dir = 0x07;
167 s->outputs = 0x00;
168 s->bbsms = 0x00;
169 s->pull[0] = 0x00;
170 s->pull[1] = 0x00;
171 s->pull[2] = 0x00;
172 s->pull[3] = 0x00;
173 s->mmc_ctrl[0] = 0x03;
174 s->mmc_ctrl[1] = 0xc0;
175 s->mmc_ctrl[2] = 0x00;
176 s->mmc_debounce = 0x05;
177
7e7c5e4c
AZ		 178 if (s->rtc.ctrl & 1)
179 menelaus_rtc_stop(s);
180 s->rtc.ctrl = 0x00;
181 s->rtc.comp = 0x0000;
182 s->rtc.next = 1000;
aec454d2
AZ		 183 s->rtc.sec_offset = 0;
184 s->rtc.next_comp = 1800;
185 s->rtc.alm_sec = 1800;
7e7c5e4c
AZ		 186 s->rtc.alm.tm_sec = 0x00;
187 s->rtc.alm.tm_min = 0x00;
188 s->rtc.alm.tm_hour = 0x00;
189 s->rtc.alm.tm_mday = 0x01;
190 s->rtc.alm.tm_mon = 0x00;
191 s->rtc.alm.tm_year = 2004;
192 menelaus_update(s);
193}
194
7e7c5e4c
AZ		 195static void menelaus_gpio_set(void *opaque, int line, int level)
196{
bc24a225 197 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c 198
dd4427a6
PB		 199 if (line < 3) {
200 /* No interrupt generated */
201 s->inputs &= ~(1 << line);
202 s->inputs |= level << line;
203 return;
204 }
7e7c5e4c
AZ		 205
206 if (!s->pwrbtn_state && level) {
207 s->status |= 1 << 11; /* PSHBTN */
208 menelaus_update(s);
209 }
210 s->pwrbtn_state = level;
211}
212
213#define MENELAUS_REV 0x01
214#define MENELAUS_VCORE_CTRL1 0x02
215#define MENELAUS_VCORE_CTRL2 0x03
216#define MENELAUS_VCORE_CTRL3 0x04
217#define MENELAUS_VCORE_CTRL4 0x05
218#define MENELAUS_VCORE_CTRL5 0x06
219#define MENELAUS_DCDC_CTRL1 0x07
220#define MENELAUS_DCDC_CTRL2 0x08
221#define MENELAUS_DCDC_CTRL3 0x09
222#define MENELAUS_LDO_CTRL1 0x0a
223#define MENELAUS_LDO_CTRL2 0x0b
224#define MENELAUS_LDO_CTRL3 0x0c
225#define MENELAUS_LDO_CTRL4 0x0d
226#define MENELAUS_LDO_CTRL5 0x0e
227#define MENELAUS_LDO_CTRL6 0x0f
228#define MENELAUS_LDO_CTRL7 0x10
229#define MENELAUS_LDO_CTRL8 0x11
230#define MENELAUS_SLEEP_CTRL1 0x12
231#define MENELAUS_SLEEP_CTRL2 0x13
232#define MENELAUS_DEVICE_OFF 0x14
233#define MENELAUS_OSC_CTRL 0x15
234#define MENELAUS_DETECT_CTRL 0x16
235#define MENELAUS_INT_MASK1 0x17
236#define MENELAUS_INT_MASK2 0x18
237#define MENELAUS_INT_STATUS1 0x19
238#define MENELAUS_INT_STATUS2 0x1a
239#define MENELAUS_INT_ACK1 0x1b
240#define MENELAUS_INT_ACK2 0x1c
241#define MENELAUS_GPIO_CTRL 0x1d
242#define MENELAUS_GPIO_IN 0x1e
243#define MENELAUS_GPIO_OUT 0x1f
244#define MENELAUS_BBSMS 0x20
245#define MENELAUS_RTC_CTRL 0x21
246#define MENELAUS_RTC_UPDATE 0x22
247#define MENELAUS_RTC_SEC 0x23
248#define MENELAUS_RTC_MIN 0x24
249#define MENELAUS_RTC_HR 0x25
250#define MENELAUS_RTC_DAY 0x26
251#define MENELAUS_RTC_MON 0x27
252#define MENELAUS_RTC_YR 0x28
253#define MENELAUS_RTC_WKDAY 0x29
254#define MENELAUS_RTC_AL_SEC 0x2a
255#define MENELAUS_RTC_AL_MIN 0x2b
256#define MENELAUS_RTC_AL_HR 0x2c
257#define MENELAUS_RTC_AL_DAY 0x2d
258#define MENELAUS_RTC_AL_MON 0x2e
259#define MENELAUS_RTC_AL_YR 0x2f
260#define MENELAUS_RTC_COMP_MSB 0x30
261#define MENELAUS_RTC_COMP_LSB 0x31
262#define MENELAUS_S1_PULL_EN 0x32
263#define MENELAUS_S1_PULL_DIR 0x33
264#define MENELAUS_S2_PULL_EN 0x34
265#define MENELAUS_S2_PULL_DIR 0x35
266#define MENELAUS_MCT_CTRL1 0x36
267#define MENELAUS_MCT_CTRL2 0x37
268#define MENELAUS_MCT_CTRL3 0x38
269#define MENELAUS_MCT_PIN_ST 0x39
270#define MENELAUS_DEBOUNCE1 0x3a
271
272static uint8_t menelaus_read(void *opaque, uint8_t addr)
273{
bc24a225 274 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 275 int reg = 0;
276
277 switch (addr) {
278 case MENELAUS_REV:
279 return 0x22;
280
281 case MENELAUS_VCORE_CTRL5: reg ++;
282 case MENELAUS_VCORE_CTRL4: reg ++;
283 case MENELAUS_VCORE_CTRL3: reg ++;
284 case MENELAUS_VCORE_CTRL2: reg ++;
285 case MENELAUS_VCORE_CTRL1:
286 return s->vcore[reg];
287
288 case MENELAUS_DCDC_CTRL3: reg ++;
289 case MENELAUS_DCDC_CTRL2: reg ++;
290 case MENELAUS_DCDC_CTRL1:
291 return s->dcdc[reg];
292
293 case MENELAUS_LDO_CTRL8: reg ++;
294 case MENELAUS_LDO_CTRL7: reg ++;
295 case MENELAUS_LDO_CTRL6: reg ++;
296 case MENELAUS_LDO_CTRL5: reg ++;
297 case MENELAUS_LDO_CTRL4: reg ++;
298 case MENELAUS_LDO_CTRL3: reg ++;
299 case MENELAUS_LDO_CTRL2: reg ++;
300 case MENELAUS_LDO_CTRL1:
301 return s->ldo[reg];
302
303 case MENELAUS_SLEEP_CTRL2: reg ++;
304 case MENELAUS_SLEEP_CTRL1:
305 return s->sleep[reg];
306
307 case MENELAUS_DEVICE_OFF:
308 return 0;
309
310 case MENELAUS_OSC_CTRL:
311 return s->osc | (1 << 7); /* CLK32K_GOOD */
312
313 case MENELAUS_DETECT_CTRL:
314 return s->detect;
315
316 case MENELAUS_INT_MASK1:
317 return (s->mask >> 0) & 0xff;
318 case MENELAUS_INT_MASK2:
319 return (s->mask >> 8) & 0xff;
320
321 case MENELAUS_INT_STATUS1:
322 return (s->status >> 0) & 0xff;
323 case MENELAUS_INT_STATUS2:
324 return (s->status >> 8) & 0xff;
325
326 case MENELAUS_INT_ACK1:
327 case MENELAUS_INT_ACK2:
328 return 0;
329
330 case MENELAUS_GPIO_CTRL:
331 return s->dir;
332 case MENELAUS_GPIO_IN:
333 return s->inputs | (~s->dir & s->outputs);
334 case MENELAUS_GPIO_OUT:
335 return s->outputs;
336
337 case MENELAUS_BBSMS:
338 return s->bbsms;
339
340 case MENELAUS_RTC_CTRL:
341 return s->rtc.ctrl;
342 case MENELAUS_RTC_UPDATE:
343 return 0x00;
344 case MENELAUS_RTC_SEC:
345 menelaus_rtc_update(s);
346 return to_bcd(s->rtc.tm.tm_sec);
347 case MENELAUS_RTC_MIN:
348 menelaus_rtc_update(s);
349 return to_bcd(s->rtc.tm.tm_min);
350 case MENELAUS_RTC_HR:
351 menelaus_rtc_update(s);
352 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
353 return to_bcd((s->rtc.tm.tm_hour % 12) + 1) |
354 (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */
355 else
356 return to_bcd(s->rtc.tm.tm_hour);
357 case MENELAUS_RTC_DAY:
358 menelaus_rtc_update(s);
359 return to_bcd(s->rtc.tm.tm_mday);
360 case MENELAUS_RTC_MON:
361 menelaus_rtc_update(s);
362 return to_bcd(s->rtc.tm.tm_mon + 1);
363 case MENELAUS_RTC_YR:
364 menelaus_rtc_update(s);
365 return to_bcd(s->rtc.tm.tm_year - 2000);
366 case MENELAUS_RTC_WKDAY:
367 menelaus_rtc_update(s);
368 return to_bcd(s->rtc.tm.tm_wday);
369 case MENELAUS_RTC_AL_SEC:
370 return to_bcd(s->rtc.alm.tm_sec);
371 case MENELAUS_RTC_AL_MIN:
372 return to_bcd(s->rtc.alm.tm_min);
373 case MENELAUS_RTC_AL_HR:
374 if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */
375 return to_bcd((s->rtc.alm.tm_hour % 12) + 1) |
376 (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */
377 else
378 return to_bcd(s->rtc.alm.tm_hour);
379 case MENELAUS_RTC_AL_DAY:
380 return to_bcd(s->rtc.alm.tm_mday);
381 case MENELAUS_RTC_AL_MON:
382 return to_bcd(s->rtc.alm.tm_mon + 1);
383 case MENELAUS_RTC_AL_YR:
384 return to_bcd(s->rtc.alm.tm_year - 2000);
385 case MENELAUS_RTC_COMP_MSB:
386 return (s->rtc.comp >> 8) & 0xff;
387 case MENELAUS_RTC_COMP_LSB:
388 return (s->rtc.comp >> 0) & 0xff;
389
390 case MENELAUS_S1_PULL_EN:
391 return s->pull[0];
392 case MENELAUS_S1_PULL_DIR:
393 return s->pull[1];
394 case MENELAUS_S2_PULL_EN:
395 return s->pull[2];
396 case MENELAUS_S2_PULL_DIR:
397 return s->pull[3];
398
399 case MENELAUS_MCT_CTRL3: reg ++;
400 case MENELAUS_MCT_CTRL2: reg ++;
401 case MENELAUS_MCT_CTRL1:
402 return s->mmc_ctrl[reg];
403 case MENELAUS_MCT_PIN_ST:
404 /* TODO: return the real Card Detect */
405 return 0;
406 case MENELAUS_DEBOUNCE1:
407 return s->mmc_debounce;
408
409 default:
410#ifdef VERBOSE
a89f364a 411 printf("%s: unknown register %02x\n", __func__, addr);
7e7c5e4c
AZ		 412#endif
413 break;
414 }
415 return 0;
416}
417
418static void menelaus_write(void *opaque, uint8_t addr, uint8_t value)
419{
bc24a225 420 MenelausState *s = (MenelausState *) opaque;
7e7c5e4c
AZ		 421 int line;
422 int reg = 0;
423 struct tm tm;
424
425 switch (addr) {
426 case MENELAUS_VCORE_CTRL1:
427 s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12);
428 break;
429 case MENELAUS_VCORE_CTRL2:
430 s->vcore[1] = value;
431 break;
432 case MENELAUS_VCORE_CTRL3:
433 s->vcore[2] = MIN(value & 0x1f, 0x12);
434 break;
435 case MENELAUS_VCORE_CTRL4:
436 s->vcore[3] = MIN(value & 0x1f, 0x12);
437 break;
438 case MENELAUS_VCORE_CTRL5:
439 s->vcore[4] = value & 3;
440 /* XXX
441 * auto set to 3 on M_Active, nRESWARM
442 * auto set to 0 on M_WaitOn, M_Backup
443 */
444 break;
445
446 case MENELAUS_DCDC_CTRL1:
447 s->dcdc[0] = value & 0x3f;
448 break;
449 case MENELAUS_DCDC_CTRL2:
450 s->dcdc[1] = value & 0x07;
451 /* XXX
452 * auto set to 3 on M_Active, nRESWARM
453 * auto set to 0 on M_WaitOn, M_Backup
454 */
455 break;
456 case MENELAUS_DCDC_CTRL3:
457 s->dcdc[2] = value & 0x07;
458 break;
459
460 case MENELAUS_LDO_CTRL1:
461 s->ldo[0] = value;
462 break;
463 case MENELAUS_LDO_CTRL2:
464 s->ldo[1] = value & 0x7f;
465 /* XXX
466 * auto set to 0x7e on M_WaitOn, M_Backup
467 */
468 break;
469 case MENELAUS_LDO_CTRL3:
470 s->ldo[2] = value & 3;
471 /* XXX
472 * auto set to 3 on M_Active, nRESWARM
473 * auto set to 0 on M_WaitOn, M_Backup
474 */
475 break;
476 case MENELAUS_LDO_CTRL4:
477 s->ldo[3] = value & 3;
478 /* XXX
479 * auto set to 3 on M_Active, nRESWARM
480 * auto set to 0 on M_WaitOn, M_Backup
481 */
482 break;
483 case MENELAUS_LDO_CTRL5:
484 s->ldo[4] = value & 3;
485 /* XXX
486 * auto set to 3 on M_Active, nRESWARM
487 * auto set to 0 on M_WaitOn, M_Backup
488 */
489 break;
490 case MENELAUS_LDO_CTRL6:
491 s->ldo[5] = value & 3;
492 break;
493 case MENELAUS_LDO_CTRL7:
494 s->ldo[6] = value & 3;
495 break;
496 case MENELAUS_LDO_CTRL8:
497 s->ldo[7] = value & 3;
498 break;
499
500 case MENELAUS_SLEEP_CTRL2: reg ++;
501 case MENELAUS_SLEEP_CTRL1:
502 s->sleep[reg] = value;
503 break;
504
505 case MENELAUS_DEVICE_OFF:
dd37dfa9
AF		 506 if (value & 1) {
507 menelaus_reset(I2C_SLAVE(s));
508 }
7e7c5e4c
AZ		 509 break;
510
511 case MENELAUS_OSC_CTRL:
512 s->osc = value & 7;
513 break;
514
515 case MENELAUS_DETECT_CTRL:
516 s->detect = value & 0x7f;
517 break;
518
519 case MENELAUS_INT_MASK1:
520 s->mask &= 0xf00;
521 s->mask |= value << 0;
522 menelaus_update(s);
523 break;
524 case MENELAUS_INT_MASK2:
525 s->mask &= 0x0ff;
526 s->mask |= value << 8;
527 menelaus_update(s);
528 break;
529
530 case MENELAUS_INT_ACK1:
531 s->status &= ~(((uint16_t) value) << 0);
532 menelaus_update(s);
533 break;
534 case MENELAUS_INT_ACK2:
535 s->status &= ~(((uint16_t) value) << 8);
536 menelaus_update(s);
537 break;
538
539 case MENELAUS_GPIO_CTRL:
d3356811
PB		 540 for (line = 0; line < 3; line ++) {
541 if (((s->dir ^ value) >> line) & 1) {
542 qemu_set_irq(s->out[line],
543 ((s->outputs & ~s->dir) >> line) & 1);
544 }
545 }
7e7c5e4c
AZ		 546 s->dir = value & 0x67;
547 break;
548 case MENELAUS_GPIO_OUT:
d3356811
PB		 549 for (line = 0; line < 3; line ++) {
550 if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) {
551 qemu_set_irq(s->out[line], (s->outputs >> line) & 1);
552 }
553 }
7e7c5e4c
AZ		 554 s->outputs = value & 0x07;
555 break;
556
557 case MENELAUS_BBSMS:
558 s->bbsms = 0x0d;
559 break;
560
561 case MENELAUS_RTC_CTRL:
562 if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */
563 if (value & 1)
564 menelaus_rtc_start(s);
565 else
566 menelaus_rtc_stop(s);
567 }
568 s->rtc.ctrl = value & 0x1f;
569 menelaus_alm_update(s);
570 break;
571 case MENELAUS_RTC_UPDATE:
572 menelaus_rtc_update(s);
573 memcpy(&tm, &s->rtc.tm, sizeof(tm));
574 switch (value & 0xf) {
575 case 0:
576 break;
577 case 1:
578 tm.tm_sec = s->rtc.new.tm_sec;
579 break;
580 case 2:
581 tm.tm_min = s->rtc.new.tm_min;
582 break;
583 case 3:
584 if (s->rtc.new.tm_hour > 23)
585 goto rtc_badness;
586 tm.tm_hour = s->rtc.new.tm_hour;
587 break;
588 case 4:
589 if (s->rtc.new.tm_mday < 1)
590 goto rtc_badness;
591 /* TODO check range */
592 tm.tm_mday = s->rtc.new.tm_mday;
593 break;
594 case 5:
595 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
596 goto rtc_badness;
597 tm.tm_mon = s->rtc.new.tm_mon;
598 break;
599 case 6:
600 tm.tm_year = s->rtc.new.tm_year;
601 break;
602 case 7:
603 /* TODO set .tm_mday instead */
604 tm.tm_wday = s->rtc.new.tm_wday;
605 break;
606 case 8:
607 if (s->rtc.new.tm_hour > 23)
608 goto rtc_badness;
609 if (s->rtc.new.tm_mday < 1)
610 goto rtc_badness;
611 if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11)
612 goto rtc_badness;
613 tm.tm_sec = s->rtc.new.tm_sec;
614 tm.tm_min = s->rtc.new.tm_min;
615 tm.tm_hour = s->rtc.new.tm_hour;
616 tm.tm_mday = s->rtc.new.tm_mday;
617 tm.tm_mon = s->rtc.new.tm_mon;
618 tm.tm_year = s->rtc.new.tm_year;
619 break;
620 rtc_badness:
621 default:
622 fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
a89f364a 623 __func__, value);
7e7c5e4c
AZ		 624 s->status |= 1 << 10; /* RTCERR */
625 menelaus_update(s);
626 }
aec454d2 627 s->rtc.sec_offset = qemu_timedate_diff(&tm);
7e7c5e4c
AZ		 628 break;
629 case MENELAUS_RTC_SEC:
630 s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
631 break;
632 case MENELAUS_RTC_MIN:
633 s->rtc.tm.tm_min = from_bcd(value & 0x7f);
634 break;
635 case MENELAUS_RTC_HR:
636 s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
637 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
638 from_bcd(value & 0x3f);
639 break;
640 case MENELAUS_RTC_DAY:
641 s->rtc.tm.tm_mday = from_bcd(value);
642 break;
643 case MENELAUS_RTC_MON:
644 s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1;
645 break;
646 case MENELAUS_RTC_YR:
647 s->rtc.tm.tm_year = 2000 + from_bcd(value);
648 break;
649 case MENELAUS_RTC_WKDAY:
650 s->rtc.tm.tm_mday = from_bcd(value);
651 break;
652 case MENELAUS_RTC_AL_SEC:
653 s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
654 menelaus_alm_update(s);
655 break;
656 case MENELAUS_RTC_AL_MIN:
657 s->rtc.alm.tm_min = from_bcd(value & 0x7f);
658 menelaus_alm_update(s);
659 break;
660 case MENELAUS_RTC_AL_HR:
661 s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */
662 MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) :
663 from_bcd(value & 0x3f);
664 menelaus_alm_update(s);
665 break;
666 case MENELAUS_RTC_AL_DAY:
667 s->rtc.alm.tm_mday = from_bcd(value);
668 menelaus_alm_update(s);
669 break;
670 case MENELAUS_RTC_AL_MON:
671 s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1;
672 menelaus_alm_update(s);
673 break;
674 case MENELAUS_RTC_AL_YR:
675 s->rtc.alm.tm_year = 2000 + from_bcd(value);
676 menelaus_alm_update(s);
677 break;
678 case MENELAUS_RTC_COMP_MSB:
679 s->rtc.comp &= 0xff;
680 s->rtc.comp |= value << 8;
681 break;
682 case MENELAUS_RTC_COMP_LSB:
683 s->rtc.comp &= 0xff << 8;
684 s->rtc.comp |= value;
685 break;
686
687 case MENELAUS_S1_PULL_EN:
688 s->pull[0] = value;
689 break;
690 case MENELAUS_S1_PULL_DIR:
691 s->pull[1] = value & 0x1f;
692 break;
693 case MENELAUS_S2_PULL_EN:
694 s->pull[2] = value;
695 break;
696 case MENELAUS_S2_PULL_DIR:
697 s->pull[3] = value & 0x1f;
698 break;
699
700 case MENELAUS_MCT_CTRL1:
701 s->mmc_ctrl[0] = value & 0x7f;
702 break;
703 case MENELAUS_MCT_CTRL2:
704 s->mmc_ctrl[1] = value;
705 /* TODO update Card Detect interrupts */
706 break;
707 case MENELAUS_MCT_CTRL3:
708 s->mmc_ctrl[2] = value & 0xf;
709 break;
710 case MENELAUS_DEBOUNCE1:
711 s->mmc_debounce = value & 0x3f;
712 break;
713
714 default:
715#ifdef VERBOSE
a89f364a 716 printf("%s: unknown register %02x\n", __func__, addr);
7e7c5e4c
AZ		 717#endif
718 }
719}
720
d307c28c 721static int menelaus_event(I2CSlave *i2c, enum i2c_event event)
7e7c5e4c 722{
dd37dfa9 723 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 724
725 if (event == I2C_START_SEND)
726 s->firstbyte = 1;
d307c28c
CM		 727
728 return 0;
7e7c5e4c
AZ		 729}
730
9e07bdf8 731static int menelaus_tx(I2CSlave *i2c, uint8_t data)
7e7c5e4c 732{
dd37dfa9
AF		 733 MenelausState *s = TWL92230(i2c);
734
7e7c5e4c
AZ		 735 /* Interpret register address byte */
736 if (s->firstbyte) {
737 s->reg = data;
738 s->firstbyte = 0;
739 } else
740 menelaus_write(s, s->reg ++, data);
741
742 return 0;
743}
744
2ac4c5f4 745static uint8_t menelaus_rx(I2CSlave *i2c)
7e7c5e4c 746{
dd37dfa9 747 MenelausState *s = TWL92230(i2c);
7e7c5e4c
AZ		 748
749 return menelaus_read(s, s->reg ++);
750}
751
f0495f56
JQ		 752/* Save restore 32 bit int as uint16_t
753 This is a Big hack, but it is how the old state did it.
754 Or we broke compatibility in the state, or we can't use struct tm
755 */
7e7c5e4c 756
2c21ee76 757static int get_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
03fee66f 758 const VMStateField *field)
f0495f56
JQ		 759{
760 int *v = pv;
761 *v = qemu_get_be16(f);
762 return 0;
7e7c5e4c
AZ		 763}
764
2c21ee76 765static int put_int32_as_uint16(QEMUFile *f, void *pv, size_t size,
03fee66f 766 const VMStateField *field, QJSON *vmdesc)
7e7c5e4c 767{
f0495f56
JQ		 768 int *v = pv;
769 qemu_put_be16(f, *v);
2c21ee76
JD		 770
771 return 0;
f0495f56 772}
7e7c5e4c 773
d05ac8fa 774static const VMStateInfo vmstate_hack_int32_as_uint16 = {
f0495f56
JQ		 775 .name = "int32_as_uint16",
776 .get = get_int32_as_uint16,
777 .put = put_int32_as_uint16,
778};
7e7c5e4c 779
f0495f56
JQ		 780#define VMSTATE_UINT16_HACK(_f, _s) \
781 VMSTATE_SINGLE(_f, _s, 0, vmstate_hack_int32_as_uint16, int32_t)
782
783
784static const VMStateDescription vmstate_menelaus_tm = {
785 .name = "menelaus_tm",
786 .version_id = 0,
787 .minimum_version_id = 0,
8f1e884b 788 .fields = (VMStateField[]) {
f0495f56
JQ		 789 VMSTATE_UINT16_HACK(tm_sec, struct tm),
790 VMSTATE_UINT16_HACK(tm_min, struct tm),
791 VMSTATE_UINT16_HACK(tm_hour, struct tm),
792 VMSTATE_UINT16_HACK(tm_mday, struct tm),
793 VMSTATE_UINT16_HACK(tm_min, struct tm),
794 VMSTATE_UINT16_HACK(tm_year, struct tm),
795 VMSTATE_END_OF_LIST()
796 }
797};
7e7c5e4c 798
44b1ff31 799static int menelaus_pre_save(void *opaque)
7e7c5e4c 800{
f0495f56
JQ		 801 MenelausState *s = opaque;
802 /* Should be <= 1000 */
884f17c2 803 s->rtc_next_vmstate = s->rtc.next - qemu_clock_get_ms(rtc_clock);
44b1ff31
DDAG		 804
805 return 0;
f0495f56 806}
7e7c5e4c 807
f0495f56
JQ		 808static int menelaus_post_load(void *opaque, int version_id)
809{
810 MenelausState *s = opaque;
7e7c5e4c
AZ		 811
812 if (s->rtc.ctrl & 1) /* RTC_EN */
813 menelaus_rtc_stop(s);
f0495f56
JQ		 814
815 s->rtc.next = s->rtc_next_vmstate;
816
7e7c5e4c
AZ		 817 menelaus_alm_update(s);
818 menelaus_update(s);
819 if (s->rtc.ctrl & 1) /* RTC_EN */
820 menelaus_rtc_start(s);
7e7c5e4c
AZ		 821 return 0;
822}
823
f0495f56
JQ		 824static const VMStateDescription vmstate_menelaus = {
825 .name = "menelaus",
826 .version_id = 0,
827 .minimum_version_id = 0,
f0495f56
JQ		 828 .pre_save = menelaus_pre_save,
829 .post_load = menelaus_post_load,
8f1e884b 830 .fields = (VMStateField[]) {
f0495f56
JQ		 831 VMSTATE_INT32(firstbyte, MenelausState),
832 VMSTATE_UINT8(reg, MenelausState),
833 VMSTATE_UINT8_ARRAY(vcore, MenelausState, 5),
834 VMSTATE_UINT8_ARRAY(dcdc, MenelausState, 3),
835 VMSTATE_UINT8_ARRAY(ldo, MenelausState, 8),
836 VMSTATE_UINT8_ARRAY(sleep, MenelausState, 2),
837 VMSTATE_UINT8(osc, MenelausState),
838 VMSTATE_UINT8(detect, MenelausState),
839 VMSTATE_UINT16(mask, MenelausState),
840 VMSTATE_UINT16(status, MenelausState),
841 VMSTATE_UINT8(dir, MenelausState),
842 VMSTATE_UINT8(inputs, MenelausState),
843 VMSTATE_UINT8(outputs, MenelausState),
844 VMSTATE_UINT8(bbsms, MenelausState),
845 VMSTATE_UINT8_ARRAY(pull, MenelausState, 4),
846 VMSTATE_UINT8_ARRAY(mmc_ctrl, MenelausState, 3),
847 VMSTATE_UINT8(mmc_debounce, MenelausState),
848 VMSTATE_UINT8(rtc.ctrl, MenelausState),
849 VMSTATE_UINT16(rtc.comp, MenelausState),
850 VMSTATE_UINT16(rtc_next_vmstate, MenelausState),
851 VMSTATE_STRUCT(rtc.new, MenelausState, 0, vmstate_menelaus_tm,
852 struct tm),
853 VMSTATE_STRUCT(rtc.alm, MenelausState, 0, vmstate_menelaus_tm,
854 struct tm),
855 VMSTATE_UINT8(pwrbtn_state, MenelausState),
dd37dfa9 856 VMSTATE_I2C_SLAVE(parent_obj, MenelausState),
f0495f56
JQ		 857 VMSTATE_END_OF_LIST()
858 }
859};
860
c8c9e103 861static void twl92230_realize(DeviceState *dev, Error **errp)
7e7c5e4c 862{
c8c9e103 863 MenelausState *s = TWL92230(dev);
7e7c5e4c 864
884f17c2 865 s->rtc.hz_tm = timer_new_ms(rtc_clock, menelaus_rtc_hz, s);
d3356811 866 /* Three output pins plus one interrupt pin. */
dd37dfa9 867 qdev_init_gpio_out(dev, s->out, 4);
dd4427a6
PB		 868
869 /* Three input pins plus one power-button pin. */
dd37dfa9 870 qdev_init_gpio_in(dev, menelaus_gpio_set, 4);
7e7c5e4c 871
c8c9e103 872 menelaus_reset(I2C_SLAVE(dev));
7e7c5e4c
AZ		 873}
874
b5ea9327
AL		 875static void twl92230_class_init(ObjectClass *klass, void *data)
876{
39bffca2 877 DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327
AL		 878 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
879
c8c9e103 880 dc->realize = twl92230_realize;
b5ea9327
AL		 881 sc->event = menelaus_event;
882 sc->recv = menelaus_rx;
883 sc->send = menelaus_tx;
39bffca2 884 dc->vmsd = &vmstate_menelaus;
b5ea9327
AL		 885}
886
8c43a6f0 887static const TypeInfo twl92230_info = {
dd37dfa9 888 .name = TYPE_TWL92230,
39bffca2
AL		 889 .parent = TYPE_I2C_SLAVE,
890 .instance_size = sizeof(MenelausState),
891 .class_init = twl92230_class_init,
d3356811 892};
7e7c5e4c 893
83f7d43a 894static void twl92230_register_types(void)
7e7c5e4c 895{
39bffca2 896 type_register_static(&twl92230_info);
7e7c5e4c 897}
d3356811 898
83f7d43a 899type_init(twl92230_register_types)
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