[mirror_qemu.git] / hw / timer / xilinx_timer.c

/*
 * QEMU model of the Xilinx timer block.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/ptimer.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"

#define D(x)

#define R_TCSR     0
#define R_TLR      1
#define R_TCR      2
#define R_MAX      4

#define TCSR_MDT        (1<<0)
#define TCSR_UDT        (1<<1)
#define TCSR_GENT       (1<<2)
#define TCSR_CAPT       (1<<3)
#define TCSR_ARHT       (1<<4)
#define TCSR_LOAD       (1<<5)
#define TCSR_ENIT       (1<<6)
#define TCSR_ENT        (1<<7)
#define TCSR_TINT       (1<<8)
#define TCSR_PWMA       (1<<9)
#define TCSR_ENALL      (1<<10)

struct xlx_timer
{
    QEMUBH *bh;
    ptimer_state *ptimer;
    void *parent;
    int nr; /* for debug.  */

    unsigned long timer_div;

    uint32_t regs[R_MAX];
};

#define TYPE_XILINX_TIMER "xlnx.xps-timer"
#define XILINX_TIMER(obj) \
    OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)

struct timerblock
{
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    qemu_irq irq;
    uint8_t one_timer_only;
    uint32_t freq_hz;
    struct xlx_timer *timers;
};

static inline unsigned int num_timers(struct timerblock *t)
{
    return 2 - t->one_timer_only;
}

static inline unsigned int timer_from_addr(hwaddr addr)
{
    /* Timers get a 4x32bit control reg area each.  */
    return addr >> 2;
}

static void timer_update_irq(struct timerblock *t)
{
    unsigned int i, irq = 0;
    uint32_t csr;

    for (i = 0; i < num_timers(t); i++) {
        csr = t->timers[i].regs[R_TCSR];
        irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
    }

    /* All timers within the same slave share a single IRQ line.  */
    qemu_set_irq(t->irq, !!irq);
}

static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    uint32_t r = 0;
    unsigned int timer;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    /* Further decoding to address a specific timers reg.  */
    addr &= 0x3;
    switch (addr)
    {
        case R_TCR:
                r = ptimer_get_count(xt->ptimer);
                if (!(xt->regs[R_TCSR] & TCSR_UDT))
                    r = ~r;
                D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
                         timer, r, xt->regs[R_TCSR] & TCSR_UDT));
            break;
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                r = xt->regs[addr];
            break;

    }
    D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
    return r;
}

static void timer_enable(struct xlx_timer *xt)
{
    uint64_t count;

    D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
              xt->nr, xt->regs[R_TCSR] & TCSR_UDT));

    ptimer_stop(xt->ptimer);

    if (xt->regs[R_TCSR] & TCSR_UDT)
        count = xt->regs[R_TLR];
    else
        count = ~0 - xt->regs[R_TLR];
    ptimer_set_limit(xt->ptimer, count, 1);
    ptimer_run(xt->ptimer, 1);
}

static void
timer_write(void *opaque, hwaddr addr,
            uint64_t val64, unsigned int size)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    unsigned int timer;
    uint32_t value = val64;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
             __func__, addr * 4, value, timer, addr & 3));
    /* Further decoding to address a specific timers reg.  */
    addr &= 3;
    switch (addr) 
    {
        case R_TCSR:
            if (value & TCSR_TINT)
                value &= ~TCSR_TINT;

            xt->regs[addr] = value & 0x7ff;
            if (value & TCSR_ENT)
                timer_enable(xt);
            break;
 
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                xt->regs[addr] = value;
            break;
    }
    timer_update_irq(t);
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void timer_hit(void *opaque)
{
    struct xlx_timer *xt = opaque;
    struct timerblock *t = xt->parent;
    D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
    xt->regs[R_TCSR] |= TCSR_TINT;

    if (xt->regs[R_TCSR] & TCSR_ARHT)
        timer_enable(xt);
    timer_update_irq(t);
}

static void xilinx_timer_realize(DeviceState *dev, Error **errp)
{
    struct timerblock *t = XILINX_TIMER(dev);
    unsigned int i;

    /* Init all the ptimers.  */
    t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
    for (i = 0; i < num_timers(t); i++) {
        struct xlx_timer *xt = &t->timers[i];

        xt->parent = t;
        xt->nr = i;
        xt->bh = qemu_bh_new(timer_hit, xt);
        xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT);
        ptimer_set_freq(xt->ptimer, t->freq_hz);
    }

    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
                          R_MAX * 4 * num_timers(t));
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
}

static void xilinx_timer_init(Object *obj)
{
    struct timerblock *t = XILINX_TIMER(obj);

    /* All timers share a single irq line.  */
    sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
}

static Property xilinx_timer_properties[] = {
    DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
                                                                62 * 1000000),
    DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void xilinx_timer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = xilinx_timer_realize;
    dc->props = xilinx_timer_properties;
}

static const TypeInfo xilinx_timer_info = {
    .name          = TYPE_XILINX_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(struct timerblock),
    .instance_init = xilinx_timer_init,
    .class_init    = xilinx_timer_class_init,
};

static void xilinx_timer_register_types(void)
{
    type_register_static(&xilinx_timer_info);
}

type_init(xilinx_timer_register_types)
Commit	Line	Data
388f60b1 EI	1	/*
	2	* QEMU model of the Xilinx timer block.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
282bc81e	25	#include "qemu/osdep.h"
83c9f4ca PB	26	#include "hw/sysbus.h"
83c9f4ca PB	27	#include "hw/ptimer.h"
1de7afc9	28	#include "qemu/log.h"
6a1751b7	29	#include "qemu/main-loop.h"
0b8fa32f	30	#include "qemu/module.h"
388f60b1 EI	31
	32	#define D(x)
	33
	34	#define R_TCSR 0
	35	#define R_TLR 1
	36	#define R_TCR 2
	37	#define R_MAX 4
	38
	39	#define TCSR_MDT (1<<0)
	40	#define TCSR_UDT (1<<1)
	41	#define TCSR_GENT (1<<2)
	42	#define TCSR_CAPT (1<<3)
	43	#define TCSR_ARHT (1<<4)
	44	#define TCSR_LOAD (1<<5)
	45	#define TCSR_ENIT (1<<6)
	46	#define TCSR_ENT (1<<7)
	47	#define TCSR_TINT (1<<8)
	48	#define TCSR_PWMA (1<<9)
	49	#define TCSR_ENALL (1<<10)
	50
	51	struct xlx_timer
	52	{
	53	QEMUBH *bh;
	54	ptimer_state *ptimer;
	55	void *parent;
	56	int nr; /* for debug. */
	57
	58	unsigned long timer_div;
	59
	60	uint32_t regs[R_MAX];
	61	};
	62
760d1d00 AF	63	#define TYPE_XILINX_TIMER "xlnx.xps-timer"
	64	#define XILINX_TIMER(obj) \
	65	OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
	66
388f60b1 EI	67	struct timerblock
388f60b1 EI	68	{
760d1d00 AF	69	SysBusDevice parent_obj;
760d1d00 AF	70
010f3f5f	71	MemoryRegion mmio;
388f60b1	72	qemu_irq irq;
abe098e4	73	uint8_t one_timer_only;
ee6847d1	74	uint32_t freq_hz;
388f60b1 EI	75	struct xlx_timer *timers;
	76	};
	77
abe098e4 PC	78	static inline unsigned int num_timers(struct timerblock *t)
	79	{
	80	return 2 - t->one_timer_only;
	81	}
	82
a8170e5e	83	static inline unsigned int timer_from_addr(hwaddr addr)
388f60b1 EI	84	{
	85	/* Timers get a 4x32bit control reg area each. */
	86	return addr >> 2;
	87	}
	88
	89	static void timer_update_irq(struct timerblock *t)
	90	{
	91	unsigned int i, irq = 0;
	92	uint32_t csr;
	93
abe098e4	94	for (i = 0; i < num_timers(t); i++) {
388f60b1 EI	95	csr = t->timers[i].regs[R_TCSR];
	96	irq \|= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
	97	}
	98
	99	/* All timers within the same slave share a single IRQ line. */
	100	qemu_set_irq(t->irq, !!irq);
	101	}
	102
010f3f5f	103	static uint64_t
a8170e5e	104	timer_read(void *opaque, hwaddr addr, unsigned int size)
388f60b1 EI	105	{
	106	struct timerblock *t = opaque;
	107	struct xlx_timer *xt;
	108	uint32_t r = 0;
	109	unsigned int timer;
	110
	111	addr >>= 2;
	112	timer = timer_from_addr(addr);
	113	xt = &t->timers[timer];
	114	/* Further decoding to address a specific timers reg. */
	115	addr &= 0x3;
	116	switch (addr)
	117	{
	118	case R_TCR:
	119	r = ptimer_get_count(xt->ptimer);
	120	if (!(xt->regs[R_TCSR] & TCSR_UDT))
	121	r = ~r;
	122	D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
	123	timer, r, xt->regs[R_TCSR] & TCSR_UDT));
	124	break;
	125	default:
	126	if (addr < ARRAY_SIZE(xt->regs))
	127	r = xt->regs[addr];
	128	break;
	129
	130	}
e03377ae	131	D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
388f60b1 EI	132	return r;
	133	}
	134
	135	static void timer_enable(struct xlx_timer *xt)
	136	{
	137	uint64_t count;
	138
e03377ae	139	D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
388f60b1 EI	140	xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
	141
	142	ptimer_stop(xt->ptimer);
	143
	144	if (xt->regs[R_TCSR] & TCSR_UDT)
	145	count = xt->regs[R_TLR];
	146	else
	147	count = ~0 - xt->regs[R_TLR];
7798a882	148	ptimer_set_limit(xt->ptimer, count, 1);
388f60b1 EI	149	ptimer_run(xt->ptimer, 1);
	150	}
	151
	152	static void
a8170e5e	153	timer_write(void *opaque, hwaddr addr,
010f3f5f	154	uint64_t val64, unsigned int size)
388f60b1 EI	155	{
	156	struct timerblock *t = opaque;
	157	struct xlx_timer *xt;
	158	unsigned int timer;
010f3f5f	159	uint32_t value = val64;
388f60b1 EI	160
	161	addr >>= 2;
	162	timer = timer_from_addr(addr);
	163	xt = &t->timers[timer];
e03377ae	164	D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
388f60b1 EI	165	__func__, addr * 4, value, timer, addr & 3));
	166	/* Further decoding to address a specific timers reg. */
	167	addr &= 3;
	168	switch (addr)
	169	{
	170	case R_TCSR:
	171	if (value & TCSR_TINT)
	172	value &= ~TCSR_TINT;
	173
7dfba6df	174	xt->regs[addr] = value & 0x7ff;
388f60b1 EI	175	if (value & TCSR_ENT)
	176	timer_enable(xt);
	177	break;
	178
	179	default:
	180	if (addr < ARRAY_SIZE(xt->regs))
	181	xt->regs[addr] = value;
	182	break;
	183	}
	184	timer_update_irq(t);
	185	}
	186
010f3f5f EI	187	static const MemoryRegionOps timer_ops = {
	188	.read = timer_read,
	189	.write = timer_write,
	190	.endianness = DEVICE_NATIVE_ENDIAN,
	191	.valid = {
	192	.min_access_size = 4,
	193	.max_access_size = 4
	194	}
388f60b1 EI	195	};
	196
	197	static void timer_hit(void *opaque)
	198	{
	199	struct xlx_timer *xt = opaque;
	200	struct timerblock *t = xt->parent;
8354cd72	201	D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
388f60b1 EI	202	xt->regs[R_TCSR] \|= TCSR_TINT;
	203
	204	if (xt->regs[R_TCSR] & TCSR_ARHT)
	205	timer_enable(xt);
	206	timer_update_irq(t);
	207	}
	208
04bb4d86	209	static void xilinx_timer_realize(DeviceState dev, Error *errp)
388f60b1	210	{
760d1d00	211	struct timerblock *t = XILINX_TIMER(dev);
388f60b1	212	unsigned int i;
388f60b1	213
388f60b1	214	/* Init all the ptimers. */
abe098e4 PC	215	t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
abe098e4 PC	216	for (i = 0; i < num_timers(t); i++) {
388f60b1 EI	217	struct xlx_timer *xt = &t->timers[i];
	218
	219	xt->parent = t;
	220	xt->nr = i;
	221	xt->bh = qemu_bh_new(timer_hit, xt);
e7ea81c3	222	xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT);
ee6847d1	223	ptimer_set_freq(xt->ptimer, t->freq_hz);
388f60b1 EI	224	}
388f60b1 EI	225
853dca12	226	memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
abe098e4	227	R_MAX * 4 * num_timers(t));
04bb4d86 PC	228	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
	229	}
	230
	231	static void xilinx_timer_init(Object *obj)
	232	{
	233	struct timerblock *t = XILINX_TIMER(obj);
	234
	235	/* All timers share a single irq line. */
	236	sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
388f60b1 EI	237	}
388f60b1 EI	238
999e12bb	239	static Property xilinx_timer_properties[] = {
919f89f4 PC	240	DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
919f89f4 PC	241	62 * 1000000),
abe098e4	242	DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
999e12bb AL	243	DEFINE_PROP_END_OF_LIST(),
	244	};
	245
	246	static void xilinx_timer_class_init(ObjectClass klass, void data)
	247	{
39bffca2	248	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	249
04bb4d86	250	dc->realize = xilinx_timer_realize;
39bffca2	251	dc->props = xilinx_timer_properties;
999e12bb AL	252	}
999e12bb AL	253
8c43a6f0	254	static const TypeInfo xilinx_timer_info = {
760d1d00	255	.name = TYPE_XILINX_TIMER,
39bffca2 AL	256	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	257	.instance_size = sizeof(struct timerblock),
04bb4d86	258	.instance_init = xilinx_timer_init,
39bffca2	259	.class_init = xilinx_timer_class_init,
ee6847d1 GH	260	};
ee6847d1 GH	261
83f7d43a	262	static void xilinx_timer_register_types(void)
388f60b1	263	{
39bffca2	264	type_register_static(&xilinx_timer_info);
388f60b1 EI	265	}
388f60b1 EI	266
83f7d43a	267	type_init(xilinx_timer_register_types)