[mirror_qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
} UNINState;

static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
                                         uint32_t val)
{
    UNINState *s = opaque;

    UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    s->host_state.config_reg = val;
}

static uint32_t pci_unin_main_config_readl (void *opaque,
                                            target_phys_addr_t addr)
{
    UNINState *s = opaque;
    uint32_t val;

    val = s->host_state.config_reg;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);

    return val;
}

static CPUWriteMemoryFunc * const pci_unin_main_config_write[] = {
    &pci_unin_main_config_writel,
    &pci_unin_main_config_writel,
    &pci_unin_main_config_writel,
};

static CPUReadMemoryFunc * const pci_unin_main_config_read[] = {
    &pci_unin_main_config_readl,
    &pci_unin_main_config_readl,
    &pci_unin_main_config_readl,
};

static CPUWriteMemoryFunc * const pci_unin_main_write[] = {
    &pci_host_data_writeb,
    &pci_host_data_writew,
    &pci_host_data_writel,
};

static CPUReadMemoryFunc * const pci_unin_main_read[] = {
    &pci_host_data_readb,
    &pci_host_data_readw,
    &pci_host_data_readl,
};

static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
                                    uint32_t val)
{
    UNINState *s = opaque;

    s->host_state.config_reg = val;
}

static uint32_t pci_unin_config_readl (void *opaque,
                                       target_phys_addr_t addr)
{
    UNINState *s = opaque;

    return s->host_state.config_reg;
}

static CPUWriteMemoryFunc * const pci_unin_config_write[] = {
    &pci_unin_config_writel,
    &pci_unin_config_writel,
    &pci_unin_config_writel,
};

static CPUReadMemoryFunc * const pci_unin_config_read[] = {
    &pci_unin_config_readl,
    &pci_unin_config_readl,
    &pci_unin_config_readl,
};

static CPUWriteMemoryFunc * const pci_unin_write[] = {
    &pci_host_data_writeb,
    &pci_host_data_writew,
    &pci_host_data_writel,
};

static CPUReadMemoryFunc * const pci_unin_read[] = {
    &pci_host_data_readb,
    &pci_host_data_readw,
    &pci_host_data_readl,
};

/* Don't know if this matches real hardware, but it agrees with OHW.  */
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return (irq_num + (pci_dev->devfn >> 3)) & 3;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    qemu_set_irq(pic[irq_num + 8], level);
}

static void pci_unin_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;

    pci_device_save(d, f);
}

static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;

    if (version_id != 1)
        return -EINVAL;

    return pci_device_load(d, f);
}

static void pci_unin_reset(void *opaque)
{
}

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read,
                                            pci_unin_main_config_write, s);
    pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
                                          pci_unin_main_write, &s->host_state);

    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}

static int pci_dec_21154_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth bridge */
    s = FROM_SYSBUS(UNINState, dev);

    // XXX: s = &pci_bridge[2];
    pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
                                          pci_unin_main_write, &s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
                                          pci_unin_main_write, &s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(pci_unin_read,
                                          pci_unin_write, s);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "Uni-north main");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, 11 << 3, 4);

    pci_create_simple(d->host_state.bus, 11 << 3, "Uni-north main");

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, 12 << 3, "DEC 21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, 13 << 3, "Uni-north AGP");

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, 14 << 3, "Uni-north internal");
#endif

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int dec_21154_pci_host_init(PCIDevice *d)
{
    /* pci-to-pci bridge */
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
    d->config[0x08] = 0x05; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x20; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type

    d->config[0x18] = 0x01; // primary_bus
    d->config[0x19] = 0x02; // secondary_bus
    d->config[0x1A] = 0x02; // subordinate_bus
    d->config[0x1B] = 0x20; // secondary_latency_timer
    d->config[0x1C] = 0x11; // io_base
    d->config[0x1D] = 0x01; // io_limit
    d->config[0x20] = 0x00; // memory_base
    d->config[0x21] = 0x80;
    d->config[0x22] = 0x00; // memory_limit
    d->config[0x23] = 0x80;
    d->config[0x24] = 0x01; // prefetchable_memory_base
    d->config[0x25] = 0x80;
    d->config[0x26] = 0xF1; // prefectchable_memory_limit
    d->config[0x27] = 0x7F;
    // d->config[0x34] = 0xdc // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "Uni-north main",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
};

static PCIDeviceInfo dec_21154_pci_host_info = {
    .qdev.name = "DEC 21154",
    .qdev.size = sizeof(PCIDevice),
    .init      = dec_21154_pci_host_init,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "Uni-north AGP",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "Uni-north internal",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("Uni-north main", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("DEC 21154", sizeof(UNINState),
                        pci_dec_21154_init_device);
    pci_qdev_register(&dec_21154_pci_host_info);
    sysbus_register_dev("Uni-north AGP", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("Uni-north internal", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
	27
f3902383 BS	28	/* debug UniNorth */
	29	//#define DEBUG_UNIN
	30
	31	#ifdef DEBUG_UNIN
001faf32 BS	32	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	33	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	34	#else
001faf32	35	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	36	#endif
f3902383 BS	37
c227f099	38	typedef target_phys_addr_t pci_addr_t;
502a5395 PB	39	#include "pci_host.h"
502a5395 PB	40
2e29bd04 BS	41	typedef struct UNINState {
	42	SysBusDevice busdev;
	43	PCIHostState host_state;
	44	} UNINState;
502a5395	45
c227f099	46	static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
502a5395 PB	47	uint32_t val)
	48	{
	49	UNINState *s = opaque;
502a5395	50
f3902383	51	UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
502a5395 PB	52	#ifdef TARGET_WORDS_BIGENDIAN
	53	val = bswap32(val);
	54	#endif
	55
2e29bd04	56	s->host_state.config_reg = val;
502a5395 PB	57	}
	58
	59	static uint32_t pci_unin_main_config_readl (void *opaque,
c227f099	60	target_phys_addr_t addr)
502a5395 PB	61	{
	62	UNINState *s = opaque;
	63	uint32_t val;
502a5395	64
2e29bd04	65	val = s->host_state.config_reg;
502a5395 PB	66	#ifdef TARGET_WORDS_BIGENDIAN
	67	val = bswap32(val);
	68	#endif
f3902383	69	UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
502a5395 PB	70
	71	return val;
	72	}
	73
d60efc6b	74	static CPUWriteMemoryFunc * const pci_unin_main_config_write[] = {
502a5395 PB	75	&pci_unin_main_config_writel,
	76	&pci_unin_main_config_writel,
	77	&pci_unin_main_config_writel,
	78	};
	79
d60efc6b	80	static CPUReadMemoryFunc * const pci_unin_main_config_read[] = {
502a5395 PB	81	&pci_unin_main_config_readl,
	82	&pci_unin_main_config_readl,
	83	&pci_unin_main_config_readl,
	84	};
	85
d60efc6b	86	static CPUWriteMemoryFunc * const pci_unin_main_write[] = {
502a5395 PB	87	&pci_host_data_writeb,
	88	&pci_host_data_writew,
	89	&pci_host_data_writel,
	90	};
	91
d60efc6b	92	static CPUReadMemoryFunc * const pci_unin_main_read[] = {
502a5395 PB	93	&pci_host_data_readb,
	94	&pci_host_data_readw,
	95	&pci_host_data_readl,
	96	};
	97
c227f099	98	static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
502a5395 PB	99	uint32_t val)
	100	{
	101	UNINState *s = opaque;
	102
2e29bd04	103	s->host_state.config_reg = val;
502a5395 PB	104	}
	105
	106	static uint32_t pci_unin_config_readl (void *opaque,
c227f099	107	target_phys_addr_t addr)
502a5395 PB	108	{
502a5395 PB	109	UNINState *s = opaque;
502a5395	110
2e29bd04	111	return s->host_state.config_reg;
502a5395 PB	112	}
502a5395 PB	113
d60efc6b	114	static CPUWriteMemoryFunc * const pci_unin_config_write[] = {
502a5395 PB	115	&pci_unin_config_writel,
	116	&pci_unin_config_writel,
	117	&pci_unin_config_writel,
	118	};
	119
d60efc6b	120	static CPUReadMemoryFunc * const pci_unin_config_read[] = {
502a5395 PB	121	&pci_unin_config_readl,
	122	&pci_unin_config_readl,
	123	&pci_unin_config_readl,
	124	};
	125
d60efc6b	126	static CPUWriteMemoryFunc * const pci_unin_write[] = {
2e29bd04 BS	127	&pci_host_data_writeb,
	128	&pci_host_data_writew,
	129	&pci_host_data_writel,
502a5395 PB	130	};
502a5395 PB	131
d60efc6b	132	static CPUReadMemoryFunc * const pci_unin_read[] = {
2e29bd04 BS	133	&pci_host_data_readb,
	134	&pci_host_data_readw,
	135	&pci_host_data_readl,
502a5395	136	};
502a5395	137
d2b59317 PB	138	/* Don't know if this matches real hardware, but it agrees with OHW. */
d2b59317 PB	139	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	140	{
d2b59317 PB	141	return (irq_num + (pci_dev->devfn >> 3)) & 3;
	142	}
	143
5d4e84c8	144	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	145	{
5d4e84c8 JQ	146	qemu_irq *pic = opaque;
5d4e84c8 JQ	147
d537cf6c	148	qemu_set_irq(pic[irq_num + 8], level);
502a5395 PB	149	}
502a5395 PB	150
f3902383 BS	151	static void pci_unin_save(QEMUFile* f, void *opaque)
	152	{
	153	PCIDevice *d = opaque;
	154
	155	pci_device_save(d, f);
	156	}
	157
	158	static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
	159	{
	160	PCIDevice *d = opaque;
	161
	162	if (version_id != 1)
	163	return -EINVAL;
	164
	165	return pci_device_load(d, f);
	166	}
	167
	168	static void pci_unin_reset(void *opaque)
	169	{
	170	}
	171
81a322d4	172	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	173	{
502a5395 PB	174	UNINState *s;
502a5395 PB	175	int pci_mem_config, pci_mem_data;
	176
	177	/* Use values found on a real PowerMac */
	178	/* Uninorth main bus */
2e29bd04	179	s = FROM_SYSBUS(UNINState, dev);
502a5395	180
1eed09cb	181	pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read,
502a5395	182	pci_unin_main_config_write, s);
1eed09cb	183	pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
2e29bd04 BS	184	pci_unin_main_write, &s->host_state);
	185
	186	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	187	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	188
	189	register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
	190	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	191	return 0;
2e29bd04 BS	192	}
2e29bd04 BS	193
81a322d4	194	static int pci_dec_21154_init_device(SysBusDevice *dev)
2e29bd04 BS	195	{
	196	UNINState *s;
	197	int pci_mem_config, pci_mem_data;
	198
	199	/* Uninorth bridge */
	200	s = FROM_SYSBUS(UNINState, dev);
	201
	202	// XXX: s = &pci_bridge[2];
	203	pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
	204	pci_unin_config_write, s);
	205	pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
	206	pci_unin_main_write, &s->host_state);
	207	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	208	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	209	return 0;
2e29bd04 BS	210	}
2e29bd04 BS	211
81a322d4	212	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	213	{
	214	UNINState *s;
	215	int pci_mem_config, pci_mem_data;
	216
	217	/* Uninorth AGP bus */
	218	s = FROM_SYSBUS(UNINState, dev);
	219
	220	pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
	221	pci_unin_config_write, s);
	222	pci_mem_data = cpu_register_io_memory(pci_unin_main_read,
	223	pci_unin_main_write, &s->host_state);
	224	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	225	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	226	return 0;
2e29bd04 BS	227	}
2e29bd04 BS	228
81a322d4	229	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	230	{
	231	UNINState *s;
	232	int pci_mem_config, pci_mem_data;
	233
	234	/* Uninorth internal bus */
	235	s = FROM_SYSBUS(UNINState, dev);
	236
	237	pci_mem_config = cpu_register_io_memory(pci_unin_config_read,
	238	pci_unin_config_write, s);
	239	pci_mem_data = cpu_register_io_memory(pci_unin_read,
	240	pci_unin_write, s);
	241	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	242	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	243	return 0;
2e29bd04 BS	244	}
	245
	246	PCIBus pci_pmac_init(qemu_irq pic)
	247	{
	248	DeviceState *dev;
	249	SysBusDevice *s;
	250	UNINState *d;
	251
	252	/* Use values found on a real PowerMac */
	253	/* Uninorth main bus */
	254	dev = qdev_create(NULL, "Uni-north main");
e23a1b33	255	qdev_init_nofail(dev);
2e29bd04 BS	256	s = sysbus_from_qdev(dev);
2e29bd04 BS	257	d = FROM_SYSBUS(UNINState, s);
cdd0935c	258	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04 BS	259	pci_unin_set_irq, pci_unin_map_irq,
	260	pic, 11 << 3, 4);
	261
	262	pci_create_simple(d->host_state.bus, 11 << 3, "Uni-north main");
	263
	264	sysbus_mmio_map(s, 0, 0xf2800000);
	265	sysbus_mmio_map(s, 1, 0xf2c00000);
	266
	267	/* DEC 21154 bridge */
	268	#if 0
	269	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
	270	pci_create_simple(d->host_state.bus, 12 << 3, "DEC 21154");
	271	#endif
	272
	273	/* Uninorth AGP bus */
	274	pci_create_simple(d->host_state.bus, 13 << 3, "Uni-north AGP");
	275
	276	/* Uninorth internal bus */
	277	#if 0
	278	/* XXX: not needed for now */
	279	pci_create_simple(d->host_state.bus, 14 << 3, "Uni-north internal");
	280	#endif
	281
	282	return d->host_state.bus;
	283	}
	284
81a322d4	285	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	286	{
deb54399	287	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	288	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
502a5395	289	d->config[0x08] = 0x00; // revision
173a543b	290	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	291	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	292	d->config[0x0D] = 0x10; // latency_timer
6407f373	293	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	294	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	295	return 0;
2e29bd04	296	}
502a5395	297
81a322d4	298	static int dec_21154_pci_host_init(PCIDevice *d)
2e29bd04	299	{
502a5395	300	/* pci-to-pci bridge */
4ebcf884 BS	301	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
4ebcf884 BS	302	pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
502a5395	303	d->config[0x08] = 0x05; // revision
173a543b	304	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
502a5395 PB	305	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	306	d->config[0x0D] = 0x20; // latency_timer
6407f373	307	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
502a5395 PB	308
	309	d->config[0x18] = 0x01; // primary_bus
	310	d->config[0x19] = 0x02; // secondary_bus
	311	d->config[0x1A] = 0x02; // subordinate_bus
	312	d->config[0x1B] = 0x20; // secondary_latency_timer
	313	d->config[0x1C] = 0x11; // io_base
	314	d->config[0x1D] = 0x01; // io_limit
	315	d->config[0x20] = 0x00; // memory_base
	316	d->config[0x21] = 0x80;
	317	d->config[0x22] = 0x00; // memory_limit
	318	d->config[0x23] = 0x80;
	319	d->config[0x24] = 0x01; // prefetchable_memory_base
	320	d->config[0x25] = 0x80;
	321	d->config[0x26] = 0xF1; // prefectchable_memory_limit
	322	d->config[0x27] = 0x7F;
	323	// d->config[0x34] = 0xdc // capabilities_pointer
81a322d4	324	return 0;
2e29bd04	325	}
502a5395	326
81a322d4	327	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	328	{
deb54399 AL	329	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
deb54399 AL	330	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
502a5395	331	d->config[0x08] = 0x00; // revision
173a543b	332	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	333	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	334	d->config[0x0D] = 0x10; // latency_timer
6407f373	335	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	336	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	337	return 0;
2e29bd04	338	}
502a5395	339
81a322d4	340	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	341	{
deb54399	342	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	343	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
502a5395	344	d->config[0x08] = 0x00; // revision
173a543b	345	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	346	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	347	d->config[0x0D] = 0x10; // latency_timer
6407f373	348	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	349	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	350	return 0;
2e29bd04 BS	351	}
	352
	353	static PCIDeviceInfo unin_main_pci_host_info = {
	354	.qdev.name = "Uni-north main",
	355	.qdev.size = sizeof(PCIDevice),
	356	.init = unin_main_pci_host_init,
	357	};
	358
	359	static PCIDeviceInfo dec_21154_pci_host_info = {
	360	.qdev.name = "DEC 21154",
	361	.qdev.size = sizeof(PCIDevice),
	362	.init = dec_21154_pci_host_init,
	363	};
f3902383	364
2e29bd04 BS	365	static PCIDeviceInfo unin_agp_pci_host_info = {
	366	.qdev.name = "Uni-north AGP",
	367	.qdev.size = sizeof(PCIDevice),
	368	.init = unin_agp_pci_host_init,
	369	};
	370
	371	static PCIDeviceInfo unin_internal_pci_host_info = {
	372	.qdev.name = "Uni-north internal",
	373	.qdev.size = sizeof(PCIDevice),
	374	.init = unin_internal_pci_host_init,
	375	};
	376
	377	static void unin_register_devices(void)
	378	{
	379	sysbus_register_dev("Uni-north main", sizeof(UNINState),
	380	pci_unin_main_init_device);
	381	pci_qdev_register(&unin_main_pci_host_info);
	382	sysbus_register_dev("DEC 21154", sizeof(UNINState),
	383	pci_dec_21154_init_device);
	384	pci_qdev_register(&dec_21154_pci_host_info);
	385	sysbus_register_dev("Uni-north AGP", sizeof(UNINState),
	386	pci_unin_agp_init_device);
	387	pci_qdev_register(&unin_agp_pci_host_info);
	388	sysbus_register_dev("Uni-north internal", sizeof(UNINState),
	389	pci_unin_internal_init_device);
	390	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	391	}
2e29bd04 BS	392
2e29bd04 BS	393	device_init(unin_register_devices)