[mirror_qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
    ReadWriteHandler data_handler;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static void pci_unin_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;

    pci_device_save(d, f);
}

static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;

    if (version_id != 1)
        return -EINVAL;

    return pci_device_load(d, f);
}

static void pci_unin_reset(void *opaque)
{
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(ReadWriteHandler *handler,
                            pcibus_t addr, uint32_t val, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
#ifdef TARGET_WORDS_BIGENDIAN
    val = qemu_bswap_len(val, len);
#endif
    UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    pci_data_write(s->host_state.bus,
                   unin_get_config_reg(s->host_state.config_reg, addr),
                   val, len);
}

static uint32_t unin_data_read(ReadWriteHandler *handler,
                               pcibus_t addr, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    uint32_t val;

    val = pci_data_read(s->host_state.bus,
                        unin_get_config_reg(s->host_state.config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
#ifdef TARGET_WORDS_BIGENDIAN
    val = qemu_bswap_len(val, len);
#endif
    return val;
}

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}

static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth U3 AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, 11 << 3, 4);

#if 0
    pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
    dev = qdev_create(NULL, "uni-north-pci");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, "u3-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);

    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, 11 << 3, 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
    /* revision */
    d->config[0x08] = 0x00;
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
};

static PCIDeviceInfo u3_agp_pci_host_info = {
    .qdev.name = "u3-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = u3_agp_pci_host_init,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("uni-north", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("u3-agp", sizeof(UNINState),
                        pci_u3_agp_init_device);
    pci_qdev_register(&u3_agp_pci_host_info);
    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("uni-north-pci", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
2e29bd04 BS	41	typedef struct UNINState {
	42	SysBusDevice busdev;
	43	PCIHostState host_state;
d86f0e32	44	ReadWriteHandler data_handler;
2e29bd04	45	} UNINState;
502a5395	46
d2b59317	47	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	48	{
fa0be69a AG	49	int retval;
	50	int devfn = pci_dev->devfn & 0x00FFFFFF;
	51
	52	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	53
	54	return retval;
d2b59317 PB	55	}
d2b59317 PB	56
5d4e84c8	57	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	58	{
5d4e84c8 JQ	59	qemu_irq *pic = opaque;
5d4e84c8 JQ	60
fa0be69a AG	61	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	62	unin_irq_line[irq_num], level);
	63	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	64	}
502a5395 PB	65
f3902383 BS	66	static void pci_unin_save(QEMUFile* f, void *opaque)
	67	{
	68	PCIDevice *d = opaque;
	69
	70	pci_device_save(d, f);
	71	}
	72
	73	static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
	74	{
	75	PCIDevice *d = opaque;
	76
	77	if (version_id != 1)
	78	return -EINVAL;
	79
	80	return pci_device_load(d, f);
	81	}
	82
	83	static void pci_unin_reset(void *opaque)
	84	{
	85	}
	86
d86f0e32 AG	87	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	88	{
	89	uint32_t retval;
	90
	91	if (reg & (1u << 31)) {
	92	/* XXX OpenBIOS compatibility hack */
	93	retval = reg \| (addr & 3);
	94	} else if (reg & 1) {
	95	/* CFA1 style */
	96	retval = (reg & ~7u) \| (addr & 7);
	97	} else {
	98	uint32_t slot, func;
	99
	100	/* Grab CFA0 style values */
	101	slot = ffs(reg & 0xfffff800) - 1;
	102	func = (reg >> 8) & 7;
	103
	104	/* ... and then convert them to x86 format */
	105	/* config pointer */
	106	retval = (reg & (0xff - 7)) \| (addr & 7);
	107	/* slot */
	108	retval \|= slot << 11;
	109	/* fn */
	110	retval \|= func << 8;
	111	}
	112
	113
	114	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	115	reg, addr, retval);
	116
	117	return retval;
	118	}
	119
	120	static void unin_data_write(ReadWriteHandler *handler,
	121	pcibus_t addr, uint32_t val, int len)
	122	{
	123	UNINState *s = container_of(handler, UNINState, data_handler);
	124	#ifdef TARGET_WORDS_BIGENDIAN
	125	val = qemu_bswap_len(val, len);
	126	#endif
	127	UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
	128	pci_data_write(s->host_state.bus,
	129	unin_get_config_reg(s->host_state.config_reg, addr),
	130	val, len);
	131	}
	132
	133	static uint32_t unin_data_read(ReadWriteHandler *handler,
	134	pcibus_t addr, int len)
	135	{
	136	UNINState *s = container_of(handler, UNINState, data_handler);
	137	uint32_t val;
	138
	139	val = pci_data_read(s->host_state.bus,
	140	unin_get_config_reg(s->host_state.config_reg, addr),
	141	len);
	142	UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
	143	#ifdef TARGET_WORDS_BIGENDIAN
	144	val = qemu_bswap_len(val, len);
	145	#endif
	146	return val;
	147	}
	148
81a322d4	149	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	150	{
502a5395 PB	151	UNINState *s;
502a5395 PB	152	int pci_mem_config, pci_mem_data;
	153
	154	/* Use values found on a real PowerMac */
	155	/* Uninorth main bus */
2e29bd04	156	s = FROM_SYSBUS(UNINState, dev);
502a5395	157
952760bb	158	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
d86f0e32 AG	159	s->data_handler.read = unin_data_read;
	160	s->data_handler.write = unin_data_write;
	161	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
2e29bd04 BS	162	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	163	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	164
	165	register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
	166	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	167	return 0;
2e29bd04 BS	168	}
2e29bd04 BS	169
0f921197 AG	170	static int pci_u3_agp_init_device(SysBusDevice *dev)
	171	{
	172	UNINState *s;
	173	int pci_mem_config, pci_mem_data;
	174
	175	/* Uninorth U3 AGP bus */
	176	s = FROM_SYSBUS(UNINState, dev);
	177
952760bb	178	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
0f921197 AG	179	s->data_handler.read = unin_data_read;
	180	s->data_handler.write = unin_data_write;
	181	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
	182	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	183	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	184
	185	register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
	186	qemu_register_reset(pci_unin_reset, &s->host_state);
	187
	188	return 0;
	189	}
	190
81a322d4	191	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	192	{
	193	UNINState *s;
	194	int pci_mem_config, pci_mem_data;
	195
	196	/* Uninorth AGP bus */
	197	s = FROM_SYSBUS(UNINState, dev);
	198
952760bb BS	199	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
952760bb BS	200	pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
2e29bd04 BS	201	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	202	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	203	return 0;
2e29bd04 BS	204	}
2e29bd04 BS	205
81a322d4	206	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	207	{
	208	UNINState *s;
	209	int pci_mem_config, pci_mem_data;
	210
	211	/* Uninorth internal bus */
	212	s = FROM_SYSBUS(UNINState, dev);
	213
952760bb BS	214	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
952760bb BS	215	pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
2e29bd04 BS	216	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	217	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	218	return 0;
2e29bd04 BS	219	}
	220
	221	PCIBus pci_pmac_init(qemu_irq pic)
	222	{
	223	DeviceState *dev;
	224	SysBusDevice *s;
	225	UNINState *d;
	226
	227	/* Use values found on a real PowerMac */
	228	/* Uninorth main bus */
18dd19a7	229	dev = qdev_create(NULL, "uni-north");
e23a1b33	230	qdev_init_nofail(dev);
2e29bd04 BS	231	s = sysbus_from_qdev(dev);
2e29bd04 BS	232	d = FROM_SYSBUS(UNINState, s);
cdd0935c	233	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04 BS	234	pci_unin_set_irq, pci_unin_map_irq,
	235	pic, 11 << 3, 4);
	236
60398748	237	#if 0
18dd19a7	238	pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
60398748	239	#endif
2e29bd04 BS	240
	241	sysbus_mmio_map(s, 0, 0xf2800000);
	242	sysbus_mmio_map(s, 1, 0xf2c00000);
	243
	244	/* DEC 21154 bridge */
	245	#if 0
	246	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
556cd098	247	pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
2e29bd04 BS	248	#endif
	249
	250	/* Uninorth AGP bus */
18dd19a7 MA	251	pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
18dd19a7 MA	252	dev = qdev_create(NULL, "uni-north-agp");
d27d06f2 BS	253	qdev_init_nofail(dev);
	254	s = sysbus_from_qdev(dev);
	255	sysbus_mmio_map(s, 0, 0xf0800000);
	256	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	257
	258	/* Uninorth internal bus */
	259	#if 0
	260	/* XXX: not needed for now */
18dd19a7 MA	261	pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
18dd19a7 MA	262	dev = qdev_create(NULL, "uni-north-pci");
d27d06f2 BS	263	qdev_init_nofail(dev);
	264	s = sysbus_from_qdev(dev);
	265	sysbus_mmio_map(s, 0, 0xf4800000);
	266	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	267	#endif
	268
	269	return d->host_state.bus;
	270	}
	271
0f921197 AG	272	PCIBus pci_pmac_u3_init(qemu_irq pic)
	273	{
	274	DeviceState *dev;
	275	SysBusDevice *s;
	276	UNINState *d;
	277
	278	/* Uninorth AGP bus */
	279
	280	dev = qdev_create(NULL, "u3-agp");
	281	qdev_init_nofail(dev);
	282	s = sysbus_from_qdev(dev);
	283	d = FROM_SYSBUS(UNINState, s);
	284
	285	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
	286	pci_unin_set_irq, pci_unin_map_irq,
	287	pic, 11 << 3, 4);
	288
	289	sysbus_mmio_map(s, 0, 0xf0800000);
	290	sysbus_mmio_map(s, 1, 0xf0c00000);
	291
	292	pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
	293
	294	return d->host_state.bus;
	295	}
	296
81a322d4	297	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	298	{
deb54399	299	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	300	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
502a5395	301	d->config[0x08] = 0x00; // revision
173a543b	302	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	303	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	304	d->config[0x0D] = 0x10; // latency_timer
6407f373	305	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	306	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	307	return 0;
2e29bd04	308	}
502a5395	309
81a322d4	310	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	311	{
deb54399 AL	312	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
deb54399 AL	313	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
502a5395	314	d->config[0x08] = 0x00; // revision
173a543b	315	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	316	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	317	d->config[0x0D] = 0x10; // latency_timer
6407f373	318	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	319	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	320	return 0;
2e29bd04	321	}
502a5395	322
0f921197 AG	323	static int u3_agp_pci_host_init(PCIDevice *d)
	324	{
	325	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
	326	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
	327	/* revision */
	328	d->config[0x08] = 0x00;
	329	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
	330	/* cache line size */
	331	d->config[0x0C] = 0x08;
	332	/* latency timer */
	333	d->config[0x0D] = 0x10;
	334	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
	335	return 0;
	336	}
	337
81a322d4	338	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	339	{
deb54399	340	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	341	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
502a5395	342	d->config[0x08] = 0x00; // revision
173a543b	343	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	344	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	345	d->config[0x0D] = 0x10; // latency_timer
6407f373	346	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	347	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	348	return 0;
2e29bd04 BS	349	}
	350
	351	static PCIDeviceInfo unin_main_pci_host_info = {
18dd19a7	352	.qdev.name = "uni-north",
2e29bd04 BS	353	.qdev.size = sizeof(PCIDevice),
	354	.init = unin_main_pci_host_init,
	355	};
	356
0f921197 AG	357	static PCIDeviceInfo u3_agp_pci_host_info = {
	358	.qdev.name = "u3-agp",
	359	.qdev.size = sizeof(PCIDevice),
	360	.init = u3_agp_pci_host_init,
	361	};
	362
2e29bd04	363	static PCIDeviceInfo unin_agp_pci_host_info = {
18dd19a7	364	.qdev.name = "uni-north-agp",
2e29bd04 BS	365	.qdev.size = sizeof(PCIDevice),
	366	.init = unin_agp_pci_host_init,
	367	};
	368
	369	static PCIDeviceInfo unin_internal_pci_host_info = {
18dd19a7	370	.qdev.name = "uni-north-pci",
2e29bd04 BS	371	.qdev.size = sizeof(PCIDevice),
	372	.init = unin_internal_pci_host_init,
	373	};
	374
	375	static void unin_register_devices(void)
	376	{
18dd19a7	377	sysbus_register_dev("uni-north", sizeof(UNINState),
2e29bd04 BS	378	pci_unin_main_init_device);
2e29bd04 BS	379	pci_qdev_register(&unin_main_pci_host_info);
0f921197 AG	380	sysbus_register_dev("u3-agp", sizeof(UNINState),
	381	pci_u3_agp_init_device);
	382	pci_qdev_register(&u3_agp_pci_host_info);
18dd19a7	383	sysbus_register_dev("uni-north-agp", sizeof(UNINState),
2e29bd04 BS	384	pci_unin_agp_init_device);
2e29bd04 BS	385	pci_qdev_register(&unin_agp_pci_host_info);
18dd19a7	386	sysbus_register_dev("uni-north-pci", sizeof(UNINState),
2e29bd04 BS	387	pci_unin_internal_init_device);
2e29bd04 BS	388	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	389	}
2e29bd04 BS	390
2e29bd04 BS	391	device_init(unin_register_devices)