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502a5395 PB |
1 | /* |
2 | * QEMU Uninorth PCI host (for all Mac99 and newer machines) | |
3 | * | |
4 | * Copyright (c) 2006 Fabrice Bellard | |
5fafdf24 | 5 | * |
502a5395 PB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "ppc_mac.h" | |
26 | #include "pci.h" | |
4f5e19e6 | 27 | #include "pci_host.h" |
87ecb68b | 28 | |
f3902383 BS |
29 | /* debug UniNorth */ |
30 | //#define DEBUG_UNIN | |
31 | ||
32 | #ifdef DEBUG_UNIN | |
001faf32 BS |
33 | #define UNIN_DPRINTF(fmt, ...) \ |
34 | do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) | |
f3902383 | 35 | #else |
001faf32 | 36 | #define UNIN_DPRINTF(fmt, ...) |
f3902383 BS |
37 | #endif |
38 | ||
fa0be69a AG |
39 | static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; |
40 | ||
2e29bd04 BS |
41 | typedef struct UNINState { |
42 | SysBusDevice busdev; | |
43 | PCIHostState host_state; | |
d86f0e32 | 44 | ReadWriteHandler data_handler; |
2e29bd04 | 45 | } UNINState; |
502a5395 | 46 | |
d2b59317 | 47 | static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
502a5395 | 48 | { |
fa0be69a AG |
49 | int retval; |
50 | int devfn = pci_dev->devfn & 0x00FFFFFF; | |
51 | ||
52 | retval = (((devfn >> 11) & 0x1F) + irq_num) & 3; | |
53 | ||
54 | return retval; | |
d2b59317 PB |
55 | } |
56 | ||
5d4e84c8 | 57 | static void pci_unin_set_irq(void *opaque, int irq_num, int level) |
d2b59317 | 58 | { |
5d4e84c8 JQ |
59 | qemu_irq *pic = opaque; |
60 | ||
fa0be69a AG |
61 | UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__, |
62 | unin_irq_line[irq_num], level); | |
63 | qemu_set_irq(pic[unin_irq_line[irq_num]], level); | |
502a5395 PB |
64 | } |
65 | ||
f3902383 BS |
66 | static void pci_unin_reset(void *opaque) |
67 | { | |
68 | } | |
69 | ||
d86f0e32 AG |
70 | static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) |
71 | { | |
72 | uint32_t retval; | |
73 | ||
74 | if (reg & (1u << 31)) { | |
75 | /* XXX OpenBIOS compatibility hack */ | |
76 | retval = reg | (addr & 3); | |
77 | } else if (reg & 1) { | |
78 | /* CFA1 style */ | |
79 | retval = (reg & ~7u) | (addr & 7); | |
80 | } else { | |
81 | uint32_t slot, func; | |
82 | ||
83 | /* Grab CFA0 style values */ | |
84 | slot = ffs(reg & 0xfffff800) - 1; | |
85 | func = (reg >> 8) & 7; | |
86 | ||
87 | /* ... and then convert them to x86 format */ | |
88 | /* config pointer */ | |
89 | retval = (reg & (0xff - 7)) | (addr & 7); | |
90 | /* slot */ | |
91 | retval |= slot << 11; | |
92 | /* fn */ | |
93 | retval |= func << 8; | |
94 | } | |
95 | ||
96 | ||
97 | UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n", | |
98 | reg, addr, retval); | |
99 | ||
100 | return retval; | |
101 | } | |
102 | ||
103 | static void unin_data_write(ReadWriteHandler *handler, | |
104 | pcibus_t addr, uint32_t val, int len) | |
105 | { | |
106 | UNINState *s = container_of(handler, UNINState, data_handler); | |
d86f0e32 AG |
107 | UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val); |
108 | pci_data_write(s->host_state.bus, | |
109 | unin_get_config_reg(s->host_state.config_reg, addr), | |
110 | val, len); | |
111 | } | |
112 | ||
113 | static uint32_t unin_data_read(ReadWriteHandler *handler, | |
114 | pcibus_t addr, int len) | |
115 | { | |
116 | UNINState *s = container_of(handler, UNINState, data_handler); | |
117 | uint32_t val; | |
118 | ||
119 | val = pci_data_read(s->host_state.bus, | |
120 | unin_get_config_reg(s->host_state.config_reg, addr), | |
121 | len); | |
122 | UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val); | |
d86f0e32 AG |
123 | return val; |
124 | } | |
125 | ||
81a322d4 | 126 | static int pci_unin_main_init_device(SysBusDevice *dev) |
502a5395 PB |
127 | { |
128 | UNINState *s; | |
502a5395 PB |
129 | int pci_mem_config, pci_mem_data; |
130 | ||
131 | /* Use values found on a real PowerMac */ | |
132 | /* Uninorth main bus */ | |
2e29bd04 | 133 | s = FROM_SYSBUS(UNINState, dev); |
502a5395 | 134 | |
6ebf5905 AG |
135 | pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
136 | DEVICE_LITTLE_ENDIAN); | |
d86f0e32 AG |
137 | s->data_handler.read = unin_data_read; |
138 | s->data_handler.write = unin_data_write; | |
6bef0436 | 139 | pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, |
f23cea4d | 140 | DEVICE_LITTLE_ENDIAN); |
2e29bd04 BS |
141 | sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
142 | sysbus_init_mmio(dev, 0x1000, pci_mem_data); | |
143 | ||
2e29bd04 | 144 | qemu_register_reset(pci_unin_reset, &s->host_state); |
81a322d4 | 145 | return 0; |
2e29bd04 BS |
146 | } |
147 | ||
0f921197 AG |
148 | static int pci_u3_agp_init_device(SysBusDevice *dev) |
149 | { | |
150 | UNINState *s; | |
151 | int pci_mem_config, pci_mem_data; | |
152 | ||
153 | /* Uninorth U3 AGP bus */ | |
154 | s = FROM_SYSBUS(UNINState, dev); | |
155 | ||
6ebf5905 AG |
156 | pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
157 | DEVICE_LITTLE_ENDIAN); | |
0f921197 AG |
158 | s->data_handler.read = unin_data_read; |
159 | s->data_handler.write = unin_data_write; | |
6bef0436 | 160 | pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, |
f23cea4d | 161 | DEVICE_LITTLE_ENDIAN); |
0f921197 AG |
162 | sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
163 | sysbus_init_mmio(dev, 0x1000, pci_mem_data); | |
164 | ||
0f921197 AG |
165 | qemu_register_reset(pci_unin_reset, &s->host_state); |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
81a322d4 | 170 | static int pci_unin_agp_init_device(SysBusDevice *dev) |
2e29bd04 BS |
171 | { |
172 | UNINState *s; | |
173 | int pci_mem_config, pci_mem_data; | |
174 | ||
175 | /* Uninorth AGP bus */ | |
176 | s = FROM_SYSBUS(UNINState, dev); | |
177 | ||
6ebf5905 AG |
178 | pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
179 | DEVICE_LITTLE_ENDIAN); | |
180 | pci_mem_data = pci_host_data_register_mmio(&s->host_state, | |
181 | DEVICE_LITTLE_ENDIAN); | |
2e29bd04 BS |
182 | sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
183 | sysbus_init_mmio(dev, 0x1000, pci_mem_data); | |
81a322d4 | 184 | return 0; |
2e29bd04 BS |
185 | } |
186 | ||
81a322d4 | 187 | static int pci_unin_internal_init_device(SysBusDevice *dev) |
2e29bd04 BS |
188 | { |
189 | UNINState *s; | |
190 | int pci_mem_config, pci_mem_data; | |
191 | ||
192 | /* Uninorth internal bus */ | |
193 | s = FROM_SYSBUS(UNINState, dev); | |
194 | ||
6ebf5905 AG |
195 | pci_mem_config = pci_host_conf_register_mmio(&s->host_state, |
196 | DEVICE_LITTLE_ENDIAN); | |
197 | pci_mem_data = pci_host_data_register_mmio(&s->host_state, | |
198 | DEVICE_LITTLE_ENDIAN); | |
2e29bd04 BS |
199 | sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
200 | sysbus_init_mmio(dev, 0x1000, pci_mem_data); | |
81a322d4 | 201 | return 0; |
2e29bd04 BS |
202 | } |
203 | ||
1e39101c | 204 | PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space) |
2e29bd04 BS |
205 | { |
206 | DeviceState *dev; | |
207 | SysBusDevice *s; | |
208 | UNINState *d; | |
209 | ||
210 | /* Use values found on a real PowerMac */ | |
211 | /* Uninorth main bus */ | |
18dd19a7 | 212 | dev = qdev_create(NULL, "uni-north"); |
e23a1b33 | 213 | qdev_init_nofail(dev); |
2e29bd04 BS |
214 | s = sysbus_from_qdev(dev); |
215 | d = FROM_SYSBUS(UNINState, s); | |
cdd0935c | 216 | d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", |
2e29bd04 | 217 | pci_unin_set_irq, pci_unin_map_irq, |
1e39101c AK |
218 | pic, address_space, |
219 | PCI_DEVFN(11, 0), 4); | |
2e29bd04 | 220 | |
60398748 | 221 | #if 0 |
520128bd | 222 | pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north"); |
60398748 | 223 | #endif |
2e29bd04 BS |
224 | |
225 | sysbus_mmio_map(s, 0, 0xf2800000); | |
226 | sysbus_mmio_map(s, 1, 0xf2c00000); | |
227 | ||
228 | /* DEC 21154 bridge */ | |
229 | #if 0 | |
230 | /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */ | |
520128bd | 231 | pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154"); |
2e29bd04 BS |
232 | #endif |
233 | ||
234 | /* Uninorth AGP bus */ | |
520128bd | 235 | pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp"); |
18dd19a7 | 236 | dev = qdev_create(NULL, "uni-north-agp"); |
d27d06f2 BS |
237 | qdev_init_nofail(dev); |
238 | s = sysbus_from_qdev(dev); | |
239 | sysbus_mmio_map(s, 0, 0xf0800000); | |
240 | sysbus_mmio_map(s, 1, 0xf0c00000); | |
2e29bd04 BS |
241 | |
242 | /* Uninorth internal bus */ | |
243 | #if 0 | |
244 | /* XXX: not needed for now */ | |
520128bd | 245 | pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci"); |
18dd19a7 | 246 | dev = qdev_create(NULL, "uni-north-pci"); |
d27d06f2 BS |
247 | qdev_init_nofail(dev); |
248 | s = sysbus_from_qdev(dev); | |
249 | sysbus_mmio_map(s, 0, 0xf4800000); | |
250 | sysbus_mmio_map(s, 1, 0xf4c00000); | |
2e29bd04 BS |
251 | #endif |
252 | ||
253 | return d->host_state.bus; | |
254 | } | |
255 | ||
1e39101c | 256 | PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space) |
0f921197 AG |
257 | { |
258 | DeviceState *dev; | |
259 | SysBusDevice *s; | |
260 | UNINState *d; | |
261 | ||
262 | /* Uninorth AGP bus */ | |
263 | ||
264 | dev = qdev_create(NULL, "u3-agp"); | |
265 | qdev_init_nofail(dev); | |
266 | s = sysbus_from_qdev(dev); | |
267 | d = FROM_SYSBUS(UNINState, s); | |
268 | ||
269 | d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", | |
270 | pci_unin_set_irq, pci_unin_map_irq, | |
1e39101c AK |
271 | pic, address_space, |
272 | PCI_DEVFN(11, 0), 4); | |
0f921197 AG |
273 | |
274 | sysbus_mmio_map(s, 0, 0xf0800000); | |
275 | sysbus_mmio_map(s, 1, 0xf0c00000); | |
276 | ||
277 | pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp"); | |
278 | ||
279 | return d->host_state.bus; | |
280 | } | |
281 | ||
81a322d4 | 282 | static int unin_main_pci_host_init(PCIDevice *d) |
2e29bd04 | 283 | { |
502a5395 PB |
284 | d->config[0x0C] = 0x08; // cache_line_size |
285 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 | 286 | d->config[0x34] = 0x00; // capabilities_pointer |
81a322d4 | 287 | return 0; |
2e29bd04 | 288 | } |
502a5395 | 289 | |
81a322d4 | 290 | static int unin_agp_pci_host_init(PCIDevice *d) |
2e29bd04 | 291 | { |
502a5395 PB |
292 | d->config[0x0C] = 0x08; // cache_line_size |
293 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 | 294 | // d->config[0x34] = 0x80; // capabilities_pointer |
81a322d4 | 295 | return 0; |
2e29bd04 | 296 | } |
502a5395 | 297 | |
0f921197 AG |
298 | static int u3_agp_pci_host_init(PCIDevice *d) |
299 | { | |
0f921197 AG |
300 | /* cache line size */ |
301 | d->config[0x0C] = 0x08; | |
302 | /* latency timer */ | |
303 | d->config[0x0D] = 0x10; | |
0f921197 AG |
304 | return 0; |
305 | } | |
306 | ||
81a322d4 | 307 | static int unin_internal_pci_host_init(PCIDevice *d) |
2e29bd04 | 308 | { |
502a5395 PB |
309 | d->config[0x0C] = 0x08; // cache_line_size |
310 | d->config[0x0D] = 0x10; // latency_timer | |
502a5395 | 311 | d->config[0x34] = 0x00; // capabilities_pointer |
81a322d4 | 312 | return 0; |
2e29bd04 BS |
313 | } |
314 | ||
315 | static PCIDeviceInfo unin_main_pci_host_info = { | |
18dd19a7 | 316 | .qdev.name = "uni-north", |
2e29bd04 BS |
317 | .qdev.size = sizeof(PCIDevice), |
318 | .init = unin_main_pci_host_init, | |
d7b61ecc IY |
319 | .vendor_id = PCI_VENDOR_ID_APPLE, |
320 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI, | |
321 | .revision = 0x00, | |
322 | .class_id = PCI_CLASS_BRIDGE_HOST, | |
2e29bd04 BS |
323 | }; |
324 | ||
0f921197 AG |
325 | static PCIDeviceInfo u3_agp_pci_host_info = { |
326 | .qdev.name = "u3-agp", | |
327 | .qdev.size = sizeof(PCIDevice), | |
328 | .init = u3_agp_pci_host_init, | |
d7b61ecc IY |
329 | .vendor_id = PCI_VENDOR_ID_APPLE, |
330 | .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, | |
331 | .revision = 0x00, | |
332 | .class_id = PCI_CLASS_BRIDGE_HOST, | |
0f921197 AG |
333 | }; |
334 | ||
2e29bd04 | 335 | static PCIDeviceInfo unin_agp_pci_host_info = { |
18dd19a7 | 336 | .qdev.name = "uni-north-agp", |
2e29bd04 BS |
337 | .qdev.size = sizeof(PCIDevice), |
338 | .init = unin_agp_pci_host_init, | |
d7b61ecc IY |
339 | .vendor_id = PCI_VENDOR_ID_APPLE, |
340 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, | |
341 | .revision = 0x00, | |
342 | .class_id = PCI_CLASS_BRIDGE_HOST, | |
2e29bd04 BS |
343 | }; |
344 | ||
345 | static PCIDeviceInfo unin_internal_pci_host_info = { | |
18dd19a7 | 346 | .qdev.name = "uni-north-pci", |
2e29bd04 BS |
347 | .qdev.size = sizeof(PCIDevice), |
348 | .init = unin_internal_pci_host_init, | |
d7b61ecc IY |
349 | .vendor_id = PCI_VENDOR_ID_APPLE, |
350 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI, | |
351 | .revision = 0x00, | |
352 | .class_id = PCI_CLASS_BRIDGE_HOST, | |
2e29bd04 BS |
353 | }; |
354 | ||
355 | static void unin_register_devices(void) | |
356 | { | |
18dd19a7 | 357 | sysbus_register_dev("uni-north", sizeof(UNINState), |
2e29bd04 BS |
358 | pci_unin_main_init_device); |
359 | pci_qdev_register(&unin_main_pci_host_info); | |
0f921197 AG |
360 | sysbus_register_dev("u3-agp", sizeof(UNINState), |
361 | pci_u3_agp_init_device); | |
362 | pci_qdev_register(&u3_agp_pci_host_info); | |
18dd19a7 | 363 | sysbus_register_dev("uni-north-agp", sizeof(UNINState), |
2e29bd04 BS |
364 | pci_unin_agp_init_device); |
365 | pci_qdev_register(&unin_agp_pci_host_info); | |
18dd19a7 | 366 | sysbus_register_dev("uni-north-pci", sizeof(UNINState), |
2e29bd04 BS |
367 | pci_unin_internal_init_device); |
368 | pci_qdev_register(&unin_internal_pci_host_info); | |
502a5395 | 369 | } |
2e29bd04 BS |
370 | |
371 | device_init(unin_register_devices) |