[mirror_qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

typedef struct UNINState {
    PCIHostState host_state;
    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(s->host_state.bus,
                   unin_get_config_reg(s->host_state.config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
                               unsigned len)
{
    UNINState *s = opaque;
    uint32_t val;

    val = pci_data_read(s->host_state.bus,
                        unin_get_config_reg(s->host_state.config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    PCIHostState *h;
    UNINState *s;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    h = FROM_SYSBUS(PCIHostState, dev);
    s = DO_UPCAST(UNINState, host_state, h);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);

    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;
    UNINState *s;

    /* Uninorth U3 AGP bus */
    h = FROM_SYSBUS(PCIHostState, dev);
    s = DO_UPCAST(UNINState, host_state, h);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;
    UNINState *s;

    /* Uninorth AGP bus */
    h = FROM_SYSBUS(PCIHostState, dev);
    s = DO_UPCAST(UNINState, host_state, h);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
                          &s->host_state, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    PCIHostState *h;
    UNINState *s;

    /* Uninorth internal bus */
    h = FROM_SYSBUS(PCIHostState, dev);
    s = DO_UPCAST(UNINState, host_state, h);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
                          &s->host_state, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north-pci-pcihost");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    h = FROM_SYSBUS(PCIHostState, s);
    d = DO_UPCAST(UNINState, host_state, h);
    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    d->host_state.bus = pci_register_bus(dev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic,
                                         &d->pci_mmio,
                                         address_space_io,
                                         PCI_DEVFN(11, 0), 4);

#if 0
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp-pcihost");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0),
                      "uni-north-internal-pci");
    dev = qdev_create(NULL, "uni-north-internal-pci-pcihost");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, "u3-agp-pcihost");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    h = FROM_SYSBUS(PCIHostState, s);
    d = DO_UPCAST(UNINState, host_state, h);

    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    d->host_state.bus = pci_register_bus(dev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic,
                                         &d->pci_mmio,
                                         address_space_io,
                                         PCI_DEVFN(11, 0), 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo u3_agp_pci_host_info = {
    .qdev.name = "u3-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = u3_agp_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-internal-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static SysBusDeviceInfo sysbus_unin_pci_host_info = {
    .qdev.name = "uni-north-pci-pcihost",
    .qdev.size = sizeof(UNINState),
    .init      = pci_unin_main_init_device,
};

static SysBusDeviceInfo sysbus_u3_agp_pci_host_info = {
    .qdev.name = "u3-agp-pcihost",
    .qdev.size = sizeof(UNINState),
    .init      = pci_u3_agp_init_device,
};

static SysBusDeviceInfo sysbus_unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp-pcihost",
    .qdev.size = sizeof(UNINState),
    .init      = pci_unin_agp_init_device,
};

static SysBusDeviceInfo sysbus_unin_internal_pci_host_info = {
    .qdev.name = "uni-north-internal-pci-pcihost",
    .qdev.size = sizeof(UNINState),
    .init      = pci_unin_internal_init_device,
};

static void unin_register_devices(void)
{
    sysbus_register_withprop(&sysbus_unin_pci_host_info);
    pci_qdev_register(&unin_main_pci_host_info);

    sysbus_register_withprop(&sysbus_u3_agp_pci_host_info);
    pci_qdev_register(&u3_agp_pci_host_info);

    sysbus_register_withprop(&sysbus_unin_agp_pci_host_info);
    pci_qdev_register(&unin_agp_pci_host_info);

    sysbus_register_withprop(&sysbus_unin_internal_pci_host_info);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
2e29bd04	41	typedef struct UNINState {
2e29bd04	42	PCIHostState host_state;
46f3069c BS	43	MemoryRegion pci_mmio;
46f3069c BS	44	MemoryRegion pci_hole;
2e29bd04	45	} UNINState;
502a5395	46
d2b59317	47	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	48	{
fa0be69a AG	49	int retval;
	50	int devfn = pci_dev->devfn & 0x00FFFFFF;
	51
	52	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	53
	54	return retval;
d2b59317 PB	55	}
d2b59317 PB	56
5d4e84c8	57	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	58	{
5d4e84c8 JQ	59	qemu_irq *pic = opaque;
5d4e84c8 JQ	60
fa0be69a AG	61	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	62	unin_irq_line[irq_num], level);
	63	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	64	}
502a5395 PB	65
d86f0e32 AG	66	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	67	{
	68	uint32_t retval;
	69
	70	if (reg & (1u << 31)) {
	71	/* XXX OpenBIOS compatibility hack */
	72	retval = reg \| (addr & 3);
	73	} else if (reg & 1) {
	74	/* CFA1 style */
	75	retval = (reg & ~7u) \| (addr & 7);
	76	} else {
	77	uint32_t slot, func;
	78
	79	/* Grab CFA0 style values */
	80	slot = ffs(reg & 0xfffff800) - 1;
	81	func = (reg >> 8) & 7;
	82
	83	/* ... and then convert them to x86 format */
	84	/* config pointer */
	85	retval = (reg & (0xff - 7)) \| (addr & 7);
	86	/* slot */
	87	retval \|= slot << 11;
	88	/* fn */
	89	retval \|= func << 8;
	90	}
	91
	92
	93	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	94	reg, addr, retval);
	95
	96	return retval;
	97	}
	98
d0ed8076 AK	99	static void unin_data_write(void *opaque, target_phys_addr_t addr,
d0ed8076 AK	100	uint64_t val, unsigned len)
d86f0e32	101	{
d0ed8076 AK	102	UNINState *s = opaque;
	103	UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
	104	addr, len, val);
d86f0e32 AG	105	pci_data_write(s->host_state.bus,
	106	unin_get_config_reg(s->host_state.config_reg, addr),
	107	val, len);
	108	}
	109
d0ed8076 AK	110	static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
d0ed8076 AK	111	unsigned len)
d86f0e32	112	{
d0ed8076	113	UNINState *s = opaque;
d86f0e32 AG	114	uint32_t val;
	115
	116	val = pci_data_read(s->host_state.bus,
	117	unin_get_config_reg(s->host_state.config_reg, addr),
	118	len);
d0ed8076 AK	119	UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
d0ed8076 AK	120	addr, len, val);
d86f0e32 AG	121	return val;
	122	}
	123
d0ed8076 AK	124	static const MemoryRegionOps unin_data_ops = {
	125	.read = unin_data_read,
	126	.write = unin_data_write,
	127	.endianness = DEVICE_LITTLE_ENDIAN,
	128	};
	129
81a322d4	130	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395	131	{
ff452ace	132	PCIHostState *h;
502a5395	133	UNINState *s;
502a5395 PB	134
	135	/* Use values found on a real PowerMac */
	136	/* Uninorth main bus */
ff452ace AF	137	h = FROM_SYSBUS(PCIHostState, dev);
ff452ace AF	138	s = DO_UPCAST(UNINState, host_state, h);
502a5395	139
d0ed8076 AK	140	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	141	&s->host_state, "pci-conf-idx", 0x1000);
	142	memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
	143	"pci-conf-data", 0x1000);
750ecd44 AK	144	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	145	sysbus_init_mmio(dev, &s->host_state.data_mem);
2e29bd04	146
81a322d4	147	return 0;
2e29bd04 BS	148	}
2e29bd04 BS	149
d0ed8076	150
0f921197 AG	151	static int pci_u3_agp_init_device(SysBusDevice *dev)
0f921197 AG	152	{
ff452ace	153	PCIHostState *h;
0f921197	154	UNINState *s;
0f921197 AG	155
0f921197 AG	156	/* Uninorth U3 AGP bus */
ff452ace AF	157	h = FROM_SYSBUS(PCIHostState, dev);
ff452ace AF	158	s = DO_UPCAST(UNINState, host_state, h);
0f921197	159
d0ed8076 AK	160	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	161	&s->host_state, "pci-conf-idx", 0x1000);
	162	memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
	163	"pci-conf-data", 0x1000);
750ecd44 AK	164	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	165	sysbus_init_mmio(dev, &s->host_state.data_mem);
0f921197	166
0f921197 AG	167	return 0;
	168	}
	169
81a322d4	170	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04	171	{
ff452ace	172	PCIHostState *h;
2e29bd04	173	UNINState *s;
2e29bd04 BS	174
2e29bd04 BS	175	/* Uninorth AGP bus */
ff452ace AF	176	h = FROM_SYSBUS(PCIHostState, dev);
ff452ace AF	177	s = DO_UPCAST(UNINState, host_state, h);
2e29bd04	178
d0ed8076 AK	179	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	180	&s->host_state, "pci-conf-idx", 0x1000);
	181	memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
	182	&s->host_state, "pci-conf-data", 0x1000);
750ecd44 AK	183	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	184	sysbus_init_mmio(dev, &s->host_state.data_mem);
81a322d4	185	return 0;
2e29bd04 BS	186	}
2e29bd04 BS	187
81a322d4	188	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04	189	{
ff452ace	190	PCIHostState *h;
2e29bd04	191	UNINState *s;
2e29bd04 BS	192
2e29bd04 BS	193	/* Uninorth internal bus */
ff452ace AF	194	h = FROM_SYSBUS(PCIHostState, dev);
ff452ace AF	195	s = DO_UPCAST(UNINState, host_state, h);
2e29bd04	196
d0ed8076 AK	197	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	198	&s->host_state, "pci-conf-idx", 0x1000);
	199	memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
	200	&s->host_state, "pci-conf-data", 0x1000);
750ecd44 AK	201	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	202	sysbus_init_mmio(dev, &s->host_state.data_mem);
81a322d4	203	return 0;
2e29bd04 BS	204	}
2e29bd04 BS	205
aee97b84 AK	206	PCIBus pci_pmac_init(qemu_irq pic,
	207	MemoryRegion *address_space_mem,
	208	MemoryRegion *address_space_io)
2e29bd04 BS	209	{
	210	DeviceState *dev;
	211	SysBusDevice *s;
ff452ace	212	PCIHostState *h;
2e29bd04 BS	213	UNINState *d;
	214
	215	/* Use values found on a real PowerMac */
	216	/* Uninorth main bus */
70f9c987	217	dev = qdev_create(NULL, "uni-north-pci-pcihost");
e23a1b33	218	qdev_init_nofail(dev);
2e29bd04	219	s = sysbus_from_qdev(dev);
ff452ace AF	220	h = FROM_SYSBUS(PCIHostState, s);
ff452ace AF	221	d = DO_UPCAST(UNINState, host_state, h);
46f3069c BS	222	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	223	memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
	224	0x80000000ULL, 0x70000000ULL);
	225	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	226	&d->pci_hole);
	227
ff452ace	228	d->host_state.bus = pci_register_bus(dev, "pci",
2e29bd04	229	pci_unin_set_irq, pci_unin_map_irq,
aee97b84	230	pic,
46f3069c	231	&d->pci_mmio,
aee97b84	232	address_space_io,
1e39101c	233	PCI_DEVFN(11, 0), 4);
2e29bd04	234
60398748	235	#if 0
520128bd	236	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
60398748	237	#endif
2e29bd04 BS	238
	239	sysbus_mmio_map(s, 0, 0xf2800000);
	240	sysbus_mmio_map(s, 1, 0xf2c00000);
	241
	242	/* DEC 21154 bridge */
	243	#if 0
	244	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
520128bd	245	pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	246	#endif
	247
	248	/* Uninorth AGP bus */
520128bd	249	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
70f9c987	250	dev = qdev_create(NULL, "uni-north-agp-pcihost");
d27d06f2 BS	251	qdev_init_nofail(dev);
	252	s = sysbus_from_qdev(dev);
	253	sysbus_mmio_map(s, 0, 0xf0800000);
	254	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	255
	256	/* Uninorth internal bus */
	257	#if 0
	258	/* XXX: not needed for now */
70f9c987 AF	259	pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0),
	260	"uni-north-internal-pci");
	261	dev = qdev_create(NULL, "uni-north-internal-pci-pcihost");
d27d06f2 BS	262	qdev_init_nofail(dev);
	263	s = sysbus_from_qdev(dev);
	264	sysbus_mmio_map(s, 0, 0xf4800000);
	265	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	266	#endif
	267
	268	return d->host_state.bus;
	269	}
	270
aee97b84 AK	271	PCIBus pci_pmac_u3_init(qemu_irq pic,
	272	MemoryRegion *address_space_mem,
	273	MemoryRegion *address_space_io)
0f921197 AG	274	{
	275	DeviceState *dev;
	276	SysBusDevice *s;
ff452ace	277	PCIHostState *h;
0f921197 AG	278	UNINState *d;
	279
	280	/* Uninorth AGP bus */
	281
70f9c987	282	dev = qdev_create(NULL, "u3-agp-pcihost");
0f921197 AG	283	qdev_init_nofail(dev);
0f921197 AG	284	s = sysbus_from_qdev(dev);
ff452ace AF	285	h = FROM_SYSBUS(PCIHostState, s);
ff452ace AF	286	d = DO_UPCAST(UNINState, host_state, h);
0f921197	287
46f3069c BS	288	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	289	memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
	290	0x80000000ULL, 0x70000000ULL);
	291	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	292	&d->pci_hole);
	293
ff452ace	294	d->host_state.bus = pci_register_bus(dev, "pci",
0f921197	295	pci_unin_set_irq, pci_unin_map_irq,
aee97b84	296	pic,
46f3069c	297	&d->pci_mmio,
aee97b84	298	address_space_io,
1e39101c	299	PCI_DEVFN(11, 0), 4);
0f921197 AG	300
	301	sysbus_mmio_map(s, 0, 0xf0800000);
	302	sysbus_mmio_map(s, 1, 0xf0c00000);
	303
	304	pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
	305
	306	return d->host_state.bus;
	307	}
	308
81a322d4	309	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	310	{
502a5395 PB	311	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	312	d->config[0x0D] = 0x10; // latency_timer
502a5395	313	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	314	return 0;
2e29bd04	315	}
502a5395	316
81a322d4	317	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	318	{
502a5395 PB	319	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	320	d->config[0x0D] = 0x10; // latency_timer
502a5395	321	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	322	return 0;
2e29bd04	323	}
502a5395	324
0f921197 AG	325	static int u3_agp_pci_host_init(PCIDevice *d)
0f921197 AG	326	{
0f921197 AG	327	/* cache line size */
	328	d->config[0x0C] = 0x08;
	329	/* latency timer */
	330	d->config[0x0D] = 0x10;
0f921197 AG	331	return 0;
	332	}
	333
81a322d4	334	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	335	{
502a5395 PB	336	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	337	d->config[0x0D] = 0x10; // latency_timer
502a5395	338	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	339	return 0;
2e29bd04 BS	340	}
	341
	342	static PCIDeviceInfo unin_main_pci_host_info = {
70f9c987	343	.qdev.name = "uni-north-pci",
2e29bd04 BS	344	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	345	.init = unin_main_pci_host_init,
d7b61ecc IY	346	.vendor_id = PCI_VENDOR_ID_APPLE,
	347	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
	348	.revision = 0x00,
	349	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	350	};
2e29bd04 BS	351
0f921197 AG	352	static PCIDeviceInfo u3_agp_pci_host_info = {
	353	.qdev.name = "u3-agp",
	354	.qdev.size = sizeof(PCIDevice),
	355	.init = u3_agp_pci_host_init,
d7b61ecc IY	356	.vendor_id = PCI_VENDOR_ID_APPLE,
	357	.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
	358	.revision = 0x00,
	359	.class_id = PCI_CLASS_BRIDGE_HOST,
0f921197 AG	360	};
0f921197 AG	361
2e29bd04	362	static PCIDeviceInfo unin_agp_pci_host_info = {
18dd19a7	363	.qdev.name = "uni-north-agp",
2e29bd04 BS	364	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	365	.init = unin_agp_pci_host_init,
d7b61ecc IY	366	.vendor_id = PCI_VENDOR_ID_APPLE,
	367	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
	368	.revision = 0x00,
	369	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	370	};
	371
	372	static PCIDeviceInfo unin_internal_pci_host_info = {
70f9c987	373	.qdev.name = "uni-north-internal-pci",
2e29bd04 BS	374	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	375	.init = unin_internal_pci_host_init,
d7b61ecc IY	376	.vendor_id = PCI_VENDOR_ID_APPLE,
	377	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
	378	.revision = 0x00,
	379	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	380	};
2e29bd04 BS	381
70f9c987 AF	382	static SysBusDeviceInfo sysbus_unin_pci_host_info = {
	383	.qdev.name = "uni-north-pci-pcihost",
	384	.qdev.size = sizeof(UNINState),
	385	.init = pci_unin_main_init_device,
	386	};
	387
	388	static SysBusDeviceInfo sysbus_u3_agp_pci_host_info = {
	389	.qdev.name = "u3-agp-pcihost",
	390	.qdev.size = sizeof(UNINState),
	391	.init = pci_u3_agp_init_device,
	392	};
	393
	394	static SysBusDeviceInfo sysbus_unin_agp_pci_host_info = {
	395	.qdev.name = "uni-north-agp-pcihost",
	396	.qdev.size = sizeof(UNINState),
	397	.init = pci_unin_agp_init_device,
	398	};
	399
	400	static SysBusDeviceInfo sysbus_unin_internal_pci_host_info = {
	401	.qdev.name = "uni-north-internal-pci-pcihost",
	402	.qdev.size = sizeof(UNINState),
	403	.init = pci_unin_internal_init_device,
	404	};
	405
2e29bd04 BS	406	static void unin_register_devices(void)
2e29bd04 BS	407	{
70f9c987	408	sysbus_register_withprop(&sysbus_unin_pci_host_info);
2e29bd04	409	pci_qdev_register(&unin_main_pci_host_info);
70f9c987 AF	410
70f9c987 AF	411	sysbus_register_withprop(&sysbus_u3_agp_pci_host_info);
0f921197	412	pci_qdev_register(&u3_agp_pci_host_info);
70f9c987 AF	413
70f9c987 AF	414	sysbus_register_withprop(&sysbus_unin_agp_pci_host_info);
2e29bd04	415	pci_qdev_register(&unin_agp_pci_host_info);
70f9c987 AF	416
70f9c987 AF	417	sysbus_register_withprop(&sysbus_unin_internal_pci_host_info);
2e29bd04	418	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	419	}
2e29bd04 BS	420
2e29bd04 BS	421	device_init(unin_register_devices)