[mirror_qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
    ReadWriteHandler data_handler;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static void pci_unin_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;

    pci_device_save(d, f);
}

static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;

    if (version_id != 1)
        return -EINVAL;

    return pci_device_load(d, f);
}

static void pci_unin_reset(void *opaque)
{
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(ReadWriteHandler *handler,
                            pcibus_t addr, uint32_t val, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    val = qemu_bswap_len(val, len);
    UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    pci_data_write(s->host_state.bus,
                   unin_get_config_reg(s->host_state.config_reg, addr),
                   val, len);
}

static uint32_t unin_data_read(ReadWriteHandler *handler,
                               pcibus_t addr, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    uint32_t val;

    val = pci_data_read(s->host_state.bus,
                        unin_get_config_reg(s->host_state.config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    val = qemu_bswap_len(val, len);
    return val;
}

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm(&dev->qdev, "uninorth", 0, 1,
                    pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}

static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth U3 AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm(&dev->qdev, "uninorth", 0, 1,
                    pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, PCI_DEVFN(11, 0), 4);

#if 0
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
    dev = qdev_create(NULL, "uni-north-pci");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, "u3-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);

    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, PCI_DEVFN(11, 0), 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
    /* revision */
    d->config[0x08] = 0x00;
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
};

static PCIDeviceInfo u3_agp_pci_host_info = {
    .qdev.name = "u3-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = u3_agp_pci_host_init,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("uni-north", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("u3-agp", sizeof(UNINState),
                        pci_u3_agp_init_device);
    pci_qdev_register(&u3_agp_pci_host_info);
    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("uni-north-pci", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
2e29bd04 BS	41	typedef struct UNINState {
	42	SysBusDevice busdev;
	43	PCIHostState host_state;
d86f0e32	44	ReadWriteHandler data_handler;
2e29bd04	45	} UNINState;
502a5395	46
d2b59317	47	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	48	{
fa0be69a AG	49	int retval;
	50	int devfn = pci_dev->devfn & 0x00FFFFFF;
	51
	52	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	53
	54	return retval;
d2b59317 PB	55	}
d2b59317 PB	56
5d4e84c8	57	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	58	{
5d4e84c8 JQ	59	qemu_irq *pic = opaque;
5d4e84c8 JQ	60
fa0be69a AG	61	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	62	unin_irq_line[irq_num], level);
	63	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	64	}
502a5395 PB	65
f3902383 BS	66	static void pci_unin_save(QEMUFile* f, void *opaque)
	67	{
	68	PCIDevice *d = opaque;
	69
	70	pci_device_save(d, f);
	71	}
	72
	73	static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
	74	{
	75	PCIDevice *d = opaque;
	76
	77	if (version_id != 1)
	78	return -EINVAL;
	79
	80	return pci_device_load(d, f);
	81	}
	82
	83	static void pci_unin_reset(void *opaque)
	84	{
	85	}
	86
d86f0e32 AG	87	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	88	{
	89	uint32_t retval;
	90
	91	if (reg & (1u << 31)) {
	92	/* XXX OpenBIOS compatibility hack */
	93	retval = reg \| (addr & 3);
	94	} else if (reg & 1) {
	95	/* CFA1 style */
	96	retval = (reg & ~7u) \| (addr & 7);
	97	} else {
	98	uint32_t slot, func;
	99
	100	/* Grab CFA0 style values */
	101	slot = ffs(reg & 0xfffff800) - 1;
	102	func = (reg >> 8) & 7;
	103
	104	/* ... and then convert them to x86 format */
	105	/* config pointer */
	106	retval = (reg & (0xff - 7)) \| (addr & 7);
	107	/* slot */
	108	retval \|= slot << 11;
	109	/* fn */
	110	retval \|= func << 8;
	111	}
	112
	113
	114	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	115	reg, addr, retval);
	116
	117	return retval;
	118	}
	119
	120	static void unin_data_write(ReadWriteHandler *handler,
	121	pcibus_t addr, uint32_t val, int len)
	122	{
	123	UNINState *s = container_of(handler, UNINState, data_handler);
d86f0e32	124	val = qemu_bswap_len(val, len);
d86f0e32 AG	125	UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
	126	pci_data_write(s->host_state.bus,
	127	unin_get_config_reg(s->host_state.config_reg, addr),
	128	val, len);
	129	}
	130
	131	static uint32_t unin_data_read(ReadWriteHandler *handler,
	132	pcibus_t addr, int len)
	133	{
	134	UNINState *s = container_of(handler, UNINState, data_handler);
	135	uint32_t val;
	136
	137	val = pci_data_read(s->host_state.bus,
	138	unin_get_config_reg(s->host_state.config_reg, addr),
	139	len);
	140	UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
d86f0e32	141	val = qemu_bswap_len(val, len);
d86f0e32 AG	142	return val;
	143	}
	144
81a322d4	145	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	146	{
502a5395 PB	147	UNINState *s;
502a5395 PB	148	int pci_mem_config, pci_mem_data;
	149
	150	/* Use values found on a real PowerMac */
	151	/* Uninorth main bus */
2e29bd04	152	s = FROM_SYSBUS(UNINState, dev);
502a5395	153
952760bb	154	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
d86f0e32 AG	155	s->data_handler.read = unin_data_read;
	156	s->data_handler.write = unin_data_write;
	157	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
2e29bd04 BS	158	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	159	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	160
0be71e32 AW	161	register_savevm(&dev->qdev, "uninorth", 0, 1,
0be71e32 AW	162	pci_unin_save, pci_unin_load, &s->host_state);
2e29bd04	163	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	164	return 0;
2e29bd04 BS	165	}
2e29bd04 BS	166
0f921197 AG	167	static int pci_u3_agp_init_device(SysBusDevice *dev)
	168	{
	169	UNINState *s;
	170	int pci_mem_config, pci_mem_data;
	171
	172	/* Uninorth U3 AGP bus */
	173	s = FROM_SYSBUS(UNINState, dev);
	174
952760bb	175	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
0f921197 AG	176	s->data_handler.read = unin_data_read;
	177	s->data_handler.write = unin_data_write;
	178	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler);
	179	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	180	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	181
0be71e32 AW	182	register_savevm(&dev->qdev, "uninorth", 0, 1,
0be71e32 AW	183	pci_unin_save, pci_unin_load, &s->host_state);
0f921197 AG	184	qemu_register_reset(pci_unin_reset, &s->host_state);
	185
	186	return 0;
	187	}
	188
81a322d4	189	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	190	{
	191	UNINState *s;
	192	int pci_mem_config, pci_mem_data;
	193
	194	/* Uninorth AGP bus */
	195	s = FROM_SYSBUS(UNINState, dev);
	196
952760bb BS	197	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
952760bb BS	198	pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
2e29bd04 BS	199	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	200	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	201	return 0;
2e29bd04 BS	202	}
2e29bd04 BS	203
81a322d4	204	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	205	{
	206	UNINState *s;
	207	int pci_mem_config, pci_mem_data;
	208
	209	/* Uninorth internal bus */
	210	s = FROM_SYSBUS(UNINState, dev);
	211
952760bb BS	212	pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
952760bb BS	213	pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
2e29bd04 BS	214	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	215	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	216	return 0;
2e29bd04 BS	217	}
	218
	219	PCIBus pci_pmac_init(qemu_irq pic)
	220	{
	221	DeviceState *dev;
	222	SysBusDevice *s;
	223	UNINState *d;
	224
	225	/* Use values found on a real PowerMac */
	226	/* Uninorth main bus */
18dd19a7	227	dev = qdev_create(NULL, "uni-north");
e23a1b33	228	qdev_init_nofail(dev);
2e29bd04 BS	229	s = sysbus_from_qdev(dev);
2e29bd04 BS	230	d = FROM_SYSBUS(UNINState, s);
cdd0935c	231	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04	232	pci_unin_set_irq, pci_unin_map_irq,
520128bd	233	pic, PCI_DEVFN(11, 0), 4);
2e29bd04	234
60398748	235	#if 0
520128bd	236	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
60398748	237	#endif
2e29bd04 BS	238
	239	sysbus_mmio_map(s, 0, 0xf2800000);
	240	sysbus_mmio_map(s, 1, 0xf2c00000);
	241
	242	/* DEC 21154 bridge */
	243	#if 0
	244	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
520128bd	245	pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	246	#endif
	247
	248	/* Uninorth AGP bus */
520128bd	249	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
18dd19a7	250	dev = qdev_create(NULL, "uni-north-agp");
d27d06f2 BS	251	qdev_init_nofail(dev);
	252	s = sysbus_from_qdev(dev);
	253	sysbus_mmio_map(s, 0, 0xf0800000);
	254	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	255
	256	/* Uninorth internal bus */
	257	#if 0
	258	/* XXX: not needed for now */
520128bd	259	pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
18dd19a7	260	dev = qdev_create(NULL, "uni-north-pci");
d27d06f2 BS	261	qdev_init_nofail(dev);
	262	s = sysbus_from_qdev(dev);
	263	sysbus_mmio_map(s, 0, 0xf4800000);
	264	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	265	#endif
	266
	267	return d->host_state.bus;
	268	}
	269
0f921197 AG	270	PCIBus pci_pmac_u3_init(qemu_irq pic)
	271	{
	272	DeviceState *dev;
	273	SysBusDevice *s;
	274	UNINState *d;
	275
	276	/* Uninorth AGP bus */
	277
	278	dev = qdev_create(NULL, "u3-agp");
	279	qdev_init_nofail(dev);
	280	s = sysbus_from_qdev(dev);
	281	d = FROM_SYSBUS(UNINState, s);
	282
	283	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
	284	pci_unin_set_irq, pci_unin_map_irq,
520128bd	285	pic, PCI_DEVFN(11, 0), 4);
0f921197 AG	286
	287	sysbus_mmio_map(s, 0, 0xf0800000);
	288	sysbus_mmio_map(s, 1, 0xf0c00000);
	289
	290	pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
	291
	292	return d->host_state.bus;
	293	}
	294
81a322d4	295	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	296	{
deb54399	297	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	298	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
502a5395	299	d->config[0x08] = 0x00; // revision
173a543b	300	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	301	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	302	d->config[0x0D] = 0x10; // latency_timer
502a5395	303	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	304	return 0;
2e29bd04	305	}
502a5395	306
81a322d4	307	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	308	{
deb54399 AL	309	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
deb54399 AL	310	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
502a5395	311	d->config[0x08] = 0x00; // revision
173a543b	312	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	313	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	314	d->config[0x0D] = 0x10; // latency_timer
502a5395	315	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	316	return 0;
2e29bd04	317	}
502a5395	318
0f921197 AG	319	static int u3_agp_pci_host_init(PCIDevice *d)
	320	{
	321	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
	322	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
	323	/* revision */
	324	d->config[0x08] = 0x00;
	325	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
	326	/* cache line size */
	327	d->config[0x0C] = 0x08;
	328	/* latency timer */
	329	d->config[0x0D] = 0x10;
0f921197 AG	330	return 0;
	331	}
	332
81a322d4	333	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	334	{
deb54399	335	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	336	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
502a5395	337	d->config[0x08] = 0x00; // revision
173a543b	338	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	339	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	340	d->config[0x0D] = 0x10; // latency_timer
502a5395	341	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	342	return 0;
2e29bd04 BS	343	}
	344
	345	static PCIDeviceInfo unin_main_pci_host_info = {
18dd19a7	346	.qdev.name = "uni-north",
2e29bd04 BS	347	.qdev.size = sizeof(PCIDevice),
	348	.init = unin_main_pci_host_init,
	349	};
	350
0f921197 AG	351	static PCIDeviceInfo u3_agp_pci_host_info = {
	352	.qdev.name = "u3-agp",
	353	.qdev.size = sizeof(PCIDevice),
	354	.init = u3_agp_pci_host_init,
	355	};
	356
2e29bd04	357	static PCIDeviceInfo unin_agp_pci_host_info = {
18dd19a7	358	.qdev.name = "uni-north-agp",
2e29bd04 BS	359	.qdev.size = sizeof(PCIDevice),
	360	.init = unin_agp_pci_host_init,
	361	};
	362
	363	static PCIDeviceInfo unin_internal_pci_host_info = {
18dd19a7	364	.qdev.name = "uni-north-pci",
2e29bd04 BS	365	.qdev.size = sizeof(PCIDevice),
	366	.init = unin_internal_pci_host_init,
	367	};
	368
	369	static void unin_register_devices(void)
	370	{
18dd19a7	371	sysbus_register_dev("uni-north", sizeof(UNINState),
2e29bd04 BS	372	pci_unin_main_init_device);
2e29bd04 BS	373	pci_qdev_register(&unin_main_pci_host_info);
0f921197 AG	374	sysbus_register_dev("u3-agp", sizeof(UNINState),
	375	pci_u3_agp_init_device);
	376	pci_qdev_register(&u3_agp_pci_host_info);
18dd19a7	377	sysbus_register_dev("uni-north-agp", sizeof(UNINState),
2e29bd04 BS	378	pci_unin_agp_init_device);
2e29bd04 BS	379	pci_qdev_register(&unin_agp_pci_host_info);
18dd19a7	380	sysbus_register_dev("uni-north-pci", sizeof(UNINState),
2e29bd04 BS	381	pci_unin_internal_init_device);
2e29bd04 BS	382	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	383	}
2e29bd04 BS	384
2e29bd04 BS	385	device_init(unin_register_devices)