]>
Commit | Line | Data |
---|---|---|
94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
522079dd HG |
5 | * Copyright(c) 2011-2012 Red Hat, Inc. |
6 | * | |
7 | * Red Hat Authors: | |
8 | * Gerd Hoffmann <kraxel@redhat.com> | |
9 | * Hans de Goede <hdegoede@redhat.com> | |
94527ead GH |
10 | * |
11 | * EHCI project was started by Mark Burkley, with contributions by | |
12 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
13 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
14 | * | |
15 | * | |
16 | * This library is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU Lesser General Public | |
18 | * License as published by the Free Software Foundation; either | |
19 | * version 2 of the License, or(at your option) any later version. | |
20 | * | |
21 | * This library is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
24 | * Lesser General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
28 | */ |
29 | ||
0bf96f94 | 30 | #include "hw/usb/hcd-ehci.h" |
94527ead | 31 | |
94527ead | 32 | /* Capability Registers Base Address - section 2.2 */ |
27a11324 PC |
33 | #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ |
34 | #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ | |
35 | #define HCSPARAMS 0x0004 /* 4-bytes, structural params */ | |
36 | #define HCCPARAMS 0x0008 /* 4-bytes, capability params */ | |
94527ead | 37 | #define EECP HCCPARAMS + 1 |
27a11324 PC |
38 | #define HCSPPORTROUTE1 0x000c |
39 | #define HCSPPORTROUTE2 0x0010 | |
94527ead | 40 | |
27a11324 | 41 | #define USBCMD 0x0000 |
94527ead GH |
42 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop |
43 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
44 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
45 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
46 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
47 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
48 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
49 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
50 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
51 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
52 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
53 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
54 | ||
27a11324 | 55 | #define USBSTS 0x0004 |
94527ead GH |
56 | #define USBSTS_RO_MASK 0x0000003f |
57 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
58 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
59 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
60 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
61 | #define USBSTS_HSE (1 << 4) // Host System Error | |
62 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
63 | #define USBSTS_HALT (1 << 12) // HC Halted | |
64 | #define USBSTS_REC (1 << 13) // Reclamation | |
65 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
66 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
67 | ||
68 | /* | |
69 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
70 | * so no need to redefine here. | |
71 | */ | |
27a11324 | 72 | #define USBINTR 0x0008 |
94527ead GH |
73 | #define USBINTR_MASK 0x0000003f |
74 | ||
27a11324 PC |
75 | #define FRINDEX 0x000c |
76 | #define CTRLDSSEGMENT 0x0010 | |
77 | #define PERIODICLISTBASE 0x0014 | |
78 | #define ASYNCLISTADDR 0x0018 | |
94527ead GH |
79 | #define ASYNCLISTADDR_MASK 0xffffffe0 |
80 | ||
27a11324 | 81 | #define CONFIGFLAG 0x0040 |
94527ead | 82 | |
94527ead | 83 | /* |
c44fd61c | 84 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
85 | * written to us by software |
86 | */ | |
a0a3167a | 87 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
88 | #define PORTSC_RWC_MASK 0x0000002a |
89 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
90 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
91 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
92 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
93 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
94 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
95 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
96 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
97 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
98 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
99 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
100 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
101 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
102 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
103 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
104 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
105 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
106 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
107 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
108 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
109 | ||
110 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 111 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
112 | |
113 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
94527ead | 114 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
94527ead | 115 | #define MAX_QH 100 // Max allowable queue heads in a chain |
8f74ed1e | 116 | #define MIN_FR_PER_TICK 3 // Min frames to process when catching up |
80826240 | 117 | #define PERIODIC_ACTIVE 64 |
94527ead GH |
118 | |
119 | /* Internal periodic / asynchronous schedule state machine states | |
120 | */ | |
121 | typedef enum { | |
122 | EST_INACTIVE = 1000, | |
123 | EST_ACTIVE, | |
124 | EST_EXECUTING, | |
125 | EST_SLEEPING, | |
126 | /* The following states are internal to the state machine function | |
127 | */ | |
128 | EST_WAITLISTHEAD, | |
129 | EST_FETCHENTRY, | |
130 | EST_FETCHQH, | |
131 | EST_FETCHITD, | |
2fe80192 | 132 | EST_FETCHSITD, |
94527ead GH |
133 | EST_ADVANCEQUEUE, |
134 | EST_FETCHQTD, | |
135 | EST_EXECUTE, | |
136 | EST_WRITEBACK, | |
137 | EST_HORIZONTALQH | |
138 | } EHCI_STATES; | |
139 | ||
140 | /* macros for accessing fields within next link pointer entry */ | |
141 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
142 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
143 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
144 | ||
145 | /* link pointer types */ | |
146 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
147 | #define NLPTR_TYPE_QH 1 // queue head | |
148 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
149 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
150 | ||
94527ead | 151 | #define SET_LAST_RUN_CLOCK(s) \ |
adddecb1 | 152 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
153 | |
154 | /* nifty macros from Arnon's EHCI version */ | |
155 | #define get_field(data, field) \ | |
156 | (((data) & field##_MASK) >> field##_SH) | |
157 | ||
158 | #define set_field(data, newval, field) do { \ | |
159 | uint32_t val = *data; \ | |
160 | val &= ~ field##_MASK; \ | |
161 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
162 | *data = val; \ | |
163 | } while(0) | |
164 | ||
26d53979 | 165 | static const char *ehci_state_names[] = { |
aac882e7 GH |
166 | [EST_INACTIVE] = "INACTIVE", |
167 | [EST_ACTIVE] = "ACTIVE", | |
168 | [EST_EXECUTING] = "EXECUTING", | |
169 | [EST_SLEEPING] = "SLEEPING", | |
170 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
171 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
172 | [EST_FETCHQH] = "FETCH QH", | |
173 | [EST_FETCHITD] = "FETCH ITD", | |
174 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
175 | [EST_FETCHQTD] = "FETCH QTD", | |
176 | [EST_EXECUTE] = "EXECUTE", | |
177 | [EST_WRITEBACK] = "WRITEBACK", | |
178 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
179 | }; |
180 | ||
181 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
182 | [USBCMD] = "USBCMD", |
183 | [USBSTS] = "USBSTS", | |
184 | [USBINTR] = "USBINTR", | |
185 | [FRINDEX] = "FRINDEX", | |
186 | [PERIODICLISTBASE] = "P-LIST BASE", | |
187 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
aac882e7 | 188 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 189 | }; |
94527ead | 190 | |
4b63a0df HG |
191 | static int ehci_state_executing(EHCIQueue *q); |
192 | static int ehci_state_writeback(EHCIQueue *q); | |
ff80ce59 | 193 | static int ehci_state_advqueue(EHCIQueue *q); |
b4ea8664 | 194 | static int ehci_fill_queue(EHCIPacket *p); |
4b63a0df | 195 | |
26d53979 | 196 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 197 | { |
26d53979 GH |
198 | if (nr < len && n[nr] != NULL) { |
199 | return n[nr]; | |
94527ead | 200 | } else { |
26d53979 | 201 | return "unknown"; |
94527ead GH |
202 | } |
203 | } | |
94527ead | 204 | |
26d53979 GH |
205 | static const char *state2str(uint32_t state) |
206 | { | |
207 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
208 | } | |
209 | ||
a8170e5e | 210 | static const char *addr2str(hwaddr addr) |
26d53979 | 211 | { |
27a11324 | 212 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); |
26d53979 GH |
213 | } |
214 | ||
439a97cc GH |
215 | static void ehci_trace_usbsts(uint32_t mask, int state) |
216 | { | |
217 | /* interrupts */ | |
218 | if (mask & USBSTS_INT) { | |
219 | trace_usb_ehci_usbsts("INT", state); | |
220 | } | |
221 | if (mask & USBSTS_ERRINT) { | |
222 | trace_usb_ehci_usbsts("ERRINT", state); | |
223 | } | |
224 | if (mask & USBSTS_PCD) { | |
225 | trace_usb_ehci_usbsts("PCD", state); | |
226 | } | |
227 | if (mask & USBSTS_FLR) { | |
228 | trace_usb_ehci_usbsts("FLR", state); | |
229 | } | |
230 | if (mask & USBSTS_HSE) { | |
231 | trace_usb_ehci_usbsts("HSE", state); | |
232 | } | |
233 | if (mask & USBSTS_IAA) { | |
234 | trace_usb_ehci_usbsts("IAA", state); | |
235 | } | |
236 | ||
237 | /* status */ | |
238 | if (mask & USBSTS_HALT) { | |
239 | trace_usb_ehci_usbsts("HALT", state); | |
240 | } | |
241 | if (mask & USBSTS_REC) { | |
242 | trace_usb_ehci_usbsts("REC", state); | |
243 | } | |
244 | if (mask & USBSTS_PSS) { | |
245 | trace_usb_ehci_usbsts("PSS", state); | |
246 | } | |
247 | if (mask & USBSTS_ASS) { | |
248 | trace_usb_ehci_usbsts("ASS", state); | |
249 | } | |
250 | } | |
251 | ||
252 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
253 | { | |
254 | if ((s->usbsts & mask) == mask) { | |
255 | return; | |
256 | } | |
257 | ehci_trace_usbsts(mask, 1); | |
258 | s->usbsts |= mask; | |
259 | } | |
260 | ||
261 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
262 | { | |
263 | if ((s->usbsts & mask) == 0) { | |
264 | return; | |
265 | } | |
266 | ehci_trace_usbsts(mask, 0); | |
267 | s->usbsts &= ~mask; | |
268 | } | |
94527ead | 269 | |
7efc17af GH |
270 | /* update irq line */ |
271 | static inline void ehci_update_irq(EHCIState *s) | |
94527ead GH |
272 | { |
273 | int level = 0; | |
274 | ||
94527ead GH |
275 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { |
276 | level = 1; | |
277 | } | |
278 | ||
7efc17af | 279 | trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); |
94527ead GH |
280 | qemu_set_irq(s->irq, level); |
281 | } | |
282 | ||
7efc17af GH |
283 | /* flag interrupt condition */ |
284 | static inline void ehci_raise_irq(EHCIState *s, int intr) | |
94527ead | 285 | { |
6d3b6d3d GH |
286 | if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) { |
287 | s->usbsts |= intr; | |
288 | ehci_update_irq(s); | |
289 | } else { | |
290 | s->usbsts_pending |= intr; | |
291 | } | |
94527ead GH |
292 | } |
293 | ||
7efc17af GH |
294 | /* |
295 | * Commit pending interrupts (added via ehci_raise_irq), | |
296 | * at the rate allowed by "Interrupt Threshold Control". | |
297 | */ | |
298 | static inline void ehci_commit_irq(EHCIState *s) | |
94527ead | 299 | { |
7efc17af GH |
300 | uint32_t itc; |
301 | ||
94527ead GH |
302 | if (!s->usbsts_pending) { |
303 | return; | |
304 | } | |
7efc17af GH |
305 | if (s->usbsts_frindex > s->frindex) { |
306 | return; | |
307 | } | |
308 | ||
309 | itc = (s->usbcmd >> 16) & 0xff; | |
310 | s->usbsts |= s->usbsts_pending; | |
94527ead | 311 | s->usbsts_pending = 0; |
7efc17af GH |
312 | s->usbsts_frindex = s->frindex + itc; |
313 | ehci_update_irq(s); | |
94527ead GH |
314 | } |
315 | ||
daf25307 GH |
316 | static void ehci_update_halt(EHCIState *s) |
317 | { | |
318 | if (s->usbcmd & USBCMD_RUNSTOP) { | |
319 | ehci_clear_usbsts(s, USBSTS_HALT); | |
320 | } else { | |
321 | if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { | |
322 | ehci_set_usbsts(s, USBSTS_HALT); | |
323 | } | |
324 | } | |
325 | } | |
326 | ||
26d53979 GH |
327 | static void ehci_set_state(EHCIState *s, int async, int state) |
328 | { | |
329 | if (async) { | |
330 | trace_usb_ehci_state("async", state2str(state)); | |
331 | s->astate = state; | |
b53f685d GH |
332 | if (s->astate == EST_INACTIVE) { |
333 | ehci_clear_usbsts(s, USBSTS_ASS); | |
daf25307 | 334 | ehci_update_halt(s); |
b53f685d GH |
335 | } else { |
336 | ehci_set_usbsts(s, USBSTS_ASS); | |
337 | } | |
26d53979 GH |
338 | } else { |
339 | trace_usb_ehci_state("periodic", state2str(state)); | |
340 | s->pstate = state; | |
b53f685d GH |
341 | if (s->pstate == EST_INACTIVE) { |
342 | ehci_clear_usbsts(s, USBSTS_PSS); | |
daf25307 | 343 | ehci_update_halt(s); |
b53f685d GH |
344 | } else { |
345 | ehci_set_usbsts(s, USBSTS_PSS); | |
346 | } | |
26d53979 GH |
347 | } |
348 | } | |
349 | ||
350 | static int ehci_get_state(EHCIState *s, int async) | |
351 | { | |
352 | return async ? s->astate : s->pstate; | |
353 | } | |
354 | ||
0122f472 GH |
355 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
356 | { | |
357 | if (async) { | |
358 | s->a_fetch_addr = addr; | |
359 | } else { | |
360 | s->p_fetch_addr = addr; | |
361 | } | |
362 | } | |
363 | ||
364 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
365 | { | |
366 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
367 | } | |
368 | ||
a8170e5e | 369 | static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh) |
26d53979 | 370 | { |
025b168c GH |
371 | /* need three here due to argument count limits */ |
372 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
373 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
374 | trace_usb_ehci_qh_fields(addr, | |
375 | get_field(qh->epchar, QH_EPCHAR_RL), | |
376 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
377 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
378 | get_field(qh->epchar, QH_EPCHAR_EP), | |
379 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
380 | trace_usb_ehci_qh_bits(addr, | |
381 | (bool)(qh->epchar & QH_EPCHAR_C), | |
382 | (bool)(qh->epchar & QH_EPCHAR_H), | |
383 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
384 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
385 | } |
386 | ||
a8170e5e | 387 | static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd) |
26d53979 | 388 | { |
025b168c GH |
389 | /* need three here due to argument count limits */ |
390 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
391 | trace_usb_ehci_qtd_fields(addr, | |
392 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
393 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
394 | get_field(qtd->token, QTD_TOKEN_CERR), | |
395 | get_field(qtd->token, QTD_TOKEN_PID)); | |
396 | trace_usb_ehci_qtd_bits(addr, | |
397 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
398 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
399 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
400 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
401 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
402 | } |
403 | ||
a8170e5e | 404 | static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd) |
26d53979 | 405 | { |
e654887f GH |
406 | trace_usb_ehci_itd(addr, itd->next, |
407 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
408 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
409 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
410 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
411 | } |
412 | ||
a8170e5e | 413 | static void ehci_trace_sitd(EHCIState *s, hwaddr addr, |
2fe80192 GH |
414 | EHCIsitd *sitd) |
415 | { | |
416 | trace_usb_ehci_sitd(addr, sitd->next, | |
417 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
418 | } | |
419 | ||
5c514681 GH |
420 | static void ehci_trace_guest_bug(EHCIState *s, const char *message) |
421 | { | |
422 | trace_usb_ehci_guest_bug(message); | |
423 | fprintf(stderr, "ehci warning: %s\n", message); | |
424 | } | |
425 | ||
ec807d12 GH |
426 | static inline bool ehci_enabled(EHCIState *s) |
427 | { | |
428 | return s->usbcmd & USBCMD_RUNSTOP; | |
429 | } | |
430 | ||
431 | static inline bool ehci_async_enabled(EHCIState *s) | |
432 | { | |
433 | return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); | |
434 | } | |
435 | ||
436 | static inline bool ehci_periodic_enabled(EHCIState *s) | |
437 | { | |
438 | return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); | |
439 | } | |
440 | ||
eb36a88e GH |
441 | /* packet management */ |
442 | ||
443 | static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) | |
444 | { | |
445 | EHCIPacket *p; | |
446 | ||
eb36a88e GH |
447 | p = g_new0(EHCIPacket, 1); |
448 | p->queue = q; | |
449 | usb_packet_init(&p->packet); | |
450 | QTAILQ_INSERT_TAIL(&q->packets, p, next); | |
451 | trace_usb_ehci_packet_action(p->queue, p, "alloc"); | |
452 | return p; | |
453 | } | |
454 | ||
455 | static void ehci_free_packet(EHCIPacket *p) | |
456 | { | |
4b63a0df | 457 | if (p->async == EHCI_ASYNC_FINISHED) { |
30d68cf6 HG |
458 | EHCIQueue *q = p->queue; |
459 | int state = ehci_get_state(q->ehci, q->async); | |
4b63a0df HG |
460 | /* This is a normal, but rare condition (cancel racing completion) */ |
461 | fprintf(stderr, "EHCI: Warning packet completed but not processed\n"); | |
30d68cf6 HG |
462 | ehci_state_executing(q); |
463 | ehci_state_writeback(q); | |
ff80ce59 HG |
464 | if (!(q->qh.token & QTD_TOKEN_HALT)) { |
465 | ehci_state_advqueue(q); | |
466 | } | |
30d68cf6 | 467 | ehci_set_state(q->ehci, q->async, state); |
4b63a0df HG |
468 | /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */ |
469 | return; | |
470 | } | |
616789cd | 471 | trace_usb_ehci_packet_action(p->queue, p, "free"); |
ef5b2344 HG |
472 | if (p->async == EHCI_ASYNC_INITIALIZED) { |
473 | usb_packet_unmap(&p->packet, &p->sgl); | |
474 | qemu_sglist_destroy(&p->sgl); | |
475 | } | |
616789cd GH |
476 | if (p->async == EHCI_ASYNC_INFLIGHT) { |
477 | usb_cancel_packet(&p->packet); | |
478 | usb_packet_unmap(&p->packet, &p->sgl); | |
479 | qemu_sglist_destroy(&p->sgl); | |
480 | } | |
eb36a88e GH |
481 | QTAILQ_REMOVE(&p->queue->packets, p, next); |
482 | usb_packet_cleanup(&p->packet); | |
483 | g_free(p); | |
484 | } | |
485 | ||
8ac6d699 GH |
486 | /* queue management */ |
487 | ||
8f6d5e26 | 488 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
8ac6d699 | 489 | { |
df5d5c5c | 490 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
491 | EHCIQueue *q; |
492 | ||
7267c094 | 493 | q = g_malloc0(sizeof(*q)); |
8ac6d699 | 494 | q->ehci = ehci; |
8f6d5e26 | 495 | q->qhaddr = addr; |
ae0138a8 | 496 | q->async = async; |
eb36a88e | 497 | QTAILQ_INIT(&q->packets); |
df5d5c5c | 498 | QTAILQ_INSERT_HEAD(head, q, next); |
8ac6d699 GH |
499 | trace_usb_ehci_queue_action(q, "alloc"); |
500 | return q; | |
501 | } | |
502 | ||
5c514681 | 503 | static int ehci_cancel_queue(EHCIQueue *q) |
c7cdca3b GH |
504 | { |
505 | EHCIPacket *p; | |
5c514681 | 506 | int packets = 0; |
c7cdca3b GH |
507 | |
508 | p = QTAILQ_FIRST(&q->packets); | |
509 | if (p == NULL) { | |
5c514681 | 510 | return 0; |
c7cdca3b GH |
511 | } |
512 | ||
513 | trace_usb_ehci_queue_action(q, "cancel"); | |
514 | do { | |
515 | ehci_free_packet(p); | |
5c514681 | 516 | packets++; |
c7cdca3b | 517 | } while ((p = QTAILQ_FIRST(&q->packets)) != NULL); |
5c514681 | 518 | return packets; |
c7cdca3b GH |
519 | } |
520 | ||
5c514681 | 521 | static int ehci_reset_queue(EHCIQueue *q) |
dafe31fc | 522 | { |
5c514681 GH |
523 | int packets; |
524 | ||
dafe31fc | 525 | trace_usb_ehci_queue_action(q, "reset"); |
5c514681 | 526 | packets = ehci_cancel_queue(q); |
dafe31fc HG |
527 | q->dev = NULL; |
528 | q->qtdaddr = 0; | |
5c514681 | 529 | return packets; |
dafe31fc HG |
530 | } |
531 | ||
3a8ca08e | 532 | static void ehci_free_queue(EHCIQueue *q, const char *warn) |
8ac6d699 | 533 | { |
ae0138a8 | 534 | EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
3a8ca08e | 535 | int cancelled; |
eb36a88e | 536 | |
8ac6d699 | 537 | trace_usb_ehci_queue_action(q, "free"); |
3a8ca08e HG |
538 | cancelled = ehci_cancel_queue(q); |
539 | if (warn && cancelled > 0) { | |
540 | ehci_trace_guest_bug(q->ehci, warn); | |
541 | } | |
df5d5c5c | 542 | QTAILQ_REMOVE(head, q, next); |
7267c094 | 543 | g_free(q); |
8ac6d699 GH |
544 | } |
545 | ||
df5d5c5c HG |
546 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, |
547 | int async) | |
8ac6d699 | 548 | { |
df5d5c5c | 549 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
550 | EHCIQueue *q; |
551 | ||
df5d5c5c | 552 | QTAILQ_FOREACH(q, head, next) { |
8ac6d699 GH |
553 | if (addr == q->qhaddr) { |
554 | return q; | |
555 | } | |
556 | } | |
557 | return NULL; | |
558 | } | |
559 | ||
8f5457eb | 560 | static void ehci_queues_rip_unused(EHCIState *ehci, int async) |
8ac6d699 | 561 | { |
df5d5c5c | 562 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8f5457eb | 563 | const char *warn = async ? "guest unlinked busy QH" : NULL; |
3a215326 | 564 | uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4; |
8ac6d699 GH |
565 | EHCIQueue *q, *tmp; |
566 | ||
df5d5c5c | 567 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
8ac6d699 GH |
568 | if (q->seen) { |
569 | q->seen = 0; | |
adddecb1 | 570 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
571 | continue; |
572 | } | |
8f5457eb | 573 | if (ehci->last_run_ns < q->ts + maxage) { |
8ac6d699 GH |
574 | continue; |
575 | } | |
3a8ca08e | 576 | ehci_free_queue(q, warn); |
8ac6d699 GH |
577 | } |
578 | } | |
579 | ||
8f5457eb HG |
580 | static void ehci_queues_rip_unseen(EHCIState *ehci, int async) |
581 | { | |
582 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; | |
583 | EHCIQueue *q, *tmp; | |
584 | ||
585 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { | |
586 | if (!q->seen) { | |
587 | ehci_free_queue(q, NULL); | |
588 | } | |
589 | } | |
590 | } | |
591 | ||
df5d5c5c | 592 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
07771f6f | 593 | { |
df5d5c5c | 594 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
07771f6f GH |
595 | EHCIQueue *q, *tmp; |
596 | ||
df5d5c5c | 597 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
e59928b3 | 598 | if (q->dev != dev) { |
07771f6f GH |
599 | continue; |
600 | } | |
3a8ca08e | 601 | ehci_free_queue(q, NULL); |
07771f6f GH |
602 | } |
603 | } | |
604 | ||
df5d5c5c | 605 | static void ehci_queues_rip_all(EHCIState *ehci, int async) |
8ac6d699 | 606 | { |
df5d5c5c | 607 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
3a8ca08e | 608 | const char *warn = async ? "guest stopped busy async schedule" : NULL; |
8ac6d699 GH |
609 | EHCIQueue *q, *tmp; |
610 | ||
df5d5c5c | 611 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
3a8ca08e | 612 | ehci_free_queue(q, warn); |
8ac6d699 GH |
613 | } |
614 | } | |
615 | ||
94527ead GH |
616 | /* Attach or detach a device on root hub */ |
617 | ||
618 | static void ehci_attach(USBPort *port) | |
619 | { | |
620 | EHCIState *s = port->opaque; | |
621 | uint32_t *portsc = &s->portsc[port->index]; | |
30e9d412 | 622 | const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
94527ead | 623 | |
30e9d412 | 624 | trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); |
94527ead | 625 | |
a0a3167a HG |
626 | if (*portsc & PORTSC_POWNER) { |
627 | USBPort *companion = s->companion_ports[port->index]; | |
628 | companion->dev = port->dev; | |
629 | companion->ops->attach(companion); | |
630 | return; | |
631 | } | |
632 | ||
94527ead GH |
633 | *portsc |= PORTSC_CONNECT; |
634 | *portsc |= PORTSC_CSC; | |
635 | ||
7efc17af GH |
636 | ehci_raise_irq(s, USBSTS_PCD); |
637 | ehci_commit_irq(s); | |
94527ead GH |
638 | } |
639 | ||
640 | static void ehci_detach(USBPort *port) | |
641 | { | |
642 | EHCIState *s = port->opaque; | |
643 | uint32_t *portsc = &s->portsc[port->index]; | |
30e9d412 | 644 | const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
94527ead | 645 | |
30e9d412 | 646 | trace_usb_ehci_port_detach(port->index, owner); |
94527ead | 647 | |
a0a3167a HG |
648 | if (*portsc & PORTSC_POWNER) { |
649 | USBPort *companion = s->companion_ports[port->index]; | |
650 | companion->ops->detach(companion); | |
651 | companion->dev = NULL; | |
f76e1d81 HG |
652 | /* |
653 | * EHCI spec 4.2.2: "When a disconnect occurs... On the event, | |
654 | * the port ownership is returned immediately to the EHCI controller." | |
655 | */ | |
656 | *portsc &= ~PORTSC_POWNER; | |
a0a3167a HG |
657 | return; |
658 | } | |
659 | ||
df5d5c5c HG |
660 | ehci_queues_rip_device(s, port->dev, 0); |
661 | ehci_queues_rip_device(s, port->dev, 1); | |
4706ab6c | 662 | |
fbd97532 | 663 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
664 | *portsc |= PORTSC_CSC; |
665 | ||
7efc17af GH |
666 | ehci_raise_irq(s, USBSTS_PCD); |
667 | ehci_commit_irq(s); | |
94527ead GH |
668 | } |
669 | ||
4706ab6c HG |
670 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
671 | { | |
672 | EHCIState *s = port->opaque; | |
a0a3167a HG |
673 | uint32_t portsc = s->portsc[port->index]; |
674 | ||
675 | if (portsc & PORTSC_POWNER) { | |
676 | USBPort *companion = s->companion_ports[port->index]; | |
677 | companion->ops->child_detach(companion, child); | |
a0a3167a HG |
678 | return; |
679 | } | |
4706ab6c | 680 | |
df5d5c5c HG |
681 | ehci_queues_rip_device(s, child, 0); |
682 | ehci_queues_rip_device(s, child, 1); | |
4706ab6c HG |
683 | } |
684 | ||
a0a3167a HG |
685 | static void ehci_wakeup(USBPort *port) |
686 | { | |
687 | EHCIState *s = port->opaque; | |
688 | uint32_t portsc = s->portsc[port->index]; | |
689 | ||
690 | if (portsc & PORTSC_POWNER) { | |
691 | USBPort *companion = s->companion_ports[port->index]; | |
692 | if (companion->ops->wakeup) { | |
693 | companion->ops->wakeup(companion); | |
694 | } | |
37952117 | 695 | return; |
a0a3167a | 696 | } |
37952117 HG |
697 | |
698 | qemu_bh_schedule(s->async_bh); | |
a0a3167a HG |
699 | } |
700 | ||
701 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
702 | uint32_t portcount, uint32_t firstport) | |
703 | { | |
704 | EHCIState *s = container_of(bus, EHCIState, bus); | |
705 | uint32_t i; | |
706 | ||
707 | if (firstport + portcount > NB_PORTS) { | |
708 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
709 | "firstport on masterbus"); | |
710 | error_printf_unless_qmp( | |
711 | "firstport value of %u makes companion take ports %u - %u, which " | |
712 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
713 | firstport + portcount - 1, NB_PORTS - 1); | |
714 | return -1; | |
715 | } | |
716 | ||
717 | for (i = 0; i < portcount; i++) { | |
718 | if (s->companion_ports[firstport + i]) { | |
719 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
720 | "an USB masterbus"); | |
721 | error_printf_unless_qmp( | |
722 | "port %u on masterbus %s already has a companion assigned\n", | |
723 | firstport + i, bus->qbus.name); | |
724 | return -1; | |
725 | } | |
726 | } | |
727 | ||
728 | for (i = 0; i < portcount; i++) { | |
729 | s->companion_ports[firstport + i] = ports[i]; | |
730 | s->ports[firstport + i].speedmask |= | |
731 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
732 | /* Ensure devs attached before the initial reset go to the companion */ | |
733 | s->portsc[firstport + i] = PORTSC_POWNER; | |
734 | } | |
735 | ||
736 | s->companion_count++; | |
3e4f910c | 737 | s->caps[0x05] = (s->companion_count << 4) | portcount; |
a0a3167a HG |
738 | |
739 | return 0; | |
740 | } | |
741 | ||
80826240 HG |
742 | static void ehci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) |
743 | { | |
744 | EHCIState *s = container_of(bus, EHCIState, bus); | |
745 | uint32_t portsc = s->portsc[ep->dev->port->index]; | |
746 | ||
747 | if (portsc & PORTSC_POWNER) { | |
748 | return; | |
749 | } | |
750 | ||
751 | s->periodic_sched_active = PERIODIC_ACTIVE; | |
752 | qemu_bh_schedule(s->async_bh); | |
753 | } | |
754 | ||
828143c6 GH |
755 | static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) |
756 | { | |
757 | USBDevice *dev; | |
758 | USBPort *port; | |
759 | int i; | |
760 | ||
761 | for (i = 0; i < NB_PORTS; i++) { | |
762 | port = &ehci->ports[i]; | |
763 | if (!(ehci->portsc[i] & PORTSC_PED)) { | |
764 | DPRINTF("Port %d not enabled\n", i); | |
765 | continue; | |
766 | } | |
767 | dev = usb_find_device(port, addr); | |
768 | if (dev != NULL) { | |
769 | return dev; | |
770 | } | |
771 | } | |
772 | return NULL; | |
773 | } | |
774 | ||
94527ead GH |
775 | /* 4.1 host controller initialization */ |
776 | static void ehci_reset(void *opaque) | |
777 | { | |
778 | EHCIState *s = opaque; | |
94527ead | 779 | int i; |
a0a3167a | 780 | USBDevice *devs[NB_PORTS]; |
94527ead | 781 | |
439a97cc | 782 | trace_usb_ehci_reset(); |
94527ead | 783 | |
a0a3167a HG |
784 | /* |
785 | * Do the detach before touching portsc, so that it correctly gets send to | |
786 | * us or to our companion based on PORTSC_POWNER before the reset. | |
787 | */ | |
788 | for(i = 0; i < NB_PORTS; i++) { | |
789 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
790 | if (devs[i] && devs[i]->attached) { |
791 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
792 | } |
793 | } | |
794 | ||
3e4f910c GH |
795 | memset(&s->opreg, 0x00, sizeof(s->opreg)); |
796 | memset(&s->portsc, 0x00, sizeof(s->portsc)); | |
94527ead GH |
797 | |
798 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
799 | s->usbsts = USBSTS_HALT; | |
7efc17af GH |
800 | s->usbsts_pending = 0; |
801 | s->usbsts_frindex = 0; | |
94527ead GH |
802 | |
803 | s->astate = EST_INACTIVE; | |
804 | s->pstate = EST_INACTIVE; | |
94527ead GH |
805 | |
806 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
807 | if (s->companion_ports[i]) { |
808 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
809 | } else { | |
810 | s->portsc[i] = PORTSC_PPOWER; | |
811 | } | |
891fb2cd GH |
812 | if (devs[i] && devs[i]->attached) { |
813 | usb_attach(&s->ports[i]); | |
d28f4e2d | 814 | usb_device_reset(devs[i]); |
94527ead GH |
815 | } |
816 | } | |
df5d5c5c HG |
817 | ehci_queues_rip_all(s, 0); |
818 | ehci_queues_rip_all(s, 1); | |
81d37739 | 819 | qemu_del_timer(s->frame_timer); |
0fb3e299 | 820 | qemu_bh_cancel(s->async_bh); |
94527ead GH |
821 | } |
822 | ||
a8170e5e | 823 | static uint64_t ehci_caps_read(void *ptr, hwaddr addr, |
3e4f910c | 824 | unsigned size) |
94527ead GH |
825 | { |
826 | EHCIState *s = ptr; | |
3e4f910c | 827 | return s->caps[addr]; |
94527ead GH |
828 | } |
829 | ||
a8170e5e | 830 | static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, |
3e4f910c | 831 | unsigned size) |
94527ead GH |
832 | { |
833 | EHCIState *s = ptr; | |
834 | uint32_t val; | |
835 | ||
3e4f910c | 836 | val = s->opreg[addr >> 2]; |
27a11324 | 837 | trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); |
94527ead GH |
838 | return val; |
839 | } | |
840 | ||
a8170e5e | 841 | static uint64_t ehci_port_read(void *ptr, hwaddr addr, |
3e4f910c | 842 | unsigned size) |
94527ead GH |
843 | { |
844 | EHCIState *s = ptr; | |
845 | uint32_t val; | |
846 | ||
3e4f910c GH |
847 | val = s->portsc[addr >> 2]; |
848 | trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val); | |
94527ead GH |
849 | return val; |
850 | } | |
851 | ||
a0a3167a HG |
852 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
853 | { | |
854 | USBDevice *dev = s->ports[port].dev; | |
855 | uint32_t *portsc = &s->portsc[port]; | |
856 | uint32_t orig; | |
857 | ||
858 | if (s->companion_ports[port] == NULL) | |
859 | return; | |
860 | ||
861 | owner = owner & PORTSC_POWNER; | |
862 | orig = *portsc & PORTSC_POWNER; | |
863 | ||
864 | if (!(owner ^ orig)) { | |
865 | return; | |
866 | } | |
867 | ||
891fb2cd GH |
868 | if (dev && dev->attached) { |
869 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
870 | } |
871 | ||
872 | *portsc &= ~PORTSC_POWNER; | |
873 | *portsc |= owner; | |
874 | ||
891fb2cd GH |
875 | if (dev && dev->attached) { |
876 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
877 | } |
878 | } | |
879 | ||
a8170e5e | 880 | static void ehci_port_write(void *ptr, hwaddr addr, |
3e4f910c | 881 | uint64_t val, unsigned size) |
94527ead | 882 | { |
3e4f910c GH |
883 | EHCIState *s = ptr; |
884 | int port = addr >> 2; | |
94527ead | 885 | uint32_t *portsc = &s->portsc[port]; |
3e4f910c | 886 | uint32_t old = *portsc; |
94527ead GH |
887 | USBDevice *dev = s->ports[port].dev; |
888 | ||
3e4f910c GH |
889 | trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val); |
890 | ||
fbd97532 HG |
891 | /* Clear rwc bits */ |
892 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
893 | /* The guest may clear, but not set the PED bit */ | |
894 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
895 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
896 | handle_port_owner_write(s, port, val); | |
897 | /* And finally apply RO_MASK */ | |
94527ead GH |
898 | val &= PORTSC_RO_MASK; |
899 | ||
94527ead | 900 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 901 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
902 | } |
903 | ||
904 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 905 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 906 | if (dev && dev->attached) { |
d28f4e2d | 907 | usb_port_reset(&s->ports[port]); |
94527ead GH |
908 | *portsc &= ~PORTSC_CSC; |
909 | } | |
910 | ||
fbd97532 HG |
911 | /* |
912 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 913 | * to SW that this port has a high speed device attached |
94527ead | 914 | */ |
891fb2cd | 915 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
916 | val |= PORTSC_PED; |
917 | } | |
94527ead GH |
918 | } |
919 | ||
920 | *portsc &= ~PORTSC_RO_MASK; | |
921 | *portsc |= val; | |
3e4f910c | 922 | trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old); |
94527ead GH |
923 | } |
924 | ||
a8170e5e | 925 | static void ehci_opreg_write(void *ptr, hwaddr addr, |
3e4f910c | 926 | uint64_t val, unsigned size) |
94527ead GH |
927 | { |
928 | EHCIState *s = ptr; | |
3e4f910c | 929 | uint32_t *mmio = s->opreg + (addr >> 2); |
c4f8e211 | 930 | uint32_t old = *mmio; |
94527ead | 931 | int i; |
439a97cc | 932 | |
27a11324 | 933 | trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); |
94527ead | 934 | |
27a11324 | 935 | switch (addr) { |
94527ead | 936 | case USBCMD: |
7046530c GH |
937 | if (val & USBCMD_HCRESET) { |
938 | ehci_reset(s); | |
939 | val = s->usbcmd; | |
940 | break; | |
941 | } | |
942 | ||
47d073cc HG |
943 | /* not supporting dynamic frame list size at the moment */ |
944 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
945 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
3e4f910c | 946 | (int)val & USBCMD_FLS); |
47d073cc HG |
947 | val &= ~USBCMD_FLS; |
948 | } | |
949 | ||
a1c3e4b8 HG |
950 | if (val & USBCMD_IAAD) { |
951 | /* | |
952 | * Process IAAD immediately, otherwise the Linux IAAD watchdog may | |
953 | * trigger and re-use a qh without us seeing the unlink. | |
954 | */ | |
955 | s->async_stepdown = 0; | |
956 | qemu_bh_schedule(s->async_bh); | |
1defcbd1 | 957 | trace_usb_ehci_doorbell_ring(); |
a1c3e4b8 HG |
958 | } |
959 | ||
daf25307 GH |
960 | if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != |
961 | ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { | |
3a215326 | 962 | if (s->pstate == EST_INACTIVE) { |
daf25307 GH |
963 | SET_LAST_RUN_CLOCK(s); |
964 | } | |
47d073cc | 965 | s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */ |
daf25307 | 966 | ehci_update_halt(s); |
3a215326 | 967 | s->async_stepdown = 0; |
0262f65a | 968 | qemu_bh_schedule(s->async_bh); |
94527ead | 969 | } |
94527ead GH |
970 | break; |
971 | ||
94527ead | 972 | case USBSTS: |
a31f0531 JM |
973 | val &= USBSTS_RO_MASK; // bits 6 through 31 are RO |
974 | ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC | |
439a97cc | 975 | val = s->usbsts; |
7efc17af | 976 | ehci_update_irq(s); |
94527ead GH |
977 | break; |
978 | ||
94527ead GH |
979 | case USBINTR: |
980 | val &= USBINTR_MASK; | |
40862309 GH |
981 | if (ehci_enabled(s) && (USBSTS_FLR & val)) { |
982 | qemu_bh_schedule(s->async_bh); | |
983 | } | |
94527ead GH |
984 | break; |
985 | ||
8a771f77 HG |
986 | case FRINDEX: |
987 | val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ | |
988 | break; | |
989 | ||
94527ead | 990 | case CONFIGFLAG: |
94527ead GH |
991 | val &= 0x1; |
992 | if (val) { | |
993 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 994 | handle_port_owner_write(s, i, 0); |
94527ead GH |
995 | } |
996 | break; | |
997 | ||
998 | case PERIODICLISTBASE: | |
ec807d12 | 999 | if (ehci_periodic_enabled(s)) { |
94527ead GH |
1000 | fprintf(stderr, |
1001 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1002 | " is enabled and HC is enabled\n"); | |
1003 | } | |
94527ead GH |
1004 | break; |
1005 | ||
1006 | case ASYNCLISTADDR: | |
ec807d12 | 1007 | if (ehci_async_enabled(s)) { |
94527ead GH |
1008 | fprintf(stderr, |
1009 | "ehci: ASYNC list address register set while async schedule\n" | |
1010 | " is enabled and HC is enabled\n"); | |
1011 | } | |
94527ead GH |
1012 | break; |
1013 | } | |
1014 | ||
c4f8e211 | 1015 | *mmio = val; |
27a11324 PC |
1016 | trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), |
1017 | *mmio, old); | |
94527ead GH |
1018 | } |
1019 | ||
94527ead | 1020 | /* Get an array of dwords from main memory */ |
68d55358 DG |
1021 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1022 | uint32_t *buf, int num) | |
94527ead GH |
1023 | { |
1024 | int i; | |
1025 | ||
55903f1d GH |
1026 | if (!ehci->dma) { |
1027 | ehci_raise_irq(ehci, USBSTS_HSE); | |
1028 | ehci->usbcmd &= ~USBCMD_RUNSTOP; | |
1029 | trace_usb_ehci_dma_error(); | |
1030 | return -1; | |
1031 | } | |
1032 | ||
94527ead | 1033 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
7ae6ce02 | 1034 | dma_memory_read(ehci->dma, addr, buf, sizeof(*buf)); |
94527ead GH |
1035 | *buf = le32_to_cpu(*buf); |
1036 | } | |
1037 | ||
55903f1d | 1038 | return num; |
94527ead GH |
1039 | } |
1040 | ||
1041 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1042 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1043 | uint32_t *buf, int num) | |
94527ead GH |
1044 | { |
1045 | int i; | |
1046 | ||
55903f1d GH |
1047 | if (!ehci->dma) { |
1048 | ehci_raise_irq(ehci, USBSTS_HSE); | |
1049 | ehci->usbcmd &= ~USBCMD_RUNSTOP; | |
1050 | trace_usb_ehci_dma_error(); | |
1051 | return -1; | |
1052 | } | |
1053 | ||
94527ead GH |
1054 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
1055 | uint32_t tmp = cpu_to_le32(*buf); | |
7ae6ce02 | 1056 | dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp)); |
94527ead GH |
1057 | } |
1058 | ||
55903f1d | 1059 | return num; |
94527ead GH |
1060 | } |
1061 | ||
a5e0139a GH |
1062 | /* |
1063 | * Write the qh back to guest physical memory. This step isn't | |
1064 | * in the EHCI spec but we need to do it since we don't share | |
1065 | * physical memory with our guest VM. | |
1066 | * | |
1067 | * The first three dwords are read-only for the EHCI, so skip them | |
1068 | * when writing back the qh. | |
1069 | */ | |
1070 | static void ehci_flush_qh(EHCIQueue *q) | |
1071 | { | |
1072 | uint32_t *qh = (uint32_t *) &q->qh; | |
1073 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1074 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1075 | ||
1076 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); | |
1077 | } | |
1078 | ||
94527ead GH |
1079 | // 4.10.2 |
1080 | ||
0122f472 | 1081 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead | 1082 | { |
eb36a88e | 1083 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead GH |
1084 | int i; |
1085 | int dtoggle; | |
1086 | int ping; | |
1087 | int eps; | |
1088 | int reload; | |
1089 | ||
eb36a88e GH |
1090 | assert(p != NULL); |
1091 | assert(p->qtdaddr == q->qtdaddr); | |
1092 | ||
94527ead GH |
1093 | // remember values in fields to preserve in qh after overlay |
1094 | ||
0122f472 GH |
1095 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1096 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1097 | |
eb36a88e GH |
1098 | q->qh.current_qtd = p->qtdaddr; |
1099 | q->qh.next_qtd = p->qtd.next; | |
1100 | q->qh.altnext_qtd = p->qtd.altnext; | |
1101 | q->qh.token = p->qtd.token; | |
94527ead GH |
1102 | |
1103 | ||
0122f472 | 1104 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1105 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1106 | q->qh.token &= ~QTD_TOKEN_PING; |
1107 | q->qh.token |= ping; | |
94527ead GH |
1108 | } |
1109 | ||
0122f472 GH |
1110 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1111 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1112 | |
1113 | for (i = 0; i < 5; i++) { | |
eb36a88e | 1114 | q->qh.bufptr[i] = p->qtd.bufptr[i]; |
94527ead GH |
1115 | } |
1116 | ||
0122f472 | 1117 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1118 | // preserve QH DT bit |
0122f472 GH |
1119 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1120 | q->qh.token |= dtoggle; | |
94527ead GH |
1121 | } |
1122 | ||
0122f472 GH |
1123 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1124 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1125 | |
a5e0139a | 1126 | ehci_flush_qh(q); |
94527ead GH |
1127 | |
1128 | return 0; | |
1129 | } | |
1130 | ||
eb36a88e | 1131 | static int ehci_init_transfer(EHCIPacket *p) |
94527ead | 1132 | { |
0ce668bc | 1133 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1134 | dma_addr_t page; |
94527ead | 1135 | |
eb36a88e GH |
1136 | cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1137 | bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); | |
1138 | offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; | |
7ae6ce02 | 1139 | qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma); |
94527ead | 1140 | |
0ce668bc GH |
1141 | while (bytes > 0) { |
1142 | if (cpage > 4) { | |
1143 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
01e26b0e | 1144 | return -1; |
0ce668bc | 1145 | } |
94527ead | 1146 | |
eb36a88e | 1147 | page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
0ce668bc GH |
1148 | page += offset; |
1149 | plen = bytes; | |
1150 | if (plen > 4096 - offset) { | |
1151 | plen = 4096 - offset; | |
1152 | offset = 0; | |
1153 | cpage++; | |
94527ead GH |
1154 | } |
1155 | ||
eb36a88e | 1156 | qemu_sglist_add(&p->sgl, page, plen); |
0ce668bc GH |
1157 | bytes -= plen; |
1158 | } | |
1159 | return 0; | |
1160 | } | |
94527ead | 1161 | |
e696b1da | 1162 | static void ehci_finish_transfer(EHCIQueue *q, int len) |
0ce668bc GH |
1163 | { |
1164 | uint32_t cpage, offset; | |
94527ead | 1165 | |
e696b1da | 1166 | if (len > 0) { |
0ce668bc GH |
1167 | /* update cpage & offset */ |
1168 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1169 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1170 | |
e696b1da | 1171 | offset += len; |
0ce668bc GH |
1172 | cpage += offset >> QTD_BUFPTR_SH; |
1173 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1174 | |
0ce668bc GH |
1175 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1176 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1177 | q->qh.bufptr[0] |= offset; | |
1178 | } | |
94527ead GH |
1179 | } |
1180 | ||
d47e59b8 | 1181 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1182 | { |
eb36a88e | 1183 | EHCIPacket *p; |
a0a3167a HG |
1184 | EHCIState *s = port->opaque; |
1185 | uint32_t portsc = s->portsc[port->index]; | |
1186 | ||
1187 | if (portsc & PORTSC_POWNER) { | |
1188 | USBPort *companion = s->companion_ports[port->index]; | |
1189 | companion->ops->complete(companion, packet); | |
1190 | return; | |
1191 | } | |
94527ead | 1192 | |
eb36a88e | 1193 | p = container_of(packet, EHCIPacket, packet); |
eb36a88e | 1194 | assert(p->async == EHCI_ASYNC_INFLIGHT); |
0cae7b1a | 1195 | |
9a77a0f5 | 1196 | if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { |
0cae7b1a HG |
1197 | trace_usb_ehci_packet_action(p->queue, p, "remove"); |
1198 | ehci_free_packet(p); | |
1199 | return; | |
1200 | } | |
1201 | ||
1202 | trace_usb_ehci_packet_action(p->queue, p, "wakeup"); | |
eb36a88e | 1203 | p->async = EHCI_ASYNC_FINISHED; |
ae710b99 | 1204 | |
80826240 HG |
1205 | if (!p->queue->async) { |
1206 | s->periodic_sched_active = PERIODIC_ACTIVE; | |
ae710b99 | 1207 | } |
80826240 | 1208 | qemu_bh_schedule(s->async_bh); |
94527ead GH |
1209 | } |
1210 | ||
0122f472 | 1211 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead | 1212 | { |
eb36a88e | 1213 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
e696b1da | 1214 | uint32_t tbytes; |
eb36a88e GH |
1215 | |
1216 | assert(p != NULL); | |
1217 | assert(p->qtdaddr == q->qtdaddr); | |
ef5b2344 HG |
1218 | assert(p->async == EHCI_ASYNC_INITIALIZED || |
1219 | p->async == EHCI_ASYNC_FINISHED); | |
94527ead | 1220 | |
e696b1da HG |
1221 | DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, " |
1222 | "status %d, actual_length %d\n", | |
1223 | q->qhaddr, q->qh.next, q->qtdaddr, | |
1224 | p->packet.status, p->packet.actual_length); | |
94527ead | 1225 | |
e696b1da HG |
1226 | switch (p->packet.status) { |
1227 | case USB_RET_SUCCESS: | |
1228 | break; | |
1229 | case USB_RET_IOERROR: | |
1230 | case USB_RET_NODEV: | |
1231 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); | |
1232 | set_field(&q->qh.token, 0, QTD_TOKEN_CERR); | |
1233 | ehci_raise_irq(q->ehci, USBSTS_ERRINT); | |
1234 | break; | |
1235 | case USB_RET_STALL: | |
1236 | q->qh.token |= QTD_TOKEN_HALT; | |
1237 | ehci_raise_irq(q->ehci, USBSTS_ERRINT); | |
1238 | break; | |
1239 | case USB_RET_NAK: | |
1240 | set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); | |
1241 | return; /* We're not done yet with this transaction */ | |
1242 | case USB_RET_BABBLE: | |
1243 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); | |
1244 | ehci_raise_irq(q->ehci, USBSTS_ERRINT); | |
1245 | break; | |
1246 | default: | |
1247 | /* should not be triggerable */ | |
1248 | fprintf(stderr, "USB invalid response %d\n", p->packet.status); | |
1249 | assert(0); | |
1250 | break; | |
1251 | } | |
1252 | ||
1253 | /* TODO check 4.12 for splits */ | |
1254 | tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); | |
1255 | if (tbytes && p->pid == USB_TOKEN_IN) { | |
1256 | tbytes -= p->packet.actual_length; | |
1257 | if (tbytes) { | |
1258 | /* 4.15.1.2 must raise int on a short input packet */ | |
1259 | ehci_raise_irq(q->ehci, USBSTS_INT); | |
94527ead GH |
1260 | } |
1261 | } else { | |
e696b1da | 1262 | tbytes = 0; |
94527ead | 1263 | } |
e696b1da HG |
1264 | DPRINTF("updating tbytes to %d\n", tbytes); |
1265 | set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES); | |
1266 | ||
1267 | ehci_finish_transfer(q, p->packet.actual_length); | |
e2f89926 | 1268 | usb_packet_unmap(&p->packet, &p->sgl); |
eb36a88e | 1269 | qemu_sglist_destroy(&p->sgl); |
ef5b2344 | 1270 | p->async = EHCI_ASYNC_NONE; |
94527ead | 1271 | |
0122f472 GH |
1272 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1273 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1274 | |
553a6a59 | 1275 | if (q->qh.token & QTD_TOKEN_IOC) { |
7efc17af | 1276 | ehci_raise_irq(q->ehci, USBSTS_INT); |
44272b0f HG |
1277 | if (q->async) { |
1278 | q->ehci->int_req_by_async = true; | |
1279 | } | |
94527ead | 1280 | } |
94527ead GH |
1281 | } |
1282 | ||
01e26b0e | 1283 | /* 4.10.3 returns "again" */ |
773dc9cd | 1284 | static int ehci_execute(EHCIPacket *p, const char *action) |
94527ead | 1285 | { |
079d0b7f | 1286 | USBEndpoint *ep; |
94527ead | 1287 | int endp; |
6ba43f1f | 1288 | bool spd; |
94527ead | 1289 | |
ef5b2344 HG |
1290 | assert(p->async == EHCI_ASYNC_NONE || |
1291 | p->async == EHCI_ASYNC_INITIALIZED); | |
1292 | ||
4224558f GH |
1293 | if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { |
1294 | fprintf(stderr, "Attempting to execute inactive qtd\n"); | |
01e26b0e | 1295 | return -1; |
94527ead GH |
1296 | } |
1297 | ||
549a3c3d | 1298 | if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) { |
3a8ca08e HG |
1299 | ehci_trace_guest_bug(p->queue->ehci, |
1300 | "guest requested more bytes than allowed"); | |
01e26b0e | 1301 | return -1; |
94527ead GH |
1302 | } |
1303 | ||
4224558f | 1304 | p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
eb36a88e GH |
1305 | switch (p->pid) { |
1306 | case 0: | |
1307 | p->pid = USB_TOKEN_OUT; | |
1308 | break; | |
1309 | case 1: | |
1310 | p->pid = USB_TOKEN_IN; | |
1311 | break; | |
1312 | case 2: | |
1313 | p->pid = USB_TOKEN_SETUP; | |
1314 | break; | |
1315 | default: | |
1316 | fprintf(stderr, "bad token\n"); | |
1317 | break; | |
94527ead GH |
1318 | } |
1319 | ||
4224558f | 1320 | endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
e59928b3 | 1321 | ep = usb_ep_get(p->queue->dev, p->pid, endp); |
94527ead | 1322 | |
ef5b2344 HG |
1323 | if (p->async == EHCI_ASYNC_NONE) { |
1324 | if (ehci_init_transfer(p) != 0) { | |
01e26b0e | 1325 | return -1; |
ef5b2344 HG |
1326 | } |
1327 | ||
6ba43f1f | 1328 | spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0); |
a6fb2ddb HG |
1329 | usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr, spd, |
1330 | (p->qtd.token & QTD_TOKEN_IOC) != 0); | |
ef5b2344 HG |
1331 | usb_packet_map(&p->packet, &p->sgl); |
1332 | p->async = EHCI_ASYNC_INITIALIZED; | |
1333 | } | |
0ce668bc | 1334 | |
773dc9cd | 1335 | trace_usb_ehci_packet_action(p->queue, p, action); |
9a77a0f5 HG |
1336 | usb_handle_packet(p->queue->dev, &p->packet); |
1337 | DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x " | |
1338 | "status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next, | |
1339 | p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status, | |
1340 | p->packet.actual_length); | |
94527ead | 1341 | |
9a77a0f5 | 1342 | if (p->packet.actual_length > BUFF_SIZE) { |
94527ead | 1343 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); |
01e26b0e | 1344 | return -1; |
94527ead GH |
1345 | } |
1346 | ||
01e26b0e | 1347 | return 1; |
94527ead GH |
1348 | } |
1349 | ||
1350 | /* 4.7.2 | |
1351 | */ | |
1352 | ||
1353 | static int ehci_process_itd(EHCIState *ehci, | |
e983395d GH |
1354 | EHCIitd *itd, |
1355 | uint32_t addr) | |
94527ead | 1356 | { |
94527ead | 1357 | USBDevice *dev; |
079d0b7f | 1358 | USBEndpoint *ep; |
828143c6 | 1359 | uint32_t i, len, pid, dir, devaddr, endp; |
e654887f | 1360 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead | 1361 | |
80826240 HG |
1362 | ehci->periodic_sched_active = PERIODIC_ACTIVE; |
1363 | ||
94527ead | 1364 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); |
e654887f | 1365 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1366 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1367 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1368 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1369 | |
1370 | for(i = 0; i < 8; i++) { | |
1371 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1372 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1373 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1374 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1375 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1376 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1377 | ||
1378 | if (len > max * mult) { | |
1379 | len = max * mult; | |
1380 | } | |
94527ead GH |
1381 | |
1382 | if (len > BUFF_SIZE) { | |
01e26b0e | 1383 | return -1; |
94527ead GH |
1384 | } |
1385 | ||
7ae6ce02 | 1386 | qemu_sglist_init(&ehci->isgl, 2, ehci->dma); |
e654887f GH |
1387 | if (off + len > 4096) { |
1388 | /* transfer crosses page border */ | |
0ce668bc GH |
1389 | uint32_t len2 = off + len - 4096; |
1390 | uint32_t len1 = len - len2; | |
1391 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1392 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1393 | } else { |
0ce668bc | 1394 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1395 | } |
94527ead | 1396 | |
0ce668bc | 1397 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1398 | |
079d0b7f GH |
1399 | dev = ehci_find_device(ehci, devaddr); |
1400 | ep = usb_ep_get(dev, pid, endp); | |
7ce86aa1 | 1401 | if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { |
a6fb2ddb HG |
1402 | usb_packet_setup(&ehci->ipacket, pid, ep, addr, false, |
1403 | (itd->transact[i] & ITD_XACT_IOC) != 0); | |
aa0568ff | 1404 | usb_packet_map(&ehci->ipacket, &ehci->isgl); |
9a77a0f5 | 1405 | usb_handle_packet(dev, &ehci->ipacket); |
e2f89926 | 1406 | usb_packet_unmap(&ehci->ipacket, &ehci->isgl); |
aa0568ff GH |
1407 | } else { |
1408 | DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); | |
e696b1da HG |
1409 | ehci->ipacket.status = USB_RET_NAK; |
1410 | ehci->ipacket.actual_length = 0; | |
aa0568ff | 1411 | } |
0ce668bc GH |
1412 | qemu_sglist_destroy(&ehci->isgl); |
1413 | ||
e696b1da HG |
1414 | switch (ehci->ipacket.status) { |
1415 | case USB_RET_SUCCESS: | |
1416 | break; | |
1417 | default: | |
1418 | fprintf(stderr, "Unexpected iso usb result: %d\n", | |
1419 | ehci->ipacket.status); | |
1420 | /* Fall through */ | |
1421 | case USB_RET_IOERROR: | |
1422 | case USB_RET_NODEV: | |
1423 | /* 3.3.2: XACTERR is only allowed on IN transactions */ | |
1424 | if (dir) { | |
1425 | itd->transact[i] |= ITD_XACT_XACTERR; | |
7efc17af | 1426 | ehci_raise_irq(ehci, USBSTS_ERRINT); |
5eafd438 | 1427 | } |
e696b1da HG |
1428 | break; |
1429 | case USB_RET_BABBLE: | |
1430 | itd->transact[i] |= ITD_XACT_BABBLE; | |
1431 | ehci_raise_irq(ehci, USBSTS_ERRINT); | |
1432 | break; | |
1433 | case USB_RET_NAK: | |
1434 | /* no data for us, so do a zero-length transfer */ | |
1435 | ehci->ipacket.actual_length = 0; | |
1436 | break; | |
5eafd438 | 1437 | } |
e696b1da HG |
1438 | if (!dir) { |
1439 | set_field(&itd->transact[i], len - ehci->ipacket.actual_length, | |
1440 | ITD_XACT_LENGTH); /* OUT */ | |
1441 | } else { | |
1442 | set_field(&itd->transact[i], ehci->ipacket.actual_length, | |
1443 | ITD_XACT_LENGTH); /* IN */ | |
94527ead | 1444 | } |
df787185 | 1445 | if (itd->transact[i] & ITD_XACT_IOC) { |
7efc17af | 1446 | ehci_raise_irq(ehci, USBSTS_INT); |
df787185 | 1447 | } |
e654887f | 1448 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1449 | } |
1450 | } | |
1451 | return 0; | |
1452 | } | |
1453 | ||
cd665715 | 1454 | |
94527ead GH |
1455 | /* This state is the entry point for asynchronous schedule |
1456 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1457 | */ | |
26d53979 | 1458 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1459 | { |
0122f472 | 1460 | EHCIqh qh; |
94527ead GH |
1461 | int i = 0; |
1462 | int again = 0; | |
1463 | uint32_t entry = ehci->asynclistaddr; | |
1464 | ||
1465 | /* set reclamation flag at start event (4.8.6) */ | |
1466 | if (async) { | |
439a97cc | 1467 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1468 | } |
1469 | ||
8f5457eb | 1470 | ehci_queues_rip_unused(ehci, async); |
8ac6d699 | 1471 | |
94527ead GH |
1472 | /* Find the head of the list (4.9.1.1) */ |
1473 | for(i = 0; i < MAX_QH; i++) { | |
55903f1d GH |
1474 | if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1475 | sizeof(EHCIqh) >> 2) < 0) { | |
1476 | return 0; | |
1477 | } | |
8ac6d699 | 1478 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1479 | |
0122f472 | 1480 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1481 | if (async) { |
1482 | entry |= (NLPTR_TYPE_QH << 1); | |
1483 | } | |
1484 | ||
0122f472 | 1485 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1486 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1487 | again = 1; |
1488 | goto out; | |
1489 | } | |
1490 | ||
0122f472 | 1491 | entry = qh.next; |
94527ead | 1492 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1493 | break; |
1494 | } | |
1495 | } | |
1496 | ||
1497 | /* no head found for list. */ | |
1498 | ||
26d53979 | 1499 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1500 | |
1501 | out: | |
1502 | return again; | |
1503 | } | |
1504 | ||
1505 | ||
1506 | /* This state is the entry point for periodic schedule processing as | |
1507 | * well as being a continuation state for async processing. | |
1508 | */ | |
26d53979 | 1509 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1510 | { |
1511 | int again = 0; | |
0122f472 | 1512 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1513 | |
2a5ff735 | 1514 | if (NLPTR_TBIT(entry)) { |
26d53979 | 1515 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1516 | goto out; |
1517 | } | |
1518 | ||
1519 | /* section 4.8, only QH in async schedule */ | |
1520 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1521 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1522 | return -1; | |
1523 | } | |
1524 | ||
1525 | switch (NLPTR_TYPE_GET(entry)) { | |
1526 | case NLPTR_TYPE_QH: | |
26d53979 | 1527 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1528 | again = 1; |
1529 | break; | |
1530 | ||
1531 | case NLPTR_TYPE_ITD: | |
26d53979 | 1532 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1533 | again = 1; |
1534 | break; | |
1535 | ||
2fe80192 GH |
1536 | case NLPTR_TYPE_STITD: |
1537 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1538 | again = 1; | |
1539 | break; | |
1540 | ||
94527ead | 1541 | default: |
2fe80192 | 1542 | /* TODO: handle FSTN type */ |
94527ead GH |
1543 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1544 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1545 | return -1; | |
1546 | } | |
1547 | ||
1548 | out: | |
1549 | return again; | |
1550 | } | |
1551 | ||
0122f472 | 1552 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1553 | { |
eb36a88e | 1554 | EHCIPacket *p; |
dafe31fc | 1555 | uint32_t entry, devaddr, endp; |
0122f472 | 1556 | EHCIQueue *q; |
dafe31fc | 1557 | EHCIqh qh; |
94527ead | 1558 | |
0122f472 | 1559 | entry = ehci_get_fetch_addr(ehci, async); |
df5d5c5c | 1560 | q = ehci_find_queue_by_qh(ehci, entry, async); |
8ac6d699 | 1561 | if (NULL == q) { |
8f6d5e26 | 1562 | q = ehci_alloc_queue(ehci, entry, async); |
8ac6d699 | 1563 | } |
eb36a88e | 1564 | p = QTAILQ_FIRST(&q->packets); |
8ac6d699 | 1565 | |
8f6d5e26 | 1566 | q->seen++; |
8ac6d699 GH |
1567 | if (q->seen > 1) { |
1568 | /* we are going in circles -- stop processing */ | |
1569 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1570 | q = NULL; | |
1571 | goto out; | |
1572 | } | |
94527ead | 1573 | |
55903f1d GH |
1574 | if (get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1575 | (uint32_t *) &qh, sizeof(EHCIqh) >> 2) < 0) { | |
1576 | q = NULL; | |
1577 | goto out; | |
1578 | } | |
dafe31fc HG |
1579 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); |
1580 | ||
1581 | /* | |
1582 | * The overlay area of the qh should never be changed by the guest, | |
1583 | * except when idle, in which case the reset is a nop. | |
1584 | */ | |
1585 | devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR); | |
1586 | endp = get_field(qh.epchar, QH_EPCHAR_EP); | |
1587 | if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) || | |
1588 | (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || | |
2c7b15c1 HG |
1589 | (qh.current_qtd != q->qh.current_qtd) || |
1590 | (q->async && qh.next_qtd != q->qh.next_qtd) || | |
1591 | (memcmp(&qh.altnext_qtd, &q->qh.altnext_qtd, | |
1592 | 7 * sizeof(uint32_t)) != 0) || | |
dafe31fc | 1593 | (q->dev != NULL && q->dev->addr != devaddr)) { |
5c514681 GH |
1594 | if (ehci_reset_queue(q) > 0) { |
1595 | ehci_trace_guest_bug(ehci, "guest updated active QH"); | |
1596 | } | |
dafe31fc HG |
1597 | p = NULL; |
1598 | } | |
1599 | q->qh = qh; | |
1600 | ||
cae5d3f4 HG |
1601 | q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
1602 | if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */ | |
1603 | q->transact_ctr = 4; | |
1604 | } | |
1605 | ||
e59928b3 GH |
1606 | if (q->dev == NULL) { |
1607 | q->dev = ehci_find_device(q->ehci, devaddr); | |
1608 | } | |
1609 | ||
eb36a88e | 1610 | if (p && p->async == EHCI_ASYNC_FINISHED) { |
8ac6d699 | 1611 | /* I/O finished -- continue processing queue */ |
773dc9cd | 1612 | trace_usb_ehci_packet_action(p->queue, p, "complete"); |
8ac6d699 GH |
1613 | ehci_set_state(ehci, async, EST_EXECUTING); |
1614 | goto out; | |
1615 | } | |
0122f472 GH |
1616 | |
1617 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1618 | |
1619 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1620 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1621 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1622 | } else { |
1623 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1624 | " - done processing\n", q->qhaddr); |
26d53979 | 1625 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1626 | q = NULL; |
94527ead GH |
1627 | goto out; |
1628 | } | |
1629 | } | |
1630 | ||
1631 | #if EHCI_DEBUG | |
0122f472 | 1632 | if (q->qhaddr != q->qh.next) { |
94527ead | 1633 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1634 | q->qhaddr, |
1635 | q->qh.epchar & QH_EPCHAR_H, | |
1636 | q->qh.token & QTD_TOKEN_HALT, | |
1637 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1638 | q->qh.next); | |
94527ead GH |
1639 | } |
1640 | #endif | |
1641 | ||
0122f472 | 1642 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1643 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1644 | |
2a5ff735 HG |
1645 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1646 | (NLPTR_TBIT(q->qh.current_qtd) == 0)) { | |
0122f472 | 1647 | q->qtdaddr = q->qh.current_qtd; |
26d53979 | 1648 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1649 | |
1650 | } else { | |
1651 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1652 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1653 | } |
1654 | ||
1655 | out: | |
0122f472 | 1656 | return q; |
94527ead GH |
1657 | } |
1658 | ||
26d53979 | 1659 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1660 | { |
0122f472 | 1661 | uint32_t entry; |
94527ead GH |
1662 | EHCIitd itd; |
1663 | ||
0122f472 GH |
1664 | assert(!async); |
1665 | entry = ehci_get_fetch_addr(ehci, async); | |
1666 | ||
55903f1d GH |
1667 | if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1668 | sizeof(EHCIitd) >> 2) < 0) { | |
1669 | return -1; | |
1670 | } | |
0122f472 | 1671 | ehci_trace_itd(ehci, entry, &itd); |
94527ead | 1672 | |
e983395d | 1673 | if (ehci_process_itd(ehci, &itd, entry) != 0) { |
94527ead GH |
1674 | return -1; |
1675 | } | |
1676 | ||
68d55358 DG |
1677 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1678 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1679 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1680 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1681 | |
1682 | return 1; | |
1683 | } | |
1684 | ||
2fe80192 GH |
1685 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1686 | { | |
1687 | uint32_t entry; | |
1688 | EHCIsitd sitd; | |
1689 | ||
1690 | assert(!async); | |
1691 | entry = ehci_get_fetch_addr(ehci, async); | |
1692 | ||
55903f1d GH |
1693 | if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
1694 | sizeof(EHCIsitd) >> 2) < 0) { | |
1695 | return 0; | |
1696 | } | |
2fe80192 GH |
1697 | ehci_trace_sitd(ehci, entry, &sitd); |
1698 | ||
1699 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1700 | /* siTD is not active, nothing to do */; | |
1701 | } else { | |
1702 | /* TODO: split transfers are not implemented */ | |
1703 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1704 | } | |
1705 | ||
1706 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1707 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1708 | return 1; | |
1709 | } | |
1710 | ||
94527ead | 1711 | /* Section 4.10.2 - paragraph 3 */ |
ae0138a8 | 1712 | static int ehci_state_advqueue(EHCIQueue *q) |
94527ead GH |
1713 | { |
1714 | #if 0 | |
1715 | /* TO-DO: 4.10.2 - paragraph 2 | |
1716 | * if I-bit is set to 1 and QH is not active | |
1717 | * go to horizontal QH | |
1718 | */ | |
1719 | if (I-bit set) { | |
26d53979 | 1720 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1721 | goto out; |
1722 | } | |
1723 | #endif | |
1724 | ||
1725 | /* | |
1726 | * want data and alt-next qTD is valid | |
1727 | */ | |
0122f472 | 1728 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
0122f472 GH |
1729 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { |
1730 | q->qtdaddr = q->qh.altnext_qtd; | |
ae0138a8 | 1731 | ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
94527ead GH |
1732 | |
1733 | /* | |
1734 | * next qTD is valid | |
1735 | */ | |
2a5ff735 | 1736 | } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
0122f472 | 1737 | q->qtdaddr = q->qh.next_qtd; |
ae0138a8 | 1738 | ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
94527ead GH |
1739 | |
1740 | /* | |
1741 | * no valid qTD, try next QH | |
1742 | */ | |
1743 | } else { | |
ae0138a8 | 1744 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead GH |
1745 | } |
1746 | ||
1747 | return 1; | |
1748 | } | |
1749 | ||
1750 | /* Section 4.10.2 - paragraph 4 */ | |
ae0138a8 | 1751 | static int ehci_state_fetchqtd(EHCIQueue *q) |
94527ead | 1752 | { |
eb36a88e GH |
1753 | EHCIqtd qtd; |
1754 | EHCIPacket *p; | |
b4ea8664 | 1755 | int again = 1; |
94527ead | 1756 | |
55903f1d GH |
1757 | if (get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
1758 | sizeof(EHCIqtd) >> 2) < 0) { | |
1759 | return 0; | |
1760 | } | |
eb36a88e | 1761 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
94527ead | 1762 | |
773dc9cd | 1763 | p = QTAILQ_FIRST(&q->packets); |
773dc9cd | 1764 | if (p != NULL) { |
287fd3f1 | 1765 | if (p->qtdaddr != q->qtdaddr || |
2c7b15c1 HG |
1766 | (q->async && !NLPTR_TBIT(p->qtd.next) && |
1767 | (p->qtd.next != qtd.next)) || | |
287fd3f1 GH |
1768 | (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) || |
1769 | p->qtd.bufptr[0] != qtd.bufptr[0]) { | |
287fd3f1 | 1770 | ehci_cancel_queue(q); |
5c514681 | 1771 | ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD"); |
287fd3f1 GH |
1772 | p = NULL; |
1773 | } else { | |
1774 | p->qtd = qtd; | |
1775 | ehci_qh_do_overlay(q); | |
1776 | } | |
1777 | } | |
1778 | ||
1779 | if (!(qtd.token & QTD_TOKEN_ACTIVE)) { | |
1780 | if (p != NULL) { | |
1781 | /* transfer canceled by guest (clear active) */ | |
1782 | ehci_cancel_queue(q); | |
1783 | p = NULL; | |
1784 | } | |
1785 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); | |
287fd3f1 | 1786 | } else if (p != NULL) { |
adf47834 HG |
1787 | switch (p->async) { |
1788 | case EHCI_ASYNC_NONE: | |
ef5b2344 | 1789 | case EHCI_ASYNC_INITIALIZED: |
cae5d3f4 | 1790 | /* Not yet executed (MULT), or previously nacked (int) packet */ |
ef5b2344 HG |
1791 | ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
1792 | break; | |
adf47834 | 1793 | case EHCI_ASYNC_INFLIGHT: |
b4ea8664 | 1794 | /* Check if the guest has added new tds to the queue */ |
01e26b0e | 1795 | again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head)); |
ef5b2344 | 1796 | /* Unfinished async handled packet, go horizontal */ |
ae0138a8 | 1797 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
adf47834 HG |
1798 | break; |
1799 | case EHCI_ASYNC_FINISHED: | |
cf1f8169 HG |
1800 | /* |
1801 | * We get here when advqueue moves to a packet which is already | |
1802 | * finished, which can happen with packets queued up by fill_queue | |
1803 | */ | |
ae0138a8 | 1804 | ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
adf47834 | 1805 | break; |
773dc9cd | 1806 | } |
287fd3f1 | 1807 | } else { |
eb36a88e GH |
1808 | p = ehci_alloc_packet(q); |
1809 | p->qtdaddr = q->qtdaddr; | |
1810 | p->qtd = qtd; | |
ae0138a8 | 1811 | ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
94527ead GH |
1812 | } |
1813 | ||
1814 | return again; | |
1815 | } | |
1816 | ||
ae0138a8 | 1817 | static int ehci_state_horizqh(EHCIQueue *q) |
94527ead GH |
1818 | { |
1819 | int again = 0; | |
1820 | ||
ae0138a8 GH |
1821 | if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { |
1822 | ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); | |
1823 | ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); | |
94527ead GH |
1824 | again = 1; |
1825 | } else { | |
ae0138a8 | 1826 | ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
94527ead GH |
1827 | } |
1828 | ||
1829 | return again; | |
1830 | } | |
1831 | ||
01e26b0e | 1832 | /* Returns "again" */ |
eff6dce7 | 1833 | static int ehci_fill_queue(EHCIPacket *p) |
773dc9cd | 1834 | { |
36dfe324 | 1835 | USBEndpoint *ep = p->packet.ep; |
773dc9cd GH |
1836 | EHCIQueue *q = p->queue; |
1837 | EHCIqtd qtd = p->qtd; | |
601a2347 | 1838 | uint32_t qtdaddr; |
773dc9cd GH |
1839 | |
1840 | for (;;) { | |
773dc9cd GH |
1841 | if (NLPTR_TBIT(qtd.next) != 0) { |
1842 | break; | |
1843 | } | |
1844 | qtdaddr = qtd.next; | |
e3a36bce HG |
1845 | /* |
1846 | * Detect circular td lists, Windows creates these, counting on the | |
1847 | * active bit going low after execution to make the queue stop. | |
1848 | */ | |
601a2347 HG |
1849 | QTAILQ_FOREACH(p, &q->packets, next) { |
1850 | if (p->qtdaddr == qtdaddr) { | |
1851 | goto leave; | |
1852 | } | |
e3a36bce | 1853 | } |
55903f1d GH |
1854 | if (get_dwords(q->ehci, NLPTR_GET(qtdaddr), |
1855 | (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2) < 0) { | |
1856 | return -1; | |
1857 | } | |
773dc9cd GH |
1858 | ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); |
1859 | if (!(qtd.token & QTD_TOKEN_ACTIVE)) { | |
1860 | break; | |
1861 | } | |
1862 | p = ehci_alloc_packet(q); | |
1863 | p->qtdaddr = qtdaddr; | |
1864 | p->qtd = qtd; | |
01e26b0e HG |
1865 | if (ehci_execute(p, "queue") == -1) { |
1866 | return -1; | |
eff6dce7 | 1867 | } |
01e26b0e | 1868 | assert(p->packet.status == USB_RET_ASYNC); |
773dc9cd GH |
1869 | p->async = EHCI_ASYNC_INFLIGHT; |
1870 | } | |
601a2347 | 1871 | leave: |
01e26b0e HG |
1872 | usb_device_flush_ep_queue(ep->dev, ep); |
1873 | return 1; | |
773dc9cd GH |
1874 | } |
1875 | ||
ae0138a8 | 1876 | static int ehci_state_execute(EHCIQueue *q) |
94527ead | 1877 | { |
eb36a88e | 1878 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 1879 | int again = 0; |
94527ead | 1880 | |
eb36a88e GH |
1881 | assert(p != NULL); |
1882 | assert(p->qtdaddr == q->qtdaddr); | |
1883 | ||
0122f472 | 1884 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1885 | return -1; |
1886 | } | |
1887 | ||
94527ead GH |
1888 | // TODO verify enough time remains in the uframe as in 4.4.1.1 |
1889 | // TODO write back ptr to async list when done or out of time | |
94527ead | 1890 | |
cae5d3f4 HG |
1891 | /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */ |
1892 | if (!q->async && q->transact_ctr == 0) { | |
1893 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); | |
1894 | again = 1; | |
1895 | goto out; | |
94527ead GH |
1896 | } |
1897 | ||
ae0138a8 | 1898 | if (q->async) { |
0122f472 | 1899 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1900 | } |
1901 | ||
01e26b0e HG |
1902 | again = ehci_execute(p, "process"); |
1903 | if (again == -1) { | |
94527ead GH |
1904 | goto out; |
1905 | } | |
01e26b0e | 1906 | if (p->packet.status == USB_RET_ASYNC) { |
8ac6d699 | 1907 | ehci_flush_qh(q); |
773dc9cd | 1908 | trace_usb_ehci_packet_action(p->queue, p, "async"); |
eb36a88e | 1909 | p->async = EHCI_ASYNC_INFLIGHT; |
ae0138a8 | 1910 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
cae5d3f4 | 1911 | if (q->async) { |
01e26b0e | 1912 | again = ehci_fill_queue(p); |
cae5d3f4 HG |
1913 | } else { |
1914 | again = 1; | |
1915 | } | |
8ac6d699 | 1916 | goto out; |
94527ead GH |
1917 | } |
1918 | ||
ae0138a8 | 1919 | ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
8ac6d699 GH |
1920 | again = 1; |
1921 | ||
94527ead GH |
1922 | out: |
1923 | return again; | |
1924 | } | |
1925 | ||
ae0138a8 | 1926 | static int ehci_state_executing(EHCIQueue *q) |
94527ead | 1927 | { |
eb36a88e | 1928 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 1929 | |
eb36a88e GH |
1930 | assert(p != NULL); |
1931 | assert(p->qtdaddr == q->qtdaddr); | |
1932 | ||
0122f472 | 1933 | ehci_execute_complete(q); |
94527ead | 1934 | |
cae5d3f4 HG |
1935 | /* 4.10.3 */ |
1936 | if (!q->async && q->transact_ctr > 0) { | |
1937 | q->transact_ctr--; | |
94527ead GH |
1938 | } |
1939 | ||
94527ead | 1940 | /* 4.10.5 */ |
e696b1da | 1941 | if (p->packet.status == USB_RET_NAK) { |
ae0138a8 | 1942 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead | 1943 | } else { |
ae0138a8 | 1944 | ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
94527ead GH |
1945 | } |
1946 | ||
8ac6d699 | 1947 | ehci_flush_qh(q); |
574ef171 | 1948 | return 1; |
94527ead GH |
1949 | } |
1950 | ||
1951 | ||
ae0138a8 | 1952 | static int ehci_state_writeback(EHCIQueue *q) |
94527ead | 1953 | { |
eb36a88e | 1954 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
4ed1c57a | 1955 | uint32_t *qtd, addr; |
94527ead GH |
1956 | int again = 0; |
1957 | ||
1958 | /* Write back the QTD from the QH area */ | |
eb36a88e GH |
1959 | assert(p != NULL); |
1960 | assert(p->qtdaddr == q->qtdaddr); | |
1961 | ||
1962 | ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); | |
4ed1c57a GH |
1963 | qtd = (uint32_t *) &q->qh.next_qtd; |
1964 | addr = NLPTR_GET(p->qtdaddr); | |
1965 | put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); | |
eb36a88e | 1966 | ehci_free_packet(p); |
94527ead | 1967 | |
d2bd525f GH |
1968 | /* |
1969 | * EHCI specs say go horizontal here. | |
1970 | * | |
1971 | * We can also advance the queue here for performance reasons. We | |
1972 | * need to take care to only take that shortcut in case we've | |
1973 | * processed the qtd just written back without errors, i.e. halt | |
1974 | * bit is clear. | |
94527ead | 1975 | */ |
d2bd525f | 1976 | if (q->qh.token & QTD_TOKEN_HALT) { |
ae0138a8 | 1977 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
d2bd525f GH |
1978 | again = 1; |
1979 | } else { | |
ae0138a8 | 1980 | ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
94527ead | 1981 | again = 1; |
d2bd525f | 1982 | } |
94527ead GH |
1983 | return again; |
1984 | } | |
1985 | ||
1986 | /* | |
1987 | * This is the state machine that is common to both async and periodic | |
1988 | */ | |
1989 | ||
ae0138a8 | 1990 | static void ehci_advance_state(EHCIState *ehci, int async) |
94527ead | 1991 | { |
0122f472 | 1992 | EHCIQueue *q = NULL; |
94527ead | 1993 | int again; |
94527ead GH |
1994 | |
1995 | do { | |
26d53979 | 1996 | switch(ehci_get_state(ehci, async)) { |
94527ead | 1997 | case EST_WAITLISTHEAD: |
26d53979 | 1998 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
1999 | break; |
2000 | ||
2001 | case EST_FETCHENTRY: | |
26d53979 | 2002 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
2003 | break; |
2004 | ||
2005 | case EST_FETCHQH: | |
0122f472 | 2006 | q = ehci_state_fetchqh(ehci, async); |
ae0138a8 GH |
2007 | if (q != NULL) { |
2008 | assert(q->async == async); | |
2009 | again = 1; | |
2010 | } else { | |
2011 | again = 0; | |
2012 | } | |
94527ead GH |
2013 | break; |
2014 | ||
2015 | case EST_FETCHITD: | |
26d53979 | 2016 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
2017 | break; |
2018 | ||
2fe80192 GH |
2019 | case EST_FETCHSITD: |
2020 | again = ehci_state_fetchsitd(ehci, async); | |
2021 | break; | |
2022 | ||
94527ead | 2023 | case EST_ADVANCEQUEUE: |
ae0138a8 | 2024 | again = ehci_state_advqueue(q); |
94527ead GH |
2025 | break; |
2026 | ||
2027 | case EST_FETCHQTD: | |
ae0138a8 | 2028 | again = ehci_state_fetchqtd(q); |
94527ead GH |
2029 | break; |
2030 | ||
2031 | case EST_HORIZONTALQH: | |
ae0138a8 | 2032 | again = ehci_state_horizqh(q); |
94527ead GH |
2033 | break; |
2034 | ||
2035 | case EST_EXECUTE: | |
ae0138a8 | 2036 | again = ehci_state_execute(q); |
3a215326 GH |
2037 | if (async) { |
2038 | ehci->async_stepdown = 0; | |
2039 | } | |
94527ead GH |
2040 | break; |
2041 | ||
2042 | case EST_EXECUTING: | |
8ac6d699 | 2043 | assert(q != NULL); |
3a215326 GH |
2044 | if (async) { |
2045 | ehci->async_stepdown = 0; | |
2046 | } | |
ae0138a8 | 2047 | again = ehci_state_executing(q); |
94527ead GH |
2048 | break; |
2049 | ||
2050 | case EST_WRITEBACK: | |
b2467216 | 2051 | assert(q != NULL); |
ae0138a8 | 2052 | again = ehci_state_writeback(q); |
80826240 HG |
2053 | if (!async) { |
2054 | ehci->periodic_sched_active = PERIODIC_ACTIVE; | |
2055 | } | |
94527ead GH |
2056 | break; |
2057 | ||
2058 | default: | |
2059 | fprintf(stderr, "Bad state!\n"); | |
2060 | again = -1; | |
8ac6d699 | 2061 | assert(0); |
94527ead GH |
2062 | break; |
2063 | } | |
2064 | ||
2065 | if (again < 0) { | |
2066 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2067 | ehci_reset(ehci); | |
2068 | again = 0; | |
2069 | } | |
2070 | } | |
2071 | while (again); | |
94527ead GH |
2072 | } |
2073 | ||
2074 | static void ehci_advance_async_state(EHCIState *ehci) | |
2075 | { | |
df5d5c5c | 2076 | const int async = 1; |
94527ead | 2077 | |
26d53979 | 2078 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2079 | case EST_INACTIVE: |
ec807d12 | 2080 | if (!ehci_async_enabled(ehci)) { |
94527ead GH |
2081 | break; |
2082 | } | |
26d53979 | 2083 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2084 | // No break, fall through to ACTIVE |
2085 | ||
2086 | case EST_ACTIVE: | |
ec807d12 | 2087 | if (!ehci_async_enabled(ehci)) { |
e850c2b4 | 2088 | ehci_queues_rip_all(ehci, async); |
26d53979 | 2089 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2090 | break; |
2091 | } | |
2092 | ||
4be23939 | 2093 | /* make sure guest has acknowledged the doorbell interrupt */ |
94527ead GH |
2094 | /* TO-DO: is this really needed? */ |
2095 | if (ehci->usbsts & USBSTS_IAA) { | |
2096 | DPRINTF("IAA status bit still set.\n"); | |
2097 | break; | |
2098 | } | |
2099 | ||
94527ead GH |
2100 | /* check that address register has been set */ |
2101 | if (ehci->asynclistaddr == 0) { | |
2102 | break; | |
2103 | } | |
2104 | ||
26d53979 | 2105 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2106 | ehci_advance_state(ehci, async); |
4be23939 HG |
2107 | |
2108 | /* If the doorbell is set, the guest wants to make a change to the | |
2109 | * schedule. The host controller needs to release cached data. | |
2110 | * (section 4.8.2) | |
2111 | */ | |
2112 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2113 | /* Remove all unseen qhs from the async qhs queue */ | |
8f5457eb | 2114 | ehci_queues_rip_unseen(ehci, async); |
1defcbd1 | 2115 | trace_usb_ehci_doorbell_ack(); |
4be23939 | 2116 | ehci->usbcmd &= ~USBCMD_IAAD; |
7efc17af | 2117 | ehci_raise_irq(ehci, USBSTS_IAA); |
4be23939 | 2118 | } |
94527ead GH |
2119 | break; |
2120 | ||
2121 | default: | |
2122 | /* this should only be due to a developer mistake */ | |
2123 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2124 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2125 | assert(0); |
94527ead GH |
2126 | } |
2127 | } | |
2128 | ||
2129 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2130 | { | |
2131 | uint32_t entry; | |
2132 | uint32_t list; | |
df5d5c5c | 2133 | const int async = 0; |
94527ead GH |
2134 | |
2135 | // 4.6 | |
2136 | ||
26d53979 | 2137 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2138 | case EST_INACTIVE: |
ec807d12 | 2139 | if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
26d53979 | 2140 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2141 | // No break, fall through to ACTIVE |
2142 | } else | |
2143 | break; | |
2144 | ||
2145 | case EST_ACTIVE: | |
ec807d12 | 2146 | if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
e850c2b4 | 2147 | ehci_queues_rip_all(ehci, async); |
26d53979 | 2148 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2149 | break; |
2150 | } | |
2151 | ||
2152 | list = ehci->periodiclistbase & 0xfffff000; | |
2153 | /* check that register has been set */ | |
2154 | if (list == 0) { | |
2155 | break; | |
2156 | } | |
2157 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2158 | ||
55903f1d GH |
2159 | if (get_dwords(ehci, list, &entry, 1) < 0) { |
2160 | break; | |
2161 | } | |
94527ead GH |
2162 | |
2163 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2164 | ehci->frindex / 8, list, entry); | |
0122f472 | 2165 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2166 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2167 | ehci_advance_state(ehci, async); | |
8f5457eb | 2168 | ehci_queues_rip_unused(ehci, async); |
94527ead GH |
2169 | break; |
2170 | ||
94527ead GH |
2171 | default: |
2172 | /* this should only be due to a developer mistake */ | |
2173 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2174 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2175 | assert(0); |
94527ead GH |
2176 | } |
2177 | } | |
2178 | ||
6ceced0b GH |
2179 | static void ehci_update_frindex(EHCIState *ehci, int frames) |
2180 | { | |
2181 | int i; | |
2182 | ||
2183 | if (!ehci_enabled(ehci)) { | |
2184 | return; | |
2185 | } | |
2186 | ||
2187 | for (i = 0; i < frames; i++) { | |
2188 | ehci->frindex += 8; | |
2189 | ||
2190 | if (ehci->frindex == 0x00002000) { | |
7efc17af | 2191 | ehci_raise_irq(ehci, USBSTS_FLR); |
6ceced0b GH |
2192 | } |
2193 | ||
2194 | if (ehci->frindex == 0x00004000) { | |
7efc17af | 2195 | ehci_raise_irq(ehci, USBSTS_FLR); |
6ceced0b | 2196 | ehci->frindex = 0; |
ffa1f2e0 | 2197 | if (ehci->usbsts_frindex >= 0x00004000) { |
7efc17af GH |
2198 | ehci->usbsts_frindex -= 0x00004000; |
2199 | } else { | |
2200 | ehci->usbsts_frindex = 0; | |
2201 | } | |
6ceced0b GH |
2202 | } |
2203 | } | |
2204 | } | |
2205 | ||
94527ead GH |
2206 | static void ehci_frame_timer(void *opaque) |
2207 | { | |
2208 | EHCIState *ehci = opaque; | |
7efc17af | 2209 | int need_timer = 0; |
94527ead | 2210 | int64_t expire_time, t_now; |
adddecb1 | 2211 | uint64_t ns_elapsed; |
f020ed36 | 2212 | int frames, skipped_frames; |
94527ead | 2213 | int i; |
94527ead | 2214 | |
94527ead | 2215 | t_now = qemu_get_clock_ns(vm_clock); |
adddecb1 GH |
2216 | ns_elapsed = t_now - ehci->last_run_ns; |
2217 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead | 2218 | |
3a215326 | 2219 | if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { |
7efc17af | 2220 | need_timer++; |
94527ead | 2221 | |
f020ed36 GH |
2222 | if (frames > ehci->maxframes) { |
2223 | skipped_frames = frames - ehci->maxframes; | |
2224 | ehci_update_frindex(ehci, skipped_frames); | |
2225 | ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; | |
2226 | frames -= skipped_frames; | |
2227 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2228 | } | |
2229 | ||
3a215326 | 2230 | for (i = 0; i < frames; i++) { |
8f74ed1e HG |
2231 | /* |
2232 | * If we're running behind schedule, we should not catch up | |
2233 | * too fast, as that will make some guests unhappy: | |
2234 | * 1) We must process a minimum of MIN_FR_PER_TICK frames, | |
2235 | * otherwise we will never catch up | |
2236 | * 2) Process frames until the guest has requested an irq (IOC) | |
2237 | */ | |
2238 | if (i >= MIN_FR_PER_TICK) { | |
2239 | ehci_commit_irq(ehci); | |
2240 | if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) { | |
2241 | break; | |
2242 | } | |
2243 | } | |
80826240 HG |
2244 | if (ehci->periodic_sched_active) { |
2245 | ehci->periodic_sched_active--; | |
2246 | } | |
3a215326 | 2247 | ehci_update_frindex(ehci, 1); |
f020ed36 | 2248 | ehci_advance_periodic_state(ehci); |
3a215326 GH |
2249 | ehci->last_run_ns += FRAME_TIMER_NS; |
2250 | } | |
2251 | } else { | |
80826240 | 2252 | ehci->periodic_sched_active = 0; |
3a215326 GH |
2253 | ehci_update_frindex(ehci, frames); |
2254 | ehci->last_run_ns += FRAME_TIMER_NS * frames; | |
94527ead GH |
2255 | } |
2256 | ||
80826240 HG |
2257 | if (ehci->periodic_sched_active) { |
2258 | ehci->async_stepdown = 0; | |
2259 | } else if (ehci->async_stepdown < ehci->maxframes / 2) { | |
2260 | ehci->async_stepdown++; | |
2261 | } | |
2262 | ||
94527ead GH |
2263 | /* Async is not inside loop since it executes everything it can once |
2264 | * called | |
2265 | */ | |
3a215326 | 2266 | if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) { |
7efc17af | 2267 | need_timer++; |
afb7a0b8 | 2268 | ehci_advance_async_state(ehci); |
3a215326 | 2269 | } |
94527ead | 2270 | |
7efc17af GH |
2271 | ehci_commit_irq(ehci); |
2272 | if (ehci->usbsts_pending) { | |
2273 | need_timer++; | |
2274 | ehci->async_stepdown = 0; | |
daf25307 | 2275 | } |
f0ad01f9 | 2276 | |
40862309 GH |
2277 | if (ehci_enabled(ehci) && (ehci->usbintr & USBSTS_FLR)) { |
2278 | need_timer++; | |
2279 | } | |
2280 | ||
7efc17af | 2281 | if (need_timer) { |
44272b0f HG |
2282 | /* If we've raised int, we speed up the timer, so that we quickly |
2283 | * notice any new packets queued up in response */ | |
2284 | if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) { | |
2285 | expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 2); | |
2286 | ehci->int_req_by_async = false; | |
2287 | } else { | |
2288 | expire_time = t_now + (get_ticks_per_sec() | |
afb7a0b8 | 2289 | * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ); |
44272b0f | 2290 | } |
7efc17af GH |
2291 | qemu_mod_timer(ehci->frame_timer, expire_time); |
2292 | } | |
94527ead GH |
2293 | } |
2294 | ||
3e4f910c GH |
2295 | static const MemoryRegionOps ehci_mmio_caps_ops = { |
2296 | .read = ehci_caps_read, | |
2297 | .valid.min_access_size = 1, | |
2298 | .valid.max_access_size = 4, | |
2299 | .impl.min_access_size = 1, | |
2300 | .impl.max_access_size = 1, | |
2301 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2302 | }; | |
2303 | ||
2304 | static const MemoryRegionOps ehci_mmio_opreg_ops = { | |
2305 | .read = ehci_opreg_read, | |
2306 | .write = ehci_opreg_write, | |
2307 | .valid.min_access_size = 4, | |
2308 | .valid.max_access_size = 4, | |
2309 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2310 | }; | |
2311 | ||
2312 | static const MemoryRegionOps ehci_mmio_port_ops = { | |
2313 | .read = ehci_port_read, | |
2314 | .write = ehci_port_write, | |
2315 | .valid.min_access_size = 4, | |
2316 | .valid.max_access_size = 4, | |
e57964f5 | 2317 | .endianness = DEVICE_LITTLE_ENDIAN, |
94527ead GH |
2318 | }; |
2319 | ||
94527ead GH |
2320 | static USBPortOps ehci_port_ops = { |
2321 | .attach = ehci_attach, | |
2322 | .detach = ehci_detach, | |
4706ab6c | 2323 | .child_detach = ehci_child_detach, |
a0a3167a | 2324 | .wakeup = ehci_wakeup, |
94527ead GH |
2325 | .complete = ehci_async_complete_packet, |
2326 | }; | |
2327 | ||
07771f6f | 2328 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2329 | .register_companion = ehci_register_companion, |
80826240 | 2330 | .wakeup_endpoint = ehci_wakeup_endpoint, |
07771f6f GH |
2331 | }; |
2332 | ||
9a773408 GH |
2333 | static int usb_ehci_post_load(void *opaque, int version_id) |
2334 | { | |
2335 | EHCIState *s = opaque; | |
2336 | int i; | |
2337 | ||
2338 | for (i = 0; i < NB_PORTS; i++) { | |
2339 | USBPort *companion = s->companion_ports[i]; | |
2340 | if (companion == NULL) { | |
2341 | continue; | |
2342 | } | |
2343 | if (s->portsc[i] & PORTSC_POWNER) { | |
2344 | companion->dev = s->ports[i].dev; | |
2345 | } else { | |
2346 | companion->dev = NULL; | |
2347 | } | |
2348 | } | |
2349 | ||
2350 | return 0; | |
2351 | } | |
2352 | ||
ceab6f96 HG |
2353 | static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) |
2354 | { | |
2355 | EHCIState *ehci = opaque; | |
2356 | ||
2357 | /* | |
2358 | * We don't migrate the EHCIQueue-s, instead we rebuild them for the | |
2359 | * schedule in guest memory. We must do the rebuilt ASAP, so that | |
2360 | * USB-devices which have async handled packages have a packet in the | |
2361 | * ep queue to match the completion with. | |
2362 | */ | |
2363 | if (state == RUN_STATE_RUNNING) { | |
2364 | ehci_advance_async_state(ehci); | |
2365 | } | |
2366 | ||
2367 | /* | |
2368 | * The schedule rebuilt from guest memory could cause the migration dest | |
2369 | * to miss a QH unlink, and fail to cancel packets, since the unlinked QH | |
2370 | * will never have existed on the destination. Therefor we must flush the | |
2371 | * async schedule on savevm to catch any not yet noticed unlinks. | |
2372 | */ | |
2373 | if (state == RUN_STATE_SAVE_VM) { | |
2374 | ehci_advance_async_state(ehci); | |
2375 | ehci_queues_rip_unseen(ehci, 1); | |
2376 | } | |
2377 | } | |
2378 | ||
0bf96f94 | 2379 | const VMStateDescription vmstate_ehci = { |
5010d4dc | 2380 | .name = "ehci-core", |
6d3b6d3d GH |
2381 | .version_id = 2, |
2382 | .minimum_version_id = 1, | |
9a773408 GH |
2383 | .post_load = usb_ehci_post_load, |
2384 | .fields = (VMStateField[]) { | |
9a773408 GH |
2385 | /* mmio registers */ |
2386 | VMSTATE_UINT32(usbcmd, EHCIState), | |
2387 | VMSTATE_UINT32(usbsts, EHCIState), | |
6d3b6d3d GH |
2388 | VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2), |
2389 | VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2), | |
9a773408 GH |
2390 | VMSTATE_UINT32(usbintr, EHCIState), |
2391 | VMSTATE_UINT32(frindex, EHCIState), | |
2392 | VMSTATE_UINT32(ctrldssegment, EHCIState), | |
2393 | VMSTATE_UINT32(periodiclistbase, EHCIState), | |
2394 | VMSTATE_UINT32(asynclistaddr, EHCIState), | |
2395 | VMSTATE_UINT32(configflag, EHCIState), | |
2396 | VMSTATE_UINT32(portsc[0], EHCIState), | |
2397 | VMSTATE_UINT32(portsc[1], EHCIState), | |
2398 | VMSTATE_UINT32(portsc[2], EHCIState), | |
2399 | VMSTATE_UINT32(portsc[3], EHCIState), | |
2400 | VMSTATE_UINT32(portsc[4], EHCIState), | |
2401 | VMSTATE_UINT32(portsc[5], EHCIState), | |
2402 | /* frame timer */ | |
2403 | VMSTATE_TIMER(frame_timer, EHCIState), | |
2404 | VMSTATE_UINT64(last_run_ns, EHCIState), | |
2405 | VMSTATE_UINT32(async_stepdown, EHCIState), | |
2406 | /* schedule state */ | |
2407 | VMSTATE_UINT32(astate, EHCIState), | |
2408 | VMSTATE_UINT32(pstate, EHCIState), | |
2409 | VMSTATE_UINT32(a_fetch_addr, EHCIState), | |
2410 | VMSTATE_UINT32(p_fetch_addr, EHCIState), | |
2411 | VMSTATE_END_OF_LIST() | |
2412 | } | |
9490fb06 GH |
2413 | }; |
2414 | ||
0bf96f94 | 2415 | void usb_ehci_initfn(EHCIState *s, DeviceState *dev) |
94527ead | 2416 | { |
94527ead GH |
2417 | int i; |
2418 | ||
3e4f910c | 2419 | /* 2.2 host controller interface version */ |
27a11324 | 2420 | s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase); |
3e4f910c GH |
2421 | s->caps[0x01] = 0x00; |
2422 | s->caps[0x02] = 0x00; | |
2423 | s->caps[0x03] = 0x01; /* HC version */ | |
2424 | s->caps[0x04] = NB_PORTS; /* Number of downstream ports */ | |
2425 | s->caps[0x05] = 0x00; /* No companion ports at present */ | |
2426 | s->caps[0x06] = 0x00; | |
2427 | s->caps[0x07] = 0x00; | |
2428 | s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ | |
3e4f910c GH |
2429 | s->caps[0x0a] = 0x00; |
2430 | s->caps[0x0b] = 0x00; | |
94527ead | 2431 | |
5010d4dc | 2432 | usb_bus_new(&s->bus, &ehci_bus_ops, dev); |
94527ead GH |
2433 | for(i = 0; i < NB_PORTS; i++) { |
2434 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2435 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2436 | s->ports[i].dev = 0; |
2437 | } | |
2438 | ||
2439 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
0262f65a | 2440 | s->async_bh = qemu_bh_new(ehci_frame_timer, s); |
df5d5c5c HG |
2441 | QTAILQ_INIT(&s->aqueues); |
2442 | QTAILQ_INIT(&s->pqueues); | |
7341ea07 | 2443 | usb_packet_init(&s->ipacket); |
94527ead GH |
2444 | |
2445 | qemu_register_reset(ehci_reset, s); | |
ceab6f96 | 2446 | qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s); |
94527ead | 2447 | |
3e4f910c GH |
2448 | memory_region_init(&s->mem, "ehci", MMIO_SIZE); |
2449 | memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, | |
27a11324 | 2450 | "capabilities", CAPA_SIZE); |
3e4f910c | 2451 | memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, |
27a11324 | 2452 | "operational", PORTSC_BEGIN); |
3e4f910c GH |
2453 | memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, |
2454 | "ports", PORTSC_END - PORTSC_BEGIN); | |
2455 | ||
27a11324 PC |
2456 | memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); |
2457 | memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); | |
2458 | memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, | |
2459 | &s->mem_ports); | |
5010d4dc PC |
2460 | } |
2461 | ||
94527ead GH |
2462 | /* |
2463 | * vim: expandtab ts=4 | |
2464 | */ |