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qom: Fix warning from Sparse
[mirror_qemu.git] / hw / usb / hcd-musb.c
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942ac052
AZ		 1/*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
942ac052
AZ		 20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23#include "qemu-common.h"
1de7afc9 24#include "qemu/timer.h"
f1ae32a1
GH		 25#include "hw/usb.h"
26#include "hw/irq.h"
27#include "hw/hw.h"
942ac052
AZ		 28
29/* Common USB registers */
30#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31#define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34#define MUSB_HDRC_INTRRX 0x04
35#define MUSB_HDRC_INTRTXE 0x06
36#define MUSB_HDRC_INTRRXE 0x08
37#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43/* Per-EP registers in indexed mode */
44#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46/* EP FIFOs */
47#define MUSB_HDRC_FIFO 0x20
48
49/* Additional Control Registers */
50#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52/* These are indexed */
53#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58/* Some more registers */
59#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62/* Added in HDRC 1.9(?) & MHDRC 1.4 */
63/* ULPI pass-through */
64#define MUSB_HDRC_ULPI_VBUSCTL 0x70
65#define MUSB_HDRC_ULPI_REGDATA 0x74
66#define MUSB_HDRC_ULPI_REGADDR 0x75
67#define MUSB_HDRC_ULPI_REGCTL 0x76
68
69/* Extended config & PHY control */
70#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78/* Per-EP BUSCTL registers */
79#define MUSB_HDRC_BUSCTL 0x80
80
81/* Per-EP registers in flat mode */
82#define MUSB_HDRC_EP 0x100
83
84/* offsets to registers in flat model */
85#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101/* "Bus control" registers */
102#define MUSB_HDRC_TXFUNCADDR 0x00
103#define MUSB_HDRC_TXHUBADDR 0x02
104#define MUSB_HDRC_TXHUBPORT 0x03
105
106#define MUSB_HDRC_RXFUNCADDR 0x04
107#define MUSB_HDRC_RXHUBADDR 0x06
108#define MUSB_HDRC_RXHUBPORT 0x07
109
110/*
111 * MUSBHDRC Register bit masks
112 */
113
114/* POWER */
115#define MGC_M_POWER_ISOUPDATE 0x80
116#define MGC_M_POWER_SOFTCONN 0x40
117#define MGC_M_POWER_HSENAB 0x20
118#define MGC_M_POWER_HSMODE 0x10
119#define MGC_M_POWER_RESET 0x08
120#define MGC_M_POWER_RESUME 0x04
121#define MGC_M_POWER_SUSPENDM 0x02
122#define MGC_M_POWER_ENSUSPEND 0x01
123
124/* INTRUSB */
125#define MGC_M_INTR_SUSPEND 0x01
126#define MGC_M_INTR_RESUME 0x02
127#define MGC_M_INTR_RESET 0x04
128#define MGC_M_INTR_BABBLE 0x04
129#define MGC_M_INTR_SOF 0x08
130#define MGC_M_INTR_CONNECT 0x10
131#define MGC_M_INTR_DISCONNECT 0x20
132#define MGC_M_INTR_SESSREQ 0x40
133#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136/* DEVCTL */
137#define MGC_M_DEVCTL_BDEVICE 0x80
138#define MGC_M_DEVCTL_FSDEV 0x40
139#define MGC_M_DEVCTL_LSDEV 0x20
140#define MGC_M_DEVCTL_VBUS 0x18
141#define MGC_S_DEVCTL_VBUS 3
142#define MGC_M_DEVCTL_HM 0x04
143#define MGC_M_DEVCTL_HR 0x02
144#define MGC_M_DEVCTL_SESSION 0x01
145
146/* TESTMODE */
147#define MGC_M_TEST_FORCE_HOST 0x80
148#define MGC_M_TEST_FIFO_ACCESS 0x40
149#define MGC_M_TEST_FORCE_FS 0x20
150#define MGC_M_TEST_FORCE_HS 0x10
151#define MGC_M_TEST_PACKET 0x08
152#define MGC_M_TEST_K 0x04
153#define MGC_M_TEST_J 0x02
154#define MGC_M_TEST_SE0_NAK 0x01
155
156/* CSR0 */
157#define MGC_M_CSR0_FLUSHFIFO 0x0100
158#define MGC_M_CSR0_TXPKTRDY 0x0002
159#define MGC_M_CSR0_RXPKTRDY 0x0001
160
161/* CSR0 in Peripheral mode */
162#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164#define MGC_M_CSR0_P_SENDSTALL 0x0020
165#define MGC_M_CSR0_P_SETUPEND 0x0010
166#define MGC_M_CSR0_P_DATAEND 0x0008
167#define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169/* CSR0 in Host mode */
170#define MGC_M_CSR0_H_NO_PING 0x0800
171#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174#define MGC_M_CSR0_H_STATUSPKT 0x0040
175#define MGC_M_CSR0_H_REQPKT 0x0020
176#define MGC_M_CSR0_H_ERROR 0x0010
177#define MGC_M_CSR0_H_SETUPPKT 0x0008
178#define MGC_M_CSR0_H_RXSTALL 0x0004
179
180/* CONFIGDATA */
181#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190/* TXCSR in Peripheral and Host mode */
191#define MGC_M_TXCSR_AUTOSET 0x8000
192#define MGC_M_TXCSR_ISO 0x4000
193#define MGC_M_TXCSR_MODE 0x2000
194#define MGC_M_TXCSR_DMAENAB 0x1000
195#define MGC_M_TXCSR_FRCDATATOG 0x0800
196#define MGC_M_TXCSR_DMAMODE 0x0400
197#define MGC_M_TXCSR_CLRDATATOG 0x0040
198#define MGC_M_TXCSR_FLUSHFIFO 0x0008
199#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200#define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202/* TXCSR in Peripheral mode */
203#define MGC_M_TXCSR_P_INCOMPTX 0x0080
204#define MGC_M_TXCSR_P_SENTSTALL 0x0020
205#define MGC_M_TXCSR_P_SENDSTALL 0x0010
206#define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208/* TXCSR in Host mode */
209#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212#define MGC_M_TXCSR_H_RXSTALL 0x0020
213#define MGC_M_TXCSR_H_ERROR 0x0004
214
215/* RXCSR in Peripheral and Host mode */
216#define MGC_M_RXCSR_AUTOCLEAR 0x8000
217#define MGC_M_RXCSR_DMAENAB 0x2000
218#define MGC_M_RXCSR_DISNYET 0x1000
219#define MGC_M_RXCSR_DMAMODE 0x0800
220#define MGC_M_RXCSR_INCOMPRX 0x0100
221#define MGC_M_RXCSR_CLRDATATOG 0x0080
222#define MGC_M_RXCSR_FLUSHFIFO 0x0010
223#define MGC_M_RXCSR_DATAERROR 0x0008
224#define MGC_M_RXCSR_FIFOFULL 0x0002
225#define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227/* RXCSR in Peripheral mode */
228#define MGC_M_RXCSR_P_ISO 0x4000
229#define MGC_M_RXCSR_P_SENTSTALL 0x0040
230#define MGC_M_RXCSR_P_SENDSTALL 0x0020
231#define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233/* RXCSR in Host mode */
234#define MGC_M_RXCSR_H_AUTOREQ 0x4000
235#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237#define MGC_M_RXCSR_H_RXSTALL 0x0040
238#define MGC_M_RXCSR_H_REQPKT 0x0020
239#define MGC_M_RXCSR_H_ERROR 0x0004
240
241/* HUBADDR */
242#define MGC_M_HUBADDR_MULTI_TT 0x80
243
244/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250#define MGC_M_ULPI_REGCTL_REG 0x01
251
384dce1e
RV		 252/* #define MUSB_DEBUG */
253
254#ifdef MUSB_DEBUG
255#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257#else
258#define TRACE(...)
259#endif
260
261
618c169b
GH		 262static void musb_attach(USBPort *port);
263static void musb_detach(USBPort *port);
4706ab6c 264static void musb_child_detach(USBPort *port, USBDevice *child);
d47e59b8 265static void musb_schedule_cb(USBPort *port, USBPacket *p);
4706ab6c 266static void musb_async_cancel_device(MUSBState *s, USBDevice *dev);
942ac052 267
0d86d2be
GH		 268static USBPortOps musb_port_ops = {
269 .attach = musb_attach,
618c169b 270 .detach = musb_detach,
4706ab6c 271 .child_detach = musb_child_detach,
13a9a0d3 272 .complete = musb_schedule_cb,
0d86d2be
GH		 273};
274
07771f6f 275static USBBusOps musb_bus_ops = {
07771f6f
GH		 276};
277
5dc1672b
GH		 278typedef struct MUSBPacket MUSBPacket;
279typedef struct MUSBEndPoint MUSBEndPoint;
280
281struct MUSBPacket {
282 USBPacket p;
283 MUSBEndPoint *ep;
284 int dir;
285};
286
287struct MUSBEndPoint {
bc24a225
PB		 288 uint16_t faddr[2];
289 uint8_t haddr[2];
290 uint8_t hport[2];
291 uint16_t csr[2];
292 uint16_t maxp[2];
293 uint16_t rxcount;
294 uint8_t type[2];
295 uint8_t interval[2];
296 uint8_t config;
297 uint8_t fifosize;
298 int timeout[2]; /* Always in microframes */
299
384dce1e 300 uint8_t *buf[2];
bc24a225
PB		 301 int fifolen[2];
302 int fifostart[2];
303 int fifoaddr[2];
5dc1672b 304 MUSBPacket packey[2];
bc24a225
PB		 305 int status[2];
306 int ext_size[2];
307
308 /* For callbacks' use */
309 int epnum;
310 int interrupt[2];
311 MUSBState *musb;
312 USBCallback *delayed_cb[2];
313 QEMUTimer *intv_timer[2];
5dc1672b 314};
bc24a225
PB		 315
316struct MUSBState {
406c2075 317 qemu_irq irqs[musb_irq_max];
b2317837 318 USBBus bus;
942ac052
AZ		 319 USBPort port;
320
321 int idx;
322 uint8_t devctl;
323 uint8_t power;
324 uint8_t faddr;
325
326 uint8_t intr;
327 uint8_t mask;
328 uint16_t tx_intr;
329 uint16_t tx_mask;
330 uint16_t rx_intr;
331 uint16_t rx_mask;
332
333 int setup_len;
334 int session;
335
384dce1e 336 uint8_t buf[0x8000];
942ac052 337
942ac052
AZ		 338 /* Duplicating the world since 2008!... probably we should have 32
339 * logical, single endpoints instead. */
bc24a225 340 MUSBEndPoint ep[16];
5dc1672b
GH		 341};
342
5b1cdb4e 343void musb_reset(MUSBState *s)
942ac052 344{
942ac052
AZ		 345 int i;
346
942ac052 347 s->faddr = 0x00;
5b1cdb4e 348 s->devctl = 0;
942ac052
AZ		 349 s->power = MGC_M_POWER_HSENAB;
350 s->tx_intr = 0x0000;
351 s->rx_intr = 0x0000;
352 s->tx_mask = 0xffff;
353 s->rx_mask = 0xffff;
354 s->intr = 0x00;
355 s->mask = 0x06;
356 s->idx = 0;
357
5b1cdb4e
JR		 358 s->setup_len = 0;
359 s->session = 0;
360 memset(s->buf, 0, sizeof(s->buf));
361
942ac052
AZ		 362 /* TODO: _DW */
363 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
364 for (i = 0; i < 16; i ++) {
365 s->ep[i].fifosize = 64;
366 s->ep[i].maxp[0] = 0x40;
367 s->ep[i].maxp[1] = 0x40;
368 s->ep[i].musb = s;
369 s->ep[i].epnum = i;
4f4321c1
GH		 370 usb_packet_init(&s->ep[i].packey[0].p);
371 usb_packet_init(&s->ep[i].packey[1].p);
942ac052 372 }
5b1cdb4e
JR		 373}
374
375struct MUSBState *musb_init(DeviceState *parent_device, int gpio_base)
376{
377 MUSBState *s = g_malloc0(sizeof(*s));
378 int i;
379
380 for (i = 0; i < musb_irq_max; i++) {
381 s->irqs[i] = qdev_get_gpio_in(parent_device, gpio_base + i);
382 }
383
384 musb_reset(s);
942ac052 385
c889b3a5 386 usb_bus_new(&s->bus, sizeof(s->bus), &musb_bus_ops, parent_device);
ace1318b 387 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
843d4e0c 388 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
942ac052
AZ		 389
390 return s;
391}
392
bc24a225 393static void musb_vbus_set(MUSBState *s, int level)
942ac052
AZ		 394{
395 if (level)
396 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
397 else
398 s->devctl &= ~MGC_M_DEVCTL_VBUS;
399
400 qemu_set_irq(s->irqs[musb_set_vbus], level);
401}
402
bc24a225 403static void musb_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 404{
405 if (!level) {
406 s->intr &= ~(1 << line);
407 qemu_irq_lower(s->irqs[line]);
408 } else if (s->mask & (1 << line)) {
409 s->intr |= 1 << line;
410 qemu_irq_raise(s->irqs[line]);
411 }
412}
413
bc24a225 414static void musb_tx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 415{
416 if (!level) {
417 s->tx_intr &= ~(1 << line);
418 if (!s->tx_intr)
419 qemu_irq_lower(s->irqs[musb_irq_tx]);
420 } else if (s->tx_mask & (1 << line)) {
421 s->tx_intr |= 1 << line;
422 qemu_irq_raise(s->irqs[musb_irq_tx]);
423 }
424}
425
bc24a225 426static void musb_rx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 427{
428 if (line) {
429 if (!level) {
430 s->rx_intr &= ~(1 << line);
431 if (!s->rx_intr)
432 qemu_irq_lower(s->irqs[musb_irq_rx]);
433 } else if (s->rx_mask & (1 << line)) {
434 s->rx_intr |= 1 << line;
435 qemu_irq_raise(s->irqs[musb_irq_rx]);
436 }
437 } else
438 musb_tx_intr_set(s, line, level);
439}
440
bc24a225 441uint32_t musb_core_intr_get(MUSBState *s)
942ac052
AZ		 442{
443 return (s->rx_intr << 15) | s->tx_intr;
444}
445
bc24a225 446void musb_core_intr_clear(MUSBState *s, uint32_t mask)
942ac052
AZ		 447{
448 if (s->rx_intr) {
449 s->rx_intr &= mask >> 15;
450 if (!s->rx_intr)
451 qemu_irq_lower(s->irqs[musb_irq_rx]);
452 }
453
454 if (s->tx_intr) {
455 s->tx_intr &= mask & 0xffff;
456 if (!s->tx_intr)
457 qemu_irq_lower(s->irqs[musb_irq_tx]);
458 }
459}
460
bc24a225 461void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
942ac052
AZ		 462{
463 s->ep[epnum].ext_size[!is_tx] = size;
464 s->ep[epnum].fifostart[0] = 0;
465 s->ep[epnum].fifostart[1] = 0;
466 s->ep[epnum].fifolen[0] = 0;
467 s->ep[epnum].fifolen[1] = 0;
468}
469
bc24a225 470static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
942ac052
AZ		 471{
472 int detect_prev = prev_dev && prev_sess;
473 int detect = !!s->port.dev && s->session;
474
475 if (detect && !detect_prev) {
476 /* Let's skip the ID pin sense and VBUS sense formalities and
477 * and signal a successful SRP directly. This should work at least
478 * for the Linux driver stack. */
479 musb_intr_set(s, musb_irq_connect, 1);
480
481 if (s->port.dev->speed == USB_SPEED_LOW) {
482 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
483 s->devctl |= MGC_M_DEVCTL_LSDEV;
484 } else {
485 s->devctl |= MGC_M_DEVCTL_FSDEV;
486 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
487 }
488
489 /* A-mode? */
490 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
491
492 /* Host-mode bit? */
493 s->devctl |= MGC_M_DEVCTL_HM;
494#if 1
495 musb_vbus_set(s, 1);
496#endif
497 } else if (!detect && detect_prev) {
498#if 1
499 musb_vbus_set(s, 0);
500#endif
501 }
502}
503
504/* Attach or detach a device on our only port. */
618c169b 505static void musb_attach(USBPort *port)
942ac052 506{
bc24a225 507 MUSBState *s = (MUSBState *) port->opaque;
942ac052 508
618c169b
GH		 509 musb_intr_set(s, musb_irq_vbus_request, 1);
510 musb_session_update(s, 0, s->session);
511}
942ac052 512
618c169b
GH		 513static void musb_detach(USBPort *port)
514{
515 MUSBState *s = (MUSBState *) port->opaque;
942ac052 516
4706ab6c
HG		 517 musb_async_cancel_device(s, port->dev);
518
618c169b
GH		 519 musb_intr_set(s, musb_irq_disconnect, 1);
520 musb_session_update(s, 1, s->session);
942ac052
AZ		 521}
522
4706ab6c
HG		 523static void musb_child_detach(USBPort *port, USBDevice *child)
524{
525 MUSBState *s = (MUSBState *) port->opaque;
526
527 musb_async_cancel_device(s, child);
528}
529
b3e5759e 530static void musb_cb_tick0(void *opaque)
942ac052 531{
bc24a225 532 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 533
5dc1672b 534 ep->delayed_cb[0](&ep->packey[0].p, opaque);
942ac052
AZ		 535}
536
b3e5759e 537static void musb_cb_tick1(void *opaque)
942ac052 538{
bc24a225 539 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 540
5dc1672b 541 ep->delayed_cb[1](&ep->packey[1].p, opaque);
942ac052
AZ		 542}
543
544#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
545
d47e59b8 546static void musb_schedule_cb(USBPort *port, USBPacket *packey)
942ac052 547{
13a9a0d3
GH		 548 MUSBPacket *p = container_of(packey, MUSBPacket, p);
549 MUSBEndPoint *ep = p->ep;
550 int dir = p->dir;
942ac052
AZ		 551 int timeout = 0;
552
553 if (ep->status[dir] == USB_RET_NAK)
554 timeout = ep->timeout[dir];
555 else if (ep->interrupt[dir])
556 timeout = 8;
557 else
13a9a0d3 558 return musb_cb_tick(ep);
942ac052
AZ		 559
560 if (!ep->intv_timer[dir])
bc72ad67 561 ep->intv_timer[dir] = timer_new_ns(QEMU_CLOCK_VIRTUAL, musb_cb_tick, ep);
942ac052 562
bc72ad67 563 timer_mod(ep->intv_timer[dir], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
6ee093c9 564 muldiv64(timeout, get_ticks_per_sec(), 8000));
942ac052
AZ		 565}
566
942ac052
AZ		 567static int musb_timeout(int ttype, int speed, int val)
568{
569#if 1
570 return val << 3;
571#endif
572
573 switch (ttype) {
574 case USB_ENDPOINT_XFER_CONTROL:
575 if (val < 2)
576 return 0;
577 else if (speed == USB_SPEED_HIGH)
578 return 1 << (val - 1);
579 else
580 return 8 << (val - 1);
581
582 case USB_ENDPOINT_XFER_INT:
583 if (speed == USB_SPEED_HIGH)
584 if (val < 2)
585 return 0;
586 else
587 return 1 << (val - 1);
588 else
589 return val << 3;
590
591 case USB_ENDPOINT_XFER_BULK:
592 case USB_ENDPOINT_XFER_ISOC:
593 if (val < 2)
594 return 0;
595 else if (speed == USB_SPEED_HIGH)
596 return 1 << (val - 1);
597 else
598 return 8 << (val - 1);
599 /* TODO: what with low-speed Bulk and Isochronous? */
600 }
601
2ac71179 602 hw_error("bad interval\n");
942ac052
AZ		 603}
604
b3e5759e 605static void musb_packet(MUSBState *s, MUSBEndPoint *ep,
942ac052
AZ		 606 int epnum, int pid, int len, USBCallback cb, int dir)
607{
87e043f1 608 USBDevice *dev;
079d0b7f 609 USBEndpoint *uep;
942ac052 610 int idx = epnum && dir;
a9be7657 611 int id;
942ac052
AZ		 612 int ttype;
613
614 /* ep->type[0,1] contains:
615 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
616 * in bits 5:4 the transfer type (BULK / INT)
617 * in bits 3:0 the EP num
618 */
619 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
620
621 ep->timeout[dir] = musb_timeout(ttype,
622 ep->type[idx] >> 6, ep->interval[idx]);
623 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
624 ep->delayed_cb[dir] = cb;
942ac052 625
942ac052 626 /* A wild guess on the FADDR semantics... */
079d0b7f
GH		 627 dev = usb_find_device(&s->port, ep->faddr[idx]);
628 uep = usb_ep_get(dev, pid, ep->type[idx] & 0xf);
a9be7657
PB		 629 id = pid;
630 if (uep) {
631 id |= (dev->addr << 16) | (uep->nr << 8);
632 }
633 usb_packet_setup(&ep->packey[dir].p, pid, uep, 0, id, false, true);
4f4321c1 634 usb_packet_addbuf(&ep->packey[dir].p, ep->buf[idx], len);
5dc1672b
GH		 635 ep->packey[dir].ep = ep;
636 ep->packey[dir].dir = dir;
942ac052 637
9a77a0f5 638 usb_handle_packet(dev, &ep->packey[dir].p);
942ac052 639
9a77a0f5 640 if (ep->packey[dir].p.status == USB_RET_ASYNC) {
36dfe324 641 usb_device_flush_ep_queue(dev, uep);
942ac052
AZ		 642 ep->status[dir] = len;
643 return;
644 }
645
9a77a0f5
HG		 646 if (ep->packey[dir].p.status == USB_RET_SUCCESS) {
647 ep->status[dir] = ep->packey[dir].p.actual_length;
648 } else {
649 ep->status[dir] = ep->packey[dir].p.status;
650 }
d47e59b8 651 musb_schedule_cb(&s->port, &ep->packey[dir].p);
942ac052
AZ		 652}
653
654static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
655{
656 /* Unfortunately we can't use packey->devep because that's the remote
657 * endpoint number and may be different than our local. */
bc24a225 658 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 659 int epnum = ep->epnum;
bc24a225 660 MUSBState *s = ep->musb;
942ac052
AZ		 661
662 ep->fifostart[0] = 0;
663 ep->fifolen[0] = 0;
664#ifdef CLEAR_NAK
665 if (ep->status[0] != USB_RET_NAK) {
666#endif
667 if (epnum)
668 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
669 else
670 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
671#ifdef CLEAR_NAK
672 }
673#endif
674
675 /* Clear all of the error bits first */
676 if (epnum)
677 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
678 MGC_M_TXCSR_H_NAKTIMEOUT);
679 else
680 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
681 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
682
683 if (ep->status[0] == USB_RET_STALL) {
684 /* Command not supported by target! */
685 ep->status[0] = 0;
686
687 if (epnum)
688 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
689 else
690 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
691 }
692
693 if (ep->status[0] == USB_RET_NAK) {
694 ep->status[0] = 0;
695
696 /* NAK timeouts are only generated in Bulk transfers and
697 * Data-errors in Isochronous. */
698 if (ep->interrupt[0]) {
699 return;
700 }
701
702 if (epnum)
703 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
704 else
705 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
706 }
707
708 if (ep->status[0] < 0) {
709 if (ep->status[0] == USB_RET_BABBLE)
710 musb_intr_set(s, musb_irq_rst_babble, 1);
711
712 /* Pretend we've tried three times already and failed (in
713 * case of USB_TOKEN_SETUP). */
714 if (epnum)
715 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
716 else
717 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
718
719 musb_tx_intr_set(s, epnum, 1);
720 return;
721 }
722 /* TODO: check len for over/underruns of an OUT packet? */
723
724#ifdef SETUPLEN_HACK
725 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
726 s->setup_len = ep->packey[0].data[6];
727#endif
728
729 /* In DMA mode: if no error, assert DMA request for this EP,
730 * and skip the interrupt. */
731 musb_tx_intr_set(s, epnum, 1);
732}
733
734static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
735{
736 /* Unfortunately we can't use packey->devep because that's the remote
737 * endpoint number and may be different than our local. */
bc24a225 738 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 739 int epnum = ep->epnum;
bc24a225 740 MUSBState *s = ep->musb;
942ac052
AZ		 741
742 ep->fifostart[1] = 0;
743 ep->fifolen[1] = 0;
744
745#ifdef CLEAR_NAK
746 if (ep->status[1] != USB_RET_NAK) {
747#endif
748 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
749 if (!epnum)
750 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
751#ifdef CLEAR_NAK
752 }
753#endif
754
755 /* Clear all of the imaginable error bits first */
756 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
757 MGC_M_RXCSR_DATAERROR);
758 if (!epnum)
759 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
760 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
761
762 if (ep->status[1] == USB_RET_STALL) {
763 ep->status[1] = 0;
942ac052
AZ		 764
765 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
766 if (!epnum)
767 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
768 }
769
770 if (ep->status[1] == USB_RET_NAK) {
771 ep->status[1] = 0;
772
773 /* NAK timeouts are only generated in Bulk transfers and
774 * Data-errors in Isochronous. */
775 if (ep->interrupt[1])
776 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
4f4321c1 777 packey->iov.size, musb_rx_packet_complete, 1);
942ac052
AZ		 778
779 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
780 if (!epnum)
781 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
782 }
783
784 if (ep->status[1] < 0) {
785 if (ep->status[1] == USB_RET_BABBLE) {
786 musb_intr_set(s, musb_irq_rst_babble, 1);
787 return;
788 }
789
790 /* Pretend we've tried three times already and failed (in
791 * case of a control transfer). */
792 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
793 if (!epnum)
794 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
795
796 musb_rx_intr_set(s, epnum, 1);
797 return;
798 }
799 /* TODO: check len for over/underruns of an OUT packet? */
800 /* TODO: perhaps make use of e->ext_size[1] here. */
801
942ac052
AZ		 802 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
803 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
804 if (!epnum)
805 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
806
9a77a0f5 807 ep->rxcount = ep->status[1]; /* XXX: MIN(packey->len, ep->maxp[1]); */
942ac052
AZ		 808 /* In DMA mode: assert DMA request for this EP */
809 }
810
811 /* Only if DMA has not been asserted */
812 musb_rx_intr_set(s, epnum, 1);
813}
814
4706ab6c 815static void musb_async_cancel_device(MUSBState *s, USBDevice *dev)
07771f6f 816{
07771f6f
GH		 817 int ep, dir;
818
819 for (ep = 0; ep < 16; ep++) {
820 for (dir = 0; dir < 2; dir++) {
f53c398a
GH		 821 if (!usb_packet_is_inflight(&s->ep[ep].packey[dir].p) ||
822 s->ep[ep].packey[dir].p.ep->dev != dev) {
07771f6f
GH		 823 continue;
824 }
825 usb_cancel_packet(&s->ep[ep].packey[dir].p);
826 /* status updates needed here? */
827 }
828 }
829}
830
bc24a225 831static void musb_tx_rdy(MUSBState *s, int epnum)
942ac052 832{
bc24a225 833 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 834 int pid;
835 int total, valid = 0;
384dce1e 836 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
942ac052
AZ		 837 ep->fifostart[0] += ep->fifolen[0];
838 ep->fifolen[0] = 0;
839
840 /* XXX: how's the total size of the packet retrieved exactly in
841 * the generic case? */
842 total = ep->maxp[0] & 0x3ff;
843
844 if (ep->ext_size[0]) {
845 total = ep->ext_size[0];
846 ep->ext_size[0] = 0;
847 valid = 1;
848 }
849
850 /* If the packet is not fully ready yet, wait for a next segment. */
384dce1e 851 if (epnum && (ep->fifostart[0]) < total)
942ac052
AZ		 852 return;
853
854 if (!valid)
384dce1e 855 total = ep->fifostart[0];
942ac052
AZ		 856
857 pid = USB_TOKEN_OUT;
858 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
859 pid = USB_TOKEN_SETUP;
384dce1e
RV		 860 if (total != 8) {
861 TRACE("illegal SETUPPKT length of %i bytes", total);
862 }
942ac052
AZ		 863 /* Controller should retry SETUP packets three times on errors
864 * but it doesn't make sense for us to do that. */
865 }
866
867 return musb_packet(s, ep, epnum, pid,
868 total, musb_tx_packet_complete, 0);
869}
870
bc24a225 871static void musb_rx_req(MUSBState *s, int epnum)
942ac052 872{
bc24a225 873 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 874 int total;
875
876 /* If we already have a packet, which didn't fit into the
877 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
5dc1672b 878 if (ep->packey[1].p.pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
384dce1e 879 (ep->fifostart[1]) + ep->rxcount <
4f4321c1 880 ep->packey[1].p.iov.size) {
384dce1e
RV		 881 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
882 ep->fifostart[1] += ep->rxcount;
942ac052
AZ		 883 ep->fifolen[1] = 0;
884
4f4321c1 885 ep->rxcount = MIN(ep->packey[0].p.iov.size - (ep->fifostart[1]),
942ac052
AZ		 886 ep->maxp[1]);
887
888 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
889 if (!epnum)
890 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
891
892 /* Clear all of the error bits first */
893 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
894 MGC_M_RXCSR_DATAERROR);
895 if (!epnum)
896 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
897 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
898
899 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
900 if (!epnum)
901 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
902 musb_rx_intr_set(s, epnum, 1);
903 return;
904 }
905
906 /* The driver sets maxp[1] to 64 or less because it knows the hardware
907 * FIFO is this deep. Bigger packets get split in
908 * usb_generic_handle_packet but we can also do the splitting locally
909 * for performance. It turns out we can also have a bigger FIFO and
910 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
911 * OK with single packets of even 32KB and we avoid splitting, however
912 * usb_msd.c sometimes sends a packet bigger than what Linux expects
913 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
914 * hides this overrun from Linux. Up to 4096 everything is fine
915 * though. Currently this is disabled.
916 *
917 * XXX: mind ep->fifosize. */
918 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
919
920#ifdef SETUPLEN_HACK
921 /* Why should *we* do that instead of Linux? */
922 if (!epnum) {
5dc1672b 923 if (ep->packey[0].p.devaddr == 2) {
942ac052 924 total = MIN(s->setup_len, 8);
5dc1672b 925 } else {
942ac052 926 total = MIN(s->setup_len, 64);
5dc1672b 927 }
942ac052
AZ		 928 s->setup_len -= total;
929 }
930#endif
931
932 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
933 total, musb_rx_packet_complete, 1);
934}
935
384dce1e
RV		 936static uint8_t musb_read_fifo(MUSBEndPoint *ep)
937{
938 uint8_t value;
939 if (ep->fifolen[1] >= 64) {
940 /* We have a FIFO underrun */
941 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
942 return 0x00000000;
943 }
944 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
945 * (if AUTOREQ is set) */
946
947 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
948 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
949 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
950 return value;
951}
952
953static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
954{
955 TRACE("EP%d = %02x", ep->epnum, value);
956 if (ep->fifolen[0] >= 64) {
957 /* We have a FIFO overrun */
958 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
959 return;
960 }
961
962 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
963 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
964}
965
bc24a225 966static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
942ac052
AZ		 967{
968 if (ep->intv_timer[dir])
bc72ad67 969 timer_del(ep->intv_timer[dir]);
942ac052
AZ		 970}
971
972/* Bus control */
973static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
974{
bc24a225 975 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 976
977 switch (addr) {
978 /* For USB2.0 HS hubs only */
979 case MUSB_HDRC_TXHUBADDR:
980 return s->ep[ep].haddr[0];
981 case MUSB_HDRC_TXHUBPORT:
982 return s->ep[ep].hport[0];
983 case MUSB_HDRC_RXHUBADDR:
984 return s->ep[ep].haddr[1];
985 case MUSB_HDRC_RXHUBPORT:
986 return s->ep[ep].hport[1];
987
988 default:
384dce1e 989 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 990 return 0x00;
991 };
992}
993
994static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
995{
bc24a225 996 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 997
998 switch (addr) {
384dce1e
RV		 999 case MUSB_HDRC_TXFUNCADDR:
1000 s->ep[ep].faddr[0] = value;
1001 break;
1002 case MUSB_HDRC_RXFUNCADDR:
1003 s->ep[ep].faddr[1] = value;
1004 break;
942ac052
AZ		 1005 case MUSB_HDRC_TXHUBADDR:
1006 s->ep[ep].haddr[0] = value;
1007 break;
1008 case MUSB_HDRC_TXHUBPORT:
1009 s->ep[ep].hport[0] = value;
1010 break;
1011 case MUSB_HDRC_RXHUBADDR:
1012 s->ep[ep].haddr[1] = value;
1013 break;
1014 case MUSB_HDRC_RXHUBPORT:
1015 s->ep[ep].hport[1] = value;
1016 break;
1017
1018 default:
384dce1e
RV		 1019 TRACE("unknown register 0x%02x", addr);
1020 break;
942ac052
AZ		 1021 };
1022}
1023
1024static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
1025{
bc24a225 1026 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1027
1028 switch (addr) {
1029 case MUSB_HDRC_TXFUNCADDR:
1030 return s->ep[ep].faddr[0];
1031 case MUSB_HDRC_RXFUNCADDR:
1032 return s->ep[ep].faddr[1];
1033
1034 default:
1035 return musb_busctl_readb(s, ep, addr) |
1036 (musb_busctl_readb(s, ep, addr | 1) << 8);
1037 };
1038}
1039
1040static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
1041{
bc24a225 1042 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1043
1044 switch (addr) {
1045 case MUSB_HDRC_TXFUNCADDR:
1046 s->ep[ep].faddr[0] = value;
1047 break;
1048 case MUSB_HDRC_RXFUNCADDR:
1049 s->ep[ep].faddr[1] = value;
1050 break;
1051
1052 default:
1053 musb_busctl_writeb(s, ep, addr, value & 0xff);
1054 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1055 };
1056}
1057
1058/* Endpoint control */
1059static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1060{
bc24a225 1061 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1062
1063 switch (addr) {
1064 case MUSB_HDRC_TXTYPE:
1065 return s->ep[ep].type[0];
1066 case MUSB_HDRC_TXINTERVAL:
1067 return s->ep[ep].interval[0];
1068 case MUSB_HDRC_RXTYPE:
1069 return s->ep[ep].type[1];
1070 case MUSB_HDRC_RXINTERVAL:
1071 return s->ep[ep].interval[1];
1072 case (MUSB_HDRC_FIFOSIZE & ~1):
1073 return 0x00;
1074 case MUSB_HDRC_FIFOSIZE:
1075 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
384dce1e
RV		 1076 case MUSB_HDRC_RXCOUNT:
1077 return s->ep[ep].rxcount;
942ac052
AZ		 1078
1079 default:
384dce1e 1080 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 1081 return 0x00;
1082 };
1083}
1084
1085static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1086{
bc24a225 1087 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1088
1089 switch (addr) {
1090 case MUSB_HDRC_TXTYPE:
1091 s->ep[ep].type[0] = value;
1092 break;
1093 case MUSB_HDRC_TXINTERVAL:
1094 s->ep[ep].interval[0] = value;
1095 musb_ep_frame_cancel(&s->ep[ep], 0);
1096 break;
1097 case MUSB_HDRC_RXTYPE:
1098 s->ep[ep].type[1] = value;
1099 break;
1100 case MUSB_HDRC_RXINTERVAL:
1101 s->ep[ep].interval[1] = value;
1102 musb_ep_frame_cancel(&s->ep[ep], 1);
1103 break;
1104 case (MUSB_HDRC_FIFOSIZE & ~1):
1105 break;
1106 case MUSB_HDRC_FIFOSIZE:
384dce1e 1107 TRACE("somebody messes with fifosize (now %i bytes)", value);
942ac052
AZ		 1108 s->ep[ep].fifosize = value;
1109 break;
942ac052 1110 default:
384dce1e
RV		 1111 TRACE("unknown register 0x%02x", addr);
1112 break;
942ac052
AZ		 1113 };
1114}
1115
1116static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1117{
bc24a225 1118 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1119 uint16_t ret;
1120
1121 switch (addr) {
1122 case MUSB_HDRC_TXMAXP:
1123 return s->ep[ep].maxp[0];
1124 case MUSB_HDRC_TXCSR:
1125 return s->ep[ep].csr[0];
1126 case MUSB_HDRC_RXMAXP:
1127 return s->ep[ep].maxp[1];
1128 case MUSB_HDRC_RXCSR:
1129 ret = s->ep[ep].csr[1];
1130
1131 /* TODO: This and other bits probably depend on
1132 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1133 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1134 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1135
1136 return ret;
1137 case MUSB_HDRC_RXCOUNT:
1138 return s->ep[ep].rxcount;
1139
1140 default:
1141 return musb_ep_readb(s, ep, addr) |
1142 (musb_ep_readb(s, ep, addr | 1) << 8);
1143 };
1144}
1145
1146static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1147{
bc24a225 1148 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1149
1150 switch (addr) {
1151 case MUSB_HDRC_TXMAXP:
1152 s->ep[ep].maxp[0] = value;
1153 break;
1154 case MUSB_HDRC_TXCSR:
1155 if (ep) {
1156 s->ep[ep].csr[0] &= value & 0xa6;
1157 s->ep[ep].csr[0] |= value & 0xff59;
1158 } else {
1159 s->ep[ep].csr[0] &= value & 0x85;
1160 s->ep[ep].csr[0] |= value & 0xf7a;
1161 }
1162
1163 musb_ep_frame_cancel(&s->ep[ep], 0);
1164
1165 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1166 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1167 s->ep[ep].fifolen[0] = 0;
1168 s->ep[ep].fifostart[0] = 0;
1169 if (ep)
1170 s->ep[ep].csr[0] &=
1171 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1172 else
1173 s->ep[ep].csr[0] &=
1174 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1175 }
1176 if (
1177 (ep &&
1178#ifdef CLEAR_NAK
1179 (value & MGC_M_TXCSR_TXPKTRDY) &&
1180 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1181#else
1182 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1183#endif
1184 (!ep &&
1185#ifdef CLEAR_NAK
1186 (value & MGC_M_CSR0_TXPKTRDY) &&
1187 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1188#else
1189 (value & MGC_M_CSR0_TXPKTRDY)))
1190#endif
1191 musb_tx_rdy(s, ep);
1192 if (!ep &&
1193 (value & MGC_M_CSR0_H_REQPKT) &&
1194#ifdef CLEAR_NAK
1195 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1196 MGC_M_CSR0_RXPKTRDY)))
1197#else
1198 !(value & MGC_M_CSR0_RXPKTRDY))
1199#endif
1200 musb_rx_req(s, ep);
1201 break;
1202
1203 case MUSB_HDRC_RXMAXP:
1204 s->ep[ep].maxp[1] = value;
1205 break;
1206 case MUSB_HDRC_RXCSR:
1207 /* (DMA mode only) */
1208 if (
1209 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1210 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1211 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1212 value |= MGC_M_RXCSR_H_REQPKT;
1213
1214 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1215 s->ep[ep].csr[1] |= value & 0xfeb0;
1216
1217 musb_ep_frame_cancel(&s->ep[ep], 1);
1218
1219 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1220 s->ep[ep].fifolen[1] = 0;
1221 s->ep[ep].fifostart[1] = 0;
1222 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1223 /* If double buffering and we have two packets ready, flush
1224 * only the first one and set up the fifo at the second packet. */
1225 }
1226#ifdef CLEAR_NAK
1227 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1228#else
1229 if (value & MGC_M_RXCSR_H_REQPKT)
1230#endif
1231 musb_rx_req(s, ep);
1232 break;
1233 case MUSB_HDRC_RXCOUNT:
1234 s->ep[ep].rxcount = value;
1235 break;
1236
1237 default:
1238 musb_ep_writeb(s, ep, addr, value & 0xff);
1239 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1240 };
1241}
1242
1243/* Generic control */
a8170e5e 1244static uint32_t musb_readb(void *opaque, hwaddr addr)
942ac052 1245{
bc24a225 1246 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1247 int ep, i;
1248 uint8_t ret;
1249
1250 switch (addr) {
1251 case MUSB_HDRC_FADDR:
1252 return s->faddr;
1253 case MUSB_HDRC_POWER:
1254 return s->power;
1255 case MUSB_HDRC_INTRUSB:
1256 ret = s->intr;
1257 for (i = 0; i < sizeof(ret) * 8; i ++)
1258 if (ret & (1 << i))
1259 musb_intr_set(s, i, 0);
1260 return ret;
1261 case MUSB_HDRC_INTRUSBE:
1262 return s->mask;
1263 case MUSB_HDRC_INDEX:
1264 return s->idx;
1265 case MUSB_HDRC_TESTMODE:
1266 return 0x00;
1267
1268 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1269 return musb_ep_readb(s, s->idx, addr & 0xf);
1270
1271 case MUSB_HDRC_DEVCTL:
1272 return s->devctl;
1273
1274 case MUSB_HDRC_TXFIFOSZ:
1275 case MUSB_HDRC_RXFIFOSZ:
1276 case MUSB_HDRC_VCTRL:
1277 /* TODO */
1278 return 0x00;
1279
1280 case MUSB_HDRC_HWVERS:
1281 return (1 << 10) | 400;
1282
1283 case (MUSB_HDRC_VCTRL | 1):
1284 case (MUSB_HDRC_HWVERS | 1):
1285 case (MUSB_HDRC_DEVCTL | 1):
1286 return 0x00;
1287
1288 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1289 ep = (addr >> 3) & 0xf;
1290 return musb_busctl_readb(s, ep, addr & 0x7);
1291
1292 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1293 ep = (addr >> 4) & 0xf;
1294 return musb_ep_readb(s, ep, addr & 0xf);
1295
384dce1e
RV		 1296 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1297 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1298 return musb_read_fifo(s->ep + ep);
1299
942ac052 1300 default:
384dce1e 1301 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1302 return 0x00;
1303 };
1304}
1305
a8170e5e 1306static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
942ac052 1307{
bc24a225 1308 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1309 int ep;
1310
1311 switch (addr) {
1312 case MUSB_HDRC_FADDR:
1313 s->faddr = value & 0x7f;
1314 break;
1315 case MUSB_HDRC_POWER:
1316 s->power = (value & 0xef) | (s->power & 0x10);
1317 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1318 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
d28f4e2d 1319 usb_device_reset(s->port.dev);
942ac052
AZ		 1320 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1321 if ((value & MGC_M_POWER_HSENAB) &&
1322 s->port.dev->speed == USB_SPEED_HIGH)
1323 s->power |= MGC_M_POWER_HSMODE; /* Success */
1324 /* Restart frame counting. */
1325 }
1326 if (value & MGC_M_POWER_SUSPENDM) {
1327 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1328 * is set, also go into low power mode. Frame counting stops. */
1329 /* XXX: Cleared when the interrupt register is read */
1330 }
1331 if (value & MGC_M_POWER_RESUME) {
1332 /* Wait 20ms and signal resuming on the bus. Frame counting
1333 * restarts. */
1334 }
1335 break;
1336 case MUSB_HDRC_INTRUSB:
1337 break;
1338 case MUSB_HDRC_INTRUSBE:
1339 s->mask = value & 0xff;
1340 break;
1341 case MUSB_HDRC_INDEX:
1342 s->idx = value & 0xf;
1343 break;
1344 case MUSB_HDRC_TESTMODE:
1345 break;
1346
1347 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1348 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1349 break;
1350
1351 case MUSB_HDRC_DEVCTL:
1352 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1353 musb_session_update(s,
1354 !!s->port.dev,
1355 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1356
1357 /* It seems this is the only R/W bit in this register? */
1358 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1359 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1360 break;
1361
1362 case MUSB_HDRC_TXFIFOSZ:
1363 case MUSB_HDRC_RXFIFOSZ:
1364 case MUSB_HDRC_VCTRL:
1365 /* TODO */
1366 break;
1367
1368 case (MUSB_HDRC_VCTRL | 1):
1369 case (MUSB_HDRC_DEVCTL | 1):
1370 break;
1371
1372 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1373 ep = (addr >> 3) & 0xf;
1374 musb_busctl_writeb(s, ep, addr & 0x7, value);
1375 break;
1376
1377 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1378 ep = (addr >> 4) & 0xf;
1379 musb_ep_writeb(s, ep, addr & 0xf, value);
1380 break;
1381
384dce1e
RV		 1382 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1383 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1384 musb_write_fifo(s->ep + ep, value & 0xff);
1385 break;
1386
942ac052 1387 default:
384dce1e
RV		 1388 TRACE("unknown register 0x%02x", (int) addr);
1389 break;
942ac052
AZ		 1390 };
1391}
1392
a8170e5e 1393static uint32_t musb_readh(void *opaque, hwaddr addr)
942ac052 1394{
bc24a225 1395 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1396 int ep, i;
1397 uint16_t ret;
1398
1399 switch (addr) {
1400 case MUSB_HDRC_INTRTX:
1401 ret = s->tx_intr;
1402 /* Auto clear */
1403 for (i = 0; i < sizeof(ret) * 8; i ++)
1404 if (ret & (1 << i))
1405 musb_tx_intr_set(s, i, 0);
1406 return ret;
1407 case MUSB_HDRC_INTRRX:
1408 ret = s->rx_intr;
1409 /* Auto clear */
1410 for (i = 0; i < sizeof(ret) * 8; i ++)
1411 if (ret & (1 << i))
1412 musb_rx_intr_set(s, i, 0);
1413 return ret;
1414 case MUSB_HDRC_INTRTXE:
1415 return s->tx_mask;
1416 case MUSB_HDRC_INTRRXE:
1417 return s->rx_mask;
1418
1419 case MUSB_HDRC_FRAME:
1420 /* TODO */
1421 return 0x0000;
1422 case MUSB_HDRC_TXFIFOADDR:
1423 return s->ep[s->idx].fifoaddr[0];
1424 case MUSB_HDRC_RXFIFOADDR:
1425 return s->ep[s->idx].fifoaddr[1];
1426
1427 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1428 return musb_ep_readh(s, s->idx, addr & 0xf);
1429
1430 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1431 ep = (addr >> 3) & 0xf;
1432 return musb_busctl_readh(s, ep, addr & 0x7);
1433
1434 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1435 ep = (addr >> 4) & 0xf;
1436 return musb_ep_readh(s, ep, addr & 0xf);
1437
384dce1e
RV		 1438 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1439 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1440 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1441
942ac052
AZ		 1442 default:
1443 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1444 };
1445}
1446
a8170e5e 1447static void musb_writeh(void *opaque, hwaddr addr, uint32_t value)
942ac052 1448{
bc24a225 1449 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1450 int ep;
1451
1452 switch (addr) {
1453 case MUSB_HDRC_INTRTXE:
1454 s->tx_mask = value;
1455 /* XXX: the masks seem to apply on the raising edge like with
1456 * edge-triggered interrupts, thus no need to update. I may be
1457 * wrong though. */
1458 break;
1459 case MUSB_HDRC_INTRRXE:
1460 s->rx_mask = value;
1461 break;
1462
1463 case MUSB_HDRC_FRAME:
1464 /* TODO */
1465 break;
1466 case MUSB_HDRC_TXFIFOADDR:
1467 s->ep[s->idx].fifoaddr[0] = value;
1468 s->ep[s->idx].buf[0] =
384dce1e 1469 s->buf + ((value << 3) & 0x7ff );
942ac052
AZ		 1470 break;
1471 case MUSB_HDRC_RXFIFOADDR:
1472 s->ep[s->idx].fifoaddr[1] = value;
1473 s->ep[s->idx].buf[1] =
384dce1e 1474 s->buf + ((value << 3) & 0x7ff);
942ac052
AZ		 1475 break;
1476
1477 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1478 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1479 break;
1480
1481 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1482 ep = (addr >> 3) & 0xf;
1483 musb_busctl_writeh(s, ep, addr & 0x7, value);
1484 break;
1485
1486 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1487 ep = (addr >> 4) & 0xf;
1488 musb_ep_writeh(s, ep, addr & 0xf, value);
1489 break;
1490
384dce1e
RV		 1491 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1492 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1493 musb_write_fifo(s->ep + ep, value & 0xff);
1494 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1495 break;
1496
942ac052
AZ		 1497 default:
1498 musb_writeb(s, addr, value & 0xff);
1499 musb_writeb(s, addr | 1, value >> 8);
1500 };
1501}
1502
a8170e5e 1503static uint32_t musb_readw(void *opaque, hwaddr addr)
942ac052 1504{
bc24a225 1505 MUSBState *s = (MUSBState *) opaque;
384dce1e 1506 int ep;
942ac052
AZ		 1507
1508 switch (addr) {
1509 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1510 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1511 return ( musb_read_fifo(s->ep + ep) |
1512 musb_read_fifo(s->ep + ep) << 8 |
1513 musb_read_fifo(s->ep + ep) << 16 |
1514 musb_read_fifo(s->ep + ep) << 24 );
942ac052 1515 default:
384dce1e 1516 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1517 return 0x00000000;
1518 };
1519}
1520
a8170e5e 1521static void musb_writew(void *opaque, hwaddr addr, uint32_t value)
942ac052 1522{
bc24a225 1523 MUSBState *s = (MUSBState *) opaque;
384dce1e 1524 int ep;
942ac052
AZ		 1525
1526 switch (addr) {
1527 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1528 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1529 musb_write_fifo(s->ep + ep, value & 0xff);
1530 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1531 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1532 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
942ac052 1533 break;
942ac052 1534 default:
384dce1e
RV		 1535 TRACE("unknown register 0x%02x", (int) addr);
1536 break;
942ac052
AZ		 1537 };
1538}
1539
d60efc6b 1540CPUReadMemoryFunc * const musb_read[] = {
942ac052
AZ		 1541 musb_readb,
1542 musb_readh,
1543 musb_readw,
1544};
1545
d60efc6b 1546CPUWriteMemoryFunc * const musb_write[] = {
942ac052
AZ		 1547 musb_writeb,
1548 musb_writeh,
1549 musb_writew,
1550};
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