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1/*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "qemu/osdep.h"
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22#include "qapi/error.h"
23#include "qemu/timer.h"
24#include "hw/usb.h"
d6454270 25#include "migration/vmstate.h"
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26#include "hw/pci/pci.h"
27#include "hw/sysbus.h"
28#include "hw/qdev-dma.h"
a27bd6c7 29#include "hw/qdev-properties.h"
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30#include "trace.h"
31#include "hcd-ohci.h"
db1015e9 32#include "qom/object.h"
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33
34#define TYPE_PCI_OHCI "pci-ohci"
db1015e9 35typedef struct OHCIPCIState OHCIPCIState;
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36DECLARE_INSTANCE_CHECKER(OHCIPCIState, PCI_OHCI,
37 TYPE_PCI_OHCI)
34d97308 38
db1015e9 39struct OHCIPCIState {
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40 /*< private >*/
41 PCIDevice parent_obj;
42 /*< public >*/
43
44 OHCIState state;
45 char *masterbus;
46 uint32_t num_ports;
47 uint32_t firstport;
db1015e9 48};
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49
50/**
51 * A typical PCI OHCI will additionally set PERR in its configspace to
52 * signal that it got an error.
53 */
54static void ohci_pci_die(struct OHCIState *ohci)
55{
56 OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state);
57
58 ohci_sysbus_die(ohci);
59
60 pci_set_word(dev->parent_obj.config + PCI_STATUS,
61 PCI_STATUS_DETECTED_PARITY);
62}
63
64static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp)
65{
66 Error *err = NULL;
67 OHCIPCIState *ohci = PCI_OHCI(dev);
68
69 dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */
70 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
71
72 usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0,
73 ohci->masterbus, ohci->firstport,
74 pci_get_address_space(dev), ohci_pci_die, &err);
75 if (err) {
76 error_propagate(errp, err);
77 return;
78 }
79
80 ohci->state.irq = pci_allocate_irq(dev);
81 pci_register_bar(dev, 0, 0, &ohci->state.mem);
82}
83
84static void usb_ohci_exit(PCIDevice *dev)
85{
86 OHCIPCIState *ohci = PCI_OHCI(dev);
87 OHCIState *s = &ohci->state;
88
89 trace_usb_ohci_exit(s->name);
90 ohci_bus_stop(s);
91
92 if (s->async_td) {
93 usb_cancel_packet(&s->usb_packet);
94 s->async_td = 0;
95 }
96 ohci_stop_endpoints(s);
97
98 if (!ohci->masterbus) {
99 usb_bus_release(&s->bus);
100 }
101
102 timer_del(s->eof_timer);
103 timer_free(s->eof_timer);
104}
105
106static void usb_ohci_reset_pci(DeviceState *d)
107{
108 PCIDevice *dev = PCI_DEVICE(d);
109 OHCIPCIState *ohci = PCI_OHCI(dev);
110 OHCIState *s = &ohci->state;
111
112 ohci_hard_reset(s);
113}
114
115static Property ohci_pci_properties[] = {
116 DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
117 DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
118 DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
119 DEFINE_PROP_END_OF_LIST(),
120};
121
122static const VMStateDescription vmstate_ohci = {
123 .name = "ohci",
124 .version_id = 1,
125 .minimum_version_id = 1,
126 .fields = (VMStateField[]) {
127 VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState),
128 VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState),
129 VMSTATE_END_OF_LIST()
130 }
131};
132
133static void ohci_pci_class_init(ObjectClass *klass, void *data)
134{
135 DeviceClass *dc = DEVICE_CLASS(klass);
136 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
137
138 k->realize = usb_ohci_realize_pci;
139 k->exit = usb_ohci_exit;
140 k->vendor_id = PCI_VENDOR_ID_APPLE;
141 k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
142 k->class_id = PCI_CLASS_SERIAL_USB;
143 set_bit(DEVICE_CATEGORY_USB, dc->categories);
144 dc->desc = "Apple USB Controller";
4f67d30b 145 device_class_set_props(dc, ohci_pci_properties);
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146 dc->hotpluggable = false;
147 dc->vmsd = &vmstate_ohci;
148 dc->reset = usb_ohci_reset_pci;
149}
150
151static const TypeInfo ohci_pci_info = {
152 .name = TYPE_PCI_OHCI,
153 .parent = TYPE_PCI_DEVICE,
154 .instance_size = sizeof(OHCIPCIState),
155 .class_init = ohci_pci_class_init,
156 .interfaces = (InterfaceInfo[]) {
157 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
158 { },
159 },
160};
161
162static void ohci_pci_register_types(void)
163{
164 type_register_static(&ohci_pci_info);
165}
166
167type_init(ohci_pci_register_types)