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Commit | Line | Data |
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0d92ed30 PB |
1 | /* |
2 | * QEMU USB OHCI Emulation | |
3 | * Copyright (c) 2004 Gianni Tedesco | |
4 | * Copyright (c) 2006 CodeSourcery | |
e24ad6f1 | 5 | * Copyright (c) 2006 Openedhand Ltd. |
0d92ed30 PB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
0d92ed30 PB |
19 | * |
20 | * TODO: | |
21 | * o Isochronous transfers | |
22 | * o Allocate bandwidth in frames properly | |
23 | * o Disable timers when nothing needs to be done, or remove timer usage | |
24 | * all together. | |
0d92ed30 PB |
25 | * o BIOS work to boot from USB storage |
26 | */ | |
27 | ||
f1ae32a1 | 28 | #include "hw/hw.h" |
1de7afc9 | 29 | #include "qemu/timer.h" |
f1ae32a1 | 30 | #include "hw/usb.h" |
a2cb15b0 | 31 | #include "hw/pci/pci.h" |
f1ae32a1 | 32 | #include "hw/sysbus.h" |
9ac6a217 | 33 | #include "hw/qdev-dma.h" |
dc1f5988 | 34 | #include "trace.h" |
0d92ed30 | 35 | |
0d92ed30 PB |
36 | /* This causes frames to occur 1000x slower */ |
37 | //#define OHCI_TIME_WARP 1 | |
38 | ||
0d92ed30 PB |
39 | /* Number of Downstream Ports on the root hub. */ |
40 | ||
41 | #define OHCI_MAX_PORTS 15 | |
42 | ||
43 | static int64_t usb_frame_time; | |
44 | static int64_t usb_bit_time; | |
45 | ||
46 | typedef struct OHCIPort { | |
47 | USBPort port; | |
48 | uint32_t ctrl; | |
49 | } OHCIPort; | |
50 | ||
51 | typedef struct { | |
b2317837 | 52 | USBBus bus; |
d537cf6c | 53 | qemu_irq irq; |
6da48311 | 54 | MemoryRegion mem; |
df32fd1c | 55 | AddressSpace *as; |
0d92ed30 | 56 | int num_ports; |
e24ad6f1 | 57 | const char *name; |
0d92ed30 PB |
58 | |
59 | QEMUTimer *eof_timer; | |
60 | int64_t sof_time; | |
61 | ||
62 | /* OHCI state */ | |
63 | /* Control partition */ | |
64 | uint32_t ctl, status; | |
65 | uint32_t intr_status; | |
66 | uint32_t intr; | |
67 | ||
68 | /* memory pointer partition */ | |
69 | uint32_t hcca; | |
70 | uint32_t ctrl_head, ctrl_cur; | |
71 | uint32_t bulk_head, bulk_cur; | |
72 | uint32_t per_cur; | |
73 | uint32_t done; | |
69e25d26 | 74 | int32_t done_count; |
0d92ed30 PB |
75 | |
76 | /* Frame counter partition */ | |
69e25d26 AK |
77 | uint16_t fsmps; |
78 | uint8_t fit; | |
79 | uint16_t fi; | |
80 | uint8_t frt; | |
0d92ed30 PB |
81 | uint16_t frame_number; |
82 | uint16_t padding; | |
83 | uint32_t pstart; | |
84 | uint32_t lst; | |
85 | ||
86 | /* Root Hub partition */ | |
87 | uint32_t rhdesc_a, rhdesc_b; | |
88 | uint32_t rhstatus; | |
89 | OHCIPort rhport[OHCI_MAX_PORTS]; | |
4d611c9a | 90 | |
e24ad6f1 PB |
91 | /* PXA27x Non-OHCI events */ |
92 | uint32_t hstatus; | |
93 | uint32_t hmask; | |
94 | uint32_t hreset; | |
95 | uint32_t htest; | |
96 | ||
ac611340 | 97 | /* SM501 local memory offset */ |
9ac6a217 | 98 | dma_addr_t localmem_base; |
ac611340 | 99 | |
4d611c9a PB |
100 | /* Active packets. */ |
101 | uint32_t old_ctl; | |
102 | USBPacket usb_packet; | |
103 | uint8_t usb_buf[8192]; | |
104 | uint32_t async_td; | |
69e25d26 | 105 | bool async_complete; |
4d611c9a | 106 | |
0d92ed30 PB |
107 | } OHCIState; |
108 | ||
109 | /* Host Controller Communications Area */ | |
110 | struct ohci_hcca { | |
111 | uint32_t intr[32]; | |
112 | uint16_t frame, pad; | |
113 | uint32_t done; | |
114 | }; | |
86e18cae WY |
115 | #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) |
116 | #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ | |
117 | ||
118 | #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) | |
119 | #define ED_WBACK_SIZE 4 | |
0d92ed30 | 120 | |
73221b12 | 121 | static void ohci_bus_stop(OHCIState *ohci); |
4706ab6c | 122 | static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); |
73221b12 | 123 | |
0d92ed30 PB |
124 | /* Bitfields for the first word of an Endpoint Desciptor. */ |
125 | #define OHCI_ED_FA_SHIFT 0 | |
126 | #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) | |
127 | #define OHCI_ED_EN_SHIFT 7 | |
128 | #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) | |
129 | #define OHCI_ED_D_SHIFT 11 | |
130 | #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) | |
131 | #define OHCI_ED_S (1<<13) | |
132 | #define OHCI_ED_K (1<<14) | |
133 | #define OHCI_ED_F (1<<15) | |
7bfe5777 AZ |
134 | #define OHCI_ED_MPS_SHIFT 16 |
135 | #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) | |
0d92ed30 PB |
136 | |
137 | /* Flags in the head field of an Endpoint Desciptor. */ | |
138 | #define OHCI_ED_H 1 | |
139 | #define OHCI_ED_C 2 | |
140 | ||
141 | /* Bitfields for the first word of a Transfer Desciptor. */ | |
142 | #define OHCI_TD_R (1<<18) | |
143 | #define OHCI_TD_DP_SHIFT 19 | |
144 | #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) | |
145 | #define OHCI_TD_DI_SHIFT 21 | |
146 | #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) | |
147 | #define OHCI_TD_T0 (1<<24) | |
8d11b78c | 148 | #define OHCI_TD_T1 (1<<25) |
0d92ed30 PB |
149 | #define OHCI_TD_EC_SHIFT 26 |
150 | #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) | |
151 | #define OHCI_TD_CC_SHIFT 28 | |
152 | #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) | |
153 | ||
7bfe5777 AZ |
154 | /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ |
155 | /* CC & DI - same as in the General Transfer Desciptor */ | |
156 | #define OHCI_TD_SF_SHIFT 0 | |
157 | #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) | |
158 | #define OHCI_TD_FC_SHIFT 24 | |
159 | #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) | |
160 | ||
161 | /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ | |
162 | #define OHCI_TD_PSW_CC_SHIFT 12 | |
163 | #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) | |
164 | #define OHCI_TD_PSW_SIZE_SHIFT 0 | |
165 | #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) | |
166 | ||
167 | #define OHCI_PAGE_MASK 0xfffff000 | |
168 | #define OHCI_OFFSET_MASK 0xfff | |
169 | ||
0d92ed30 PB |
170 | #define OHCI_DPTR_MASK 0xfffffff0 |
171 | ||
172 | #define OHCI_BM(val, field) \ | |
173 | (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) | |
174 | ||
175 | #define OHCI_SET_BM(val, field, newval) do { \ | |
176 | val &= ~OHCI_##field##_MASK; \ | |
177 | val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ | |
178 | } while(0) | |
179 | ||
180 | /* endpoint descriptor */ | |
181 | struct ohci_ed { | |
182 | uint32_t flags; | |
183 | uint32_t tail; | |
184 | uint32_t head; | |
185 | uint32_t next; | |
186 | }; | |
187 | ||
188 | /* General transfer descriptor */ | |
189 | struct ohci_td { | |
190 | uint32_t flags; | |
191 | uint32_t cbp; | |
192 | uint32_t next; | |
193 | uint32_t be; | |
194 | }; | |
195 | ||
7bfe5777 AZ |
196 | /* Isochronous transfer descriptor */ |
197 | struct ohci_iso_td { | |
198 | uint32_t flags; | |
199 | uint32_t bp; | |
200 | uint32_t next; | |
201 | uint32_t be; | |
202 | uint16_t offset[8]; | |
203 | }; | |
204 | ||
0d92ed30 PB |
205 | #define USB_HZ 12000000 |
206 | ||
207 | /* OHCI Local stuff */ | |
208 | #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) | |
209 | #define OHCI_CTL_PLE (1<<2) | |
210 | #define OHCI_CTL_IE (1<<3) | |
211 | #define OHCI_CTL_CLE (1<<4) | |
212 | #define OHCI_CTL_BLE (1<<5) | |
213 | #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) | |
214 | #define OHCI_USB_RESET 0x00 | |
215 | #define OHCI_USB_RESUME 0x40 | |
216 | #define OHCI_USB_OPERATIONAL 0x80 | |
217 | #define OHCI_USB_SUSPEND 0xc0 | |
218 | #define OHCI_CTL_IR (1<<8) | |
219 | #define OHCI_CTL_RWC (1<<9) | |
220 | #define OHCI_CTL_RWE (1<<10) | |
221 | ||
222 | #define OHCI_STATUS_HCR (1<<0) | |
223 | #define OHCI_STATUS_CLF (1<<1) | |
224 | #define OHCI_STATUS_BLF (1<<2) | |
225 | #define OHCI_STATUS_OCR (1<<3) | |
226 | #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) | |
227 | ||
00b01793 PM |
228 | #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ |
229 | #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ | |
230 | #define OHCI_INTR_SF (1U<<2) /* Start of frame */ | |
231 | #define OHCI_INTR_RD (1U<<3) /* Resume detect */ | |
232 | #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ | |
233 | #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ | |
234 | #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ | |
235 | #define OHCI_INTR_OC (1U<<30) /* Ownership change */ | |
236 | #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ | |
0d92ed30 PB |
237 | |
238 | #define OHCI_HCCA_SIZE 0x100 | |
239 | #define OHCI_HCCA_MASK 0xffffff00 | |
240 | ||
241 | #define OHCI_EDPTR_MASK 0xfffffff0 | |
242 | ||
243 | #define OHCI_FMI_FI 0x00003fff | |
244 | #define OHCI_FMI_FSMPS 0xffff0000 | |
245 | #define OHCI_FMI_FIT 0x80000000 | |
246 | ||
00b01793 | 247 | #define OHCI_FR_RT (1U<<31) |
0d92ed30 PB |
248 | |
249 | #define OHCI_LS_THRESH 0x628 | |
250 | ||
251 | #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ | |
252 | #define OHCI_RHA_PSM (1<<8) | |
253 | #define OHCI_RHA_NPS (1<<9) | |
254 | #define OHCI_RHA_DT (1<<10) | |
255 | #define OHCI_RHA_OCPM (1<<11) | |
256 | #define OHCI_RHA_NOCP (1<<12) | |
257 | #define OHCI_RHA_POTPGT_MASK 0xff000000 | |
258 | ||
00b01793 PM |
259 | #define OHCI_RHS_LPS (1U<<0) |
260 | #define OHCI_RHS_OCI (1U<<1) | |
261 | #define OHCI_RHS_DRWE (1U<<15) | |
262 | #define OHCI_RHS_LPSC (1U<<16) | |
263 | #define OHCI_RHS_OCIC (1U<<17) | |
264 | #define OHCI_RHS_CRWE (1U<<31) | |
0d92ed30 PB |
265 | |
266 | #define OHCI_PORT_CCS (1<<0) | |
267 | #define OHCI_PORT_PES (1<<1) | |
268 | #define OHCI_PORT_PSS (1<<2) | |
269 | #define OHCI_PORT_POCI (1<<3) | |
270 | #define OHCI_PORT_PRS (1<<4) | |
271 | #define OHCI_PORT_PPS (1<<8) | |
272 | #define OHCI_PORT_LSDA (1<<9) | |
273 | #define OHCI_PORT_CSC (1<<16) | |
274 | #define OHCI_PORT_PESC (1<<17) | |
275 | #define OHCI_PORT_PSSC (1<<18) | |
276 | #define OHCI_PORT_OCIC (1<<19) | |
277 | #define OHCI_PORT_PRSC (1<<20) | |
278 | #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ | |
279 | |OHCI_PORT_OCIC|OHCI_PORT_PRSC) | |
280 | ||
281 | #define OHCI_TD_DIR_SETUP 0x0 | |
282 | #define OHCI_TD_DIR_OUT 0x1 | |
283 | #define OHCI_TD_DIR_IN 0x2 | |
284 | #define OHCI_TD_DIR_RESERVED 0x3 | |
285 | ||
286 | #define OHCI_CC_NOERROR 0x0 | |
287 | #define OHCI_CC_CRC 0x1 | |
288 | #define OHCI_CC_BITSTUFFING 0x2 | |
289 | #define OHCI_CC_DATATOGGLEMISMATCH 0x3 | |
290 | #define OHCI_CC_STALL 0x4 | |
291 | #define OHCI_CC_DEVICENOTRESPONDING 0x5 | |
292 | #define OHCI_CC_PIDCHECKFAILURE 0x6 | |
293 | #define OHCI_CC_UNDEXPETEDPID 0x7 | |
294 | #define OHCI_CC_DATAOVERRUN 0x8 | |
295 | #define OHCI_CC_DATAUNDERRUN 0x9 | |
296 | #define OHCI_CC_BUFFEROVERRUN 0xc | |
297 | #define OHCI_CC_BUFFERUNDERRUN 0xd | |
298 | ||
e24ad6f1 PB |
299 | #define OHCI_HRESET_FSBIR (1 << 0) |
300 | ||
cf66ee8e AK |
301 | static void ohci_die(OHCIState *ohci); |
302 | ||
61064870 PB |
303 | /* Update IRQ levels */ |
304 | static inline void ohci_intr_update(OHCIState *ohci) | |
305 | { | |
306 | int level = 0; | |
307 | ||
308 | if ((ohci->intr & OHCI_INTR_MIE) && | |
309 | (ohci->intr_status & ohci->intr)) | |
310 | level = 1; | |
311 | ||
d537cf6c | 312 | qemu_set_irq(ohci->irq, level); |
61064870 PB |
313 | } |
314 | ||
315 | /* Set an interrupt */ | |
316 | static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) | |
317 | { | |
318 | ohci->intr_status |= intr; | |
319 | ohci_intr_update(ohci); | |
320 | } | |
321 | ||
322 | /* Attach or detach a device on a root hub port. */ | |
618c169b | 323 | static void ohci_attach(USBPort *port1) |
0d92ed30 PB |
324 | { |
325 | OHCIState *s = port1->opaque; | |
326 | OHCIPort *port = &s->rhport[port1->index]; | |
3dc345d5 | 327 | uint32_t old_state = port->ctrl; |
0d92ed30 | 328 | |
618c169b GH |
329 | /* set connect status */ |
330 | port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; | |
331 | ||
332 | /* update speed */ | |
333 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
334 | port->ctrl |= OHCI_PORT_LSDA; | |
0d92ed30 | 335 | } else { |
618c169b GH |
336 | port->ctrl &= ~OHCI_PORT_LSDA; |
337 | } | |
338 | ||
339 | /* notify of remote-wakeup */ | |
340 | if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { | |
341 | ohci_set_interrupt(s, OHCI_INTR_RD); | |
342 | } | |
343 | ||
dc1f5988 | 344 | trace_usb_ohci_port_attach(port1->index); |
3dc345d5 GH |
345 | |
346 | if (old_state != port->ctrl) { | |
347 | ohci_set_interrupt(s, OHCI_INTR_RHSC); | |
348 | } | |
618c169b GH |
349 | } |
350 | ||
351 | static void ohci_detach(USBPort *port1) | |
352 | { | |
353 | OHCIState *s = port1->opaque; | |
354 | OHCIPort *port = &s->rhport[port1->index]; | |
355 | uint32_t old_state = port->ctrl; | |
356 | ||
4706ab6c HG |
357 | ohci_async_cancel_device(s, port1->dev); |
358 | ||
618c169b GH |
359 | /* set connect status */ |
360 | if (port->ctrl & OHCI_PORT_CCS) { | |
361 | port->ctrl &= ~OHCI_PORT_CCS; | |
362 | port->ctrl |= OHCI_PORT_CSC; | |
363 | } | |
364 | /* disable port */ | |
365 | if (port->ctrl & OHCI_PORT_PES) { | |
366 | port->ctrl &= ~OHCI_PORT_PES; | |
367 | port->ctrl |= OHCI_PORT_PESC; | |
0d92ed30 | 368 | } |
dc1f5988 | 369 | trace_usb_ohci_port_detach(port1->index); |
61064870 | 370 | |
3dc345d5 | 371 | if (old_state != port->ctrl) { |
61064870 | 372 | ohci_set_interrupt(s, OHCI_INTR_RHSC); |
3dc345d5 | 373 | } |
0d92ed30 PB |
374 | } |
375 | ||
d47e59b8 | 376 | static void ohci_wakeup(USBPort *port1) |
9bba1eb1 | 377 | { |
d47e59b8 HG |
378 | OHCIState *s = port1->opaque; |
379 | OHCIPort *port = &s->rhport[port1->index]; | |
f3dc0051 | 380 | uint32_t intr = 0; |
9bba1eb1 | 381 | if (port->ctrl & OHCI_PORT_PSS) { |
dc1f5988 | 382 | trace_usb_ohci_port_wakeup(port1->index); |
9bba1eb1 PM |
383 | port->ctrl |= OHCI_PORT_PSSC; |
384 | port->ctrl &= ~OHCI_PORT_PSS; | |
f3dc0051 | 385 | intr = OHCI_INTR_RHSC; |
9bba1eb1 | 386 | } |
f3dc0051 PM |
387 | /* Note that the controller can be suspended even if this port is not */ |
388 | if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { | |
dc1f5988 | 389 | trace_usb_ohci_remote_wakeup(s->name); |
f3dc0051 PM |
390 | /* This is the one state transition the controller can do by itself */ |
391 | s->ctl &= ~OHCI_CTL_HCFS; | |
392 | s->ctl |= OHCI_USB_RESUME; | |
393 | /* In suspend mode only ResumeDetected is possible, not RHSC: | |
394 | * see the OHCI spec 5.1.2.3. | |
395 | */ | |
396 | intr = OHCI_INTR_RD; | |
397 | } | |
398 | ohci_set_interrupt(s, intr); | |
9bba1eb1 PM |
399 | } |
400 | ||
4706ab6c HG |
401 | static void ohci_child_detach(USBPort *port1, USBDevice *child) |
402 | { | |
403 | OHCIState *s = port1->opaque; | |
404 | ||
405 | ohci_async_cancel_device(s, child); | |
406 | } | |
407 | ||
993048bb GH |
408 | static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) |
409 | { | |
410 | USBDevice *dev; | |
411 | int i; | |
412 | ||
413 | for (i = 0; i < ohci->num_ports; i++) { | |
414 | if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { | |
415 | continue; | |
416 | } | |
417 | dev = usb_find_device(&ohci->rhport[i].port, addr); | |
418 | if (dev != NULL) { | |
419 | return dev; | |
420 | } | |
421 | } | |
422 | return NULL; | |
423 | } | |
424 | ||
f79738b0 HG |
425 | static void ohci_stop_endpoints(OHCIState *ohci) |
426 | { | |
427 | USBDevice *dev; | |
428 | int i, j; | |
429 | ||
430 | for (i = 0; i < ohci->num_ports; i++) { | |
431 | dev = ohci->rhport[i].port.dev; | |
432 | if (dev && dev->attached) { | |
433 | usb_device_ep_stopped(dev, &dev->ep_ctl); | |
434 | for (j = 0; j < USB_MAX_ENDPOINTS; j++) { | |
435 | usb_device_ep_stopped(dev, &dev->ep_in[j]); | |
436 | usb_device_ep_stopped(dev, &dev->ep_out[j]); | |
437 | } | |
438 | } | |
439 | } | |
440 | } | |
441 | ||
84d04e21 | 442 | static void ohci_roothub_reset(OHCIState *ohci) |
0d92ed30 PB |
443 | { |
444 | OHCIPort *port; | |
445 | int i; | |
446 | ||
73221b12 | 447 | ohci_bus_stop(ohci); |
84d04e21 HP |
448 | ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
449 | ohci->rhdesc_b = 0x0; /* Impl. specific */ | |
450 | ohci->rhstatus = 0; | |
451 | ||
452 | for (i = 0; i < ohci->num_ports; i++) { | |
453 | port = &ohci->rhport[i]; | |
454 | port->ctrl = 0; | |
455 | if (port->port.dev && port->port.dev->attached) { | |
456 | usb_port_reset(&port->port); | |
457 | } | |
458 | } | |
459 | if (ohci->async_td) { | |
460 | usb_cancel_packet(&ohci->usb_packet); | |
461 | ohci->async_td = 0; | |
462 | } | |
463 | ohci_stop_endpoints(ohci); | |
464 | } | |
465 | ||
466 | /* Reset the controller */ | |
467 | static void ohci_soft_reset(OHCIState *ohci) | |
468 | { | |
469 | trace_usb_ohci_reset(ohci->name); | |
470 | ||
471 | ohci_bus_stop(ohci); | |
472 | ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; | |
4d611c9a | 473 | ohci->old_ctl = 0; |
0d92ed30 PB |
474 | ohci->status = 0; |
475 | ohci->intr_status = 0; | |
476 | ohci->intr = OHCI_INTR_MIE; | |
477 | ||
478 | ohci->hcca = 0; | |
479 | ohci->ctrl_head = ohci->ctrl_cur = 0; | |
480 | ohci->bulk_head = ohci->bulk_cur = 0; | |
481 | ohci->per_cur = 0; | |
482 | ohci->done = 0; | |
483 | ohci->done_count = 7; | |
484 | ||
485 | /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? | |
486 | * I took the value linux sets ... | |
487 | */ | |
488 | ohci->fsmps = 0x2778; | |
489 | ohci->fi = 0x2edf; | |
490 | ohci->fit = 0; | |
491 | ohci->frt = 0; | |
492 | ohci->frame_number = 0; | |
493 | ohci->pstart = 0; | |
494 | ohci->lst = OHCI_LS_THRESH; | |
84d04e21 | 495 | } |
0d92ed30 | 496 | |
84d04e21 HP |
497 | static void ohci_hard_reset(OHCIState *ohci) |
498 | { | |
499 | ohci_soft_reset(ohci); | |
500 | ohci->ctl = 0; | |
501 | ohci_roothub_reset(ohci); | |
0d92ed30 PB |
502 | } |
503 | ||
0d92ed30 | 504 | /* Get an array of dwords from main memory */ |
ac611340 | 505 | static inline int get_dwords(OHCIState *ohci, |
9ac6a217 | 506 | dma_addr_t addr, uint32_t *buf, int num) |
0d92ed30 PB |
507 | { |
508 | int i; | |
509 | ||
ac611340 AJ |
510 | addr += ohci->localmem_base; |
511 | ||
0d92ed30 | 512 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
cf66ee8e AK |
513 | if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { |
514 | return -1; | |
515 | } | |
0d92ed30 PB |
516 | *buf = le32_to_cpu(*buf); |
517 | } | |
518 | ||
cf66ee8e | 519 | return 0; |
0d92ed30 PB |
520 | } |
521 | ||
522 | /* Put an array of dwords in to main memory */ | |
ac611340 | 523 | static inline int put_dwords(OHCIState *ohci, |
9ac6a217 | 524 | dma_addr_t addr, uint32_t *buf, int num) |
0d92ed30 PB |
525 | { |
526 | int i; | |
527 | ||
ac611340 AJ |
528 | addr += ohci->localmem_base; |
529 | ||
0d92ed30 PB |
530 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
531 | uint32_t tmp = cpu_to_le32(*buf); | |
cf66ee8e AK |
532 | if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { |
533 | return -1; | |
534 | } | |
0d92ed30 PB |
535 | } |
536 | ||
cf66ee8e | 537 | return 0; |
0d92ed30 PB |
538 | } |
539 | ||
7bfe5777 | 540 | /* Get an array of words from main memory */ |
ac611340 | 541 | static inline int get_words(OHCIState *ohci, |
9ac6a217 | 542 | dma_addr_t addr, uint16_t *buf, int num) |
7bfe5777 AZ |
543 | { |
544 | int i; | |
545 | ||
ac611340 AJ |
546 | addr += ohci->localmem_base; |
547 | ||
7bfe5777 | 548 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
cf66ee8e AK |
549 | if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { |
550 | return -1; | |
551 | } | |
7bfe5777 AZ |
552 | *buf = le16_to_cpu(*buf); |
553 | } | |
554 | ||
cf66ee8e | 555 | return 0; |
7bfe5777 AZ |
556 | } |
557 | ||
558 | /* Put an array of words in to main memory */ | |
ac611340 | 559 | static inline int put_words(OHCIState *ohci, |
9ac6a217 | 560 | dma_addr_t addr, uint16_t *buf, int num) |
7bfe5777 AZ |
561 | { |
562 | int i; | |
563 | ||
ac611340 AJ |
564 | addr += ohci->localmem_base; |
565 | ||
7bfe5777 AZ |
566 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
567 | uint16_t tmp = cpu_to_le16(*buf); | |
cf66ee8e AK |
568 | if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { |
569 | return -1; | |
570 | } | |
7bfe5777 AZ |
571 | } |
572 | ||
cf66ee8e | 573 | return 0; |
7bfe5777 AZ |
574 | } |
575 | ||
ac611340 | 576 | static inline int ohci_read_ed(OHCIState *ohci, |
9ac6a217 | 577 | dma_addr_t addr, struct ohci_ed *ed) |
0d92ed30 | 578 | { |
ac611340 | 579 | return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
0d92ed30 PB |
580 | } |
581 | ||
ac611340 | 582 | static inline int ohci_read_td(OHCIState *ohci, |
9ac6a217 | 583 | dma_addr_t addr, struct ohci_td *td) |
0d92ed30 | 584 | { |
ac611340 | 585 | return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
0d92ed30 PB |
586 | } |
587 | ||
ac611340 | 588 | static inline int ohci_read_iso_td(OHCIState *ohci, |
9ac6a217 | 589 | dma_addr_t addr, struct ohci_iso_td *td) |
7bfe5777 | 590 | { |
cf66ee8e AK |
591 | return get_dwords(ohci, addr, (uint32_t *)td, 4) || |
592 | get_words(ohci, addr + 16, td->offset, 8); | |
7bfe5777 AZ |
593 | } |
594 | ||
ac611340 | 595 | static inline int ohci_read_hcca(OHCIState *ohci, |
9ac6a217 | 596 | dma_addr_t addr, struct ohci_hcca *hcca) |
0d92ed30 | 597 | { |
cf66ee8e AK |
598 | return dma_memory_read(ohci->as, addr + ohci->localmem_base, |
599 | hcca, sizeof(*hcca)); | |
0d92ed30 PB |
600 | } |
601 | ||
ac611340 | 602 | static inline int ohci_put_ed(OHCIState *ohci, |
9ac6a217 | 603 | dma_addr_t addr, struct ohci_ed *ed) |
0d92ed30 | 604 | { |
86e18cae WY |
605 | /* ed->tail is under control of the HCD. |
606 | * Since just ed->head is changed by HC, just write back this | |
607 | */ | |
608 | ||
609 | return put_dwords(ohci, addr + ED_WBACK_OFFSET, | |
610 | (uint32_t *)((char *)ed + ED_WBACK_OFFSET), | |
611 | ED_WBACK_SIZE >> 2); | |
0d92ed30 PB |
612 | } |
613 | ||
ac611340 | 614 | static inline int ohci_put_td(OHCIState *ohci, |
9ac6a217 | 615 | dma_addr_t addr, struct ohci_td *td) |
7bfe5777 | 616 | { |
ac611340 AJ |
617 | return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
618 | } | |
619 | ||
620 | static inline int ohci_put_iso_td(OHCIState *ohci, | |
9ac6a217 | 621 | dma_addr_t addr, struct ohci_iso_td *td) |
ac611340 | 622 | { |
cae7f29c JU |
623 | return put_dwords(ohci, addr, (uint32_t *)td, 4) || |
624 | put_words(ohci, addr + 16, td->offset, 8); | |
ac611340 AJ |
625 | } |
626 | ||
627 | static inline int ohci_put_hcca(OHCIState *ohci, | |
9ac6a217 | 628 | dma_addr_t addr, struct ohci_hcca *hcca) |
ac611340 | 629 | { |
cf66ee8e AK |
630 | return dma_memory_write(ohci->as, |
631 | addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, | |
632 | (char *)hcca + HCCA_WRITEBACK_OFFSET, | |
633 | HCCA_WRITEBACK_SIZE); | |
7bfe5777 AZ |
634 | } |
635 | ||
0d92ed30 | 636 | /* Read/Write the contents of a TD from/to main memory. */ |
cf66ee8e AK |
637 | static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, |
638 | uint8_t *buf, int len, DMADirection dir) | |
0d92ed30 | 639 | { |
9ac6a217 | 640 | dma_addr_t ptr, n; |
0d92ed30 PB |
641 | |
642 | ptr = td->cbp; | |
643 | n = 0x1000 - (ptr & 0xfff); | |
644 | if (n > len) | |
645 | n = len; | |
cf66ee8e AK |
646 | |
647 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { | |
648 | return -1; | |
649 | } | |
650 | if (n == len) { | |
651 | return 0; | |
652 | } | |
0d92ed30 | 653 | ptr = td->be & ~0xfffu; |
e6f3e5e0 | 654 | buf += n; |
cf66ee8e AK |
655 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, |
656 | len - n, dir)) { | |
657 | return -1; | |
658 | } | |
659 | return 0; | |
0d92ed30 PB |
660 | } |
661 | ||
7bfe5777 | 662 | /* Read/Write the contents of an ISO TD from/to main memory. */ |
cf66ee8e AK |
663 | static int ohci_copy_iso_td(OHCIState *ohci, |
664 | uint32_t start_addr, uint32_t end_addr, | |
665 | uint8_t *buf, int len, DMADirection dir) | |
7bfe5777 | 666 | { |
9ac6a217 | 667 | dma_addr_t ptr, n; |
4d611c9a | 668 | |
7bfe5777 AZ |
669 | ptr = start_addr; |
670 | n = 0x1000 - (ptr & 0xfff); | |
671 | if (n > len) | |
672 | n = len; | |
cf66ee8e AK |
673 | |
674 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { | |
675 | return -1; | |
676 | } | |
677 | if (n == len) { | |
678 | return 0; | |
679 | } | |
7bfe5777 AZ |
680 | ptr = end_addr & ~0xfffu; |
681 | buf += n; | |
cf66ee8e AK |
682 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, |
683 | len - n, dir)) { | |
684 | return -1; | |
685 | } | |
686 | return 0; | |
7bfe5777 AZ |
687 | } |
688 | ||
689 | static void ohci_process_lists(OHCIState *ohci, int completion); | |
690 | ||
d47e59b8 | 691 | static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) |
4d611c9a | 692 | { |
9066df13 | 693 | OHCIState *ohci = container_of(packet, OHCIState, usb_packet); |
dc1f5988 AK |
694 | |
695 | trace_usb_ohci_async_complete(); | |
69e25d26 | 696 | ohci->async_complete = true; |
7bfe5777 AZ |
697 | ohci_process_lists(ohci, 1); |
698 | } | |
699 | ||
700 | #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) | |
701 | ||
702 | static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, | |
703 | int completion) | |
704 | { | |
705 | int dir; | |
706 | size_t len = 0; | |
7ccfb2eb | 707 | const char *str = NULL; |
7bfe5777 AZ |
708 | int pid; |
709 | int ret; | |
710 | int i; | |
711 | USBDevice *dev; | |
079d0b7f | 712 | USBEndpoint *ep; |
7bfe5777 AZ |
713 | struct ohci_iso_td iso_td; |
714 | uint32_t addr; | |
715 | uint16_t starting_frame; | |
716 | int16_t relative_frame_number; | |
717 | int frame_count; | |
718 | uint32_t start_offset, next_offset, end_offset = 0; | |
719 | uint32_t start_addr, end_addr; | |
720 | ||
721 | addr = ed->head & OHCI_DPTR_MASK; | |
722 | ||
cf66ee8e | 723 | if (ohci_read_iso_td(ohci, addr, &iso_td)) { |
dc1f5988 | 724 | trace_usb_ohci_iso_td_read_failed(addr); |
cf66ee8e | 725 | ohci_die(ohci); |
7bfe5777 AZ |
726 | return 0; |
727 | } | |
728 | ||
729 | starting_frame = OHCI_BM(iso_td.flags, TD_SF); | |
730 | frame_count = OHCI_BM(iso_td.flags, TD_FC); | |
731 | relative_frame_number = USUB(ohci->frame_number, starting_frame); | |
732 | ||
dc1f5988 | 733 | trace_usb_ohci_iso_td_head( |
7bfe5777 AZ |
734 | ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, |
735 | iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, | |
3af8f177 | 736 | ohci->frame_number, starting_frame, |
bc0d104c | 737 | frame_count, relative_frame_number); |
3af8f177 AK |
738 | trace_usb_ohci_iso_td_head_offset( |
739 | iso_td.offset[0], iso_td.offset[1], | |
740 | iso_td.offset[2], iso_td.offset[3], | |
741 | iso_td.offset[4], iso_td.offset[5], | |
742 | iso_td.offset[6], iso_td.offset[7]); | |
7bfe5777 AZ |
743 | |
744 | if (relative_frame_number < 0) { | |
dc1f5988 | 745 | trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); |
7bfe5777 AZ |
746 | return 1; |
747 | } else if (relative_frame_number > frame_count) { | |
748 | /* ISO TD expired - retire the TD to the Done Queue and continue with | |
749 | the next ISO TD of the same ED */ | |
dc1f5988 AK |
750 | trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, |
751 | frame_count); | |
7bfe5777 AZ |
752 | OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
753 | ed->head &= ~OHCI_DPTR_MASK; | |
754 | ed->head |= (iso_td.next & OHCI_DPTR_MASK); | |
755 | iso_td.next = ohci->done; | |
756 | ohci->done = addr; | |
757 | i = OHCI_BM(iso_td.flags, TD_DI); | |
758 | if (i < ohci->done_count) | |
759 | ohci->done_count = i; | |
cf66ee8e AK |
760 | if (ohci_put_iso_td(ohci, addr, &iso_td)) { |
761 | ohci_die(ohci); | |
762 | return 1; | |
763 | } | |
7bfe5777 AZ |
764 | return 0; |
765 | } | |
766 | ||
767 | dir = OHCI_BM(ed->flags, ED_D); | |
768 | switch (dir) { | |
769 | case OHCI_TD_DIR_IN: | |
770 | str = "in"; | |
771 | pid = USB_TOKEN_IN; | |
772 | break; | |
773 | case OHCI_TD_DIR_OUT: | |
774 | str = "out"; | |
775 | pid = USB_TOKEN_OUT; | |
776 | break; | |
777 | case OHCI_TD_DIR_SETUP: | |
778 | str = "setup"; | |
779 | pid = USB_TOKEN_SETUP; | |
780 | break; | |
781 | default: | |
dc1f5988 | 782 | trace_usb_ohci_iso_td_bad_direction(dir); |
7bfe5777 AZ |
783 | return 1; |
784 | } | |
785 | ||
786 | if (!iso_td.bp || !iso_td.be) { | |
dc1f5988 | 787 | trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); |
7bfe5777 AZ |
788 | return 1; |
789 | } | |
790 | ||
791 | start_offset = iso_td.offset[relative_frame_number]; | |
792 | next_offset = iso_td.offset[relative_frame_number + 1]; | |
793 | ||
794 | if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || | |
795 | ((relative_frame_number < frame_count) && | |
796 | !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { | |
dc1f5988 | 797 | trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); |
7bfe5777 AZ |
798 | return 1; |
799 | } | |
800 | ||
801 | if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { | |
dc1f5988 | 802 | trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); |
7bfe5777 AZ |
803 | return 1; |
804 | } | |
805 | ||
806 | if ((start_offset & 0x1000) == 0) { | |
807 | start_addr = (iso_td.bp & OHCI_PAGE_MASK) | | |
808 | (start_offset & OHCI_OFFSET_MASK); | |
809 | } else { | |
810 | start_addr = (iso_td.be & OHCI_PAGE_MASK) | | |
811 | (start_offset & OHCI_OFFSET_MASK); | |
812 | } | |
813 | ||
814 | if (relative_frame_number < frame_count) { | |
815 | end_offset = next_offset - 1; | |
816 | if ((end_offset & 0x1000) == 0) { | |
817 | end_addr = (iso_td.bp & OHCI_PAGE_MASK) | | |
818 | (end_offset & OHCI_OFFSET_MASK); | |
819 | } else { | |
820 | end_addr = (iso_td.be & OHCI_PAGE_MASK) | | |
821 | (end_offset & OHCI_OFFSET_MASK); | |
822 | } | |
823 | } else { | |
824 | /* Last packet in the ISO TD */ | |
825 | end_addr = iso_td.be; | |
826 | } | |
827 | ||
828 | if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { | |
829 | len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 | |
830 | - (start_addr & OHCI_OFFSET_MASK); | |
831 | } else { | |
832 | len = end_addr - start_addr + 1; | |
833 | } | |
834 | ||
835 | if (len && dir != OHCI_TD_DIR_IN) { | |
cf66ee8e AK |
836 | if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, |
837 | DMA_DIRECTION_TO_DEVICE)) { | |
838 | ohci_die(ohci); | |
839 | return 1; | |
840 | } | |
7bfe5777 AZ |
841 | } |
842 | ||
9a77a0f5 | 843 | if (!completion) { |
a6fb2ddb HG |
844 | bool int_req = relative_frame_number == frame_count && |
845 | OHCI_BM(iso_td.flags, TD_DI) == 0; | |
079d0b7f GH |
846 | dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); |
847 | ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); | |
8550a02d | 848 | usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req); |
993048bb | 849 | usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); |
9a77a0f5 HG |
850 | usb_handle_packet(dev, &ohci->usb_packet); |
851 | if (ohci->usb_packet.status == USB_RET_ASYNC) { | |
36dfe324 | 852 | usb_device_flush_ep_queue(dev, ep); |
7bfe5777 AZ |
853 | return 1; |
854 | } | |
855 | } | |
9a77a0f5 HG |
856 | if (ohci->usb_packet.status == USB_RET_SUCCESS) { |
857 | ret = ohci->usb_packet.actual_length; | |
858 | } else { | |
859 | ret = ohci->usb_packet.status; | |
860 | } | |
7bfe5777 | 861 | |
dc1f5988 AK |
862 | trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, |
863 | str, len, ret); | |
7bfe5777 AZ |
864 | |
865 | /* Writeback */ | |
866 | if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { | |
867 | /* IN transfer succeeded */ | |
cf66ee8e AK |
868 | if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, |
869 | DMA_DIRECTION_FROM_DEVICE)) { | |
870 | ohci_die(ohci); | |
871 | return 1; | |
872 | } | |
7bfe5777 AZ |
873 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
874 | OHCI_CC_NOERROR); | |
875 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); | |
876 | } else if (dir == OHCI_TD_DIR_OUT && ret == len) { | |
877 | /* OUT transfer succeeded */ | |
878 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
879 | OHCI_CC_NOERROR); | |
880 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); | |
881 | } else { | |
87283515 | 882 | if (ret > (ssize_t) len) { |
dc1f5988 | 883 | trace_usb_ohci_iso_td_data_overrun(ret, len); |
7bfe5777 AZ |
884 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
885 | OHCI_CC_DATAOVERRUN); | |
886 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
887 | len); | |
888 | } else if (ret >= 0) { | |
dc1f5988 | 889 | trace_usb_ohci_iso_td_data_underrun(ret); |
7bfe5777 AZ |
890 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
891 | OHCI_CC_DATAUNDERRUN); | |
892 | } else { | |
893 | switch (ret) { | |
d61000a8 | 894 | case USB_RET_IOERROR: |
7bfe5777 AZ |
895 | case USB_RET_NODEV: |
896 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
897 | OHCI_CC_DEVICENOTRESPONDING); | |
898 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
899 | 0); | |
900 | break; | |
901 | case USB_RET_NAK: | |
902 | case USB_RET_STALL: | |
dc1f5988 | 903 | trace_usb_ohci_iso_td_nak(ret); |
7bfe5777 AZ |
904 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
905 | OHCI_CC_STALL); | |
906 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
907 | 0); | |
908 | break; | |
909 | default: | |
dc1f5988 | 910 | trace_usb_ohci_iso_td_bad_response(ret); |
7bfe5777 AZ |
911 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
912 | OHCI_CC_UNDEXPETEDPID); | |
913 | break; | |
914 | } | |
915 | } | |
916 | } | |
917 | ||
918 | if (relative_frame_number == frame_count) { | |
919 | /* Last data packet of ISO TD - retire the TD to the Done Queue */ | |
920 | OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); | |
921 | ed->head &= ~OHCI_DPTR_MASK; | |
922 | ed->head |= (iso_td.next & OHCI_DPTR_MASK); | |
923 | iso_td.next = ohci->done; | |
924 | ohci->done = addr; | |
925 | i = OHCI_BM(iso_td.flags, TD_DI); | |
926 | if (i < ohci->done_count) | |
927 | ohci->done_count = i; | |
928 | } | |
cf66ee8e AK |
929 | if (ohci_put_iso_td(ohci, addr, &iso_td)) { |
930 | ohci_die(ohci); | |
931 | } | |
7bfe5777 | 932 | return 1; |
4d611c9a PB |
933 | } |
934 | ||
dc1f5988 AK |
935 | #ifdef trace_event_get_state |
936 | static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) | |
937 | { | |
938 | bool print16 = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_SHORT); | |
939 | bool printall = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_FULL); | |
940 | const int width = 16; | |
941 | int i; | |
942 | char tmp[3 * width + 1]; | |
943 | char *p = tmp; | |
944 | ||
945 | if (!printall && !print16) { | |
946 | return; | |
947 | } | |
948 | ||
949 | for (i = 0; ; i++) { | |
950 | if (i && (!(i % width) || (i == len))) { | |
951 | if (!printall) { | |
952 | trace_usb_ohci_td_pkt_short(msg, tmp); | |
953 | break; | |
954 | } | |
955 | trace_usb_ohci_td_pkt_full(msg, tmp); | |
956 | p = tmp; | |
957 | *p = 0; | |
958 | } | |
959 | if (i == len) { | |
960 | break; | |
961 | } | |
962 | ||
963 | p += sprintf(p, " %.2x", buf[i]); | |
964 | } | |
965 | } | |
966 | #else | |
967 | static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) | |
968 | { | |
969 | } | |
970 | #endif | |
971 | ||
0d92ed30 PB |
972 | /* Service a transport descriptor. |
973 | Returns nonzero to terminate processing of this endpoint. */ | |
974 | ||
975 | static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) | |
976 | { | |
977 | int dir; | |
905fb034 | 978 | size_t len = 0, pktlen = 0; |
7ccfb2eb | 979 | const char *str = NULL; |
0d92ed30 PB |
980 | int pid; |
981 | int ret; | |
982 | int i; | |
983 | USBDevice *dev; | |
079d0b7f | 984 | USBEndpoint *ep; |
0d92ed30 PB |
985 | struct ohci_td td; |
986 | uint32_t addr; | |
987 | int flag_r; | |
4d611c9a | 988 | int completion; |
0d92ed30 PB |
989 | |
990 | addr = ed->head & OHCI_DPTR_MASK; | |
4d611c9a PB |
991 | /* See if this TD has already been submitted to the device. */ |
992 | completion = (addr == ohci->async_td); | |
993 | if (completion && !ohci->async_complete) { | |
dc1f5988 | 994 | trace_usb_ohci_td_skip_async(); |
4d611c9a PB |
995 | return 1; |
996 | } | |
cf66ee8e | 997 | if (ohci_read_td(ohci, addr, &td)) { |
dc1f5988 | 998 | trace_usb_ohci_td_read_error(addr); |
cf66ee8e | 999 | ohci_die(ohci); |
0d92ed30 PB |
1000 | return 0; |
1001 | } | |
1002 | ||
1003 | dir = OHCI_BM(ed->flags, ED_D); | |
1004 | switch (dir) { | |
1005 | case OHCI_TD_DIR_OUT: | |
1006 | case OHCI_TD_DIR_IN: | |
1007 | /* Same value. */ | |
1008 | break; | |
1009 | default: | |
1010 | dir = OHCI_BM(td.flags, TD_DP); | |
1011 | break; | |
1012 | } | |
1013 | ||
1014 | switch (dir) { | |
1015 | case OHCI_TD_DIR_IN: | |
1016 | str = "in"; | |
1017 | pid = USB_TOKEN_IN; | |
1018 | break; | |
1019 | case OHCI_TD_DIR_OUT: | |
1020 | str = "out"; | |
1021 | pid = USB_TOKEN_OUT; | |
1022 | break; | |
1023 | case OHCI_TD_DIR_SETUP: | |
1024 | str = "setup"; | |
1025 | pid = USB_TOKEN_SETUP; | |
1026 | break; | |
1027 | default: | |
dc1f5988 | 1028 | trace_usb_ohci_td_bad_direction(dir); |
0d92ed30 PB |
1029 | return 1; |
1030 | } | |
1031 | if (td.cbp && td.be) { | |
e6f3e5e0 PB |
1032 | if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
1033 | len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); | |
1034 | } else { | |
1035 | len = (td.be - td.cbp) + 1; | |
1036 | } | |
1037 | ||
905fb034 PM |
1038 | pktlen = len; |
1039 | if (len && dir != OHCI_TD_DIR_IN) { | |
1040 | /* The endpoint may not allow us to transfer it all now */ | |
1041 | pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; | |
1042 | if (pktlen > len) { | |
1043 | pktlen = len; | |
1044 | } | |
1045 | if (!completion) { | |
cf66ee8e AK |
1046 | if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, |
1047 | DMA_DIRECTION_TO_DEVICE)) { | |
1048 | ohci_die(ohci); | |
1049 | } | |
905fb034 | 1050 | } |
0d92ed30 PB |
1051 | } |
1052 | } | |
1053 | ||
1054 | flag_r = (td.flags & OHCI_TD_R) != 0; | |
dc1f5988 AK |
1055 | trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, |
1056 | flag_r, td.cbp, td.be); | |
1057 | ohci_td_pkt("OUT", ohci->usb_buf, pktlen); | |
1058 | ||
4d611c9a | 1059 | if (completion) { |
4d611c9a | 1060 | ohci->async_td = 0; |
69e25d26 | 1061 | ohci->async_complete = false; |
4d611c9a | 1062 | } else { |
993048bb GH |
1063 | if (ohci->async_td) { |
1064 | /* ??? The hardware should allow one active packet per | |
1065 | endpoint. We only allow one active packet per controller. | |
1066 | This should be sufficient as long as devices respond in a | |
1067 | timely manner. | |
1068 | */ | |
dc1f5988 | 1069 | trace_usb_ohci_td_too_many_pending(); |
993048bb | 1070 | return 1; |
4d611c9a | 1071 | } |
079d0b7f GH |
1072 | dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); |
1073 | ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); | |
8550a02d | 1074 | usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, |
a6fb2ddb | 1075 | OHCI_BM(td.flags, TD_DI) == 0); |
993048bb | 1076 | usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); |
9a77a0f5 | 1077 | usb_handle_packet(dev, &ohci->usb_packet); |
dc1f5988 AK |
1078 | trace_usb_ohci_td_packet_status(ohci->usb_packet.status); |
1079 | ||
9a77a0f5 | 1080 | if (ohci->usb_packet.status == USB_RET_ASYNC) { |
36dfe324 | 1081 | usb_device_flush_ep_queue(dev, ep); |
4d611c9a PB |
1082 | ohci->async_td = addr; |
1083 | return 1; | |
1084 | } | |
1085 | } | |
9a77a0f5 HG |
1086 | if (ohci->usb_packet.status == USB_RET_SUCCESS) { |
1087 | ret = ohci->usb_packet.actual_length; | |
1088 | } else { | |
1089 | ret = ohci->usb_packet.status; | |
1090 | } | |
1091 | ||
0d92ed30 PB |
1092 | if (ret >= 0) { |
1093 | if (dir == OHCI_TD_DIR_IN) { | |
cf66ee8e AK |
1094 | if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, |
1095 | DMA_DIRECTION_FROM_DEVICE)) { | |
1096 | ohci_die(ohci); | |
1097 | } | |
dc1f5988 | 1098 | ohci_td_pkt("IN", ohci->usb_buf, pktlen); |
0d92ed30 | 1099 | } else { |
905fb034 | 1100 | ret = pktlen; |
0d92ed30 PB |
1101 | } |
1102 | } | |
1103 | ||
1104 | /* Writeback */ | |
905fb034 | 1105 | if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
0d92ed30 PB |
1106 | /* Transmission succeeded. */ |
1107 | if (ret == len) { | |
1108 | td.cbp = 0; | |
1109 | } else { | |
0d92ed30 | 1110 | if ((td.cbp & 0xfff) + ret > 0xfff) { |
fd891c93 AG |
1111 | td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); |
1112 | } else { | |
1113 | td.cbp += ret; | |
0d92ed30 PB |
1114 | } |
1115 | } | |
1116 | td.flags |= OHCI_TD_T1; | |
1117 | td.flags ^= OHCI_TD_T0; | |
1118 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); | |
1119 | OHCI_SET_BM(td.flags, TD_EC, 0); | |
1120 | ||
905fb034 PM |
1121 | if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { |
1122 | /* Partial packet transfer: TD not ready to retire yet */ | |
1123 | goto exit_no_retire; | |
1124 | } | |
1125 | ||
1126 | /* Setting ED_C is part of the TD retirement process */ | |
0d92ed30 PB |
1127 | ed->head &= ~OHCI_ED_C; |
1128 | if (td.flags & OHCI_TD_T0) | |
1129 | ed->head |= OHCI_ED_C; | |
1130 | } else { | |
1131 | if (ret >= 0) { | |
dc1f5988 | 1132 | trace_usb_ohci_td_underrun(); |
0d92ed30 PB |
1133 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
1134 | } else { | |
1135 | switch (ret) { | |
d61000a8 | 1136 | case USB_RET_IOERROR: |
0d92ed30 | 1137 | case USB_RET_NODEV: |
dc1f5988 | 1138 | trace_usb_ohci_td_dev_error(); |
0d92ed30 | 1139 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
4b351a0f | 1140 | break; |
0d92ed30 | 1141 | case USB_RET_NAK: |
dc1f5988 | 1142 | trace_usb_ohci_td_nak(); |
0d92ed30 PB |
1143 | return 1; |
1144 | case USB_RET_STALL: | |
dc1f5988 | 1145 | trace_usb_ohci_td_stall(); |
0d92ed30 PB |
1146 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
1147 | break; | |
1148 | case USB_RET_BABBLE: | |
dc1f5988 | 1149 | trace_usb_ohci_td_babble(); |
0d92ed30 PB |
1150 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
1151 | break; | |
1152 | default: | |
dc1f5988 | 1153 | trace_usb_ohci_td_bad_device_response(ret); |
0d92ed30 PB |
1154 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
1155 | OHCI_SET_BM(td.flags, TD_EC, 3); | |
1156 | break; | |
1157 | } | |
1158 | } | |
1159 | ed->head |= OHCI_ED_H; | |
1160 | } | |
1161 | ||
1162 | /* Retire this TD */ | |
1163 | ed->head &= ~OHCI_DPTR_MASK; | |
1164 | ed->head |= td.next & OHCI_DPTR_MASK; | |
1165 | td.next = ohci->done; | |
1166 | ohci->done = addr; | |
1167 | i = OHCI_BM(td.flags, TD_DI); | |
1168 | if (i < ohci->done_count) | |
1169 | ohci->done_count = i; | |
905fb034 | 1170 | exit_no_retire: |
cf66ee8e AK |
1171 | if (ohci_put_td(ohci, addr, &td)) { |
1172 | ohci_die(ohci); | |
1173 | return 1; | |
1174 | } | |
0d92ed30 PB |
1175 | return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; |
1176 | } | |
1177 | ||
1178 | /* Service an endpoint list. Returns nonzero if active TD were found. */ | |
7bfe5777 | 1179 | static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) |
0d92ed30 PB |
1180 | { |
1181 | struct ohci_ed ed; | |
1182 | uint32_t next_ed; | |
1183 | uint32_t cur; | |
1184 | int active; | |
1185 | ||
1186 | active = 0; | |
1187 | ||
1188 | if (head == 0) | |
1189 | return 0; | |
1190 | ||
1191 | for (cur = head; cur; cur = next_ed) { | |
cf66ee8e | 1192 | if (ohci_read_ed(ohci, cur, &ed)) { |
dc1f5988 | 1193 | trace_usb_ohci_ed_read_error(cur); |
cf66ee8e | 1194 | ohci_die(ohci); |
0d92ed30 PB |
1195 | return 0; |
1196 | } | |
1197 | ||
1198 | next_ed = ed.next & OHCI_DPTR_MASK; | |
1199 | ||
4d611c9a PB |
1200 | if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { |
1201 | uint32_t addr; | |
1202 | /* Cancel pending packets for ED that have been paused. */ | |
1203 | addr = ed.head & OHCI_DPTR_MASK; | |
1204 | if (ohci->async_td && addr == ohci->async_td) { | |
1205 | usb_cancel_packet(&ohci->usb_packet); | |
1206 | ohci->async_td = 0; | |
f79738b0 HG |
1207 | usb_device_ep_stopped(ohci->usb_packet.ep->dev, |
1208 | ohci->usb_packet.ep); | |
4d611c9a | 1209 | } |
0d92ed30 | 1210 | continue; |
4d611c9a | 1211 | } |
0d92ed30 | 1212 | |
0d92ed30 | 1213 | while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { |
3af8f177 AK |
1214 | trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0, |
1215 | (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, | |
1216 | ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); | |
1217 | trace_usb_ohci_ed_pkt_flags( | |
0d92ed30 PB |
1218 | OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
1219 | OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, | |
1220 | (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, | |
3af8f177 | 1221 | OHCI_BM(ed.flags, ED_MPS)); |
dc1f5988 | 1222 | |
0d92ed30 PB |
1223 | active = 1; |
1224 | ||
7bfe5777 AZ |
1225 | if ((ed.flags & OHCI_ED_F) == 0) { |
1226 | if (ohci_service_td(ohci, &ed)) | |
1227 | break; | |
1228 | } else { | |
1229 | /* Handle isochronous endpoints */ | |
1230 | if (ohci_service_iso_td(ohci, &ed, completion)) | |
1231 | break; | |
1232 | } | |
0d92ed30 PB |
1233 | } |
1234 | ||
cf66ee8e AK |
1235 | if (ohci_put_ed(ohci, cur, &ed)) { |
1236 | ohci_die(ohci); | |
1237 | return 0; | |
1238 | } | |
0d92ed30 PB |
1239 | } |
1240 | ||
1241 | return active; | |
1242 | } | |
1243 | ||
1244 | /* Generate a SOF event, and set a timer for EOF */ | |
1245 | static void ohci_sof(OHCIState *ohci) | |
1246 | { | |
bc72ad67 AB |
1247 | ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
1248 | timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); | |
0d92ed30 PB |
1249 | ohci_set_interrupt(ohci, OHCI_INTR_SF); |
1250 | } | |
1251 | ||
4d611c9a | 1252 | /* Process Control and Bulk lists. */ |
7bfe5777 | 1253 | static void ohci_process_lists(OHCIState *ohci, int completion) |
4d611c9a PB |
1254 | { |
1255 | if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { | |
6ad6135d | 1256 | if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { |
dc1f5988 | 1257 | trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); |
6ad6135d | 1258 | } |
7bfe5777 | 1259 | if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { |
4d611c9a PB |
1260 | ohci->ctrl_cur = 0; |
1261 | ohci->status &= ~OHCI_STATUS_CLF; | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { | |
7bfe5777 | 1266 | if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { |
4d611c9a PB |
1267 | ohci->bulk_cur = 0; |
1268 | ohci->status &= ~OHCI_STATUS_BLF; | |
1269 | } | |
1270 | } | |
1271 | } | |
1272 | ||
0d92ed30 PB |
1273 | /* Do frame processing on frame boundary */ |
1274 | static void ohci_frame_boundary(void *opaque) | |
1275 | { | |
1276 | OHCIState *ohci = opaque; | |
1277 | struct ohci_hcca hcca; | |
1278 | ||
cf66ee8e | 1279 | if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { |
dc1f5988 | 1280 | trace_usb_ohci_hcca_read_error(ohci->hcca); |
cf66ee8e AK |
1281 | ohci_die(ohci); |
1282 | return; | |
1283 | } | |
0d92ed30 PB |
1284 | |
1285 | /* Process all the lists at the end of the frame */ | |
1286 | if (ohci->ctl & OHCI_CTL_PLE) { | |
1287 | int n; | |
1288 | ||
1289 | n = ohci->frame_number & 0x1f; | |
7bfe5777 | 1290 | ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); |
0d92ed30 | 1291 | } |
0d92ed30 | 1292 | |
4d611c9a | 1293 | /* Cancel all pending packets if either of the lists has been disabled. */ |
f79738b0 HG |
1294 | if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { |
1295 | if (ohci->async_td) { | |
1296 | usb_cancel_packet(&ohci->usb_packet); | |
1297 | ohci->async_td = 0; | |
1298 | } | |
1299 | ohci_stop_endpoints(ohci); | |
0d92ed30 | 1300 | } |
4d611c9a | 1301 | ohci->old_ctl = ohci->ctl; |
7bfe5777 | 1302 | ohci_process_lists(ohci, 0); |
0d92ed30 | 1303 | |
cf66ee8e AK |
1304 | /* Stop if UnrecoverableError happened or ohci_sof will crash */ |
1305 | if (ohci->intr_status & OHCI_INTR_UE) { | |
1306 | return; | |
1307 | } | |
1308 | ||
0d92ed30 PB |
1309 | /* Frame boundary, so do EOF stuf here */ |
1310 | ohci->frt = ohci->fit; | |
1311 | ||
1fa63e43 | 1312 | /* Increment frame number and take care of endianness. */ |
0d92ed30 | 1313 | ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
1fa63e43 | 1314 | hcca.frame = cpu_to_le16(ohci->frame_number); |
0d92ed30 PB |
1315 | |
1316 | if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { | |
1317 | if (!ohci->done) | |
1318 | abort(); | |
1319 | if (ohci->intr & ohci->intr_status) | |
1320 | ohci->done |= 1; | |
1321 | hcca.done = cpu_to_le32(ohci->done); | |
1322 | ohci->done = 0; | |
1323 | ohci->done_count = 7; | |
1324 | ohci_set_interrupt(ohci, OHCI_INTR_WD); | |
1325 | } | |
1326 | ||
1327 | if (ohci->done_count != 7 && ohci->done_count != 0) | |
1328 | ohci->done_count--; | |
1329 | ||
1330 | /* Do SOF stuff here */ | |
1331 | ohci_sof(ohci); | |
1332 | ||
1333 | /* Writeback HCCA */ | |
cf66ee8e AK |
1334 | if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { |
1335 | ohci_die(ohci); | |
1336 | } | |
0d92ed30 PB |
1337 | } |
1338 | ||
1339 | /* Start sending SOF tokens across the USB bus, lists are processed in | |
1340 | * next frame | |
1341 | */ | |
1342 | static int ohci_bus_start(OHCIState *ohci) | |
1343 | { | |
bc72ad67 | 1344 | ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
0d92ed30 PB |
1345 | ohci_frame_boundary, |
1346 | ohci); | |
1347 | ||
1348 | if (ohci->eof_timer == NULL) { | |
dc1f5988 | 1349 | trace_usb_ohci_bus_eof_timer_failed(ohci->name); |
cf66ee8e | 1350 | ohci_die(ohci); |
0d92ed30 PB |
1351 | return 0; |
1352 | } | |
1353 | ||
dc1f5988 | 1354 | trace_usb_ohci_start(ohci->name); |
0d92ed30 PB |
1355 | |
1356 | ohci_sof(ohci); | |
1357 | ||
1358 | return 1; | |
1359 | } | |
1360 | ||
1361 | /* Stop sending SOF tokens on the bus */ | |
1362 | static void ohci_bus_stop(OHCIState *ohci) | |
1363 | { | |
dc1f5988 | 1364 | trace_usb_ohci_stop(ohci->name); |
80be63df | 1365 | if (ohci->eof_timer) { |
bc72ad67 | 1366 | timer_del(ohci->eof_timer); |
80be63df GA |
1367 | timer_free(ohci->eof_timer); |
1368 | } | |
73221b12 | 1369 | ohci->eof_timer = NULL; |
0d92ed30 PB |
1370 | } |
1371 | ||
1372 | /* Sets a flag in a port status register but only set it if the port is | |
1373 | * connected, if not set ConnectStatusChange flag. If flag is enabled | |
1374 | * return 1. | |
1375 | */ | |
1376 | static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) | |
1377 | { | |
1378 | int ret = 1; | |
1379 | ||
1380 | /* writing a 0 has no effect */ | |
1381 | if (val == 0) | |
1382 | return 0; | |
1383 | ||
1384 | /* If CurrentConnectStatus is cleared we set | |
1385 | * ConnectStatusChange | |
1386 | */ | |
1387 | if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { | |
1388 | ohci->rhport[i].ctrl |= OHCI_PORT_CSC; | |
1389 | if (ohci->rhstatus & OHCI_RHS_DRWE) { | |
1390 | /* TODO: CSC is a wakeup event */ | |
1391 | } | |
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | if (ohci->rhport[i].ctrl & val) | |
1396 | ret = 0; | |
1397 | ||
1398 | /* set the bit */ | |
1399 | ohci->rhport[i].ctrl |= val; | |
1400 | ||
1401 | return ret; | |
1402 | } | |
1403 | ||
1404 | /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ | |
1405 | static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) | |
1406 | { | |
1407 | val &= OHCI_FMI_FI; | |
1408 | ||
1409 | if (val != ohci->fi) { | |
dc1f5988 | 1410 | trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); |
0d92ed30 PB |
1411 | } |
1412 | ||
1413 | ohci->fi = val; | |
1414 | } | |
1415 | ||
1416 | static void ohci_port_power(OHCIState *ohci, int i, int p) | |
1417 | { | |
1418 | if (p) { | |
1419 | ohci->rhport[i].ctrl |= OHCI_PORT_PPS; | |
1420 | } else { | |
1421 | ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| | |
1422 | OHCI_PORT_CCS| | |
1423 | OHCI_PORT_PSS| | |
1424 | OHCI_PORT_PRS); | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | /* Set HcControlRegister */ | |
1429 | static void ohci_set_ctl(OHCIState *ohci, uint32_t val) | |
1430 | { | |
1431 | uint32_t old_state; | |
1432 | uint32_t new_state; | |
1433 | ||
1434 | old_state = ohci->ctl & OHCI_CTL_HCFS; | |
1435 | ohci->ctl = val; | |
1436 | new_state = ohci->ctl & OHCI_CTL_HCFS; | |
1437 | ||
1438 | /* no state change */ | |
1439 | if (old_state == new_state) | |
1440 | return; | |
1441 | ||
dc1f5988 | 1442 | trace_usb_ohci_set_ctl(ohci->name, new_state); |
0d92ed30 PB |
1443 | switch (new_state) { |
1444 | case OHCI_USB_OPERATIONAL: | |
1445 | ohci_bus_start(ohci); | |
1446 | break; | |
1447 | case OHCI_USB_SUSPEND: | |
1448 | ohci_bus_stop(ohci); | |
0d92ed30 PB |
1449 | break; |
1450 | case OHCI_USB_RESUME: | |
dc1f5988 | 1451 | trace_usb_ohci_resume(ohci->name); |
0d92ed30 PB |
1452 | break; |
1453 | case OHCI_USB_RESET: | |
84d04e21 | 1454 | ohci_hard_reset(ohci); |
0d92ed30 PB |
1455 | break; |
1456 | } | |
1457 | } | |
1458 | ||
1459 | static uint32_t ohci_get_frame_remaining(OHCIState *ohci) | |
1460 | { | |
1461 | uint16_t fr; | |
1462 | int64_t tks; | |
1463 | ||
1464 | if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) | |
1465 | return (ohci->frt << 31); | |
1466 | ||
1467 | /* Being in USB operational state guarnatees sof_time was | |
1468 | * set already. | |
1469 | */ | |
bc72ad67 | 1470 | tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; |
0d92ed30 PB |
1471 | |
1472 | /* avoid muldiv if possible */ | |
1473 | if (tks >= usb_frame_time) | |
1474 | return (ohci->frt << 31); | |
1475 | ||
1476 | tks = muldiv64(1, tks, usb_bit_time); | |
1477 | fr = (uint16_t)(ohci->fi - tks); | |
1478 | ||
1479 | return (ohci->frt << 31) | fr; | |
1480 | } | |
1481 | ||
1482 | ||
1483 | /* Set root hub status */ | |
1484 | static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) | |
1485 | { | |
1486 | uint32_t old_state; | |
1487 | ||
1488 | old_state = ohci->rhstatus; | |
1489 | ||
1490 | /* write 1 to clear OCIC */ | |
1491 | if (val & OHCI_RHS_OCIC) | |
1492 | ohci->rhstatus &= ~OHCI_RHS_OCIC; | |
1493 | ||
1494 | if (val & OHCI_RHS_LPS) { | |
1495 | int i; | |
1496 | ||
1497 | for (i = 0; i < ohci->num_ports; i++) | |
1498 | ohci_port_power(ohci, i, 0); | |
dc1f5988 | 1499 | trace_usb_ohci_hub_power_down(); |
0d92ed30 PB |
1500 | } |
1501 | ||
1502 | if (val & OHCI_RHS_LPSC) { | |
1503 | int i; | |
1504 | ||
1505 | for (i = 0; i < ohci->num_ports; i++) | |
1506 | ohci_port_power(ohci, i, 1); | |
dc1f5988 | 1507 | trace_usb_ohci_hub_power_up(); |
0d92ed30 PB |
1508 | } |
1509 | ||
1510 | if (val & OHCI_RHS_DRWE) | |
1511 | ohci->rhstatus |= OHCI_RHS_DRWE; | |
1512 | ||
1513 | if (val & OHCI_RHS_CRWE) | |
1514 | ohci->rhstatus &= ~OHCI_RHS_DRWE; | |
1515 | ||
1516 | if (old_state != ohci->rhstatus) | |
1517 | ohci_set_interrupt(ohci, OHCI_INTR_RHSC); | |
1518 | } | |
1519 | ||
1520 | /* Set root hub port status */ | |
1521 | static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) | |
1522 | { | |
1523 | uint32_t old_state; | |
1524 | OHCIPort *port; | |
1525 | ||
1526 | port = &ohci->rhport[portnum]; | |
1527 | old_state = port->ctrl; | |
1528 | ||
1529 | /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ | |
1530 | if (val & OHCI_PORT_WTC) | |
1531 | port->ctrl &= ~(val & OHCI_PORT_WTC); | |
1532 | ||
1533 | if (val & OHCI_PORT_CCS) | |
1534 | port->ctrl &= ~OHCI_PORT_PES; | |
1535 | ||
1536 | ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); | |
1537 | ||
6ad6135d | 1538 | if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { |
dc1f5988 | 1539 | trace_usb_ohci_port_suspend(portnum); |
6ad6135d | 1540 | } |
0d92ed30 PB |
1541 | |
1542 | if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { | |
dc1f5988 | 1543 | trace_usb_ohci_port_reset(portnum); |
d28f4e2d | 1544 | usb_device_reset(port->port.dev); |
0d92ed30 PB |
1545 | port->ctrl &= ~OHCI_PORT_PRS; |
1546 | /* ??? Should this also set OHCI_PORT_PESC. */ | |
1547 | port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; | |
1548 | } | |
1549 | ||
1550 | /* Invert order here to ensure in ambiguous case, device is | |
1551 | * powered up... | |
1552 | */ | |
1553 | if (val & OHCI_PORT_LSDA) | |
1554 | ohci_port_power(ohci, portnum, 0); | |
1555 | if (val & OHCI_PORT_PPS) | |
1556 | ohci_port_power(ohci, portnum, 1); | |
1557 | ||
1558 | if (old_state != port->ctrl) | |
1559 | ohci_set_interrupt(ohci, OHCI_INTR_RHSC); | |
0d92ed30 PB |
1560 | } |
1561 | ||
6da48311 | 1562 | static uint64_t ohci_mem_read(void *opaque, |
a8170e5e | 1563 | hwaddr addr, |
6da48311 | 1564 | unsigned size) |
0d92ed30 | 1565 | { |
6da48311 | 1566 | OHCIState *ohci = opaque; |
65e1d81b | 1567 | uint32_t retval; |
0d92ed30 | 1568 | |
0d92ed30 PB |
1569 | /* Only aligned reads are allowed on OHCI */ |
1570 | if (addr & 3) { | |
dc1f5988 | 1571 | trace_usb_ohci_mem_read_unaligned(addr); |
0d92ed30 | 1572 | return 0xffffffff; |
65e1d81b | 1573 | } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
0d92ed30 | 1574 | /* HcRhPortStatus */ |
65e1d81b AJ |
1575 | retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1576 | } else { | |
1577 | switch (addr >> 2) { | |
1578 | case 0: /* HcRevision */ | |
1579 | retval = 0x10; | |
1580 | break; | |
1581 | ||
1582 | case 1: /* HcControl */ | |
1583 | retval = ohci->ctl; | |
1584 | break; | |
1585 | ||
1586 | case 2: /* HcCommandStatus */ | |
1587 | retval = ohci->status; | |
1588 | break; | |
1589 | ||
1590 | case 3: /* HcInterruptStatus */ | |
1591 | retval = ohci->intr_status; | |
1592 | break; | |
1593 | ||
1594 | case 4: /* HcInterruptEnable */ | |
1595 | case 5: /* HcInterruptDisable */ | |
1596 | retval = ohci->intr; | |
1597 | break; | |
1598 | ||
1599 | case 6: /* HcHCCA */ | |
1600 | retval = ohci->hcca; | |
1601 | break; | |
1602 | ||
1603 | case 7: /* HcPeriodCurrentED */ | |
1604 | retval = ohci->per_cur; | |
1605 | break; | |
1606 | ||
1607 | case 8: /* HcControlHeadED */ | |
1608 | retval = ohci->ctrl_head; | |
1609 | break; | |
1610 | ||
1611 | case 9: /* HcControlCurrentED */ | |
1612 | retval = ohci->ctrl_cur; | |
1613 | break; | |
1614 | ||
1615 | case 10: /* HcBulkHeadED */ | |
1616 | retval = ohci->bulk_head; | |
1617 | break; | |
1618 | ||
1619 | case 11: /* HcBulkCurrentED */ | |
1620 | retval = ohci->bulk_cur; | |
1621 | break; | |
1622 | ||
1623 | case 12: /* HcDoneHead */ | |
1624 | retval = ohci->done; | |
1625 | break; | |
1626 | ||
1627 | case 13: /* HcFmInterretval */ | |
1628 | retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); | |
1629 | break; | |
1630 | ||
1631 | case 14: /* HcFmRemaining */ | |
1632 | retval = ohci_get_frame_remaining(ohci); | |
1633 | break; | |
1634 | ||
1635 | case 15: /* HcFmNumber */ | |
1636 | retval = ohci->frame_number; | |
1637 | break; | |
1638 | ||
1639 | case 16: /* HcPeriodicStart */ | |
1640 | retval = ohci->pstart; | |
1641 | break; | |
1642 | ||
1643 | case 17: /* HcLSThreshold */ | |
1644 | retval = ohci->lst; | |
1645 | break; | |
1646 | ||
1647 | case 18: /* HcRhDescriptorA */ | |
1648 | retval = ohci->rhdesc_a; | |
1649 | break; | |
1650 | ||
1651 | case 19: /* HcRhDescriptorB */ | |
1652 | retval = ohci->rhdesc_b; | |
1653 | break; | |
1654 | ||
1655 | case 20: /* HcRhStatus */ | |
1656 | retval = ohci->rhstatus; | |
1657 | break; | |
1658 | ||
1659 | /* PXA27x specific registers */ | |
1660 | case 24: /* HcStatus */ | |
1661 | retval = ohci->hstatus & ohci->hmask; | |
1662 | break; | |
1663 | ||
1664 | case 25: /* HcHReset */ | |
1665 | retval = ohci->hreset; | |
1666 | break; | |
1667 | ||
1668 | case 26: /* HcHInterruptEnable */ | |
1669 | retval = ohci->hmask; | |
1670 | break; | |
1671 | ||
1672 | case 27: /* HcHInterruptTest */ | |
1673 | retval = ohci->htest; | |
1674 | break; | |
1675 | ||
1676 | default: | |
dc1f5988 | 1677 | trace_usb_ohci_mem_read_bad_offset(addr); |
65e1d81b AJ |
1678 | retval = 0xffffffff; |
1679 | } | |
0d92ed30 PB |
1680 | } |
1681 | ||
65e1d81b | 1682 | return retval; |
0d92ed30 PB |
1683 | } |
1684 | ||
6da48311 | 1685 | static void ohci_mem_write(void *opaque, |
a8170e5e | 1686 | hwaddr addr, |
6da48311 AK |
1687 | uint64_t val, |
1688 | unsigned size) | |
0d92ed30 | 1689 | { |
6da48311 | 1690 | OHCIState *ohci = opaque; |
09564574 | 1691 | |
0d92ed30 PB |
1692 | /* Only aligned reads are allowed on OHCI */ |
1693 | if (addr & 3) { | |
dc1f5988 | 1694 | trace_usb_ohci_mem_write_unaligned(addr); |
0d92ed30 PB |
1695 | return; |
1696 | } | |
1697 | ||
1698 | if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { | |
1699 | /* HcRhPortStatus */ | |
1700 | ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); | |
1701 | return; | |
1702 | } | |
1703 | ||
1704 | switch (addr >> 2) { | |
1705 | case 1: /* HcControl */ | |
1706 | ohci_set_ctl(ohci, val); | |
1707 | break; | |
1708 | ||
1709 | case 2: /* HcCommandStatus */ | |
1710 | /* SOC is read-only */ | |
1711 | val = (val & ~OHCI_STATUS_SOC); | |
1712 | ||
1713 | /* Bits written as '0' remain unchanged in the register */ | |
1714 | ohci->status |= val; | |
1715 | ||
1716 | if (ohci->status & OHCI_STATUS_HCR) | |
84d04e21 | 1717 | ohci_hard_reset(ohci); |
0d92ed30 PB |
1718 | break; |
1719 | ||
1720 | case 3: /* HcInterruptStatus */ | |
1721 | ohci->intr_status &= ~val; | |
1722 | ohci_intr_update(ohci); | |
1723 | break; | |
1724 | ||
1725 | case 4: /* HcInterruptEnable */ | |
1726 | ohci->intr |= val; | |
1727 | ohci_intr_update(ohci); | |
1728 | break; | |
1729 | ||
1730 | case 5: /* HcInterruptDisable */ | |
1731 | ohci->intr &= ~val; | |
1732 | ohci_intr_update(ohci); | |
1733 | break; | |
1734 | ||
1735 | case 6: /* HcHCCA */ | |
1736 | ohci->hcca = val & OHCI_HCCA_MASK; | |
1737 | break; | |
1738 | ||
4b0315d7 PM |
1739 | case 7: /* HcPeriodCurrentED */ |
1740 | /* Ignore writes to this read-only register, Linux does them */ | |
1741 | break; | |
1742 | ||
0d92ed30 PB |
1743 | case 8: /* HcControlHeadED */ |
1744 | ohci->ctrl_head = val & OHCI_EDPTR_MASK; | |
1745 | break; | |
1746 | ||
1747 | case 9: /* HcControlCurrentED */ | |
1748 | ohci->ctrl_cur = val & OHCI_EDPTR_MASK; | |
1749 | break; | |
1750 | ||
1751 | case 10: /* HcBulkHeadED */ | |
1752 | ohci->bulk_head = val & OHCI_EDPTR_MASK; | |
1753 | break; | |
1754 | ||
1755 | case 11: /* HcBulkCurrentED */ | |
1756 | ohci->bulk_cur = val & OHCI_EDPTR_MASK; | |
1757 | break; | |
1758 | ||
1759 | case 13: /* HcFmInterval */ | |
1760 | ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; | |
1761 | ohci->fit = (val & OHCI_FMI_FIT) >> 31; | |
1762 | ohci_set_frame_interval(ohci, val); | |
1763 | break; | |
1764 | ||
7bfe5777 AZ |
1765 | case 15: /* HcFmNumber */ |
1766 | break; | |
1767 | ||
0d92ed30 PB |
1768 | case 16: /* HcPeriodicStart */ |
1769 | ohci->pstart = val & 0xffff; | |
1770 | break; | |
1771 | ||
1772 | case 17: /* HcLSThreshold */ | |
1773 | ohci->lst = val & 0xffff; | |
1774 | break; | |
1775 | ||
1776 | case 18: /* HcRhDescriptorA */ | |
1777 | ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; | |
1778 | ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; | |
1779 | break; | |
1780 | ||
1781 | case 19: /* HcRhDescriptorB */ | |
1782 | break; | |
1783 | ||
1784 | case 20: /* HcRhStatus */ | |
1785 | ohci_set_hub_status(ohci, val); | |
1786 | break; | |
1787 | ||
e24ad6f1 PB |
1788 | /* PXA27x specific registers */ |
1789 | case 24: /* HcStatus */ | |
1790 | ohci->hstatus &= ~(val & ohci->hmask); | |
7fa96d73 | 1791 | break; |
e24ad6f1 PB |
1792 | |
1793 | case 25: /* HcHReset */ | |
1794 | ohci->hreset = val & ~OHCI_HRESET_FSBIR; | |
1795 | if (val & OHCI_HRESET_FSBIR) | |
84d04e21 | 1796 | ohci_hard_reset(ohci); |
e24ad6f1 PB |
1797 | break; |
1798 | ||
1799 | case 26: /* HcHInterruptEnable */ | |
1800 | ohci->hmask = val; | |
1801 | break; | |
1802 | ||
1803 | case 27: /* HcHInterruptTest */ | |
1804 | ohci->htest = val; | |
1805 | break; | |
1806 | ||
0d92ed30 | 1807 | default: |
dc1f5988 | 1808 | trace_usb_ohci_mem_write_bad_offset(addr); |
0d92ed30 PB |
1809 | break; |
1810 | } | |
1811 | } | |
1812 | ||
4706ab6c | 1813 | static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) |
07771f6f | 1814 | { |
25d5de7d | 1815 | if (ohci->async_td && |
f53c398a GH |
1816 | usb_packet_is_inflight(&ohci->usb_packet) && |
1817 | ohci->usb_packet.ep->dev == dev) { | |
07771f6f GH |
1818 | usb_cancel_packet(&ohci->usb_packet); |
1819 | ohci->async_td = 0; | |
1820 | } | |
1821 | } | |
1822 | ||
6da48311 AK |
1823 | static const MemoryRegionOps ohci_mem_ops = { |
1824 | .read = ohci_mem_read, | |
1825 | .write = ohci_mem_write, | |
1826 | .endianness = DEVICE_LITTLE_ENDIAN, | |
0d92ed30 PB |
1827 | }; |
1828 | ||
0d86d2be GH |
1829 | static USBPortOps ohci_port_ops = { |
1830 | .attach = ohci_attach, | |
618c169b | 1831 | .detach = ohci_detach, |
4706ab6c | 1832 | .child_detach = ohci_child_detach, |
9bba1eb1 | 1833 | .wakeup = ohci_wakeup, |
13a9a0d3 | 1834 | .complete = ohci_async_complete_packet, |
0d86d2be GH |
1835 | }; |
1836 | ||
07771f6f | 1837 | static USBBusOps ohci_bus_ops = { |
07771f6f GH |
1838 | }; |
1839 | ||
87581fea MA |
1840 | static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
1841 | int num_ports, dma_addr_t localmem_base, | |
1842 | char *masterbus, uint32_t firstport, | |
1843 | AddressSpace *as, Error **errp) | |
0d92ed30 | 1844 | { |
f4bbaaf5 | 1845 | Error *err = NULL; |
0d92ed30 PB |
1846 | int i; |
1847 | ||
df32fd1c | 1848 | ohci->as = as; |
9ac6a217 | 1849 | |
0d92ed30 | 1850 | if (usb_frame_time == 0) { |
eb38c52c | 1851 | #ifdef OHCI_TIME_WARP |
6ee093c9 JQ |
1852 | usb_frame_time = get_ticks_per_sec(); |
1853 | usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); | |
0d92ed30 | 1854 | #else |
6ee093c9 JQ |
1855 | usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); |
1856 | if (get_ticks_per_sec() >= USB_HZ) { | |
1857 | usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ); | |
0d92ed30 PB |
1858 | } else { |
1859 | usb_bit_time = 1; | |
1860 | } | |
1861 | #endif | |
dc1f5988 | 1862 | trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); |
0d92ed30 PB |
1863 | } |
1864 | ||
9c9fc334 HG |
1865 | ohci->num_ports = num_ports; |
1866 | if (masterbus) { | |
1867 | USBPort *ports[OHCI_MAX_PORTS]; | |
1868 | for(i = 0; i < num_ports; i++) { | |
1869 | ports[i] = &ohci->rhport[i].port; | |
1870 | } | |
f4bbaaf5 MA |
1871 | usb_register_companion(masterbus, ports, num_ports, |
1872 | firstport, ohci, &ohci_port_ops, | |
1873 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, | |
1874 | &err); | |
1875 | if (err) { | |
87581fea MA |
1876 | error_propagate(errp, err); |
1877 | return; | |
9c9fc334 HG |
1878 | } |
1879 | } else { | |
c889b3a5 | 1880 | usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); |
9c9fc334 HG |
1881 | for (i = 0; i < num_ports; i++) { |
1882 | usb_register_port(&ohci->bus, &ohci->rhport[i].port, | |
1883 | ohci, i, &ohci_port_ops, | |
1884 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1885 | } | |
1886 | } | |
1887 | ||
22fc860b PB |
1888 | memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, |
1889 | ohci, "ohci", 256); | |
ac611340 | 1890 | ohci->localmem_base = localmem_base; |
e24ad6f1 | 1891 | |
f79f2bfc | 1892 | ohci->name = object_get_typename(OBJECT(dev)); |
4f4321c1 | 1893 | usb_packet_init(&ohci->usb_packet); |
e24ad6f1 | 1894 | |
e24ad6f1 | 1895 | ohci->async_td = 0; |
e24ad6f1 PB |
1896 | } |
1897 | ||
1aa0c0c7 HT |
1898 | #define TYPE_PCI_OHCI "pci-ohci" |
1899 | #define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI) | |
1900 | ||
e24ad6f1 | 1901 | typedef struct { |
1aa0c0c7 HT |
1902 | /*< private >*/ |
1903 | PCIDevice parent_obj; | |
1904 | /*< public >*/ | |
1905 | ||
e24ad6f1 | 1906 | OHCIState state; |
9c9fc334 HG |
1907 | char *masterbus; |
1908 | uint32_t num_ports; | |
1909 | uint32_t firstport; | |
e24ad6f1 PB |
1910 | } OHCIPCIState; |
1911 | ||
cf66ee8e AK |
1912 | /** A typical O/EHCI will stop operating, set itself into error state |
1913 | * (which can be queried by MMIO) and will set PERR in its config | |
1914 | * space to signal that it got an error | |
1915 | */ | |
1916 | static void ohci_die(OHCIState *ohci) | |
1917 | { | |
1918 | OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state); | |
1919 | ||
dc1f5988 | 1920 | trace_usb_ohci_die(); |
cf66ee8e AK |
1921 | |
1922 | ohci_set_interrupt(ohci, OHCI_INTR_UE); | |
1923 | ohci_bus_stop(ohci); | |
1924 | pci_set_word(dev->parent_obj.config + PCI_STATUS, | |
1925 | PCI_STATUS_DETECTED_PARITY); | |
1926 | } | |
1927 | ||
87581fea | 1928 | static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp) |
e24ad6f1 | 1929 | { |
87581fea | 1930 | Error *err = NULL; |
1aa0c0c7 | 1931 | OHCIPCIState *ohci = PCI_OHCI(dev); |
0d92ed30 | 1932 | |
1aa0c0c7 HT |
1933 | dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */ |
1934 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ | |
0d92ed30 | 1935 | |
87581fea MA |
1936 | usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0, |
1937 | ohci->masterbus, ohci->firstport, | |
1938 | pci_get_address_space(dev), &err); | |
1939 | if (err) { | |
1940 | error_propagate(errp, err); | |
1941 | return; | |
9c9fc334 | 1942 | } |
0d92ed30 | 1943 | |
87581fea | 1944 | ohci->state.irq = pci_allocate_irq(dev); |
1aa0c0c7 | 1945 | pci_register_bar(dev, 0, 0, &ohci->state.mem); |
5b19d9a2 GH |
1946 | } |
1947 | ||
07832c38 GA |
1948 | static void usb_ohci_exit(PCIDevice *dev) |
1949 | { | |
1950 | OHCIPCIState *ohci = PCI_OHCI(dev); | |
1951 | OHCIState *s = &ohci->state; | |
1952 | ||
dc1f5988 | 1953 | trace_usb_ohci_exit(s->name); |
07832c38 GA |
1954 | ohci_bus_stop(s); |
1955 | ||
1956 | if (s->async_td) { | |
1957 | usb_cancel_packet(&s->usb_packet); | |
1958 | s->async_td = 0; | |
1959 | } | |
1960 | ohci_stop_endpoints(s); | |
1961 | ||
1962 | if (!ohci->masterbus) { | |
1963 | usb_bus_release(&s->bus); | |
1964 | } | |
1965 | } | |
1966 | ||
88dd1b8d GA |
1967 | static void usb_ohci_reset_pci(DeviceState *d) |
1968 | { | |
1969 | PCIDevice *dev = PCI_DEVICE(d); | |
1970 | OHCIPCIState *ohci = PCI_OHCI(dev); | |
1971 | OHCIState *s = &ohci->state; | |
1972 | ||
84d04e21 | 1973 | ohci_hard_reset(s); |
88dd1b8d GA |
1974 | } |
1975 | ||
1aa0c0c7 HT |
1976 | #define TYPE_SYSBUS_OHCI "sysbus-ohci" |
1977 | #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI) | |
1978 | ||
61d3cf93 | 1979 | typedef struct { |
1aa0c0c7 HT |
1980 | /*< private >*/ |
1981 | SysBusDevice parent_obj; | |
1982 | /*< public >*/ | |
1983 | ||
61d3cf93 PB |
1984 | OHCIState ohci; |
1985 | uint32_t num_ports; | |
9ac6a217 | 1986 | dma_addr_t dma_offset; |
61d3cf93 | 1987 | } OHCISysBusState; |
ac611340 | 1988 | |
457215ec | 1989 | static void ohci_realize_pxa(DeviceState *dev, Error **errp) |
ac611340 | 1990 | { |
1aa0c0c7 | 1991 | OHCISysBusState *s = SYSBUS_OHCI(dev); |
457215ec | 1992 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
ac611340 | 1993 | |
9c9fc334 | 1994 | /* Cannot fail as we pass NULL for masterbus */ |
457215ec | 1995 | usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, NULL, 0, |
87581fea | 1996 | &address_space_memory, &error_abort); |
457215ec HT |
1997 | sysbus_init_irq(sbd, &s->ohci.irq); |
1998 | sysbus_init_mmio(sbd, &s->ohci.mem); | |
ac611340 AJ |
1999 | } |
2000 | ||
88dd1b8d GA |
2001 | static void usb_ohci_reset_sysbus(DeviceState *dev) |
2002 | { | |
2003 | OHCISysBusState *s = SYSBUS_OHCI(dev); | |
2004 | OHCIState *ohci = &s->ohci; | |
2005 | ||
84d04e21 | 2006 | ohci_hard_reset(ohci); |
88dd1b8d GA |
2007 | } |
2008 | ||
40021f08 AL |
2009 | static Property ohci_pci_properties[] = { |
2010 | DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), | |
2011 | DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), | |
2012 | DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), | |
2013 | DEFINE_PROP_END_OF_LIST(), | |
2014 | }; | |
2015 | ||
69e25d26 AK |
2016 | static const VMStateDescription vmstate_ohci_state_port = { |
2017 | .name = "ohci-core/port", | |
2018 | .version_id = 1, | |
2019 | .minimum_version_id = 1, | |
25feab2f | 2020 | .fields = (VMStateField[]) { |
69e25d26 AK |
2021 | VMSTATE_UINT32(ctrl, OHCIPort), |
2022 | VMSTATE_END_OF_LIST() | |
2023 | }, | |
2024 | }; | |
2025 | ||
2026 | static bool ohci_eof_timer_needed(void *opaque) | |
2027 | { | |
2028 | OHCIState *ohci = opaque; | |
2029 | ||
2030 | return ohci->eof_timer != NULL; | |
2031 | } | |
2032 | ||
2033 | static int ohci_eof_timer_pre_load(void *opaque) | |
2034 | { | |
2035 | OHCIState *ohci = opaque; | |
2036 | ||
2037 | ohci_bus_start(ohci); | |
2038 | ||
2039 | return 0; | |
2040 | } | |
2041 | ||
2042 | static const VMStateDescription vmstate_ohci_eof_timer = { | |
2043 | .name = "ohci-core/eof-timer", | |
2044 | .version_id = 1, | |
2045 | .minimum_version_id = 1, | |
69e25d26 | 2046 | .pre_load = ohci_eof_timer_pre_load, |
5cd8cada | 2047 | .needed = ohci_eof_timer_needed, |
25feab2f | 2048 | .fields = (VMStateField[]) { |
e720677e | 2049 | VMSTATE_TIMER_PTR(eof_timer, OHCIState), |
69e25d26 AK |
2050 | VMSTATE_END_OF_LIST() |
2051 | }, | |
2052 | }; | |
2053 | ||
b9b45b4a | 2054 | static const VMStateDescription vmstate_ohci_state = { |
69e25d26 AK |
2055 | .name = "ohci-core", |
2056 | .version_id = 1, | |
2057 | .minimum_version_id = 1, | |
2058 | .fields = (VMStateField[]) { | |
2059 | VMSTATE_INT64(sof_time, OHCIState), | |
2060 | VMSTATE_UINT32(ctl, OHCIState), | |
2061 | VMSTATE_UINT32(status, OHCIState), | |
2062 | VMSTATE_UINT32(intr_status, OHCIState), | |
2063 | VMSTATE_UINT32(intr, OHCIState), | |
2064 | VMSTATE_UINT32(hcca, OHCIState), | |
2065 | VMSTATE_UINT32(ctrl_head, OHCIState), | |
2066 | VMSTATE_UINT32(ctrl_cur, OHCIState), | |
2067 | VMSTATE_UINT32(bulk_head, OHCIState), | |
2068 | VMSTATE_UINT32(bulk_cur, OHCIState), | |
2069 | VMSTATE_UINT32(per_cur, OHCIState), | |
2070 | VMSTATE_UINT32(done, OHCIState), | |
2071 | VMSTATE_INT32(done_count, OHCIState), | |
2072 | VMSTATE_UINT16(fsmps, OHCIState), | |
2073 | VMSTATE_UINT8(fit, OHCIState), | |
2074 | VMSTATE_UINT16(fi, OHCIState), | |
2075 | VMSTATE_UINT8(frt, OHCIState), | |
2076 | VMSTATE_UINT16(frame_number, OHCIState), | |
2077 | VMSTATE_UINT16(padding, OHCIState), | |
2078 | VMSTATE_UINT32(pstart, OHCIState), | |
2079 | VMSTATE_UINT32(lst, OHCIState), | |
2080 | VMSTATE_UINT32(rhdesc_a, OHCIState), | |
2081 | VMSTATE_UINT32(rhdesc_b, OHCIState), | |
2082 | VMSTATE_UINT32(rhstatus, OHCIState), | |
2083 | VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, | |
2084 | vmstate_ohci_state_port, OHCIPort), | |
2085 | VMSTATE_UINT32(hstatus, OHCIState), | |
2086 | VMSTATE_UINT32(hmask, OHCIState), | |
2087 | VMSTATE_UINT32(hreset, OHCIState), | |
2088 | VMSTATE_UINT32(htest, OHCIState), | |
2089 | VMSTATE_UINT32(old_ctl, OHCIState), | |
2090 | VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), | |
2091 | VMSTATE_UINT32(async_td, OHCIState), | |
2092 | VMSTATE_BOOL(async_complete, OHCIState), | |
2093 | VMSTATE_END_OF_LIST() | |
2094 | }, | |
5cd8cada JQ |
2095 | .subsections = (const VMStateDescription*[]) { |
2096 | &vmstate_ohci_eof_timer, | |
2097 | NULL | |
69e25d26 AK |
2098 | } |
2099 | }; | |
2100 | ||
2101 | static const VMStateDescription vmstate_ohci = { | |
2102 | .name = "ohci", | |
2103 | .version_id = 1, | |
2104 | .minimum_version_id = 1, | |
69e25d26 AK |
2105 | .fields = (VMStateField[]) { |
2106 | VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState), | |
2107 | VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState), | |
2108 | VMSTATE_END_OF_LIST() | |
2109 | } | |
2110 | }; | |
2111 | ||
40021f08 AL |
2112 | static void ohci_pci_class_init(ObjectClass *klass, void *data) |
2113 | { | |
39bffca2 | 2114 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2115 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2116 | ||
87581fea | 2117 | k->realize = usb_ohci_realize_pci; |
07832c38 | 2118 | k->exit = usb_ohci_exit; |
40021f08 AL |
2119 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
2120 | k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; | |
2121 | k->class_id = PCI_CLASS_SERIAL_USB; | |
125ee0ed | 2122 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
39bffca2 AL |
2123 | dc->desc = "Apple USB Controller"; |
2124 | dc->props = ohci_pci_properties; | |
2897ae02 | 2125 | dc->hotpluggable = false; |
69e25d26 | 2126 | dc->vmsd = &vmstate_ohci; |
88dd1b8d | 2127 | dc->reset = usb_ohci_reset_pci; |
40021f08 AL |
2128 | } |
2129 | ||
8c43a6f0 | 2130 | static const TypeInfo ohci_pci_info = { |
1aa0c0c7 | 2131 | .name = TYPE_PCI_OHCI, |
39bffca2 AL |
2132 | .parent = TYPE_PCI_DEVICE, |
2133 | .instance_size = sizeof(OHCIPCIState), | |
2134 | .class_init = ohci_pci_class_init, | |
2135 | }; | |
2136 | ||
2137 | static Property ohci_sysbus_properties[] = { | |
2138 | DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), | |
9ac6a217 | 2139 | DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 3), |
39bffca2 | 2140 | DEFINE_PROP_END_OF_LIST(), |
5b19d9a2 GH |
2141 | }; |
2142 | ||
999e12bb AL |
2143 | static void ohci_sysbus_class_init(ObjectClass *klass, void *data) |
2144 | { | |
39bffca2 | 2145 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2146 | |
457215ec | 2147 | dc->realize = ohci_realize_pxa; |
125ee0ed | 2148 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
39bffca2 AL |
2149 | dc->desc = "OHCI USB Controller"; |
2150 | dc->props = ohci_sysbus_properties; | |
88dd1b8d | 2151 | dc->reset = usb_ohci_reset_sysbus; |
999e12bb AL |
2152 | } |
2153 | ||
8c43a6f0 | 2154 | static const TypeInfo ohci_sysbus_info = { |
1aa0c0c7 | 2155 | .name = TYPE_SYSBUS_OHCI, |
39bffca2 AL |
2156 | .parent = TYPE_SYS_BUS_DEVICE, |
2157 | .instance_size = sizeof(OHCISysBusState), | |
2158 | .class_init = ohci_sysbus_class_init, | |
61d3cf93 PB |
2159 | }; |
2160 | ||
83f7d43a | 2161 | static void ohci_register_types(void) |
5b19d9a2 | 2162 | { |
39bffca2 AL |
2163 | type_register_static(&ohci_pci_info); |
2164 | type_register_static(&ohci_sysbus_info); | |
5b19d9a2 | 2165 | } |
83f7d43a AF |
2166 | |
2167 | type_init(ohci_register_types) |