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Commit | Line | Data |
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0d92ed30 PB |
1 | /* |
2 | * QEMU USB OHCI Emulation | |
3 | * Copyright (c) 2004 Gianni Tedesco | |
4 | * Copyright (c) 2006 CodeSourcery | |
e24ad6f1 | 5 | * Copyright (c) 2006 Openedhand Ltd. |
0d92ed30 PB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
0d92ed30 PB |
19 | * |
20 | * TODO: | |
21 | * o Isochronous transfers | |
22 | * o Allocate bandwidth in frames properly | |
23 | * o Disable timers when nothing needs to be done, or remove timer usage | |
24 | * all together. | |
0d92ed30 PB |
25 | * o BIOS work to boot from USB storage |
26 | */ | |
27 | ||
e532b2e0 | 28 | #include "qemu/osdep.h" |
f1ae32a1 | 29 | #include "hw/hw.h" |
da34e65c | 30 | #include "qapi/error.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
f1ae32a1 | 32 | #include "hw/usb.h" |
a2cb15b0 | 33 | #include "hw/pci/pci.h" |
f1ae32a1 | 34 | #include "hw/sysbus.h" |
9ac6a217 | 35 | #include "hw/qdev-dma.h" |
dc1f5988 | 36 | #include "trace.h" |
0d92ed30 | 37 | |
0d92ed30 PB |
38 | /* This causes frames to occur 1000x slower */ |
39 | //#define OHCI_TIME_WARP 1 | |
40 | ||
0d92ed30 PB |
41 | /* Number of Downstream Ports on the root hub. */ |
42 | ||
43 | #define OHCI_MAX_PORTS 15 | |
44 | ||
45 | static int64_t usb_frame_time; | |
46 | static int64_t usb_bit_time; | |
47 | ||
48 | typedef struct OHCIPort { | |
49 | USBPort port; | |
50 | uint32_t ctrl; | |
51 | } OHCIPort; | |
52 | ||
53 | typedef struct { | |
b2317837 | 54 | USBBus bus; |
d537cf6c | 55 | qemu_irq irq; |
6da48311 | 56 | MemoryRegion mem; |
df32fd1c | 57 | AddressSpace *as; |
0d92ed30 | 58 | int num_ports; |
e24ad6f1 | 59 | const char *name; |
0d92ed30 PB |
60 | |
61 | QEMUTimer *eof_timer; | |
62 | int64_t sof_time; | |
63 | ||
64 | /* OHCI state */ | |
65 | /* Control partition */ | |
66 | uint32_t ctl, status; | |
67 | uint32_t intr_status; | |
68 | uint32_t intr; | |
69 | ||
70 | /* memory pointer partition */ | |
71 | uint32_t hcca; | |
72 | uint32_t ctrl_head, ctrl_cur; | |
73 | uint32_t bulk_head, bulk_cur; | |
74 | uint32_t per_cur; | |
75 | uint32_t done; | |
69e25d26 | 76 | int32_t done_count; |
0d92ed30 PB |
77 | |
78 | /* Frame counter partition */ | |
69e25d26 AK |
79 | uint16_t fsmps; |
80 | uint8_t fit; | |
81 | uint16_t fi; | |
82 | uint8_t frt; | |
0d92ed30 PB |
83 | uint16_t frame_number; |
84 | uint16_t padding; | |
85 | uint32_t pstart; | |
86 | uint32_t lst; | |
87 | ||
88 | /* Root Hub partition */ | |
89 | uint32_t rhdesc_a, rhdesc_b; | |
90 | uint32_t rhstatus; | |
91 | OHCIPort rhport[OHCI_MAX_PORTS]; | |
4d611c9a | 92 | |
e24ad6f1 PB |
93 | /* PXA27x Non-OHCI events */ |
94 | uint32_t hstatus; | |
95 | uint32_t hmask; | |
96 | uint32_t hreset; | |
97 | uint32_t htest; | |
98 | ||
ac611340 | 99 | /* SM501 local memory offset */ |
9ac6a217 | 100 | dma_addr_t localmem_base; |
ac611340 | 101 | |
4d611c9a PB |
102 | /* Active packets. */ |
103 | uint32_t old_ctl; | |
104 | USBPacket usb_packet; | |
105 | uint8_t usb_buf[8192]; | |
106 | uint32_t async_td; | |
69e25d26 | 107 | bool async_complete; |
4d611c9a | 108 | |
0d92ed30 PB |
109 | } OHCIState; |
110 | ||
111 | /* Host Controller Communications Area */ | |
112 | struct ohci_hcca { | |
113 | uint32_t intr[32]; | |
114 | uint16_t frame, pad; | |
115 | uint32_t done; | |
116 | }; | |
86e18cae WY |
117 | #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) |
118 | #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ | |
119 | ||
120 | #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) | |
121 | #define ED_WBACK_SIZE 4 | |
0d92ed30 | 122 | |
73221b12 | 123 | static void ohci_bus_stop(OHCIState *ohci); |
4706ab6c | 124 | static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); |
73221b12 | 125 | |
0d92ed30 PB |
126 | /* Bitfields for the first word of an Endpoint Desciptor. */ |
127 | #define OHCI_ED_FA_SHIFT 0 | |
128 | #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) | |
129 | #define OHCI_ED_EN_SHIFT 7 | |
130 | #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) | |
131 | #define OHCI_ED_D_SHIFT 11 | |
132 | #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) | |
133 | #define OHCI_ED_S (1<<13) | |
134 | #define OHCI_ED_K (1<<14) | |
135 | #define OHCI_ED_F (1<<15) | |
7bfe5777 AZ |
136 | #define OHCI_ED_MPS_SHIFT 16 |
137 | #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) | |
0d92ed30 PB |
138 | |
139 | /* Flags in the head field of an Endpoint Desciptor. */ | |
140 | #define OHCI_ED_H 1 | |
141 | #define OHCI_ED_C 2 | |
142 | ||
143 | /* Bitfields for the first word of a Transfer Desciptor. */ | |
144 | #define OHCI_TD_R (1<<18) | |
145 | #define OHCI_TD_DP_SHIFT 19 | |
146 | #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) | |
147 | #define OHCI_TD_DI_SHIFT 21 | |
148 | #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) | |
149 | #define OHCI_TD_T0 (1<<24) | |
8d11b78c | 150 | #define OHCI_TD_T1 (1<<25) |
0d92ed30 PB |
151 | #define OHCI_TD_EC_SHIFT 26 |
152 | #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) | |
153 | #define OHCI_TD_CC_SHIFT 28 | |
154 | #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) | |
155 | ||
7bfe5777 AZ |
156 | /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ |
157 | /* CC & DI - same as in the General Transfer Desciptor */ | |
158 | #define OHCI_TD_SF_SHIFT 0 | |
159 | #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) | |
160 | #define OHCI_TD_FC_SHIFT 24 | |
161 | #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) | |
162 | ||
163 | /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ | |
164 | #define OHCI_TD_PSW_CC_SHIFT 12 | |
165 | #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) | |
166 | #define OHCI_TD_PSW_SIZE_SHIFT 0 | |
167 | #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) | |
168 | ||
169 | #define OHCI_PAGE_MASK 0xfffff000 | |
170 | #define OHCI_OFFSET_MASK 0xfff | |
171 | ||
0d92ed30 PB |
172 | #define OHCI_DPTR_MASK 0xfffffff0 |
173 | ||
174 | #define OHCI_BM(val, field) \ | |
175 | (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) | |
176 | ||
177 | #define OHCI_SET_BM(val, field, newval) do { \ | |
178 | val &= ~OHCI_##field##_MASK; \ | |
179 | val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ | |
180 | } while(0) | |
181 | ||
182 | /* endpoint descriptor */ | |
183 | struct ohci_ed { | |
184 | uint32_t flags; | |
185 | uint32_t tail; | |
186 | uint32_t head; | |
187 | uint32_t next; | |
188 | }; | |
189 | ||
190 | /* General transfer descriptor */ | |
191 | struct ohci_td { | |
192 | uint32_t flags; | |
193 | uint32_t cbp; | |
194 | uint32_t next; | |
195 | uint32_t be; | |
196 | }; | |
197 | ||
7bfe5777 AZ |
198 | /* Isochronous transfer descriptor */ |
199 | struct ohci_iso_td { | |
200 | uint32_t flags; | |
201 | uint32_t bp; | |
202 | uint32_t next; | |
203 | uint32_t be; | |
204 | uint16_t offset[8]; | |
205 | }; | |
206 | ||
0d92ed30 PB |
207 | #define USB_HZ 12000000 |
208 | ||
209 | /* OHCI Local stuff */ | |
210 | #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) | |
211 | #define OHCI_CTL_PLE (1<<2) | |
212 | #define OHCI_CTL_IE (1<<3) | |
213 | #define OHCI_CTL_CLE (1<<4) | |
214 | #define OHCI_CTL_BLE (1<<5) | |
215 | #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) | |
216 | #define OHCI_USB_RESET 0x00 | |
217 | #define OHCI_USB_RESUME 0x40 | |
218 | #define OHCI_USB_OPERATIONAL 0x80 | |
219 | #define OHCI_USB_SUSPEND 0xc0 | |
220 | #define OHCI_CTL_IR (1<<8) | |
221 | #define OHCI_CTL_RWC (1<<9) | |
222 | #define OHCI_CTL_RWE (1<<10) | |
223 | ||
224 | #define OHCI_STATUS_HCR (1<<0) | |
225 | #define OHCI_STATUS_CLF (1<<1) | |
226 | #define OHCI_STATUS_BLF (1<<2) | |
227 | #define OHCI_STATUS_OCR (1<<3) | |
228 | #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) | |
229 | ||
00b01793 PM |
230 | #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ |
231 | #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ | |
232 | #define OHCI_INTR_SF (1U<<2) /* Start of frame */ | |
233 | #define OHCI_INTR_RD (1U<<3) /* Resume detect */ | |
234 | #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ | |
235 | #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ | |
236 | #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ | |
237 | #define OHCI_INTR_OC (1U<<30) /* Ownership change */ | |
238 | #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ | |
0d92ed30 PB |
239 | |
240 | #define OHCI_HCCA_SIZE 0x100 | |
241 | #define OHCI_HCCA_MASK 0xffffff00 | |
242 | ||
243 | #define OHCI_EDPTR_MASK 0xfffffff0 | |
244 | ||
245 | #define OHCI_FMI_FI 0x00003fff | |
246 | #define OHCI_FMI_FSMPS 0xffff0000 | |
247 | #define OHCI_FMI_FIT 0x80000000 | |
248 | ||
00b01793 | 249 | #define OHCI_FR_RT (1U<<31) |
0d92ed30 PB |
250 | |
251 | #define OHCI_LS_THRESH 0x628 | |
252 | ||
253 | #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ | |
254 | #define OHCI_RHA_PSM (1<<8) | |
255 | #define OHCI_RHA_NPS (1<<9) | |
256 | #define OHCI_RHA_DT (1<<10) | |
257 | #define OHCI_RHA_OCPM (1<<11) | |
258 | #define OHCI_RHA_NOCP (1<<12) | |
259 | #define OHCI_RHA_POTPGT_MASK 0xff000000 | |
260 | ||
00b01793 PM |
261 | #define OHCI_RHS_LPS (1U<<0) |
262 | #define OHCI_RHS_OCI (1U<<1) | |
263 | #define OHCI_RHS_DRWE (1U<<15) | |
264 | #define OHCI_RHS_LPSC (1U<<16) | |
265 | #define OHCI_RHS_OCIC (1U<<17) | |
266 | #define OHCI_RHS_CRWE (1U<<31) | |
0d92ed30 PB |
267 | |
268 | #define OHCI_PORT_CCS (1<<0) | |
269 | #define OHCI_PORT_PES (1<<1) | |
270 | #define OHCI_PORT_PSS (1<<2) | |
271 | #define OHCI_PORT_POCI (1<<3) | |
272 | #define OHCI_PORT_PRS (1<<4) | |
273 | #define OHCI_PORT_PPS (1<<8) | |
274 | #define OHCI_PORT_LSDA (1<<9) | |
275 | #define OHCI_PORT_CSC (1<<16) | |
276 | #define OHCI_PORT_PESC (1<<17) | |
277 | #define OHCI_PORT_PSSC (1<<18) | |
278 | #define OHCI_PORT_OCIC (1<<19) | |
279 | #define OHCI_PORT_PRSC (1<<20) | |
280 | #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ | |
281 | |OHCI_PORT_OCIC|OHCI_PORT_PRSC) | |
282 | ||
283 | #define OHCI_TD_DIR_SETUP 0x0 | |
284 | #define OHCI_TD_DIR_OUT 0x1 | |
285 | #define OHCI_TD_DIR_IN 0x2 | |
286 | #define OHCI_TD_DIR_RESERVED 0x3 | |
287 | ||
288 | #define OHCI_CC_NOERROR 0x0 | |
289 | #define OHCI_CC_CRC 0x1 | |
290 | #define OHCI_CC_BITSTUFFING 0x2 | |
291 | #define OHCI_CC_DATATOGGLEMISMATCH 0x3 | |
292 | #define OHCI_CC_STALL 0x4 | |
293 | #define OHCI_CC_DEVICENOTRESPONDING 0x5 | |
294 | #define OHCI_CC_PIDCHECKFAILURE 0x6 | |
295 | #define OHCI_CC_UNDEXPETEDPID 0x7 | |
296 | #define OHCI_CC_DATAOVERRUN 0x8 | |
297 | #define OHCI_CC_DATAUNDERRUN 0x9 | |
298 | #define OHCI_CC_BUFFEROVERRUN 0xc | |
299 | #define OHCI_CC_BUFFERUNDERRUN 0xd | |
300 | ||
e24ad6f1 PB |
301 | #define OHCI_HRESET_FSBIR (1 << 0) |
302 | ||
cf66ee8e AK |
303 | static void ohci_die(OHCIState *ohci); |
304 | ||
61064870 PB |
305 | /* Update IRQ levels */ |
306 | static inline void ohci_intr_update(OHCIState *ohci) | |
307 | { | |
308 | int level = 0; | |
309 | ||
310 | if ((ohci->intr & OHCI_INTR_MIE) && | |
311 | (ohci->intr_status & ohci->intr)) | |
312 | level = 1; | |
313 | ||
d537cf6c | 314 | qemu_set_irq(ohci->irq, level); |
61064870 PB |
315 | } |
316 | ||
317 | /* Set an interrupt */ | |
318 | static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) | |
319 | { | |
320 | ohci->intr_status |= intr; | |
321 | ohci_intr_update(ohci); | |
322 | } | |
323 | ||
324 | /* Attach or detach a device on a root hub port. */ | |
618c169b | 325 | static void ohci_attach(USBPort *port1) |
0d92ed30 PB |
326 | { |
327 | OHCIState *s = port1->opaque; | |
328 | OHCIPort *port = &s->rhport[port1->index]; | |
3dc345d5 | 329 | uint32_t old_state = port->ctrl; |
0d92ed30 | 330 | |
618c169b GH |
331 | /* set connect status */ |
332 | port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; | |
333 | ||
334 | /* update speed */ | |
335 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
336 | port->ctrl |= OHCI_PORT_LSDA; | |
0d92ed30 | 337 | } else { |
618c169b GH |
338 | port->ctrl &= ~OHCI_PORT_LSDA; |
339 | } | |
340 | ||
341 | /* notify of remote-wakeup */ | |
342 | if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { | |
343 | ohci_set_interrupt(s, OHCI_INTR_RD); | |
344 | } | |
345 | ||
dc1f5988 | 346 | trace_usb_ohci_port_attach(port1->index); |
3dc345d5 GH |
347 | |
348 | if (old_state != port->ctrl) { | |
349 | ohci_set_interrupt(s, OHCI_INTR_RHSC); | |
350 | } | |
618c169b GH |
351 | } |
352 | ||
353 | static void ohci_detach(USBPort *port1) | |
354 | { | |
355 | OHCIState *s = port1->opaque; | |
356 | OHCIPort *port = &s->rhport[port1->index]; | |
357 | uint32_t old_state = port->ctrl; | |
358 | ||
4706ab6c HG |
359 | ohci_async_cancel_device(s, port1->dev); |
360 | ||
618c169b GH |
361 | /* set connect status */ |
362 | if (port->ctrl & OHCI_PORT_CCS) { | |
363 | port->ctrl &= ~OHCI_PORT_CCS; | |
364 | port->ctrl |= OHCI_PORT_CSC; | |
365 | } | |
366 | /* disable port */ | |
367 | if (port->ctrl & OHCI_PORT_PES) { | |
368 | port->ctrl &= ~OHCI_PORT_PES; | |
369 | port->ctrl |= OHCI_PORT_PESC; | |
0d92ed30 | 370 | } |
dc1f5988 | 371 | trace_usb_ohci_port_detach(port1->index); |
61064870 | 372 | |
3dc345d5 | 373 | if (old_state != port->ctrl) { |
61064870 | 374 | ohci_set_interrupt(s, OHCI_INTR_RHSC); |
3dc345d5 | 375 | } |
0d92ed30 PB |
376 | } |
377 | ||
d47e59b8 | 378 | static void ohci_wakeup(USBPort *port1) |
9bba1eb1 | 379 | { |
d47e59b8 HG |
380 | OHCIState *s = port1->opaque; |
381 | OHCIPort *port = &s->rhport[port1->index]; | |
f3dc0051 | 382 | uint32_t intr = 0; |
9bba1eb1 | 383 | if (port->ctrl & OHCI_PORT_PSS) { |
dc1f5988 | 384 | trace_usb_ohci_port_wakeup(port1->index); |
9bba1eb1 PM |
385 | port->ctrl |= OHCI_PORT_PSSC; |
386 | port->ctrl &= ~OHCI_PORT_PSS; | |
f3dc0051 | 387 | intr = OHCI_INTR_RHSC; |
9bba1eb1 | 388 | } |
f3dc0051 PM |
389 | /* Note that the controller can be suspended even if this port is not */ |
390 | if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { | |
dc1f5988 | 391 | trace_usb_ohci_remote_wakeup(s->name); |
f3dc0051 PM |
392 | /* This is the one state transition the controller can do by itself */ |
393 | s->ctl &= ~OHCI_CTL_HCFS; | |
394 | s->ctl |= OHCI_USB_RESUME; | |
395 | /* In suspend mode only ResumeDetected is possible, not RHSC: | |
396 | * see the OHCI spec 5.1.2.3. | |
397 | */ | |
398 | intr = OHCI_INTR_RD; | |
399 | } | |
400 | ohci_set_interrupt(s, intr); | |
9bba1eb1 PM |
401 | } |
402 | ||
4706ab6c HG |
403 | static void ohci_child_detach(USBPort *port1, USBDevice *child) |
404 | { | |
405 | OHCIState *s = port1->opaque; | |
406 | ||
407 | ohci_async_cancel_device(s, child); | |
408 | } | |
409 | ||
993048bb GH |
410 | static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) |
411 | { | |
412 | USBDevice *dev; | |
413 | int i; | |
414 | ||
415 | for (i = 0; i < ohci->num_ports; i++) { | |
416 | if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { | |
417 | continue; | |
418 | } | |
419 | dev = usb_find_device(&ohci->rhport[i].port, addr); | |
420 | if (dev != NULL) { | |
421 | return dev; | |
422 | } | |
423 | } | |
424 | return NULL; | |
425 | } | |
426 | ||
f79738b0 HG |
427 | static void ohci_stop_endpoints(OHCIState *ohci) |
428 | { | |
429 | USBDevice *dev; | |
430 | int i, j; | |
431 | ||
432 | for (i = 0; i < ohci->num_ports; i++) { | |
433 | dev = ohci->rhport[i].port.dev; | |
434 | if (dev && dev->attached) { | |
435 | usb_device_ep_stopped(dev, &dev->ep_ctl); | |
436 | for (j = 0; j < USB_MAX_ENDPOINTS; j++) { | |
437 | usb_device_ep_stopped(dev, &dev->ep_in[j]); | |
438 | usb_device_ep_stopped(dev, &dev->ep_out[j]); | |
439 | } | |
440 | } | |
441 | } | |
442 | } | |
443 | ||
84d04e21 | 444 | static void ohci_roothub_reset(OHCIState *ohci) |
0d92ed30 PB |
445 | { |
446 | OHCIPort *port; | |
447 | int i; | |
448 | ||
73221b12 | 449 | ohci_bus_stop(ohci); |
84d04e21 HP |
450 | ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
451 | ohci->rhdesc_b = 0x0; /* Impl. specific */ | |
452 | ohci->rhstatus = 0; | |
453 | ||
454 | for (i = 0; i < ohci->num_ports; i++) { | |
455 | port = &ohci->rhport[i]; | |
456 | port->ctrl = 0; | |
457 | if (port->port.dev && port->port.dev->attached) { | |
458 | usb_port_reset(&port->port); | |
459 | } | |
460 | } | |
461 | if (ohci->async_td) { | |
462 | usb_cancel_packet(&ohci->usb_packet); | |
463 | ohci->async_td = 0; | |
464 | } | |
465 | ohci_stop_endpoints(ohci); | |
466 | } | |
467 | ||
468 | /* Reset the controller */ | |
469 | static void ohci_soft_reset(OHCIState *ohci) | |
470 | { | |
471 | trace_usb_ohci_reset(ohci->name); | |
472 | ||
473 | ohci_bus_stop(ohci); | |
474 | ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; | |
4d611c9a | 475 | ohci->old_ctl = 0; |
0d92ed30 PB |
476 | ohci->status = 0; |
477 | ohci->intr_status = 0; | |
478 | ohci->intr = OHCI_INTR_MIE; | |
479 | ||
480 | ohci->hcca = 0; | |
481 | ohci->ctrl_head = ohci->ctrl_cur = 0; | |
482 | ohci->bulk_head = ohci->bulk_cur = 0; | |
483 | ohci->per_cur = 0; | |
484 | ohci->done = 0; | |
485 | ohci->done_count = 7; | |
486 | ||
487 | /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? | |
488 | * I took the value linux sets ... | |
489 | */ | |
490 | ohci->fsmps = 0x2778; | |
491 | ohci->fi = 0x2edf; | |
492 | ohci->fit = 0; | |
493 | ohci->frt = 0; | |
494 | ohci->frame_number = 0; | |
495 | ohci->pstart = 0; | |
496 | ohci->lst = OHCI_LS_THRESH; | |
84d04e21 | 497 | } |
0d92ed30 | 498 | |
84d04e21 HP |
499 | static void ohci_hard_reset(OHCIState *ohci) |
500 | { | |
501 | ohci_soft_reset(ohci); | |
502 | ohci->ctl = 0; | |
503 | ohci_roothub_reset(ohci); | |
0d92ed30 PB |
504 | } |
505 | ||
0d92ed30 | 506 | /* Get an array of dwords from main memory */ |
ac611340 | 507 | static inline int get_dwords(OHCIState *ohci, |
9ac6a217 | 508 | dma_addr_t addr, uint32_t *buf, int num) |
0d92ed30 PB |
509 | { |
510 | int i; | |
511 | ||
ac611340 AJ |
512 | addr += ohci->localmem_base; |
513 | ||
0d92ed30 | 514 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
cf66ee8e AK |
515 | if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { |
516 | return -1; | |
517 | } | |
0d92ed30 PB |
518 | *buf = le32_to_cpu(*buf); |
519 | } | |
520 | ||
cf66ee8e | 521 | return 0; |
0d92ed30 PB |
522 | } |
523 | ||
524 | /* Put an array of dwords in to main memory */ | |
ac611340 | 525 | static inline int put_dwords(OHCIState *ohci, |
9ac6a217 | 526 | dma_addr_t addr, uint32_t *buf, int num) |
0d92ed30 PB |
527 | { |
528 | int i; | |
529 | ||
ac611340 AJ |
530 | addr += ohci->localmem_base; |
531 | ||
0d92ed30 PB |
532 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
533 | uint32_t tmp = cpu_to_le32(*buf); | |
cf66ee8e AK |
534 | if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { |
535 | return -1; | |
536 | } | |
0d92ed30 PB |
537 | } |
538 | ||
cf66ee8e | 539 | return 0; |
0d92ed30 PB |
540 | } |
541 | ||
7bfe5777 | 542 | /* Get an array of words from main memory */ |
ac611340 | 543 | static inline int get_words(OHCIState *ohci, |
9ac6a217 | 544 | dma_addr_t addr, uint16_t *buf, int num) |
7bfe5777 AZ |
545 | { |
546 | int i; | |
547 | ||
ac611340 AJ |
548 | addr += ohci->localmem_base; |
549 | ||
7bfe5777 | 550 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
cf66ee8e AK |
551 | if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { |
552 | return -1; | |
553 | } | |
7bfe5777 AZ |
554 | *buf = le16_to_cpu(*buf); |
555 | } | |
556 | ||
cf66ee8e | 557 | return 0; |
7bfe5777 AZ |
558 | } |
559 | ||
560 | /* Put an array of words in to main memory */ | |
ac611340 | 561 | static inline int put_words(OHCIState *ohci, |
9ac6a217 | 562 | dma_addr_t addr, uint16_t *buf, int num) |
7bfe5777 AZ |
563 | { |
564 | int i; | |
565 | ||
ac611340 AJ |
566 | addr += ohci->localmem_base; |
567 | ||
7bfe5777 AZ |
568 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
569 | uint16_t tmp = cpu_to_le16(*buf); | |
cf66ee8e AK |
570 | if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { |
571 | return -1; | |
572 | } | |
7bfe5777 AZ |
573 | } |
574 | ||
cf66ee8e | 575 | return 0; |
7bfe5777 AZ |
576 | } |
577 | ||
ac611340 | 578 | static inline int ohci_read_ed(OHCIState *ohci, |
9ac6a217 | 579 | dma_addr_t addr, struct ohci_ed *ed) |
0d92ed30 | 580 | { |
ac611340 | 581 | return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
0d92ed30 PB |
582 | } |
583 | ||
ac611340 | 584 | static inline int ohci_read_td(OHCIState *ohci, |
9ac6a217 | 585 | dma_addr_t addr, struct ohci_td *td) |
0d92ed30 | 586 | { |
ac611340 | 587 | return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
0d92ed30 PB |
588 | } |
589 | ||
ac611340 | 590 | static inline int ohci_read_iso_td(OHCIState *ohci, |
9ac6a217 | 591 | dma_addr_t addr, struct ohci_iso_td *td) |
7bfe5777 | 592 | { |
cf66ee8e AK |
593 | return get_dwords(ohci, addr, (uint32_t *)td, 4) || |
594 | get_words(ohci, addr + 16, td->offset, 8); | |
7bfe5777 AZ |
595 | } |
596 | ||
ac611340 | 597 | static inline int ohci_read_hcca(OHCIState *ohci, |
9ac6a217 | 598 | dma_addr_t addr, struct ohci_hcca *hcca) |
0d92ed30 | 599 | { |
cf66ee8e AK |
600 | return dma_memory_read(ohci->as, addr + ohci->localmem_base, |
601 | hcca, sizeof(*hcca)); | |
0d92ed30 PB |
602 | } |
603 | ||
ac611340 | 604 | static inline int ohci_put_ed(OHCIState *ohci, |
9ac6a217 | 605 | dma_addr_t addr, struct ohci_ed *ed) |
0d92ed30 | 606 | { |
86e18cae WY |
607 | /* ed->tail is under control of the HCD. |
608 | * Since just ed->head is changed by HC, just write back this | |
609 | */ | |
610 | ||
611 | return put_dwords(ohci, addr + ED_WBACK_OFFSET, | |
612 | (uint32_t *)((char *)ed + ED_WBACK_OFFSET), | |
613 | ED_WBACK_SIZE >> 2); | |
0d92ed30 PB |
614 | } |
615 | ||
ac611340 | 616 | static inline int ohci_put_td(OHCIState *ohci, |
9ac6a217 | 617 | dma_addr_t addr, struct ohci_td *td) |
7bfe5777 | 618 | { |
ac611340 AJ |
619 | return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
620 | } | |
621 | ||
622 | static inline int ohci_put_iso_td(OHCIState *ohci, | |
9ac6a217 | 623 | dma_addr_t addr, struct ohci_iso_td *td) |
ac611340 | 624 | { |
cae7f29c JU |
625 | return put_dwords(ohci, addr, (uint32_t *)td, 4) || |
626 | put_words(ohci, addr + 16, td->offset, 8); | |
ac611340 AJ |
627 | } |
628 | ||
629 | static inline int ohci_put_hcca(OHCIState *ohci, | |
9ac6a217 | 630 | dma_addr_t addr, struct ohci_hcca *hcca) |
ac611340 | 631 | { |
cf66ee8e AK |
632 | return dma_memory_write(ohci->as, |
633 | addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, | |
634 | (char *)hcca + HCCA_WRITEBACK_OFFSET, | |
635 | HCCA_WRITEBACK_SIZE); | |
7bfe5777 AZ |
636 | } |
637 | ||
0d92ed30 | 638 | /* Read/Write the contents of a TD from/to main memory. */ |
cf66ee8e AK |
639 | static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, |
640 | uint8_t *buf, int len, DMADirection dir) | |
0d92ed30 | 641 | { |
9ac6a217 | 642 | dma_addr_t ptr, n; |
0d92ed30 PB |
643 | |
644 | ptr = td->cbp; | |
645 | n = 0x1000 - (ptr & 0xfff); | |
646 | if (n > len) | |
647 | n = len; | |
cf66ee8e AK |
648 | |
649 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { | |
650 | return -1; | |
651 | } | |
652 | if (n == len) { | |
653 | return 0; | |
654 | } | |
0d92ed30 | 655 | ptr = td->be & ~0xfffu; |
e6f3e5e0 | 656 | buf += n; |
cf66ee8e AK |
657 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, |
658 | len - n, dir)) { | |
659 | return -1; | |
660 | } | |
661 | return 0; | |
0d92ed30 PB |
662 | } |
663 | ||
7bfe5777 | 664 | /* Read/Write the contents of an ISO TD from/to main memory. */ |
cf66ee8e AK |
665 | static int ohci_copy_iso_td(OHCIState *ohci, |
666 | uint32_t start_addr, uint32_t end_addr, | |
667 | uint8_t *buf, int len, DMADirection dir) | |
7bfe5777 | 668 | { |
9ac6a217 | 669 | dma_addr_t ptr, n; |
4d611c9a | 670 | |
7bfe5777 AZ |
671 | ptr = start_addr; |
672 | n = 0x1000 - (ptr & 0xfff); | |
673 | if (n > len) | |
674 | n = len; | |
cf66ee8e AK |
675 | |
676 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { | |
677 | return -1; | |
678 | } | |
679 | if (n == len) { | |
680 | return 0; | |
681 | } | |
7bfe5777 AZ |
682 | ptr = end_addr & ~0xfffu; |
683 | buf += n; | |
cf66ee8e AK |
684 | if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, |
685 | len - n, dir)) { | |
686 | return -1; | |
687 | } | |
688 | return 0; | |
7bfe5777 AZ |
689 | } |
690 | ||
691 | static void ohci_process_lists(OHCIState *ohci, int completion); | |
692 | ||
d47e59b8 | 693 | static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) |
4d611c9a | 694 | { |
9066df13 | 695 | OHCIState *ohci = container_of(packet, OHCIState, usb_packet); |
dc1f5988 AK |
696 | |
697 | trace_usb_ohci_async_complete(); | |
69e25d26 | 698 | ohci->async_complete = true; |
7bfe5777 AZ |
699 | ohci_process_lists(ohci, 1); |
700 | } | |
701 | ||
702 | #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) | |
703 | ||
704 | static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, | |
705 | int completion) | |
706 | { | |
707 | int dir; | |
708 | size_t len = 0; | |
7ccfb2eb | 709 | const char *str = NULL; |
7bfe5777 AZ |
710 | int pid; |
711 | int ret; | |
712 | int i; | |
713 | USBDevice *dev; | |
079d0b7f | 714 | USBEndpoint *ep; |
7bfe5777 AZ |
715 | struct ohci_iso_td iso_td; |
716 | uint32_t addr; | |
717 | uint16_t starting_frame; | |
718 | int16_t relative_frame_number; | |
719 | int frame_count; | |
720 | uint32_t start_offset, next_offset, end_offset = 0; | |
721 | uint32_t start_addr, end_addr; | |
722 | ||
723 | addr = ed->head & OHCI_DPTR_MASK; | |
724 | ||
cf66ee8e | 725 | if (ohci_read_iso_td(ohci, addr, &iso_td)) { |
dc1f5988 | 726 | trace_usb_ohci_iso_td_read_failed(addr); |
cf66ee8e | 727 | ohci_die(ohci); |
7bfe5777 AZ |
728 | return 0; |
729 | } | |
730 | ||
731 | starting_frame = OHCI_BM(iso_td.flags, TD_SF); | |
732 | frame_count = OHCI_BM(iso_td.flags, TD_FC); | |
733 | relative_frame_number = USUB(ohci->frame_number, starting_frame); | |
734 | ||
dc1f5988 | 735 | trace_usb_ohci_iso_td_head( |
7bfe5777 AZ |
736 | ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, |
737 | iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, | |
3af8f177 | 738 | ohci->frame_number, starting_frame, |
bc0d104c | 739 | frame_count, relative_frame_number); |
3af8f177 AK |
740 | trace_usb_ohci_iso_td_head_offset( |
741 | iso_td.offset[0], iso_td.offset[1], | |
742 | iso_td.offset[2], iso_td.offset[3], | |
743 | iso_td.offset[4], iso_td.offset[5], | |
744 | iso_td.offset[6], iso_td.offset[7]); | |
7bfe5777 AZ |
745 | |
746 | if (relative_frame_number < 0) { | |
dc1f5988 | 747 | trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); |
7bfe5777 AZ |
748 | return 1; |
749 | } else if (relative_frame_number > frame_count) { | |
750 | /* ISO TD expired - retire the TD to the Done Queue and continue with | |
751 | the next ISO TD of the same ED */ | |
dc1f5988 AK |
752 | trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, |
753 | frame_count); | |
7bfe5777 AZ |
754 | OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
755 | ed->head &= ~OHCI_DPTR_MASK; | |
756 | ed->head |= (iso_td.next & OHCI_DPTR_MASK); | |
757 | iso_td.next = ohci->done; | |
758 | ohci->done = addr; | |
759 | i = OHCI_BM(iso_td.flags, TD_DI); | |
760 | if (i < ohci->done_count) | |
761 | ohci->done_count = i; | |
cf66ee8e AK |
762 | if (ohci_put_iso_td(ohci, addr, &iso_td)) { |
763 | ohci_die(ohci); | |
764 | return 1; | |
765 | } | |
7bfe5777 AZ |
766 | return 0; |
767 | } | |
768 | ||
769 | dir = OHCI_BM(ed->flags, ED_D); | |
770 | switch (dir) { | |
771 | case OHCI_TD_DIR_IN: | |
772 | str = "in"; | |
773 | pid = USB_TOKEN_IN; | |
774 | break; | |
775 | case OHCI_TD_DIR_OUT: | |
776 | str = "out"; | |
777 | pid = USB_TOKEN_OUT; | |
778 | break; | |
779 | case OHCI_TD_DIR_SETUP: | |
780 | str = "setup"; | |
781 | pid = USB_TOKEN_SETUP; | |
782 | break; | |
783 | default: | |
dc1f5988 | 784 | trace_usb_ohci_iso_td_bad_direction(dir); |
7bfe5777 AZ |
785 | return 1; |
786 | } | |
787 | ||
788 | if (!iso_td.bp || !iso_td.be) { | |
dc1f5988 | 789 | trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); |
7bfe5777 AZ |
790 | return 1; |
791 | } | |
792 | ||
793 | start_offset = iso_td.offset[relative_frame_number]; | |
794 | next_offset = iso_td.offset[relative_frame_number + 1]; | |
795 | ||
796 | if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || | |
797 | ((relative_frame_number < frame_count) && | |
798 | !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { | |
dc1f5988 | 799 | trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); |
7bfe5777 AZ |
800 | return 1; |
801 | } | |
802 | ||
803 | if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { | |
dc1f5988 | 804 | trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); |
7bfe5777 AZ |
805 | return 1; |
806 | } | |
807 | ||
808 | if ((start_offset & 0x1000) == 0) { | |
809 | start_addr = (iso_td.bp & OHCI_PAGE_MASK) | | |
810 | (start_offset & OHCI_OFFSET_MASK); | |
811 | } else { | |
812 | start_addr = (iso_td.be & OHCI_PAGE_MASK) | | |
813 | (start_offset & OHCI_OFFSET_MASK); | |
814 | } | |
815 | ||
816 | if (relative_frame_number < frame_count) { | |
817 | end_offset = next_offset - 1; | |
818 | if ((end_offset & 0x1000) == 0) { | |
819 | end_addr = (iso_td.bp & OHCI_PAGE_MASK) | | |
820 | (end_offset & OHCI_OFFSET_MASK); | |
821 | } else { | |
822 | end_addr = (iso_td.be & OHCI_PAGE_MASK) | | |
823 | (end_offset & OHCI_OFFSET_MASK); | |
824 | } | |
825 | } else { | |
826 | /* Last packet in the ISO TD */ | |
827 | end_addr = iso_td.be; | |
828 | } | |
829 | ||
830 | if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { | |
831 | len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 | |
832 | - (start_addr & OHCI_OFFSET_MASK); | |
833 | } else { | |
834 | len = end_addr - start_addr + 1; | |
835 | } | |
836 | ||
837 | if (len && dir != OHCI_TD_DIR_IN) { | |
cf66ee8e AK |
838 | if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, |
839 | DMA_DIRECTION_TO_DEVICE)) { | |
840 | ohci_die(ohci); | |
841 | return 1; | |
842 | } | |
7bfe5777 AZ |
843 | } |
844 | ||
9a77a0f5 | 845 | if (!completion) { |
a6fb2ddb HG |
846 | bool int_req = relative_frame_number == frame_count && |
847 | OHCI_BM(iso_td.flags, TD_DI) == 0; | |
079d0b7f GH |
848 | dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); |
849 | ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); | |
8550a02d | 850 | usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req); |
993048bb | 851 | usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); |
9a77a0f5 HG |
852 | usb_handle_packet(dev, &ohci->usb_packet); |
853 | if (ohci->usb_packet.status == USB_RET_ASYNC) { | |
36dfe324 | 854 | usb_device_flush_ep_queue(dev, ep); |
7bfe5777 AZ |
855 | return 1; |
856 | } | |
857 | } | |
9a77a0f5 HG |
858 | if (ohci->usb_packet.status == USB_RET_SUCCESS) { |
859 | ret = ohci->usb_packet.actual_length; | |
860 | } else { | |
861 | ret = ohci->usb_packet.status; | |
862 | } | |
7bfe5777 | 863 | |
dc1f5988 AK |
864 | trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, |
865 | str, len, ret); | |
7bfe5777 AZ |
866 | |
867 | /* Writeback */ | |
868 | if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { | |
869 | /* IN transfer succeeded */ | |
cf66ee8e AK |
870 | if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, |
871 | DMA_DIRECTION_FROM_DEVICE)) { | |
872 | ohci_die(ohci); | |
873 | return 1; | |
874 | } | |
7bfe5777 AZ |
875 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
876 | OHCI_CC_NOERROR); | |
877 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); | |
878 | } else if (dir == OHCI_TD_DIR_OUT && ret == len) { | |
879 | /* OUT transfer succeeded */ | |
880 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
881 | OHCI_CC_NOERROR); | |
882 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); | |
883 | } else { | |
87283515 | 884 | if (ret > (ssize_t) len) { |
dc1f5988 | 885 | trace_usb_ohci_iso_td_data_overrun(ret, len); |
7bfe5777 AZ |
886 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
887 | OHCI_CC_DATAOVERRUN); | |
888 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
889 | len); | |
890 | } else if (ret >= 0) { | |
dc1f5988 | 891 | trace_usb_ohci_iso_td_data_underrun(ret); |
7bfe5777 AZ |
892 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
893 | OHCI_CC_DATAUNDERRUN); | |
894 | } else { | |
895 | switch (ret) { | |
d61000a8 | 896 | case USB_RET_IOERROR: |
7bfe5777 AZ |
897 | case USB_RET_NODEV: |
898 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
899 | OHCI_CC_DEVICENOTRESPONDING); | |
900 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
901 | 0); | |
902 | break; | |
903 | case USB_RET_NAK: | |
904 | case USB_RET_STALL: | |
dc1f5988 | 905 | trace_usb_ohci_iso_td_nak(ret); |
7bfe5777 AZ |
906 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
907 | OHCI_CC_STALL); | |
908 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
909 | 0); | |
910 | break; | |
911 | default: | |
dc1f5988 | 912 | trace_usb_ohci_iso_td_bad_response(ret); |
7bfe5777 AZ |
913 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
914 | OHCI_CC_UNDEXPETEDPID); | |
915 | break; | |
916 | } | |
917 | } | |
918 | } | |
919 | ||
920 | if (relative_frame_number == frame_count) { | |
921 | /* Last data packet of ISO TD - retire the TD to the Done Queue */ | |
922 | OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); | |
923 | ed->head &= ~OHCI_DPTR_MASK; | |
924 | ed->head |= (iso_td.next & OHCI_DPTR_MASK); | |
925 | iso_td.next = ohci->done; | |
926 | ohci->done = addr; | |
927 | i = OHCI_BM(iso_td.flags, TD_DI); | |
928 | if (i < ohci->done_count) | |
929 | ohci->done_count = i; | |
930 | } | |
cf66ee8e AK |
931 | if (ohci_put_iso_td(ohci, addr, &iso_td)) { |
932 | ohci_die(ohci); | |
933 | } | |
7bfe5777 | 934 | return 1; |
4d611c9a PB |
935 | } |
936 | ||
dc1f5988 AK |
937 | #ifdef trace_event_get_state |
938 | static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) | |
939 | { | |
940 | bool print16 = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_SHORT); | |
941 | bool printall = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_FULL); | |
942 | const int width = 16; | |
943 | int i; | |
944 | char tmp[3 * width + 1]; | |
945 | char *p = tmp; | |
946 | ||
947 | if (!printall && !print16) { | |
948 | return; | |
949 | } | |
950 | ||
951 | for (i = 0; ; i++) { | |
952 | if (i && (!(i % width) || (i == len))) { | |
953 | if (!printall) { | |
954 | trace_usb_ohci_td_pkt_short(msg, tmp); | |
955 | break; | |
956 | } | |
957 | trace_usb_ohci_td_pkt_full(msg, tmp); | |
958 | p = tmp; | |
959 | *p = 0; | |
960 | } | |
961 | if (i == len) { | |
962 | break; | |
963 | } | |
964 | ||
965 | p += sprintf(p, " %.2x", buf[i]); | |
966 | } | |
967 | } | |
968 | #else | |
969 | static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) | |
970 | { | |
971 | } | |
972 | #endif | |
973 | ||
0d92ed30 PB |
974 | /* Service a transport descriptor. |
975 | Returns nonzero to terminate processing of this endpoint. */ | |
976 | ||
977 | static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) | |
978 | { | |
979 | int dir; | |
905fb034 | 980 | size_t len = 0, pktlen = 0; |
7ccfb2eb | 981 | const char *str = NULL; |
0d92ed30 PB |
982 | int pid; |
983 | int ret; | |
984 | int i; | |
985 | USBDevice *dev; | |
079d0b7f | 986 | USBEndpoint *ep; |
0d92ed30 PB |
987 | struct ohci_td td; |
988 | uint32_t addr; | |
989 | int flag_r; | |
4d611c9a | 990 | int completion; |
0d92ed30 PB |
991 | |
992 | addr = ed->head & OHCI_DPTR_MASK; | |
4d611c9a PB |
993 | /* See if this TD has already been submitted to the device. */ |
994 | completion = (addr == ohci->async_td); | |
995 | if (completion && !ohci->async_complete) { | |
dc1f5988 | 996 | trace_usb_ohci_td_skip_async(); |
4d611c9a PB |
997 | return 1; |
998 | } | |
cf66ee8e | 999 | if (ohci_read_td(ohci, addr, &td)) { |
dc1f5988 | 1000 | trace_usb_ohci_td_read_error(addr); |
cf66ee8e | 1001 | ohci_die(ohci); |
0d92ed30 PB |
1002 | return 0; |
1003 | } | |
1004 | ||
1005 | dir = OHCI_BM(ed->flags, ED_D); | |
1006 | switch (dir) { | |
1007 | case OHCI_TD_DIR_OUT: | |
1008 | case OHCI_TD_DIR_IN: | |
1009 | /* Same value. */ | |
1010 | break; | |
1011 | default: | |
1012 | dir = OHCI_BM(td.flags, TD_DP); | |
1013 | break; | |
1014 | } | |
1015 | ||
1016 | switch (dir) { | |
1017 | case OHCI_TD_DIR_IN: | |
1018 | str = "in"; | |
1019 | pid = USB_TOKEN_IN; | |
1020 | break; | |
1021 | case OHCI_TD_DIR_OUT: | |
1022 | str = "out"; | |
1023 | pid = USB_TOKEN_OUT; | |
1024 | break; | |
1025 | case OHCI_TD_DIR_SETUP: | |
1026 | str = "setup"; | |
1027 | pid = USB_TOKEN_SETUP; | |
1028 | break; | |
1029 | default: | |
dc1f5988 | 1030 | trace_usb_ohci_td_bad_direction(dir); |
0d92ed30 PB |
1031 | return 1; |
1032 | } | |
1033 | if (td.cbp && td.be) { | |
e6f3e5e0 PB |
1034 | if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
1035 | len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); | |
1036 | } else { | |
1037 | len = (td.be - td.cbp) + 1; | |
1038 | } | |
1039 | ||
905fb034 PM |
1040 | pktlen = len; |
1041 | if (len && dir != OHCI_TD_DIR_IN) { | |
1042 | /* The endpoint may not allow us to transfer it all now */ | |
1043 | pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; | |
1044 | if (pktlen > len) { | |
1045 | pktlen = len; | |
1046 | } | |
1047 | if (!completion) { | |
cf66ee8e AK |
1048 | if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, |
1049 | DMA_DIRECTION_TO_DEVICE)) { | |
1050 | ohci_die(ohci); | |
1051 | } | |
905fb034 | 1052 | } |
0d92ed30 PB |
1053 | } |
1054 | } | |
1055 | ||
1056 | flag_r = (td.flags & OHCI_TD_R) != 0; | |
dc1f5988 AK |
1057 | trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, |
1058 | flag_r, td.cbp, td.be); | |
1059 | ohci_td_pkt("OUT", ohci->usb_buf, pktlen); | |
1060 | ||
4d611c9a | 1061 | if (completion) { |
4d611c9a | 1062 | ohci->async_td = 0; |
69e25d26 | 1063 | ohci->async_complete = false; |
4d611c9a | 1064 | } else { |
993048bb GH |
1065 | if (ohci->async_td) { |
1066 | /* ??? The hardware should allow one active packet per | |
1067 | endpoint. We only allow one active packet per controller. | |
1068 | This should be sufficient as long as devices respond in a | |
1069 | timely manner. | |
1070 | */ | |
dc1f5988 | 1071 | trace_usb_ohci_td_too_many_pending(); |
993048bb | 1072 | return 1; |
4d611c9a | 1073 | } |
079d0b7f GH |
1074 | dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); |
1075 | ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); | |
8550a02d | 1076 | usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, |
a6fb2ddb | 1077 | OHCI_BM(td.flags, TD_DI) == 0); |
993048bb | 1078 | usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); |
9a77a0f5 | 1079 | usb_handle_packet(dev, &ohci->usb_packet); |
dc1f5988 AK |
1080 | trace_usb_ohci_td_packet_status(ohci->usb_packet.status); |
1081 | ||
9a77a0f5 | 1082 | if (ohci->usb_packet.status == USB_RET_ASYNC) { |
36dfe324 | 1083 | usb_device_flush_ep_queue(dev, ep); |
4d611c9a PB |
1084 | ohci->async_td = addr; |
1085 | return 1; | |
1086 | } | |
1087 | } | |
9a77a0f5 HG |
1088 | if (ohci->usb_packet.status == USB_RET_SUCCESS) { |
1089 | ret = ohci->usb_packet.actual_length; | |
1090 | } else { | |
1091 | ret = ohci->usb_packet.status; | |
1092 | } | |
1093 | ||
0d92ed30 PB |
1094 | if (ret >= 0) { |
1095 | if (dir == OHCI_TD_DIR_IN) { | |
cf66ee8e AK |
1096 | if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, |
1097 | DMA_DIRECTION_FROM_DEVICE)) { | |
1098 | ohci_die(ohci); | |
1099 | } | |
dc1f5988 | 1100 | ohci_td_pkt("IN", ohci->usb_buf, pktlen); |
0d92ed30 | 1101 | } else { |
905fb034 | 1102 | ret = pktlen; |
0d92ed30 PB |
1103 | } |
1104 | } | |
1105 | ||
1106 | /* Writeback */ | |
905fb034 | 1107 | if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
0d92ed30 PB |
1108 | /* Transmission succeeded. */ |
1109 | if (ret == len) { | |
1110 | td.cbp = 0; | |
1111 | } else { | |
0d92ed30 | 1112 | if ((td.cbp & 0xfff) + ret > 0xfff) { |
fd891c93 AG |
1113 | td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); |
1114 | } else { | |
1115 | td.cbp += ret; | |
0d92ed30 PB |
1116 | } |
1117 | } | |
1118 | td.flags |= OHCI_TD_T1; | |
1119 | td.flags ^= OHCI_TD_T0; | |
1120 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); | |
1121 | OHCI_SET_BM(td.flags, TD_EC, 0); | |
1122 | ||
905fb034 PM |
1123 | if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { |
1124 | /* Partial packet transfer: TD not ready to retire yet */ | |
1125 | goto exit_no_retire; | |
1126 | } | |
1127 | ||
1128 | /* Setting ED_C is part of the TD retirement process */ | |
0d92ed30 PB |
1129 | ed->head &= ~OHCI_ED_C; |
1130 | if (td.flags & OHCI_TD_T0) | |
1131 | ed->head |= OHCI_ED_C; | |
1132 | } else { | |
1133 | if (ret >= 0) { | |
dc1f5988 | 1134 | trace_usb_ohci_td_underrun(); |
0d92ed30 PB |
1135 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
1136 | } else { | |
1137 | switch (ret) { | |
d61000a8 | 1138 | case USB_RET_IOERROR: |
0d92ed30 | 1139 | case USB_RET_NODEV: |
dc1f5988 | 1140 | trace_usb_ohci_td_dev_error(); |
0d92ed30 | 1141 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
4b351a0f | 1142 | break; |
0d92ed30 | 1143 | case USB_RET_NAK: |
dc1f5988 | 1144 | trace_usb_ohci_td_nak(); |
0d92ed30 PB |
1145 | return 1; |
1146 | case USB_RET_STALL: | |
dc1f5988 | 1147 | trace_usb_ohci_td_stall(); |
0d92ed30 PB |
1148 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
1149 | break; | |
1150 | case USB_RET_BABBLE: | |
dc1f5988 | 1151 | trace_usb_ohci_td_babble(); |
0d92ed30 PB |
1152 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
1153 | break; | |
1154 | default: | |
dc1f5988 | 1155 | trace_usb_ohci_td_bad_device_response(ret); |
0d92ed30 PB |
1156 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
1157 | OHCI_SET_BM(td.flags, TD_EC, 3); | |
1158 | break; | |
1159 | } | |
1160 | } | |
1161 | ed->head |= OHCI_ED_H; | |
1162 | } | |
1163 | ||
1164 | /* Retire this TD */ | |
1165 | ed->head &= ~OHCI_DPTR_MASK; | |
1166 | ed->head |= td.next & OHCI_DPTR_MASK; | |
1167 | td.next = ohci->done; | |
1168 | ohci->done = addr; | |
1169 | i = OHCI_BM(td.flags, TD_DI); | |
1170 | if (i < ohci->done_count) | |
1171 | ohci->done_count = i; | |
905fb034 | 1172 | exit_no_retire: |
cf66ee8e AK |
1173 | if (ohci_put_td(ohci, addr, &td)) { |
1174 | ohci_die(ohci); | |
1175 | return 1; | |
1176 | } | |
0d92ed30 PB |
1177 | return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; |
1178 | } | |
1179 | ||
1180 | /* Service an endpoint list. Returns nonzero if active TD were found. */ | |
7bfe5777 | 1181 | static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) |
0d92ed30 PB |
1182 | { |
1183 | struct ohci_ed ed; | |
1184 | uint32_t next_ed; | |
1185 | uint32_t cur; | |
1186 | int active; | |
1187 | ||
1188 | active = 0; | |
1189 | ||
1190 | if (head == 0) | |
1191 | return 0; | |
1192 | ||
1193 | for (cur = head; cur; cur = next_ed) { | |
cf66ee8e | 1194 | if (ohci_read_ed(ohci, cur, &ed)) { |
dc1f5988 | 1195 | trace_usb_ohci_ed_read_error(cur); |
cf66ee8e | 1196 | ohci_die(ohci); |
0d92ed30 PB |
1197 | return 0; |
1198 | } | |
1199 | ||
1200 | next_ed = ed.next & OHCI_DPTR_MASK; | |
1201 | ||
4d611c9a PB |
1202 | if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { |
1203 | uint32_t addr; | |
1204 | /* Cancel pending packets for ED that have been paused. */ | |
1205 | addr = ed.head & OHCI_DPTR_MASK; | |
1206 | if (ohci->async_td && addr == ohci->async_td) { | |
1207 | usb_cancel_packet(&ohci->usb_packet); | |
1208 | ohci->async_td = 0; | |
f79738b0 HG |
1209 | usb_device_ep_stopped(ohci->usb_packet.ep->dev, |
1210 | ohci->usb_packet.ep); | |
4d611c9a | 1211 | } |
0d92ed30 | 1212 | continue; |
4d611c9a | 1213 | } |
0d92ed30 | 1214 | |
0d92ed30 | 1215 | while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { |
3af8f177 AK |
1216 | trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0, |
1217 | (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, | |
1218 | ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); | |
1219 | trace_usb_ohci_ed_pkt_flags( | |
0d92ed30 PB |
1220 | OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
1221 | OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, | |
1222 | (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, | |
3af8f177 | 1223 | OHCI_BM(ed.flags, ED_MPS)); |
dc1f5988 | 1224 | |
0d92ed30 PB |
1225 | active = 1; |
1226 | ||
7bfe5777 AZ |
1227 | if ((ed.flags & OHCI_ED_F) == 0) { |
1228 | if (ohci_service_td(ohci, &ed)) | |
1229 | break; | |
1230 | } else { | |
1231 | /* Handle isochronous endpoints */ | |
1232 | if (ohci_service_iso_td(ohci, &ed, completion)) | |
1233 | break; | |
1234 | } | |
0d92ed30 PB |
1235 | } |
1236 | ||
cf66ee8e AK |
1237 | if (ohci_put_ed(ohci, cur, &ed)) { |
1238 | ohci_die(ohci); | |
1239 | return 0; | |
1240 | } | |
0d92ed30 PB |
1241 | } |
1242 | ||
1243 | return active; | |
1244 | } | |
1245 | ||
fd0a10cd LV |
1246 | /* set a timer for EOF */ |
1247 | static void ohci_eof_timer(OHCIState *ohci) | |
0d92ed30 | 1248 | { |
bc72ad67 AB |
1249 | ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
1250 | timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); | |
fd0a10cd LV |
1251 | } |
1252 | /* Set a timer for EOF and generate a SOF event */ | |
1253 | static void ohci_sof(OHCIState *ohci) | |
1254 | { | |
1255 | ohci_eof_timer(ohci); | |
0d92ed30 PB |
1256 | ohci_set_interrupt(ohci, OHCI_INTR_SF); |
1257 | } | |
1258 | ||
4d611c9a | 1259 | /* Process Control and Bulk lists. */ |
7bfe5777 | 1260 | static void ohci_process_lists(OHCIState *ohci, int completion) |
4d611c9a PB |
1261 | { |
1262 | if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { | |
6ad6135d | 1263 | if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { |
dc1f5988 | 1264 | trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); |
6ad6135d | 1265 | } |
7bfe5777 | 1266 | if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { |
4d611c9a PB |
1267 | ohci->ctrl_cur = 0; |
1268 | ohci->status &= ~OHCI_STATUS_CLF; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { | |
7bfe5777 | 1273 | if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { |
4d611c9a PB |
1274 | ohci->bulk_cur = 0; |
1275 | ohci->status &= ~OHCI_STATUS_BLF; | |
1276 | } | |
1277 | } | |
1278 | } | |
1279 | ||
0d92ed30 PB |
1280 | /* Do frame processing on frame boundary */ |
1281 | static void ohci_frame_boundary(void *opaque) | |
1282 | { | |
1283 | OHCIState *ohci = opaque; | |
1284 | struct ohci_hcca hcca; | |
1285 | ||
cf66ee8e | 1286 | if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { |
dc1f5988 | 1287 | trace_usb_ohci_hcca_read_error(ohci->hcca); |
cf66ee8e AK |
1288 | ohci_die(ohci); |
1289 | return; | |
1290 | } | |
0d92ed30 PB |
1291 | |
1292 | /* Process all the lists at the end of the frame */ | |
1293 | if (ohci->ctl & OHCI_CTL_PLE) { | |
1294 | int n; | |
1295 | ||
1296 | n = ohci->frame_number & 0x1f; | |
7bfe5777 | 1297 | ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); |
0d92ed30 | 1298 | } |
0d92ed30 | 1299 | |
4d611c9a | 1300 | /* Cancel all pending packets if either of the lists has been disabled. */ |
f79738b0 HG |
1301 | if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { |
1302 | if (ohci->async_td) { | |
1303 | usb_cancel_packet(&ohci->usb_packet); | |
1304 | ohci->async_td = 0; | |
1305 | } | |
1306 | ohci_stop_endpoints(ohci); | |
0d92ed30 | 1307 | } |
4d611c9a | 1308 | ohci->old_ctl = ohci->ctl; |
7bfe5777 | 1309 | ohci_process_lists(ohci, 0); |
0d92ed30 | 1310 | |
cf66ee8e AK |
1311 | /* Stop if UnrecoverableError happened or ohci_sof will crash */ |
1312 | if (ohci->intr_status & OHCI_INTR_UE) { | |
1313 | return; | |
1314 | } | |
1315 | ||
0d92ed30 PB |
1316 | /* Frame boundary, so do EOF stuf here */ |
1317 | ohci->frt = ohci->fit; | |
1318 | ||
1fa63e43 | 1319 | /* Increment frame number and take care of endianness. */ |
0d92ed30 | 1320 | ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
1fa63e43 | 1321 | hcca.frame = cpu_to_le16(ohci->frame_number); |
0d92ed30 PB |
1322 | |
1323 | if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { | |
1324 | if (!ohci->done) | |
1325 | abort(); | |
1326 | if (ohci->intr & ohci->intr_status) | |
1327 | ohci->done |= 1; | |
1328 | hcca.done = cpu_to_le32(ohci->done); | |
1329 | ohci->done = 0; | |
1330 | ohci->done_count = 7; | |
1331 | ohci_set_interrupt(ohci, OHCI_INTR_WD); | |
1332 | } | |
1333 | ||
1334 | if (ohci->done_count != 7 && ohci->done_count != 0) | |
1335 | ohci->done_count--; | |
1336 | ||
1337 | /* Do SOF stuff here */ | |
1338 | ohci_sof(ohci); | |
1339 | ||
1340 | /* Writeback HCCA */ | |
cf66ee8e AK |
1341 | if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { |
1342 | ohci_die(ohci); | |
1343 | } | |
0d92ed30 PB |
1344 | } |
1345 | ||
1346 | /* Start sending SOF tokens across the USB bus, lists are processed in | |
1347 | * next frame | |
1348 | */ | |
1349 | static int ohci_bus_start(OHCIState *ohci) | |
1350 | { | |
dc1f5988 | 1351 | trace_usb_ohci_start(ohci->name); |
0d92ed30 | 1352 | |
fd0a10cd LV |
1353 | /* Delay the first SOF event by one frame time as |
1354 | * linux driver is not ready to receive it and | |
1355 | * can meet some race conditions | |
1356 | */ | |
1357 | ||
1358 | ohci_eof_timer(ohci); | |
0d92ed30 PB |
1359 | |
1360 | return 1; | |
1361 | } | |
1362 | ||
1363 | /* Stop sending SOF tokens on the bus */ | |
1364 | static void ohci_bus_stop(OHCIState *ohci) | |
1365 | { | |
dc1f5988 | 1366 | trace_usb_ohci_stop(ohci->name); |
fa1298c2 | 1367 | timer_del(ohci->eof_timer); |
0d92ed30 PB |
1368 | } |
1369 | ||
1370 | /* Sets a flag in a port status register but only set it if the port is | |
1371 | * connected, if not set ConnectStatusChange flag. If flag is enabled | |
1372 | * return 1. | |
1373 | */ | |
1374 | static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) | |
1375 | { | |
1376 | int ret = 1; | |
1377 | ||
1378 | /* writing a 0 has no effect */ | |
1379 | if (val == 0) | |
1380 | return 0; | |
1381 | ||
1382 | /* If CurrentConnectStatus is cleared we set | |
1383 | * ConnectStatusChange | |
1384 | */ | |
1385 | if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { | |
1386 | ohci->rhport[i].ctrl |= OHCI_PORT_CSC; | |
1387 | if (ohci->rhstatus & OHCI_RHS_DRWE) { | |
1388 | /* TODO: CSC is a wakeup event */ | |
1389 | } | |
1390 | return 0; | |
1391 | } | |
1392 | ||
1393 | if (ohci->rhport[i].ctrl & val) | |
1394 | ret = 0; | |
1395 | ||
1396 | /* set the bit */ | |
1397 | ohci->rhport[i].ctrl |= val; | |
1398 | ||
1399 | return ret; | |
1400 | } | |
1401 | ||
1402 | /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ | |
1403 | static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) | |
1404 | { | |
1405 | val &= OHCI_FMI_FI; | |
1406 | ||
1407 | if (val != ohci->fi) { | |
dc1f5988 | 1408 | trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); |
0d92ed30 PB |
1409 | } |
1410 | ||
1411 | ohci->fi = val; | |
1412 | } | |
1413 | ||
1414 | static void ohci_port_power(OHCIState *ohci, int i, int p) | |
1415 | { | |
1416 | if (p) { | |
1417 | ohci->rhport[i].ctrl |= OHCI_PORT_PPS; | |
1418 | } else { | |
1419 | ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| | |
1420 | OHCI_PORT_CCS| | |
1421 | OHCI_PORT_PSS| | |
1422 | OHCI_PORT_PRS); | |
1423 | } | |
1424 | } | |
1425 | ||
1426 | /* Set HcControlRegister */ | |
1427 | static void ohci_set_ctl(OHCIState *ohci, uint32_t val) | |
1428 | { | |
1429 | uint32_t old_state; | |
1430 | uint32_t new_state; | |
1431 | ||
1432 | old_state = ohci->ctl & OHCI_CTL_HCFS; | |
1433 | ohci->ctl = val; | |
1434 | new_state = ohci->ctl & OHCI_CTL_HCFS; | |
1435 | ||
1436 | /* no state change */ | |
1437 | if (old_state == new_state) | |
1438 | return; | |
1439 | ||
dc1f5988 | 1440 | trace_usb_ohci_set_ctl(ohci->name, new_state); |
0d92ed30 PB |
1441 | switch (new_state) { |
1442 | case OHCI_USB_OPERATIONAL: | |
1443 | ohci_bus_start(ohci); | |
1444 | break; | |
1445 | case OHCI_USB_SUSPEND: | |
1446 | ohci_bus_stop(ohci); | |
087462c7 LV |
1447 | /* clear pending SF otherwise linux driver loops in ohci_irq() */ |
1448 | ohci->intr_status &= ~OHCI_INTR_SF; | |
1449 | ohci_intr_update(ohci); | |
0d92ed30 PB |
1450 | break; |
1451 | case OHCI_USB_RESUME: | |
dc1f5988 | 1452 | trace_usb_ohci_resume(ohci->name); |
0d92ed30 PB |
1453 | break; |
1454 | case OHCI_USB_RESET: | |
7d938fd1 | 1455 | ohci_roothub_reset(ohci); |
0d92ed30 PB |
1456 | break; |
1457 | } | |
1458 | } | |
1459 | ||
1460 | static uint32_t ohci_get_frame_remaining(OHCIState *ohci) | |
1461 | { | |
1462 | uint16_t fr; | |
1463 | int64_t tks; | |
1464 | ||
1465 | if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) | |
1466 | return (ohci->frt << 31); | |
1467 | ||
1468 | /* Being in USB operational state guarnatees sof_time was | |
1469 | * set already. | |
1470 | */ | |
bc72ad67 | 1471 | tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; |
0d92ed30 PB |
1472 | |
1473 | /* avoid muldiv if possible */ | |
1474 | if (tks >= usb_frame_time) | |
1475 | return (ohci->frt << 31); | |
1476 | ||
1477 | tks = muldiv64(1, tks, usb_bit_time); | |
1478 | fr = (uint16_t)(ohci->fi - tks); | |
1479 | ||
1480 | return (ohci->frt << 31) | fr; | |
1481 | } | |
1482 | ||
1483 | ||
1484 | /* Set root hub status */ | |
1485 | static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) | |
1486 | { | |
1487 | uint32_t old_state; | |
1488 | ||
1489 | old_state = ohci->rhstatus; | |
1490 | ||
1491 | /* write 1 to clear OCIC */ | |
1492 | if (val & OHCI_RHS_OCIC) | |
1493 | ohci->rhstatus &= ~OHCI_RHS_OCIC; | |
1494 | ||
1495 | if (val & OHCI_RHS_LPS) { | |
1496 | int i; | |
1497 | ||
1498 | for (i = 0; i < ohci->num_ports; i++) | |
1499 | ohci_port_power(ohci, i, 0); | |
dc1f5988 | 1500 | trace_usb_ohci_hub_power_down(); |
0d92ed30 PB |
1501 | } |
1502 | ||
1503 | if (val & OHCI_RHS_LPSC) { | |
1504 | int i; | |
1505 | ||
1506 | for (i = 0; i < ohci->num_ports; i++) | |
1507 | ohci_port_power(ohci, i, 1); | |
dc1f5988 | 1508 | trace_usb_ohci_hub_power_up(); |
0d92ed30 PB |
1509 | } |
1510 | ||
1511 | if (val & OHCI_RHS_DRWE) | |
1512 | ohci->rhstatus |= OHCI_RHS_DRWE; | |
1513 | ||
1514 | if (val & OHCI_RHS_CRWE) | |
1515 | ohci->rhstatus &= ~OHCI_RHS_DRWE; | |
1516 | ||
1517 | if (old_state != ohci->rhstatus) | |
1518 | ohci_set_interrupt(ohci, OHCI_INTR_RHSC); | |
1519 | } | |
1520 | ||
1521 | /* Set root hub port status */ | |
1522 | static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) | |
1523 | { | |
1524 | uint32_t old_state; | |
1525 | OHCIPort *port; | |
1526 | ||
1527 | port = &ohci->rhport[portnum]; | |
1528 | old_state = port->ctrl; | |
1529 | ||
1530 | /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ | |
1531 | if (val & OHCI_PORT_WTC) | |
1532 | port->ctrl &= ~(val & OHCI_PORT_WTC); | |
1533 | ||
1534 | if (val & OHCI_PORT_CCS) | |
1535 | port->ctrl &= ~OHCI_PORT_PES; | |
1536 | ||
1537 | ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); | |
1538 | ||
6ad6135d | 1539 | if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { |
dc1f5988 | 1540 | trace_usb_ohci_port_suspend(portnum); |
6ad6135d | 1541 | } |
0d92ed30 PB |
1542 | |
1543 | if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { | |
dc1f5988 | 1544 | trace_usb_ohci_port_reset(portnum); |
d28f4e2d | 1545 | usb_device_reset(port->port.dev); |
0d92ed30 PB |
1546 | port->ctrl &= ~OHCI_PORT_PRS; |
1547 | /* ??? Should this also set OHCI_PORT_PESC. */ | |
1548 | port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; | |
1549 | } | |
1550 | ||
1551 | /* Invert order here to ensure in ambiguous case, device is | |
1552 | * powered up... | |
1553 | */ | |
1554 | if (val & OHCI_PORT_LSDA) | |
1555 | ohci_port_power(ohci, portnum, 0); | |
1556 | if (val & OHCI_PORT_PPS) | |
1557 | ohci_port_power(ohci, portnum, 1); | |
1558 | ||
1559 | if (old_state != port->ctrl) | |
1560 | ohci_set_interrupt(ohci, OHCI_INTR_RHSC); | |
0d92ed30 PB |
1561 | } |
1562 | ||
6da48311 | 1563 | static uint64_t ohci_mem_read(void *opaque, |
a8170e5e | 1564 | hwaddr addr, |
6da48311 | 1565 | unsigned size) |
0d92ed30 | 1566 | { |
6da48311 | 1567 | OHCIState *ohci = opaque; |
65e1d81b | 1568 | uint32_t retval; |
0d92ed30 | 1569 | |
0d92ed30 PB |
1570 | /* Only aligned reads are allowed on OHCI */ |
1571 | if (addr & 3) { | |
dc1f5988 | 1572 | trace_usb_ohci_mem_read_unaligned(addr); |
0d92ed30 | 1573 | return 0xffffffff; |
65e1d81b | 1574 | } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
0d92ed30 | 1575 | /* HcRhPortStatus */ |
65e1d81b AJ |
1576 | retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1577 | } else { | |
1578 | switch (addr >> 2) { | |
1579 | case 0: /* HcRevision */ | |
1580 | retval = 0x10; | |
1581 | break; | |
1582 | ||
1583 | case 1: /* HcControl */ | |
1584 | retval = ohci->ctl; | |
1585 | break; | |
1586 | ||
1587 | case 2: /* HcCommandStatus */ | |
1588 | retval = ohci->status; | |
1589 | break; | |
1590 | ||
1591 | case 3: /* HcInterruptStatus */ | |
1592 | retval = ohci->intr_status; | |
1593 | break; | |
1594 | ||
1595 | case 4: /* HcInterruptEnable */ | |
1596 | case 5: /* HcInterruptDisable */ | |
1597 | retval = ohci->intr; | |
1598 | break; | |
1599 | ||
1600 | case 6: /* HcHCCA */ | |
1601 | retval = ohci->hcca; | |
1602 | break; | |
1603 | ||
1604 | case 7: /* HcPeriodCurrentED */ | |
1605 | retval = ohci->per_cur; | |
1606 | break; | |
1607 | ||
1608 | case 8: /* HcControlHeadED */ | |
1609 | retval = ohci->ctrl_head; | |
1610 | break; | |
1611 | ||
1612 | case 9: /* HcControlCurrentED */ | |
1613 | retval = ohci->ctrl_cur; | |
1614 | break; | |
1615 | ||
1616 | case 10: /* HcBulkHeadED */ | |
1617 | retval = ohci->bulk_head; | |
1618 | break; | |
1619 | ||
1620 | case 11: /* HcBulkCurrentED */ | |
1621 | retval = ohci->bulk_cur; | |
1622 | break; | |
1623 | ||
1624 | case 12: /* HcDoneHead */ | |
1625 | retval = ohci->done; | |
1626 | break; | |
1627 | ||
1628 | case 13: /* HcFmInterretval */ | |
1629 | retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); | |
1630 | break; | |
1631 | ||
1632 | case 14: /* HcFmRemaining */ | |
1633 | retval = ohci_get_frame_remaining(ohci); | |
1634 | break; | |
1635 | ||
1636 | case 15: /* HcFmNumber */ | |
1637 | retval = ohci->frame_number; | |
1638 | break; | |
1639 | ||
1640 | case 16: /* HcPeriodicStart */ | |
1641 | retval = ohci->pstart; | |
1642 | break; | |
1643 | ||
1644 | case 17: /* HcLSThreshold */ | |
1645 | retval = ohci->lst; | |
1646 | break; | |
1647 | ||
1648 | case 18: /* HcRhDescriptorA */ | |
1649 | retval = ohci->rhdesc_a; | |
1650 | break; | |
1651 | ||
1652 | case 19: /* HcRhDescriptorB */ | |
1653 | retval = ohci->rhdesc_b; | |
1654 | break; | |
1655 | ||
1656 | case 20: /* HcRhStatus */ | |
1657 | retval = ohci->rhstatus; | |
1658 | break; | |
1659 | ||
1660 | /* PXA27x specific registers */ | |
1661 | case 24: /* HcStatus */ | |
1662 | retval = ohci->hstatus & ohci->hmask; | |
1663 | break; | |
1664 | ||
1665 | case 25: /* HcHReset */ | |
1666 | retval = ohci->hreset; | |
1667 | break; | |
1668 | ||
1669 | case 26: /* HcHInterruptEnable */ | |
1670 | retval = ohci->hmask; | |
1671 | break; | |
1672 | ||
1673 | case 27: /* HcHInterruptTest */ | |
1674 | retval = ohci->htest; | |
1675 | break; | |
1676 | ||
1677 | default: | |
dc1f5988 | 1678 | trace_usb_ohci_mem_read_bad_offset(addr); |
65e1d81b AJ |
1679 | retval = 0xffffffff; |
1680 | } | |
0d92ed30 PB |
1681 | } |
1682 | ||
65e1d81b | 1683 | return retval; |
0d92ed30 PB |
1684 | } |
1685 | ||
6da48311 | 1686 | static void ohci_mem_write(void *opaque, |
a8170e5e | 1687 | hwaddr addr, |
6da48311 AK |
1688 | uint64_t val, |
1689 | unsigned size) | |
0d92ed30 | 1690 | { |
6da48311 | 1691 | OHCIState *ohci = opaque; |
09564574 | 1692 | |
0d92ed30 PB |
1693 | /* Only aligned reads are allowed on OHCI */ |
1694 | if (addr & 3) { | |
dc1f5988 | 1695 | trace_usb_ohci_mem_write_unaligned(addr); |
0d92ed30 PB |
1696 | return; |
1697 | } | |
1698 | ||
1699 | if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { | |
1700 | /* HcRhPortStatus */ | |
1701 | ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); | |
1702 | return; | |
1703 | } | |
1704 | ||
1705 | switch (addr >> 2) { | |
1706 | case 1: /* HcControl */ | |
1707 | ohci_set_ctl(ohci, val); | |
1708 | break; | |
1709 | ||
1710 | case 2: /* HcCommandStatus */ | |
1711 | /* SOC is read-only */ | |
1712 | val = (val & ~OHCI_STATUS_SOC); | |
1713 | ||
1714 | /* Bits written as '0' remain unchanged in the register */ | |
1715 | ohci->status |= val; | |
1716 | ||
1717 | if (ohci->status & OHCI_STATUS_HCR) | |
0922c3f6 | 1718 | ohci_soft_reset(ohci); |
0d92ed30 PB |
1719 | break; |
1720 | ||
1721 | case 3: /* HcInterruptStatus */ | |
1722 | ohci->intr_status &= ~val; | |
1723 | ohci_intr_update(ohci); | |
1724 | break; | |
1725 | ||
1726 | case 4: /* HcInterruptEnable */ | |
1727 | ohci->intr |= val; | |
1728 | ohci_intr_update(ohci); | |
1729 | break; | |
1730 | ||
1731 | case 5: /* HcInterruptDisable */ | |
1732 | ohci->intr &= ~val; | |
1733 | ohci_intr_update(ohci); | |
1734 | break; | |
1735 | ||
1736 | case 6: /* HcHCCA */ | |
1737 | ohci->hcca = val & OHCI_HCCA_MASK; | |
1738 | break; | |
1739 | ||
4b0315d7 PM |
1740 | case 7: /* HcPeriodCurrentED */ |
1741 | /* Ignore writes to this read-only register, Linux does them */ | |
1742 | break; | |
1743 | ||
0d92ed30 PB |
1744 | case 8: /* HcControlHeadED */ |
1745 | ohci->ctrl_head = val & OHCI_EDPTR_MASK; | |
1746 | break; | |
1747 | ||
1748 | case 9: /* HcControlCurrentED */ | |
1749 | ohci->ctrl_cur = val & OHCI_EDPTR_MASK; | |
1750 | break; | |
1751 | ||
1752 | case 10: /* HcBulkHeadED */ | |
1753 | ohci->bulk_head = val & OHCI_EDPTR_MASK; | |
1754 | break; | |
1755 | ||
1756 | case 11: /* HcBulkCurrentED */ | |
1757 | ohci->bulk_cur = val & OHCI_EDPTR_MASK; | |
1758 | break; | |
1759 | ||
1760 | case 13: /* HcFmInterval */ | |
1761 | ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; | |
1762 | ohci->fit = (val & OHCI_FMI_FIT) >> 31; | |
1763 | ohci_set_frame_interval(ohci, val); | |
1764 | break; | |
1765 | ||
7bfe5777 AZ |
1766 | case 15: /* HcFmNumber */ |
1767 | break; | |
1768 | ||
0d92ed30 PB |
1769 | case 16: /* HcPeriodicStart */ |
1770 | ohci->pstart = val & 0xffff; | |
1771 | break; | |
1772 | ||
1773 | case 17: /* HcLSThreshold */ | |
1774 | ohci->lst = val & 0xffff; | |
1775 | break; | |
1776 | ||
1777 | case 18: /* HcRhDescriptorA */ | |
1778 | ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; | |
1779 | ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; | |
1780 | break; | |
1781 | ||
1782 | case 19: /* HcRhDescriptorB */ | |
1783 | break; | |
1784 | ||
1785 | case 20: /* HcRhStatus */ | |
1786 | ohci_set_hub_status(ohci, val); | |
1787 | break; | |
1788 | ||
e24ad6f1 PB |
1789 | /* PXA27x specific registers */ |
1790 | case 24: /* HcStatus */ | |
1791 | ohci->hstatus &= ~(val & ohci->hmask); | |
7fa96d73 | 1792 | break; |
e24ad6f1 PB |
1793 | |
1794 | case 25: /* HcHReset */ | |
1795 | ohci->hreset = val & ~OHCI_HRESET_FSBIR; | |
1796 | if (val & OHCI_HRESET_FSBIR) | |
84d04e21 | 1797 | ohci_hard_reset(ohci); |
e24ad6f1 PB |
1798 | break; |
1799 | ||
1800 | case 26: /* HcHInterruptEnable */ | |
1801 | ohci->hmask = val; | |
1802 | break; | |
1803 | ||
1804 | case 27: /* HcHInterruptTest */ | |
1805 | ohci->htest = val; | |
1806 | break; | |
1807 | ||
0d92ed30 | 1808 | default: |
dc1f5988 | 1809 | trace_usb_ohci_mem_write_bad_offset(addr); |
0d92ed30 PB |
1810 | break; |
1811 | } | |
1812 | } | |
1813 | ||
4706ab6c | 1814 | static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) |
07771f6f | 1815 | { |
25d5de7d | 1816 | if (ohci->async_td && |
f53c398a GH |
1817 | usb_packet_is_inflight(&ohci->usb_packet) && |
1818 | ohci->usb_packet.ep->dev == dev) { | |
07771f6f GH |
1819 | usb_cancel_packet(&ohci->usb_packet); |
1820 | ohci->async_td = 0; | |
1821 | } | |
1822 | } | |
1823 | ||
6da48311 AK |
1824 | static const MemoryRegionOps ohci_mem_ops = { |
1825 | .read = ohci_mem_read, | |
1826 | .write = ohci_mem_write, | |
1827 | .endianness = DEVICE_LITTLE_ENDIAN, | |
0d92ed30 PB |
1828 | }; |
1829 | ||
0d86d2be GH |
1830 | static USBPortOps ohci_port_ops = { |
1831 | .attach = ohci_attach, | |
618c169b | 1832 | .detach = ohci_detach, |
4706ab6c | 1833 | .child_detach = ohci_child_detach, |
9bba1eb1 | 1834 | .wakeup = ohci_wakeup, |
13a9a0d3 | 1835 | .complete = ohci_async_complete_packet, |
0d86d2be GH |
1836 | }; |
1837 | ||
07771f6f | 1838 | static USBBusOps ohci_bus_ops = { |
07771f6f GH |
1839 | }; |
1840 | ||
87581fea MA |
1841 | static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
1842 | int num_ports, dma_addr_t localmem_base, | |
1843 | char *masterbus, uint32_t firstport, | |
1844 | AddressSpace *as, Error **errp) | |
0d92ed30 | 1845 | { |
f4bbaaf5 | 1846 | Error *err = NULL; |
0d92ed30 PB |
1847 | int i; |
1848 | ||
df32fd1c | 1849 | ohci->as = as; |
9ac6a217 | 1850 | |
0d92ed30 | 1851 | if (usb_frame_time == 0) { |
eb38c52c | 1852 | #ifdef OHCI_TIME_WARP |
6ee093c9 JQ |
1853 | usb_frame_time = get_ticks_per_sec(); |
1854 | usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); | |
0d92ed30 | 1855 | #else |
6ee093c9 JQ |
1856 | usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); |
1857 | if (get_ticks_per_sec() >= USB_HZ) { | |
1858 | usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ); | |
0d92ed30 PB |
1859 | } else { |
1860 | usb_bit_time = 1; | |
1861 | } | |
1862 | #endif | |
dc1f5988 | 1863 | trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); |
0d92ed30 PB |
1864 | } |
1865 | ||
9c9fc334 HG |
1866 | ohci->num_ports = num_ports; |
1867 | if (masterbus) { | |
1868 | USBPort *ports[OHCI_MAX_PORTS]; | |
1869 | for(i = 0; i < num_ports; i++) { | |
1870 | ports[i] = &ohci->rhport[i].port; | |
1871 | } | |
f4bbaaf5 MA |
1872 | usb_register_companion(masterbus, ports, num_ports, |
1873 | firstport, ohci, &ohci_port_ops, | |
1874 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, | |
1875 | &err); | |
1876 | if (err) { | |
87581fea MA |
1877 | error_propagate(errp, err); |
1878 | return; | |
9c9fc334 HG |
1879 | } |
1880 | } else { | |
c889b3a5 | 1881 | usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); |
9c9fc334 HG |
1882 | for (i = 0; i < num_ports; i++) { |
1883 | usb_register_port(&ohci->bus, &ohci->rhport[i].port, | |
1884 | ohci, i, &ohci_port_ops, | |
1885 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1886 | } | |
1887 | } | |
1888 | ||
22fc860b PB |
1889 | memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, |
1890 | ohci, "ohci", 256); | |
ac611340 | 1891 | ohci->localmem_base = localmem_base; |
e24ad6f1 | 1892 | |
f79f2bfc | 1893 | ohci->name = object_get_typename(OBJECT(dev)); |
4f4321c1 | 1894 | usb_packet_init(&ohci->usb_packet); |
e24ad6f1 | 1895 | |
e24ad6f1 | 1896 | ohci->async_td = 0; |
fa1298c2 GH |
1897 | |
1898 | ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, | |
1899 | ohci_frame_boundary, ohci); | |
e24ad6f1 PB |
1900 | } |
1901 | ||
1aa0c0c7 HT |
1902 | #define TYPE_PCI_OHCI "pci-ohci" |
1903 | #define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI) | |
1904 | ||
e24ad6f1 | 1905 | typedef struct { |
1aa0c0c7 HT |
1906 | /*< private >*/ |
1907 | PCIDevice parent_obj; | |
1908 | /*< public >*/ | |
1909 | ||
e24ad6f1 | 1910 | OHCIState state; |
9c9fc334 HG |
1911 | char *masterbus; |
1912 | uint32_t num_ports; | |
1913 | uint32_t firstport; | |
e24ad6f1 PB |
1914 | } OHCIPCIState; |
1915 | ||
cf66ee8e AK |
1916 | /** A typical O/EHCI will stop operating, set itself into error state |
1917 | * (which can be queried by MMIO) and will set PERR in its config | |
1918 | * space to signal that it got an error | |
1919 | */ | |
1920 | static void ohci_die(OHCIState *ohci) | |
1921 | { | |
1922 | OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state); | |
1923 | ||
dc1f5988 | 1924 | trace_usb_ohci_die(); |
cf66ee8e AK |
1925 | |
1926 | ohci_set_interrupt(ohci, OHCI_INTR_UE); | |
1927 | ohci_bus_stop(ohci); | |
1928 | pci_set_word(dev->parent_obj.config + PCI_STATUS, | |
1929 | PCI_STATUS_DETECTED_PARITY); | |
1930 | } | |
1931 | ||
87581fea | 1932 | static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp) |
e24ad6f1 | 1933 | { |
87581fea | 1934 | Error *err = NULL; |
1aa0c0c7 | 1935 | OHCIPCIState *ohci = PCI_OHCI(dev); |
0d92ed30 | 1936 | |
1aa0c0c7 HT |
1937 | dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */ |
1938 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ | |
0d92ed30 | 1939 | |
87581fea MA |
1940 | usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0, |
1941 | ohci->masterbus, ohci->firstport, | |
1942 | pci_get_address_space(dev), &err); | |
1943 | if (err) { | |
1944 | error_propagate(errp, err); | |
1945 | return; | |
9c9fc334 | 1946 | } |
0d92ed30 | 1947 | |
87581fea | 1948 | ohci->state.irq = pci_allocate_irq(dev); |
1aa0c0c7 | 1949 | pci_register_bar(dev, 0, 0, &ohci->state.mem); |
5b19d9a2 GH |
1950 | } |
1951 | ||
07832c38 GA |
1952 | static void usb_ohci_exit(PCIDevice *dev) |
1953 | { | |
1954 | OHCIPCIState *ohci = PCI_OHCI(dev); | |
1955 | OHCIState *s = &ohci->state; | |
1956 | ||
dc1f5988 | 1957 | trace_usb_ohci_exit(s->name); |
07832c38 GA |
1958 | ohci_bus_stop(s); |
1959 | ||
1960 | if (s->async_td) { | |
1961 | usb_cancel_packet(&s->usb_packet); | |
1962 | s->async_td = 0; | |
1963 | } | |
1964 | ohci_stop_endpoints(s); | |
1965 | ||
1966 | if (!ohci->masterbus) { | |
1967 | usb_bus_release(&s->bus); | |
1968 | } | |
fa1298c2 GH |
1969 | |
1970 | timer_del(s->eof_timer); | |
1971 | timer_free(s->eof_timer); | |
07832c38 GA |
1972 | } |
1973 | ||
88dd1b8d GA |
1974 | static void usb_ohci_reset_pci(DeviceState *d) |
1975 | { | |
1976 | PCIDevice *dev = PCI_DEVICE(d); | |
1977 | OHCIPCIState *ohci = PCI_OHCI(dev); | |
1978 | OHCIState *s = &ohci->state; | |
1979 | ||
84d04e21 | 1980 | ohci_hard_reset(s); |
88dd1b8d GA |
1981 | } |
1982 | ||
1aa0c0c7 HT |
1983 | #define TYPE_SYSBUS_OHCI "sysbus-ohci" |
1984 | #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI) | |
1985 | ||
61d3cf93 | 1986 | typedef struct { |
1aa0c0c7 HT |
1987 | /*< private >*/ |
1988 | SysBusDevice parent_obj; | |
1989 | /*< public >*/ | |
1990 | ||
61d3cf93 PB |
1991 | OHCIState ohci; |
1992 | uint32_t num_ports; | |
9ac6a217 | 1993 | dma_addr_t dma_offset; |
61d3cf93 | 1994 | } OHCISysBusState; |
ac611340 | 1995 | |
457215ec | 1996 | static void ohci_realize_pxa(DeviceState *dev, Error **errp) |
ac611340 | 1997 | { |
1aa0c0c7 | 1998 | OHCISysBusState *s = SYSBUS_OHCI(dev); |
457215ec | 1999 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
ac611340 | 2000 | |
9c9fc334 | 2001 | /* Cannot fail as we pass NULL for masterbus */ |
457215ec | 2002 | usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, NULL, 0, |
87581fea | 2003 | &address_space_memory, &error_abort); |
457215ec HT |
2004 | sysbus_init_irq(sbd, &s->ohci.irq); |
2005 | sysbus_init_mmio(sbd, &s->ohci.mem); | |
ac611340 AJ |
2006 | } |
2007 | ||
88dd1b8d GA |
2008 | static void usb_ohci_reset_sysbus(DeviceState *dev) |
2009 | { | |
2010 | OHCISysBusState *s = SYSBUS_OHCI(dev); | |
2011 | OHCIState *ohci = &s->ohci; | |
2012 | ||
84d04e21 | 2013 | ohci_hard_reset(ohci); |
88dd1b8d GA |
2014 | } |
2015 | ||
40021f08 AL |
2016 | static Property ohci_pci_properties[] = { |
2017 | DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), | |
2018 | DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), | |
2019 | DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), | |
2020 | DEFINE_PROP_END_OF_LIST(), | |
2021 | }; | |
2022 | ||
69e25d26 AK |
2023 | static const VMStateDescription vmstate_ohci_state_port = { |
2024 | .name = "ohci-core/port", | |
2025 | .version_id = 1, | |
2026 | .minimum_version_id = 1, | |
25feab2f | 2027 | .fields = (VMStateField[]) { |
69e25d26 AK |
2028 | VMSTATE_UINT32(ctrl, OHCIPort), |
2029 | VMSTATE_END_OF_LIST() | |
2030 | }, | |
2031 | }; | |
2032 | ||
2033 | static bool ohci_eof_timer_needed(void *opaque) | |
2034 | { | |
2035 | OHCIState *ohci = opaque; | |
2036 | ||
fa1298c2 | 2037 | return timer_pending(ohci->eof_timer); |
69e25d26 AK |
2038 | } |
2039 | ||
2040 | static const VMStateDescription vmstate_ohci_eof_timer = { | |
2041 | .name = "ohci-core/eof-timer", | |
2042 | .version_id = 1, | |
2043 | .minimum_version_id = 1, | |
5cd8cada | 2044 | .needed = ohci_eof_timer_needed, |
25feab2f | 2045 | .fields = (VMStateField[]) { |
e720677e | 2046 | VMSTATE_TIMER_PTR(eof_timer, OHCIState), |
69e25d26 AK |
2047 | VMSTATE_END_OF_LIST() |
2048 | }, | |
2049 | }; | |
2050 | ||
b9b45b4a | 2051 | static const VMStateDescription vmstate_ohci_state = { |
69e25d26 AK |
2052 | .name = "ohci-core", |
2053 | .version_id = 1, | |
2054 | .minimum_version_id = 1, | |
2055 | .fields = (VMStateField[]) { | |
2056 | VMSTATE_INT64(sof_time, OHCIState), | |
2057 | VMSTATE_UINT32(ctl, OHCIState), | |
2058 | VMSTATE_UINT32(status, OHCIState), | |
2059 | VMSTATE_UINT32(intr_status, OHCIState), | |
2060 | VMSTATE_UINT32(intr, OHCIState), | |
2061 | VMSTATE_UINT32(hcca, OHCIState), | |
2062 | VMSTATE_UINT32(ctrl_head, OHCIState), | |
2063 | VMSTATE_UINT32(ctrl_cur, OHCIState), | |
2064 | VMSTATE_UINT32(bulk_head, OHCIState), | |
2065 | VMSTATE_UINT32(bulk_cur, OHCIState), | |
2066 | VMSTATE_UINT32(per_cur, OHCIState), | |
2067 | VMSTATE_UINT32(done, OHCIState), | |
2068 | VMSTATE_INT32(done_count, OHCIState), | |
2069 | VMSTATE_UINT16(fsmps, OHCIState), | |
2070 | VMSTATE_UINT8(fit, OHCIState), | |
2071 | VMSTATE_UINT16(fi, OHCIState), | |
2072 | VMSTATE_UINT8(frt, OHCIState), | |
2073 | VMSTATE_UINT16(frame_number, OHCIState), | |
2074 | VMSTATE_UINT16(padding, OHCIState), | |
2075 | VMSTATE_UINT32(pstart, OHCIState), | |
2076 | VMSTATE_UINT32(lst, OHCIState), | |
2077 | VMSTATE_UINT32(rhdesc_a, OHCIState), | |
2078 | VMSTATE_UINT32(rhdesc_b, OHCIState), | |
2079 | VMSTATE_UINT32(rhstatus, OHCIState), | |
2080 | VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, | |
2081 | vmstate_ohci_state_port, OHCIPort), | |
2082 | VMSTATE_UINT32(hstatus, OHCIState), | |
2083 | VMSTATE_UINT32(hmask, OHCIState), | |
2084 | VMSTATE_UINT32(hreset, OHCIState), | |
2085 | VMSTATE_UINT32(htest, OHCIState), | |
2086 | VMSTATE_UINT32(old_ctl, OHCIState), | |
2087 | VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), | |
2088 | VMSTATE_UINT32(async_td, OHCIState), | |
2089 | VMSTATE_BOOL(async_complete, OHCIState), | |
2090 | VMSTATE_END_OF_LIST() | |
2091 | }, | |
5cd8cada JQ |
2092 | .subsections = (const VMStateDescription*[]) { |
2093 | &vmstate_ohci_eof_timer, | |
2094 | NULL | |
69e25d26 AK |
2095 | } |
2096 | }; | |
2097 | ||
2098 | static const VMStateDescription vmstate_ohci = { | |
2099 | .name = "ohci", | |
2100 | .version_id = 1, | |
2101 | .minimum_version_id = 1, | |
69e25d26 AK |
2102 | .fields = (VMStateField[]) { |
2103 | VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState), | |
2104 | VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState), | |
2105 | VMSTATE_END_OF_LIST() | |
2106 | } | |
2107 | }; | |
2108 | ||
40021f08 AL |
2109 | static void ohci_pci_class_init(ObjectClass *klass, void *data) |
2110 | { | |
39bffca2 | 2111 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2112 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2113 | ||
87581fea | 2114 | k->realize = usb_ohci_realize_pci; |
07832c38 | 2115 | k->exit = usb_ohci_exit; |
40021f08 AL |
2116 | k->vendor_id = PCI_VENDOR_ID_APPLE; |
2117 | k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; | |
2118 | k->class_id = PCI_CLASS_SERIAL_USB; | |
125ee0ed | 2119 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
39bffca2 AL |
2120 | dc->desc = "Apple USB Controller"; |
2121 | dc->props = ohci_pci_properties; | |
2897ae02 | 2122 | dc->hotpluggable = false; |
69e25d26 | 2123 | dc->vmsd = &vmstate_ohci; |
88dd1b8d | 2124 | dc->reset = usb_ohci_reset_pci; |
40021f08 AL |
2125 | } |
2126 | ||
8c43a6f0 | 2127 | static const TypeInfo ohci_pci_info = { |
1aa0c0c7 | 2128 | .name = TYPE_PCI_OHCI, |
39bffca2 AL |
2129 | .parent = TYPE_PCI_DEVICE, |
2130 | .instance_size = sizeof(OHCIPCIState), | |
2131 | .class_init = ohci_pci_class_init, | |
2132 | }; | |
2133 | ||
2134 | static Property ohci_sysbus_properties[] = { | |
2135 | DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), | |
9ac6a217 | 2136 | DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 3), |
39bffca2 | 2137 | DEFINE_PROP_END_OF_LIST(), |
5b19d9a2 GH |
2138 | }; |
2139 | ||
999e12bb AL |
2140 | static void ohci_sysbus_class_init(ObjectClass *klass, void *data) |
2141 | { | |
39bffca2 | 2142 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2143 | |
457215ec | 2144 | dc->realize = ohci_realize_pxa; |
125ee0ed | 2145 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
39bffca2 AL |
2146 | dc->desc = "OHCI USB Controller"; |
2147 | dc->props = ohci_sysbus_properties; | |
88dd1b8d | 2148 | dc->reset = usb_ohci_reset_sysbus; |
999e12bb AL |
2149 | } |
2150 | ||
8c43a6f0 | 2151 | static const TypeInfo ohci_sysbus_info = { |
1aa0c0c7 | 2152 | .name = TYPE_SYSBUS_OHCI, |
39bffca2 AL |
2153 | .parent = TYPE_SYS_BUS_DEVICE, |
2154 | .instance_size = sizeof(OHCISysBusState), | |
2155 | .class_init = ohci_sysbus_class_init, | |
61d3cf93 PB |
2156 | }; |
2157 | ||
83f7d43a | 2158 | static void ohci_register_types(void) |
5b19d9a2 | 2159 | { |
39bffca2 AL |
2160 | type_register_static(&ohci_pci_info); |
2161 | type_register_static(&ohci_sysbus_info); | |
5b19d9a2 | 2162 | } |
83f7d43a AF |
2163 | |
2164 | type_init(ohci_register_types) |