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62c6ae04 HM |
1 | /* |
2 | * USB xHCI controller emulation | |
3 | * | |
4 | * Copyright (c) 2011 Securiforest | |
5 | * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> | |
6 | * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 | |
7 | * | |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
0b8fa32f | 21 | |
e532b2e0 | 22 | #include "qemu/osdep.h" |
1de7afc9 | 23 | #include "qemu/timer.h" |
0b8fa32f | 24 | #include "qemu/module.h" |
94b037f2 | 25 | #include "qemu/queue.h" |
f1ae32a1 | 26 | #include "hw/usb.h" |
d6454270 | 27 | #include "migration/vmstate.h" |
a2cb15b0 | 28 | #include "hw/pci/pci.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
a2cb15b0 MT |
30 | #include "hw/pci/msi.h" |
31 | #include "hw/pci/msix.h" | |
2d754a10 | 32 | #include "trace.h" |
1108b2f8 | 33 | #include "qapi/error.h" |
62c6ae04 | 34 | |
0bbb2f3d GH |
35 | #include "hcd-xhci.h" |
36 | ||
62c6ae04 HM |
37 | //#define DEBUG_XHCI |
38 | //#define DEBUG_DATA | |
39 | ||
40 | #ifdef DEBUG_XHCI | |
41 | #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) | |
42 | #else | |
43 | #define DPRINTF(...) do {} while (0) | |
44 | #endif | |
024426ac GH |
45 | #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ |
46 | __func__, __LINE__, _msg); abort(); } while (0) | |
62c6ae04 | 47 | |
99f9aeba | 48 | #define TRB_LINK_LIMIT 32 |
f89b60f6 GH |
49 | #define COMMAND_LIMIT 256 |
50 | #define TRANSFER_LIMIT 256 | |
05f43d44 | 51 | |
62c6ae04 | 52 | #define LEN_CAP 0x40 |
62c6ae04 | 53 | #define LEN_OPER (0x400 + 0x10 * MAXPORTS) |
106b214c | 54 | #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) |
62c6ae04 HM |
55 | #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) |
56 | ||
106b214c GH |
57 | #define OFF_OPER LEN_CAP |
58 | #define OFF_RUNTIME 0x1000 | |
59 | #define OFF_DOORBELL 0x2000 | |
4c47f800 GH |
60 | #define OFF_MSIX_TABLE 0x3000 |
61 | #define OFF_MSIX_PBA 0x3800 | |
62c6ae04 | 62 | /* must be power of 2 */ |
106b214c | 63 | #define LEN_REGS 0x4000 |
62c6ae04 | 64 | |
106b214c GH |
65 | #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME |
66 | #error Increase OFF_RUNTIME | |
67 | #endif | |
68 | #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL | |
69 | #error Increase OFF_DOORBELL | |
70 | #endif | |
62c6ae04 HM |
71 | #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS |
72 | # error Increase LEN_REGS | |
73 | #endif | |
74 | ||
62c6ae04 HM |
75 | /* bit definitions */ |
76 | #define USBCMD_RS (1<<0) | |
77 | #define USBCMD_HCRST (1<<1) | |
78 | #define USBCMD_INTE (1<<2) | |
79 | #define USBCMD_HSEE (1<<3) | |
80 | #define USBCMD_LHCRST (1<<7) | |
81 | #define USBCMD_CSS (1<<8) | |
82 | #define USBCMD_CRS (1<<9) | |
83 | #define USBCMD_EWE (1<<10) | |
84 | #define USBCMD_EU3S (1<<11) | |
85 | ||
86 | #define USBSTS_HCH (1<<0) | |
87 | #define USBSTS_HSE (1<<2) | |
88 | #define USBSTS_EINT (1<<3) | |
89 | #define USBSTS_PCD (1<<4) | |
90 | #define USBSTS_SSS (1<<8) | |
91 | #define USBSTS_RSS (1<<9) | |
92 | #define USBSTS_SRE (1<<10) | |
93 | #define USBSTS_CNR (1<<11) | |
94 | #define USBSTS_HCE (1<<12) | |
95 | ||
96 | ||
97 | #define PORTSC_CCS (1<<0) | |
98 | #define PORTSC_PED (1<<1) | |
99 | #define PORTSC_OCA (1<<3) | |
100 | #define PORTSC_PR (1<<4) | |
101 | #define PORTSC_PLS_SHIFT 5 | |
102 | #define PORTSC_PLS_MASK 0xf | |
103 | #define PORTSC_PP (1<<9) | |
104 | #define PORTSC_SPEED_SHIFT 10 | |
105 | #define PORTSC_SPEED_MASK 0xf | |
106 | #define PORTSC_SPEED_FULL (1<<10) | |
107 | #define PORTSC_SPEED_LOW (2<<10) | |
108 | #define PORTSC_SPEED_HIGH (3<<10) | |
109 | #define PORTSC_SPEED_SUPER (4<<10) | |
110 | #define PORTSC_PIC_SHIFT 14 | |
111 | #define PORTSC_PIC_MASK 0x3 | |
112 | #define PORTSC_LWS (1<<16) | |
113 | #define PORTSC_CSC (1<<17) | |
114 | #define PORTSC_PEC (1<<18) | |
115 | #define PORTSC_WRC (1<<19) | |
116 | #define PORTSC_OCC (1<<20) | |
117 | #define PORTSC_PRC (1<<21) | |
118 | #define PORTSC_PLC (1<<22) | |
119 | #define PORTSC_CEC (1<<23) | |
120 | #define PORTSC_CAS (1<<24) | |
121 | #define PORTSC_WCE (1<<25) | |
122 | #define PORTSC_WDE (1<<26) | |
123 | #define PORTSC_WOE (1<<27) | |
124 | #define PORTSC_DR (1<<30) | |
125 | #define PORTSC_WPR (1<<31) | |
126 | ||
127 | #define CRCR_RCS (1<<0) | |
128 | #define CRCR_CS (1<<1) | |
129 | #define CRCR_CA (1<<2) | |
130 | #define CRCR_CRR (1<<3) | |
131 | ||
132 | #define IMAN_IP (1<<0) | |
133 | #define IMAN_IE (1<<1) | |
134 | ||
135 | #define ERDP_EHB (1<<3) | |
136 | ||
137 | #define TRB_SIZE 16 | |
138 | typedef struct XHCITRB { | |
139 | uint64_t parameter; | |
140 | uint32_t status; | |
141 | uint32_t control; | |
59a70ccd | 142 | dma_addr_t addr; |
62c6ae04 HM |
143 | bool ccs; |
144 | } XHCITRB; | |
145 | ||
85e05d82 GH |
146 | enum { |
147 | PLS_U0 = 0, | |
148 | PLS_U1 = 1, | |
149 | PLS_U2 = 2, | |
150 | PLS_U3 = 3, | |
151 | PLS_DISABLED = 4, | |
152 | PLS_RX_DETECT = 5, | |
153 | PLS_INACTIVE = 6, | |
154 | PLS_POLLING = 7, | |
155 | PLS_RECOVERY = 8, | |
156 | PLS_HOT_RESET = 9, | |
157 | PLS_COMPILANCE_MODE = 10, | |
158 | PLS_TEST_MODE = 11, | |
159 | PLS_RESUME = 15, | |
160 | }; | |
62c6ae04 | 161 | |
62c6ae04 HM |
162 | #define CR_LINK TR_LINK |
163 | ||
62c6ae04 HM |
164 | #define TRB_C (1<<0) |
165 | #define TRB_TYPE_SHIFT 10 | |
166 | #define TRB_TYPE_MASK 0x3f | |
167 | #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) | |
168 | ||
169 | #define TRB_EV_ED (1<<2) | |
170 | ||
171 | #define TRB_TR_ENT (1<<1) | |
172 | #define TRB_TR_ISP (1<<2) | |
173 | #define TRB_TR_NS (1<<3) | |
174 | #define TRB_TR_CH (1<<4) | |
175 | #define TRB_TR_IOC (1<<5) | |
176 | #define TRB_TR_IDT (1<<6) | |
177 | #define TRB_TR_TBC_SHIFT 7 | |
178 | #define TRB_TR_TBC_MASK 0x3 | |
179 | #define TRB_TR_BEI (1<<9) | |
180 | #define TRB_TR_TLBPC_SHIFT 16 | |
181 | #define TRB_TR_TLBPC_MASK 0xf | |
182 | #define TRB_TR_FRAMEID_SHIFT 20 | |
183 | #define TRB_TR_FRAMEID_MASK 0x7ff | |
184 | #define TRB_TR_SIA (1<<31) | |
185 | ||
186 | #define TRB_TR_DIR (1<<16) | |
187 | ||
188 | #define TRB_CR_SLOTID_SHIFT 24 | |
189 | #define TRB_CR_SLOTID_MASK 0xff | |
190 | #define TRB_CR_EPID_SHIFT 16 | |
191 | #define TRB_CR_EPID_MASK 0x1f | |
192 | ||
193 | #define TRB_CR_BSR (1<<9) | |
194 | #define TRB_CR_DC (1<<9) | |
195 | ||
196 | #define TRB_LK_TC (1<<1) | |
197 | ||
2d1de850 GH |
198 | #define TRB_INTR_SHIFT 22 |
199 | #define TRB_INTR_MASK 0x3ff | |
200 | #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) | |
201 | ||
62c6ae04 HM |
202 | #define EP_TYPE_MASK 0x7 |
203 | #define EP_TYPE_SHIFT 3 | |
204 | ||
205 | #define EP_STATE_MASK 0x7 | |
206 | #define EP_DISABLED (0<<0) | |
207 | #define EP_RUNNING (1<<0) | |
208 | #define EP_HALTED (2<<0) | |
209 | #define EP_STOPPED (3<<0) | |
210 | #define EP_ERROR (4<<0) | |
211 | ||
212 | #define SLOT_STATE_MASK 0x1f | |
213 | #define SLOT_STATE_SHIFT 27 | |
214 | #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) | |
215 | #define SLOT_ENABLED 0 | |
216 | #define SLOT_DEFAULT 1 | |
217 | #define SLOT_ADDRESSED 2 | |
218 | #define SLOT_CONFIGURED 3 | |
219 | ||
220 | #define SLOT_CONTEXT_ENTRIES_MASK 0x1f | |
221 | #define SLOT_CONTEXT_ENTRIES_SHIFT 27 | |
222 | ||
85e05d82 GH |
223 | #define get_field(data, field) \ |
224 | (((data) >> field##_SHIFT) & field##_MASK) | |
225 | ||
226 | #define set_field(data, newval, field) do { \ | |
227 | uint32_t val = *data; \ | |
228 | val &= ~(field##_MASK << field##_SHIFT); \ | |
229 | val |= ((newval) & field##_MASK) << field##_SHIFT; \ | |
230 | *data = val; \ | |
231 | } while (0) | |
232 | ||
62c6ae04 HM |
233 | typedef enum EPType { |
234 | ET_INVALID = 0, | |
235 | ET_ISO_OUT, | |
236 | ET_BULK_OUT, | |
237 | ET_INTR_OUT, | |
238 | ET_CONTROL, | |
239 | ET_ISO_IN, | |
240 | ET_BULK_IN, | |
241 | ET_INTR_IN, | |
242 | } EPType; | |
243 | ||
62c6ae04 | 244 | typedef struct XHCITransfer { |
94b037f2 | 245 | XHCIEPContext *epctx; |
62c6ae04 | 246 | USBPacket packet; |
d5a15814 | 247 | QEMUSGList sgl; |
7c605a23 GH |
248 | bool running_async; |
249 | bool running_retry; | |
62c6ae04 | 250 | bool complete; |
a6fb2ddb | 251 | bool int_req; |
62c6ae04 | 252 | unsigned int iso_pkts; |
024426ac | 253 | unsigned int streamid; |
62c6ae04 HM |
254 | bool in_xfer; |
255 | bool iso_xfer; | |
4d7a81c0 | 256 | bool timed_xfer; |
62c6ae04 HM |
257 | |
258 | unsigned int trb_count; | |
62c6ae04 HM |
259 | XHCITRB *trbs; |
260 | ||
62c6ae04 HM |
261 | TRBCCode status; |
262 | ||
263 | unsigned int pkts; | |
264 | unsigned int pktsize; | |
265 | unsigned int cur_pkt; | |
3d139684 GH |
266 | |
267 | uint64_t mfindex_kick; | |
94b037f2 GH |
268 | |
269 | QTAILQ_ENTRY(XHCITransfer) next; | |
62c6ae04 HM |
270 | } XHCITransfer; |
271 | ||
024426ac GH |
272 | struct XHCIStreamContext { |
273 | dma_addr_t pctx; | |
274 | unsigned int sct; | |
275 | XHCIRing ring; | |
024426ac GH |
276 | }; |
277 | ||
278 | struct XHCIEPContext { | |
3d139684 GH |
279 | XHCIState *xhci; |
280 | unsigned int slotid; | |
281 | unsigned int epid; | |
282 | ||
62c6ae04 | 283 | XHCIRing ring; |
94b037f2 GH |
284 | uint32_t xfer_count; |
285 | QTAILQ_HEAD(, XHCITransfer) transfers; | |
7c605a23 | 286 | XHCITransfer *retry; |
62c6ae04 | 287 | EPType type; |
59a70ccd | 288 | dma_addr_t pctx; |
62c6ae04 | 289 | unsigned int max_psize; |
62c6ae04 | 290 | uint32_t state; |
96d87bdd | 291 | uint32_t kick_active; |
3d139684 | 292 | |
024426ac GH |
293 | /* streams */ |
294 | unsigned int max_pstreams; | |
295 | bool lsa; | |
296 | unsigned int nr_pstreams; | |
297 | XHCIStreamContext *pstreams; | |
298 | ||
3d139684 GH |
299 | /* iso xfer scheduling */ |
300 | unsigned int interval; | |
301 | int64_t mfindex_last; | |
302 | QEMUTimer *kick_timer; | |
024426ac | 303 | }; |
62c6ae04 | 304 | |
62c6ae04 HM |
305 | typedef struct XHCIEvRingSeg { |
306 | uint32_t addr_low; | |
307 | uint32_t addr_high; | |
308 | uint32_t size; | |
309 | uint32_t rsvd; | |
310 | } XHCIEvRingSeg; | |
311 | ||
01546fa6 | 312 | static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
024426ac | 313 | unsigned int epid, unsigned int streamid); |
3a533ee8 | 314 | static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid); |
0bc85da6 GH |
315 | static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, |
316 | unsigned int epid); | |
582d6f4a | 317 | static void xhci_xfer_report(XHCITransfer *xfer); |
962d11e1 GH |
318 | static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); |
319 | static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); | |
070eeef9 | 320 | static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx); |
01546fa6 | 321 | |
f10de44e GH |
322 | static const char *TRBType_names[] = { |
323 | [TRB_RESERVED] = "TRB_RESERVED", | |
324 | [TR_NORMAL] = "TR_NORMAL", | |
325 | [TR_SETUP] = "TR_SETUP", | |
326 | [TR_DATA] = "TR_DATA", | |
327 | [TR_STATUS] = "TR_STATUS", | |
328 | [TR_ISOCH] = "TR_ISOCH", | |
329 | [TR_LINK] = "TR_LINK", | |
330 | [TR_EVDATA] = "TR_EVDATA", | |
331 | [TR_NOOP] = "TR_NOOP", | |
332 | [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", | |
333 | [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", | |
334 | [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", | |
335 | [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", | |
336 | [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", | |
337 | [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", | |
338 | [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", | |
339 | [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", | |
340 | [CR_RESET_DEVICE] = "CR_RESET_DEVICE", | |
341 | [CR_FORCE_EVENT] = "CR_FORCE_EVENT", | |
342 | [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", | |
343 | [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", | |
344 | [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", | |
345 | [CR_FORCE_HEADER] = "CR_FORCE_HEADER", | |
346 | [CR_NOOP] = "CR_NOOP", | |
347 | [ER_TRANSFER] = "ER_TRANSFER", | |
348 | [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", | |
349 | [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", | |
350 | [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", | |
351 | [ER_DOORBELL] = "ER_DOORBELL", | |
352 | [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", | |
353 | [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", | |
354 | [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", | |
f10de44e GH |
355 | [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", |
356 | [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", | |
357 | }; | |
358 | ||
873123fe GH |
359 | static const char *TRBCCode_names[] = { |
360 | [CC_INVALID] = "CC_INVALID", | |
361 | [CC_SUCCESS] = "CC_SUCCESS", | |
362 | [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", | |
363 | [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", | |
364 | [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", | |
365 | [CC_TRB_ERROR] = "CC_TRB_ERROR", | |
366 | [CC_STALL_ERROR] = "CC_STALL_ERROR", | |
367 | [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", | |
368 | [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", | |
369 | [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", | |
370 | [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", | |
371 | [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", | |
372 | [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", | |
373 | [CC_SHORT_PACKET] = "CC_SHORT_PACKET", | |
374 | [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", | |
375 | [CC_RING_OVERRUN] = "CC_RING_OVERRUN", | |
376 | [CC_VF_ER_FULL] = "CC_VF_ER_FULL", | |
377 | [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", | |
378 | [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", | |
379 | [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", | |
380 | [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", | |
381 | [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", | |
382 | [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", | |
383 | [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", | |
384 | [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", | |
385 | [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", | |
386 | [CC_STOPPED] = "CC_STOPPED", | |
387 | [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", | |
388 | [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] | |
389 | = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", | |
390 | [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", | |
391 | [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", | |
392 | [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", | |
393 | [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", | |
394 | [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", | |
395 | [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", | |
396 | }; | |
397 | ||
1c82392a GH |
398 | static const char *ep_state_names[] = { |
399 | [EP_DISABLED] = "disabled", | |
400 | [EP_RUNNING] = "running", | |
401 | [EP_HALTED] = "halted", | |
402 | [EP_STOPPED] = "stopped", | |
403 | [EP_ERROR] = "error", | |
404 | }; | |
405 | ||
f10de44e GH |
406 | static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) |
407 | { | |
408 | if (index >= llen || list[index] == NULL) { | |
409 | return "???"; | |
410 | } | |
411 | return list[index]; | |
412 | } | |
413 | ||
414 | static const char *trb_name(XHCITRB *trb) | |
415 | { | |
416 | return lookup_name(TRB_TYPE(*trb), TRBType_names, | |
417 | ARRAY_SIZE(TRBType_names)); | |
418 | } | |
f10de44e | 419 | |
873123fe GH |
420 | static const char *event_name(XHCIEvent *event) |
421 | { | |
422 | return lookup_name(event->ccode, TRBCCode_names, | |
423 | ARRAY_SIZE(TRBCCode_names)); | |
424 | } | |
425 | ||
1c82392a GH |
426 | static const char *ep_state_name(uint32_t state) |
427 | { | |
428 | return lookup_name(state, ep_state_names, | |
429 | ARRAY_SIZE(ep_state_names)); | |
430 | } | |
431 | ||
f9955235 GH |
432 | static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) |
433 | { | |
434 | return xhci->flags & (1 << bit); | |
435 | } | |
436 | ||
4f72b8d2 GH |
437 | static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit) |
438 | { | |
439 | xhci->flags |= (1 << bit); | |
440 | } | |
441 | ||
01546fa6 GH |
442 | static uint64_t xhci_mfindex_get(XHCIState *xhci) |
443 | { | |
bc72ad67 | 444 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
01546fa6 GH |
445 | return (now - xhci->mfindex_start) / 125000; |
446 | } | |
447 | ||
448 | static void xhci_mfwrap_update(XHCIState *xhci) | |
449 | { | |
450 | const uint32_t bits = USBCMD_RS | USBCMD_EWE; | |
451 | uint32_t mfindex, left; | |
452 | int64_t now; | |
453 | ||
454 | if ((xhci->usbcmd & bits) == bits) { | |
bc72ad67 | 455 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
01546fa6 GH |
456 | mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; |
457 | left = 0x4000 - mfindex; | |
bc72ad67 | 458 | timer_mod(xhci->mfwrap_timer, now + left * 125000); |
01546fa6 | 459 | } else { |
bc72ad67 | 460 | timer_del(xhci->mfwrap_timer); |
01546fa6 GH |
461 | } |
462 | } | |
463 | ||
464 | static void xhci_mfwrap_timer(void *opaque) | |
465 | { | |
466 | XHCIState *xhci = opaque; | |
467 | XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; | |
468 | ||
962d11e1 | 469 | xhci_event(xhci, &wrap, 0); |
01546fa6 GH |
470 | xhci_mfwrap_update(xhci); |
471 | } | |
62c6ae04 | 472 | |
59a70ccd | 473 | static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) |
62c6ae04 | 474 | { |
59a70ccd DG |
475 | if (sizeof(dma_addr_t) == 4) { |
476 | return low; | |
477 | } else { | |
478 | return low | (((dma_addr_t)high << 16) << 16); | |
479 | } | |
62c6ae04 HM |
480 | } |
481 | ||
59a70ccd | 482 | static inline dma_addr_t xhci_mask64(uint64_t addr) |
62c6ae04 | 483 | { |
59a70ccd DG |
484 | if (sizeof(dma_addr_t) == 4) { |
485 | return addr & 0xffffffff; | |
486 | } else { | |
487 | return addr; | |
488 | } | |
62c6ae04 HM |
489 | } |
490 | ||
616b5d53 DG |
491 | static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, |
492 | uint32_t *buf, size_t len) | |
493 | { | |
494 | int i; | |
495 | ||
496 | assert((len % sizeof(uint32_t)) == 0); | |
497 | ||
9b7d3334 | 498 | pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); |
616b5d53 DG |
499 | |
500 | for (i = 0; i < (len / sizeof(uint32_t)); i++) { | |
501 | buf[i] = le32_to_cpu(buf[i]); | |
502 | } | |
503 | } | |
504 | ||
505 | static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, | |
506 | uint32_t *buf, size_t len) | |
507 | { | |
508 | int i; | |
182b391e PX |
509 | uint32_t tmp[5]; |
510 | uint32_t n = len / sizeof(uint32_t); | |
616b5d53 DG |
511 | |
512 | assert((len % sizeof(uint32_t)) == 0); | |
182b391e | 513 | assert(n <= ARRAY_SIZE(tmp)); |
616b5d53 | 514 | |
182b391e | 515 | for (i = 0; i < n; i++) { |
616b5d53 DG |
516 | tmp[i] = cpu_to_le32(buf[i]); |
517 | } | |
9b7d3334 | 518 | pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); |
616b5d53 DG |
519 | } |
520 | ||
0846e635 GH |
521 | static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) |
522 | { | |
523 | int index; | |
524 | ||
525 | if (!uport->dev) { | |
526 | return NULL; | |
527 | } | |
528 | switch (uport->dev->speed) { | |
529 | case USB_SPEED_LOW: | |
530 | case USB_SPEED_FULL: | |
531 | case USB_SPEED_HIGH: | |
7bafd888 GH |
532 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
533 | index = uport->index + xhci->numports_3; | |
534 | } else { | |
535 | index = uport->index; | |
536 | } | |
0846e635 GH |
537 | break; |
538 | case USB_SPEED_SUPER: | |
7bafd888 GH |
539 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
540 | index = uport->index; | |
541 | } else { | |
542 | index = uport->index + xhci->numports_2; | |
543 | } | |
0846e635 GH |
544 | break; |
545 | default: | |
546 | return NULL; | |
547 | } | |
548 | return &xhci->ports[index]; | |
549 | } | |
550 | ||
4c4abe7c | 551 | static void xhci_intx_update(XHCIState *xhci) |
62c6ae04 | 552 | { |
9b7d3334 | 553 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
62c6ae04 HM |
554 | int level = 0; |
555 | ||
9b7d3334 AF |
556 | if (msix_enabled(pci_dev) || |
557 | msi_enabled(pci_dev)) { | |
4c4abe7c GH |
558 | return; |
559 | } | |
560 | ||
962d11e1 GH |
561 | if (xhci->intr[0].iman & IMAN_IP && |
562 | xhci->intr[0].iman & IMAN_IE && | |
215bff17 | 563 | xhci->usbcmd & USBCMD_INTE) { |
62c6ae04 HM |
564 | level = 1; |
565 | } | |
566 | ||
4c4abe7c | 567 | trace_usb_xhci_irq_intx(level); |
9e64f8a3 | 568 | pci_set_irq(pci_dev, level); |
4c4abe7c GH |
569 | } |
570 | ||
962d11e1 | 571 | static void xhci_msix_update(XHCIState *xhci, int v) |
4c47f800 | 572 | { |
9b7d3334 | 573 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
4c47f800 GH |
574 | bool enabled; |
575 | ||
9b7d3334 | 576 | if (!msix_enabled(pci_dev)) { |
4c47f800 GH |
577 | return; |
578 | } | |
579 | ||
962d11e1 GH |
580 | enabled = xhci->intr[v].iman & IMAN_IE; |
581 | if (enabled == xhci->intr[v].msix_used) { | |
4c47f800 GH |
582 | return; |
583 | } | |
584 | ||
585 | if (enabled) { | |
962d11e1 | 586 | trace_usb_xhci_irq_msix_use(v); |
9b7d3334 | 587 | msix_vector_use(pci_dev, v); |
962d11e1 | 588 | xhci->intr[v].msix_used = true; |
4c47f800 | 589 | } else { |
962d11e1 | 590 | trace_usb_xhci_irq_msix_unuse(v); |
9b7d3334 | 591 | msix_vector_unuse(pci_dev, v); |
962d11e1 | 592 | xhci->intr[v].msix_used = false; |
4c47f800 GH |
593 | } |
594 | } | |
595 | ||
962d11e1 | 596 | static void xhci_intr_raise(XHCIState *xhci, int v) |
4c4abe7c | 597 | { |
9b7d3334 | 598 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
7da76e12 | 599 | bool pending = (xhci->intr[v].erdp_low & ERDP_EHB); |
9b7d3334 | 600 | |
962d11e1 GH |
601 | xhci->intr[v].erdp_low |= ERDP_EHB; |
602 | xhci->intr[v].iman |= IMAN_IP; | |
2cae4119 GH |
603 | xhci->usbsts |= USBSTS_EINT; |
604 | ||
7da76e12 GH |
605 | if (pending) { |
606 | return; | |
607 | } | |
962d11e1 | 608 | if (!(xhci->intr[v].iman & IMAN_IE)) { |
4c4abe7c GH |
609 | return; |
610 | } | |
611 | ||
612 | if (!(xhci->usbcmd & USBCMD_INTE)) { | |
613 | return; | |
614 | } | |
615 | ||
9b7d3334 | 616 | if (msix_enabled(pci_dev)) { |
962d11e1 | 617 | trace_usb_xhci_irq_msix(v); |
9b7d3334 | 618 | msix_notify(pci_dev, v); |
4c47f800 GH |
619 | return; |
620 | } | |
621 | ||
9b7d3334 | 622 | if (msi_enabled(pci_dev)) { |
962d11e1 | 623 | trace_usb_xhci_irq_msi(v); |
9b7d3334 | 624 | msi_notify(pci_dev, v); |
4c4abe7c | 625 | return; |
62c6ae04 | 626 | } |
4c4abe7c | 627 | |
962d11e1 GH |
628 | if (v == 0) { |
629 | trace_usb_xhci_irq_intx(1); | |
9e64f8a3 | 630 | pci_irq_assert(pci_dev); |
962d11e1 | 631 | } |
62c6ae04 HM |
632 | } |
633 | ||
634 | static inline int xhci_running(XHCIState *xhci) | |
635 | { | |
898248a3 | 636 | return !(xhci->usbsts & USBSTS_HCH); |
62c6ae04 HM |
637 | } |
638 | ||
639 | static void xhci_die(XHCIState *xhci) | |
640 | { | |
641 | xhci->usbsts |= USBSTS_HCE; | |
d6bb65fc | 642 | DPRINTF("xhci: asserted controller error\n"); |
62c6ae04 HM |
643 | } |
644 | ||
962d11e1 | 645 | static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) |
62c6ae04 | 646 | { |
9b7d3334 | 647 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
962d11e1 | 648 | XHCIInterrupter *intr = &xhci->intr[v]; |
62c6ae04 | 649 | XHCITRB ev_trb; |
59a70ccd | 650 | dma_addr_t addr; |
62c6ae04 HM |
651 | |
652 | ev_trb.parameter = cpu_to_le64(event->ptr); | |
653 | ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); | |
654 | ev_trb.control = (event->slotid << 24) | (event->epid << 16) | | |
655 | event->flags | (event->type << TRB_TYPE_SHIFT); | |
962d11e1 | 656 | if (intr->er_pcs) { |
62c6ae04 HM |
657 | ev_trb.control |= TRB_C; |
658 | } | |
659 | ev_trb.control = cpu_to_le32(ev_trb.control); | |
660 | ||
962d11e1 | 661 | trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), |
873123fe GH |
662 | event_name(event), ev_trb.parameter, |
663 | ev_trb.status, ev_trb.control); | |
62c6ae04 | 664 | |
962d11e1 | 665 | addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; |
9b7d3334 | 666 | pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); |
62c6ae04 | 667 | |
962d11e1 GH |
668 | intr->er_ep_idx++; |
669 | if (intr->er_ep_idx >= intr->er_size) { | |
670 | intr->er_ep_idx = 0; | |
671 | intr->er_pcs = !intr->er_pcs; | |
62c6ae04 HM |
672 | } |
673 | } | |
674 | ||
962d11e1 | 675 | static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) |
62c6ae04 | 676 | { |
2d1de850 | 677 | XHCIInterrupter *intr; |
59a70ccd | 678 | dma_addr_t erdp; |
62c6ae04 HM |
679 | unsigned int dp_idx; |
680 | ||
91062ae0 GH |
681 | if (v >= xhci->numintrs) { |
682 | DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); | |
2d1de850 GH |
683 | return; |
684 | } | |
685 | intr = &xhci->intr[v]; | |
686 | ||
962d11e1 GH |
687 | erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
688 | if (erdp < intr->er_start || | |
689 | erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { | |
d6bb65fc GH |
690 | DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
691 | DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", | |
962d11e1 | 692 | v, intr->er_start, intr->er_size); |
62c6ae04 HM |
693 | xhci_die(xhci); |
694 | return; | |
695 | } | |
696 | ||
962d11e1 GH |
697 | dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
698 | assert(dp_idx < intr->er_size); | |
62c6ae04 | 699 | |
898248a3 GH |
700 | if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) { |
701 | DPRINTF("xhci: ER %d full, send ring full error\n", v); | |
62c6ae04 | 702 | XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; |
898248a3 GH |
703 | xhci_write_event(xhci, &full, v); |
704 | } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) { | |
705 | DPRINTF("xhci: ER %d full, drop event\n", v); | |
62c6ae04 | 706 | } else { |
962d11e1 | 707 | xhci_write_event(xhci, event, v); |
62c6ae04 HM |
708 | } |
709 | ||
962d11e1 | 710 | xhci_intr_raise(xhci, v); |
62c6ae04 HM |
711 | } |
712 | ||
713 | static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, | |
59a70ccd | 714 | dma_addr_t base) |
62c6ae04 | 715 | { |
62c6ae04 HM |
716 | ring->dequeue = base; |
717 | ring->ccs = 1; | |
718 | } | |
719 | ||
720 | static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, | |
59a70ccd | 721 | dma_addr_t *addr) |
62c6ae04 | 722 | { |
9b7d3334 | 723 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
05f43d44 | 724 | uint32_t link_cnt = 0; |
9b7d3334 | 725 | |
62c6ae04 HM |
726 | while (1) { |
727 | TRBType type; | |
9b7d3334 | 728 | pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); |
62c6ae04 HM |
729 | trb->addr = ring->dequeue; |
730 | trb->ccs = ring->ccs; | |
731 | le64_to_cpus(&trb->parameter); | |
732 | le32_to_cpus(&trb->status); | |
733 | le32_to_cpus(&trb->control); | |
734 | ||
0703a4a7 GH |
735 | trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), |
736 | trb->parameter, trb->status, trb->control); | |
62c6ae04 HM |
737 | |
738 | if ((trb->control & TRB_C) != ring->ccs) { | |
739 | return 0; | |
740 | } | |
741 | ||
742 | type = TRB_TYPE(*trb); | |
743 | ||
744 | if (type != TR_LINK) { | |
745 | if (addr) { | |
746 | *addr = ring->dequeue; | |
747 | } | |
748 | ring->dequeue += TRB_SIZE; | |
749 | return type; | |
750 | } else { | |
05f43d44 | 751 | if (++link_cnt > TRB_LINK_LIMIT) { |
f89b60f6 | 752 | trace_usb_xhci_enforced_limit("trb-link"); |
05f43d44 GH |
753 | return 0; |
754 | } | |
62c6ae04 HM |
755 | ring->dequeue = xhci_mask64(trb->parameter); |
756 | if (trb->control & TRB_LK_TC) { | |
757 | ring->ccs = !ring->ccs; | |
758 | } | |
759 | } | |
760 | } | |
761 | } | |
762 | ||
763 | static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) | |
764 | { | |
9b7d3334 | 765 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
62c6ae04 HM |
766 | XHCITRB trb; |
767 | int length = 0; | |
59a70ccd | 768 | dma_addr_t dequeue = ring->dequeue; |
62c6ae04 HM |
769 | bool ccs = ring->ccs; |
770 | /* hack to bundle together the two/three TDs that make a setup transfer */ | |
771 | bool control_td_set = 0; | |
05f43d44 | 772 | uint32_t link_cnt = 0; |
62c6ae04 HM |
773 | |
774 | while (1) { | |
775 | TRBType type; | |
9b7d3334 | 776 | pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); |
62c6ae04 HM |
777 | le64_to_cpus(&trb.parameter); |
778 | le32_to_cpus(&trb.status); | |
779 | le32_to_cpus(&trb.control); | |
780 | ||
62c6ae04 HM |
781 | if ((trb.control & TRB_C) != ccs) { |
782 | return -length; | |
783 | } | |
784 | ||
785 | type = TRB_TYPE(trb); | |
786 | ||
787 | if (type == TR_LINK) { | |
05f43d44 GH |
788 | if (++link_cnt > TRB_LINK_LIMIT) { |
789 | return -length; | |
790 | } | |
62c6ae04 HM |
791 | dequeue = xhci_mask64(trb.parameter); |
792 | if (trb.control & TRB_LK_TC) { | |
793 | ccs = !ccs; | |
794 | } | |
795 | continue; | |
796 | } | |
797 | ||
798 | length += 1; | |
799 | dequeue += TRB_SIZE; | |
800 | ||
801 | if (type == TR_SETUP) { | |
802 | control_td_set = 1; | |
803 | } else if (type == TR_STATUS) { | |
804 | control_td_set = 0; | |
805 | } | |
806 | ||
807 | if (!control_td_set && !(trb.control & TRB_TR_CH)) { | |
808 | return length; | |
809 | } | |
810 | } | |
811 | } | |
812 | ||
962d11e1 | 813 | static void xhci_er_reset(XHCIState *xhci, int v) |
62c6ae04 | 814 | { |
962d11e1 | 815 | XHCIInterrupter *intr = &xhci->intr[v]; |
62c6ae04 | 816 | XHCIEvRingSeg seg; |
6100dda7 | 817 | dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); |
62c6ae04 | 818 | |
6100dda7 | 819 | if (intr->erstsz == 0 || erstba == 0) { |
e099ad4b GH |
820 | /* disabled */ |
821 | intr->er_start = 0; | |
822 | intr->er_size = 0; | |
823 | return; | |
824 | } | |
62c6ae04 | 825 | /* cache the (sole) event ring segment location */ |
962d11e1 | 826 | if (intr->erstsz != 1) { |
d6bb65fc | 827 | DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); |
62c6ae04 HM |
828 | xhci_die(xhci); |
829 | return; | |
830 | } | |
9b7d3334 | 831 | pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); |
62c6ae04 HM |
832 | le32_to_cpus(&seg.addr_low); |
833 | le32_to_cpus(&seg.addr_high); | |
834 | le32_to_cpus(&seg.size); | |
835 | if (seg.size < 16 || seg.size > 4096) { | |
d6bb65fc | 836 | DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); |
62c6ae04 HM |
837 | xhci_die(xhci); |
838 | return; | |
839 | } | |
962d11e1 GH |
840 | intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); |
841 | intr->er_size = seg.size; | |
62c6ae04 | 842 | |
962d11e1 GH |
843 | intr->er_ep_idx = 0; |
844 | intr->er_pcs = 1; | |
62c6ae04 | 845 | |
962d11e1 GH |
846 | DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", |
847 | v, intr->er_start, intr->er_size); | |
62c6ae04 HM |
848 | } |
849 | ||
850 | static void xhci_run(XHCIState *xhci) | |
851 | { | |
fc0ddaca | 852 | trace_usb_xhci_run(); |
62c6ae04 | 853 | xhci->usbsts &= ~USBSTS_HCH; |
bc72ad67 | 854 | xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
62c6ae04 HM |
855 | } |
856 | ||
857 | static void xhci_stop(XHCIState *xhci) | |
858 | { | |
fc0ddaca | 859 | trace_usb_xhci_stop(); |
62c6ae04 HM |
860 | xhci->usbsts |= USBSTS_HCH; |
861 | xhci->crcr_low &= ~CRCR_CRR; | |
862 | } | |
863 | ||
024426ac GH |
864 | static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, |
865 | dma_addr_t base) | |
866 | { | |
867 | XHCIStreamContext *stctx; | |
868 | unsigned int i; | |
869 | ||
870 | stctx = g_new0(XHCIStreamContext, count); | |
871 | for (i = 0; i < count; i++) { | |
872 | stctx[i].pctx = base + i * 16; | |
873 | stctx[i].sct = -1; | |
874 | } | |
875 | return stctx; | |
876 | } | |
877 | ||
878 | static void xhci_reset_streams(XHCIEPContext *epctx) | |
879 | { | |
880 | unsigned int i; | |
881 | ||
882 | for (i = 0; i < epctx->nr_pstreams; i++) { | |
883 | epctx->pstreams[i].sct = -1; | |
024426ac GH |
884 | } |
885 | } | |
886 | ||
887 | static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) | |
888 | { | |
889 | assert(epctx->pstreams == NULL); | |
f90e160b | 890 | epctx->nr_pstreams = 2 << epctx->max_pstreams; |
024426ac GH |
891 | epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); |
892 | } | |
893 | ||
894 | static void xhci_free_streams(XHCIEPContext *epctx) | |
895 | { | |
024426ac GH |
896 | assert(epctx->pstreams != NULL); |
897 | ||
024426ac GH |
898 | g_free(epctx->pstreams); |
899 | epctx->pstreams = NULL; | |
900 | epctx->nr_pstreams = 0; | |
901 | } | |
902 | ||
72391da5 HG |
903 | static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, |
904 | unsigned int slotid, | |
905 | uint32_t epmask, | |
906 | XHCIEPContext **epctxs, | |
907 | USBEndpoint **eps) | |
908 | { | |
909 | XHCISlot *slot; | |
910 | XHCIEPContext *epctx; | |
911 | USBEndpoint *ep; | |
912 | int i, j; | |
913 | ||
914 | assert(slotid >= 1 && slotid <= xhci->numslots); | |
915 | ||
916 | slot = &xhci->slots[slotid - 1]; | |
917 | ||
918 | for (i = 2, j = 0; i <= 31; i++) { | |
3d80365b | 919 | if (!(epmask & (1u << i))) { |
72391da5 HG |
920 | continue; |
921 | } | |
922 | ||
923 | epctx = slot->eps[i - 1]; | |
070eeef9 | 924 | ep = xhci_epid_to_usbep(epctx); |
72391da5 HG |
925 | if (!epctx || !epctx->nr_pstreams || !ep) { |
926 | continue; | |
927 | } | |
928 | ||
929 | if (epctxs) { | |
930 | epctxs[j] = epctx; | |
931 | } | |
932 | eps[j++] = ep; | |
933 | } | |
934 | return j; | |
935 | } | |
936 | ||
937 | static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, | |
938 | uint32_t epmask) | |
939 | { | |
940 | USBEndpoint *eps[30]; | |
941 | int nr_eps; | |
942 | ||
943 | nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); | |
944 | if (nr_eps) { | |
945 | usb_device_free_streams(eps[0]->dev, eps, nr_eps); | |
946 | } | |
947 | } | |
948 | ||
949 | static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, | |
950 | uint32_t epmask) | |
951 | { | |
952 | XHCIEPContext *epctxs[30]; | |
953 | USBEndpoint *eps[30]; | |
954 | int i, r, nr_eps, req_nr_streams, dev_max_streams; | |
955 | ||
956 | nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, | |
957 | eps); | |
958 | if (nr_eps == 0) { | |
959 | return CC_SUCCESS; | |
960 | } | |
961 | ||
962 | req_nr_streams = epctxs[0]->nr_pstreams; | |
963 | dev_max_streams = eps[0]->max_streams; | |
964 | ||
965 | for (i = 1; i < nr_eps; i++) { | |
966 | /* | |
967 | * HdG: I don't expect these to ever trigger, but if they do we need | |
968 | * to come up with another solution, ie group identical endpoints | |
969 | * together and make an usb_device_alloc_streams call per group. | |
970 | */ | |
971 | if (epctxs[i]->nr_pstreams != req_nr_streams) { | |
972 | FIXME("guest streams config not identical for all eps"); | |
973 | return CC_RESOURCE_ERROR; | |
974 | } | |
975 | if (eps[i]->max_streams != dev_max_streams) { | |
976 | FIXME("device streams config not identical for all eps"); | |
977 | return CC_RESOURCE_ERROR; | |
978 | } | |
979 | } | |
980 | ||
981 | /* | |
982 | * max-streams in both the device descriptor and in the controller is a | |
983 | * power of 2. But stream id 0 is reserved, so if a device can do up to 4 | |
984 | * streams the guest will ask for 5 rounded up to the next power of 2 which | |
985 | * becomes 8. For emulated devices usb_device_alloc_streams is a nop. | |
986 | * | |
987 | * For redirected devices however this is an issue, as there we must ask | |
988 | * the real xhci controller to alloc streams, and the host driver for the | |
989 | * real xhci controller will likely disallow allocating more streams then | |
990 | * the device can handle. | |
991 | * | |
992 | * So we limit the requested nr_streams to the maximum number the device | |
993 | * can handle. | |
994 | */ | |
995 | if (req_nr_streams > dev_max_streams) { | |
996 | req_nr_streams = dev_max_streams; | |
997 | } | |
998 | ||
999 | r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); | |
1000 | if (r != 0) { | |
d6bb65fc | 1001 | DPRINTF("xhci: alloc streams failed\n"); |
72391da5 HG |
1002 | return CC_RESOURCE_ERROR; |
1003 | } | |
1004 | ||
1005 | return CC_SUCCESS; | |
1006 | } | |
1007 | ||
024426ac GH |
1008 | static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, |
1009 | unsigned int streamid, | |
1010 | uint32_t *cc_error) | |
1011 | { | |
1012 | XHCIStreamContext *sctx; | |
1013 | dma_addr_t base; | |
1014 | uint32_t ctx[2], sct; | |
1015 | ||
1016 | assert(streamid != 0); | |
1017 | if (epctx->lsa) { | |
1018 | if (streamid >= epctx->nr_pstreams) { | |
1019 | *cc_error = CC_INVALID_STREAM_ID_ERROR; | |
1020 | return NULL; | |
1021 | } | |
1022 | sctx = epctx->pstreams + streamid; | |
1023 | } else { | |
1024 | FIXME("secondary streams not implemented yet"); | |
1025 | } | |
1026 | ||
1027 | if (sctx->sct == -1) { | |
1028 | xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); | |
024426ac GH |
1029 | sct = (ctx[0] >> 1) & 0x07; |
1030 | if (epctx->lsa && sct != 1) { | |
1031 | *cc_error = CC_INVALID_STREAM_TYPE_ERROR; | |
1032 | return NULL; | |
1033 | } | |
1034 | sctx->sct = sct; | |
1035 | base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); | |
1036 | xhci_ring_init(epctx->xhci, &sctx->ring, base); | |
1037 | } | |
1038 | return sctx; | |
1039 | } | |
1040 | ||
62c6ae04 | 1041 | static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
024426ac | 1042 | XHCIStreamContext *sctx, uint32_t state) |
62c6ae04 | 1043 | { |
c90daa1c | 1044 | XHCIRing *ring = NULL; |
62c6ae04 | 1045 | uint32_t ctx[5]; |
024426ac | 1046 | uint32_t ctx2[2]; |
62c6ae04 | 1047 | |
616b5d53 | 1048 | xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); |
62c6ae04 HM |
1049 | ctx[0] &= ~EP_STATE_MASK; |
1050 | ctx[0] |= state; | |
024426ac GH |
1051 | |
1052 | /* update ring dequeue ptr */ | |
1053 | if (epctx->nr_pstreams) { | |
1054 | if (sctx != NULL) { | |
c90daa1c | 1055 | ring = &sctx->ring; |
024426ac GH |
1056 | xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); |
1057 | ctx2[0] &= 0xe; | |
1058 | ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; | |
1059 | ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; | |
1060 | xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); | |
1061 | } | |
1062 | } else { | |
c90daa1c HG |
1063 | ring = &epctx->ring; |
1064 | } | |
1065 | if (ring) { | |
1066 | ctx[2] = ring->dequeue | ring->ccs; | |
1067 | ctx[3] = (ring->dequeue >> 16) >> 16; | |
1068 | ||
024426ac GH |
1069 | DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", |
1070 | epctx->pctx, state, ctx[3], ctx[2]); | |
1071 | } | |
1072 | ||
616b5d53 | 1073 | xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); |
1c82392a GH |
1074 | if (epctx->state != state) { |
1075 | trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, | |
1076 | ep_state_name(epctx->state), | |
1077 | ep_state_name(state)); | |
1078 | } | |
62c6ae04 HM |
1079 | epctx->state = state; |
1080 | } | |
1081 | ||
3d139684 GH |
1082 | static void xhci_ep_kick_timer(void *opaque) |
1083 | { | |
1084 | XHCIEPContext *epctx = opaque; | |
3a533ee8 | 1085 | xhci_kick_epctx(epctx, 0); |
3d139684 GH |
1086 | } |
1087 | ||
492b21f6 GH |
1088 | static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, |
1089 | unsigned int slotid, | |
1090 | unsigned int epid) | |
1091 | { | |
1092 | XHCIEPContext *epctx; | |
492b21f6 GH |
1093 | |
1094 | epctx = g_new0(XHCIEPContext, 1); | |
1095 | epctx->xhci = xhci; | |
1096 | epctx->slotid = slotid; | |
1097 | epctx->epid = epid; | |
1098 | ||
94b037f2 | 1099 | QTAILQ_INIT(&epctx->transfers); |
bc72ad67 | 1100 | epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); |
492b21f6 GH |
1101 | |
1102 | return epctx; | |
1103 | } | |
1104 | ||
003e15a1 GH |
1105 | static void xhci_init_epctx(XHCIEPContext *epctx, |
1106 | dma_addr_t pctx, uint32_t *ctx) | |
62c6ae04 | 1107 | { |
59a70ccd | 1108 | dma_addr_t dequeue; |
62c6ae04 | 1109 | |
62c6ae04 | 1110 | dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); |
62c6ae04 HM |
1111 | |
1112 | epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; | |
62c6ae04 HM |
1113 | epctx->pctx = pctx; |
1114 | epctx->max_psize = ctx[1]>>16; | |
1115 | epctx->max_psize *= 1+((ctx[1]>>8)&0xff); | |
2aa6bfcb | 1116 | epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; |
024426ac | 1117 | epctx->lsa = (ctx[0] >> 15) & 1; |
024426ac GH |
1118 | if (epctx->max_pstreams) { |
1119 | xhci_alloc_streams(epctx, dequeue); | |
1120 | } else { | |
003e15a1 | 1121 | xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); |
024426ac GH |
1122 | epctx->ring.ccs = ctx[2] & 1; |
1123 | } | |
62c6ae04 | 1124 | |
ca716278 | 1125 | epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); |
003e15a1 GH |
1126 | } |
1127 | ||
1128 | static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, | |
1129 | unsigned int epid, dma_addr_t pctx, | |
1130 | uint32_t *ctx) | |
1131 | { | |
1132 | XHCISlot *slot; | |
1133 | XHCIEPContext *epctx; | |
1134 | ||
1135 | trace_usb_xhci_ep_enable(slotid, epid); | |
1136 | assert(slotid >= 1 && slotid <= xhci->numslots); | |
1137 | assert(epid >= 1 && epid <= 31); | |
1138 | ||
1139 | slot = &xhci->slots[slotid-1]; | |
1140 | if (slot->eps[epid-1]) { | |
1141 | xhci_disable_ep(xhci, slotid, epid); | |
1142 | } | |
1143 | ||
1144 | epctx = xhci_alloc_epctx(xhci, slotid, epid); | |
1145 | slot->eps[epid-1] = epctx; | |
1146 | xhci_init_epctx(epctx, pctx, ctx); | |
1147 | ||
8c244210 GA |
1148 | DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " |
1149 | "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); | |
1150 | ||
3d139684 | 1151 | epctx->mfindex_last = 0; |
3d139684 | 1152 | |
62c6ae04 HM |
1153 | epctx->state = EP_RUNNING; |
1154 | ctx[0] &= ~EP_STATE_MASK; | |
1155 | ctx[0] |= EP_RUNNING; | |
1156 | ||
1157 | return CC_SUCCESS; | |
1158 | } | |
1159 | ||
94b037f2 GH |
1160 | static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx, |
1161 | uint32_t length) | |
1162 | { | |
1163 | uint32_t limit = epctx->nr_pstreams + 16; | |
1164 | XHCITransfer *xfer; | |
1165 | ||
1166 | if (epctx->xfer_count >= limit) { | |
1167 | return NULL; | |
1168 | } | |
1169 | ||
1170 | xfer = g_new0(XHCITransfer, 1); | |
94b037f2 | 1171 | xfer->epctx = epctx; |
94b037f2 GH |
1172 | xfer->trbs = g_new(XHCITRB, length); |
1173 | xfer->trb_count = length; | |
1174 | usb_packet_init(&xfer->packet); | |
1175 | ||
1176 | QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next); | |
1177 | epctx->xfer_count++; | |
1178 | ||
1179 | return xfer; | |
1180 | } | |
1181 | ||
1182 | static void xhci_ep_free_xfer(XHCITransfer *xfer) | |
1183 | { | |
1184 | QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next); | |
1185 | xfer->epctx->xfer_count--; | |
1186 | ||
1187 | usb_packet_cleanup(&xfer->packet); | |
1188 | g_free(xfer->trbs); | |
1189 | g_free(xfer); | |
1190 | } | |
1191 | ||
582d6f4a | 1192 | static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) |
3151f209 HG |
1193 | { |
1194 | int killed = 0; | |
1195 | ||
582d6f4a HG |
1196 | if (report && (t->running_async || t->running_retry)) { |
1197 | t->status = report; | |
1198 | xhci_xfer_report(t); | |
1199 | } | |
1200 | ||
3151f209 HG |
1201 | if (t->running_async) { |
1202 | usb_cancel_packet(&t->packet); | |
1203 | t->running_async = 0; | |
3151f209 HG |
1204 | killed = 1; |
1205 | } | |
1206 | if (t->running_retry) { | |
5612564e GH |
1207 | if (t->epctx) { |
1208 | t->epctx->retry = NULL; | |
1209 | timer_del(t->epctx->kick_timer); | |
3151f209 HG |
1210 | } |
1211 | t->running_retry = 0; | |
582d6f4a | 1212 | killed = 1; |
3151f209 | 1213 | } |
ef1e1e07 | 1214 | g_free(t->trbs); |
3151f209 HG |
1215 | |
1216 | t->trbs = NULL; | |
94b037f2 | 1217 | t->trb_count = 0; |
3151f209 HG |
1218 | |
1219 | return killed; | |
1220 | } | |
1221 | ||
62c6ae04 | 1222 | static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, |
582d6f4a | 1223 | unsigned int epid, TRBCCode report) |
62c6ae04 HM |
1224 | { |
1225 | XHCISlot *slot; | |
1226 | XHCIEPContext *epctx; | |
94b037f2 GH |
1227 | XHCITransfer *xfer; |
1228 | int killed = 0; | |
f79738b0 | 1229 | USBEndpoint *ep = NULL; |
91062ae0 | 1230 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1231 | assert(epid >= 1 && epid <= 31); |
1232 | ||
1233 | DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); | |
1234 | ||
1235 | slot = &xhci->slots[slotid-1]; | |
1236 | ||
1237 | if (!slot->eps[epid-1]) { | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | epctx = slot->eps[epid-1]; | |
1242 | ||
94b037f2 GH |
1243 | for (;;) { |
1244 | xfer = QTAILQ_FIRST(&epctx->transfers); | |
1245 | if (xfer == NULL) { | |
1246 | break; | |
1247 | } | |
1248 | killed += xhci_ep_nuke_one_xfer(xfer, report); | |
582d6f4a HG |
1249 | if (killed) { |
1250 | report = 0; /* Only report once */ | |
1251 | } | |
94b037f2 | 1252 | xhci_ep_free_xfer(xfer); |
62c6ae04 | 1253 | } |
518ad5f2 | 1254 | |
070eeef9 | 1255 | ep = xhci_epid_to_usbep(epctx); |
f79738b0 HG |
1256 | if (ep) { |
1257 | usb_device_ep_stopped(ep->dev, ep); | |
1258 | } | |
62c6ae04 HM |
1259 | return killed; |
1260 | } | |
1261 | ||
1262 | static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, | |
1263 | unsigned int epid) | |
1264 | { | |
1265 | XHCISlot *slot; | |
1266 | XHCIEPContext *epctx; | |
1267 | ||
c1f6b493 | 1268 | trace_usb_xhci_ep_disable(slotid, epid); |
91062ae0 | 1269 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1270 | assert(epid >= 1 && epid <= 31); |
1271 | ||
62c6ae04 HM |
1272 | slot = &xhci->slots[slotid-1]; |
1273 | ||
1274 | if (!slot->eps[epid-1]) { | |
1275 | DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); | |
1276 | return CC_SUCCESS; | |
1277 | } | |
1278 | ||
582d6f4a | 1279 | xhci_ep_nuke_xfers(xhci, slotid, epid, 0); |
62c6ae04 HM |
1280 | |
1281 | epctx = slot->eps[epid-1]; | |
1282 | ||
024426ac GH |
1283 | if (epctx->nr_pstreams) { |
1284 | xhci_free_streams(epctx); | |
1285 | } | |
1286 | ||
491d68d9 RK |
1287 | /* only touch guest RAM if we're not resetting the HC */ |
1288 | if (xhci->dcbaap_low || xhci->dcbaap_high) { | |
1289 | xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); | |
1290 | } | |
62c6ae04 | 1291 | |
bc72ad67 | 1292 | timer_free(epctx->kick_timer); |
62c6ae04 HM |
1293 | g_free(epctx); |
1294 | slot->eps[epid-1] = NULL; | |
1295 | ||
1296 | return CC_SUCCESS; | |
1297 | } | |
1298 | ||
1299 | static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, | |
1300 | unsigned int epid) | |
1301 | { | |
1302 | XHCISlot *slot; | |
1303 | XHCIEPContext *epctx; | |
1304 | ||
c1f6b493 | 1305 | trace_usb_xhci_ep_stop(slotid, epid); |
91062ae0 | 1306 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1307 | |
1308 | if (epid < 1 || epid > 31) { | |
d6bb65fc | 1309 | DPRINTF("xhci: bad ep %d\n", epid); |
62c6ae04 HM |
1310 | return CC_TRB_ERROR; |
1311 | } | |
1312 | ||
1313 | slot = &xhci->slots[slotid-1]; | |
1314 | ||
1315 | if (!slot->eps[epid-1]) { | |
1316 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1317 | return CC_EP_NOT_ENABLED_ERROR; | |
1318 | } | |
1319 | ||
582d6f4a | 1320 | if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { |
d6bb65fc | 1321 | DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " |
62c6ae04 HM |
1322 | "data might be lost\n"); |
1323 | } | |
1324 | ||
1325 | epctx = slot->eps[epid-1]; | |
1326 | ||
024426ac GH |
1327 | xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); |
1328 | ||
1329 | if (epctx->nr_pstreams) { | |
1330 | xhci_reset_streams(epctx); | |
1331 | } | |
62c6ae04 HM |
1332 | |
1333 | return CC_SUCCESS; | |
1334 | } | |
1335 | ||
1336 | static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, | |
1337 | unsigned int epid) | |
1338 | { | |
1339 | XHCISlot *slot; | |
1340 | XHCIEPContext *epctx; | |
62c6ae04 | 1341 | |
c1f6b493 | 1342 | trace_usb_xhci_ep_reset(slotid, epid); |
91062ae0 | 1343 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 1344 | |
62c6ae04 | 1345 | if (epid < 1 || epid > 31) { |
d6bb65fc | 1346 | DPRINTF("xhci: bad ep %d\n", epid); |
62c6ae04 HM |
1347 | return CC_TRB_ERROR; |
1348 | } | |
1349 | ||
1350 | slot = &xhci->slots[slotid-1]; | |
1351 | ||
1352 | if (!slot->eps[epid-1]) { | |
1353 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1354 | return CC_EP_NOT_ENABLED_ERROR; | |
1355 | } | |
1356 | ||
1357 | epctx = slot->eps[epid-1]; | |
1358 | ||
1359 | if (epctx->state != EP_HALTED) { | |
d6bb65fc | 1360 | DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", |
62c6ae04 HM |
1361 | epid, epctx->state); |
1362 | return CC_CONTEXT_STATE_ERROR; | |
1363 | } | |
1364 | ||
582d6f4a | 1365 | if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { |
d6bb65fc | 1366 | DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " |
62c6ae04 HM |
1367 | "data might be lost\n"); |
1368 | } | |
1369 | ||
75cc1c1f | 1370 | if (!xhci->slots[slotid-1].uport || |
de9de157 HG |
1371 | !xhci->slots[slotid-1].uport->dev || |
1372 | !xhci->slots[slotid-1].uport->dev->attached) { | |
62c6ae04 HM |
1373 | return CC_USB_TRANSACTION_ERROR; |
1374 | } | |
1375 | ||
024426ac GH |
1376 | xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); |
1377 | ||
1378 | if (epctx->nr_pstreams) { | |
1379 | xhci_reset_streams(epctx); | |
1380 | } | |
62c6ae04 HM |
1381 | |
1382 | return CC_SUCCESS; | |
1383 | } | |
1384 | ||
1385 | static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, | |
024426ac GH |
1386 | unsigned int epid, unsigned int streamid, |
1387 | uint64_t pdequeue) | |
62c6ae04 HM |
1388 | { |
1389 | XHCISlot *slot; | |
1390 | XHCIEPContext *epctx; | |
024426ac | 1391 | XHCIStreamContext *sctx; |
59a70ccd | 1392 | dma_addr_t dequeue; |
62c6ae04 | 1393 | |
91062ae0 | 1394 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1395 | |
1396 | if (epid < 1 || epid > 31) { | |
d6bb65fc | 1397 | DPRINTF("xhci: bad ep %d\n", epid); |
62c6ae04 HM |
1398 | return CC_TRB_ERROR; |
1399 | } | |
1400 | ||
024426ac | 1401 | trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); |
62c6ae04 HM |
1402 | dequeue = xhci_mask64(pdequeue); |
1403 | ||
1404 | slot = &xhci->slots[slotid-1]; | |
1405 | ||
1406 | if (!slot->eps[epid-1]) { | |
1407 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1408 | return CC_EP_NOT_ENABLED_ERROR; | |
1409 | } | |
1410 | ||
1411 | epctx = slot->eps[epid-1]; | |
1412 | ||
62c6ae04 | 1413 | if (epctx->state != EP_STOPPED) { |
d6bb65fc | 1414 | DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); |
62c6ae04 HM |
1415 | return CC_CONTEXT_STATE_ERROR; |
1416 | } | |
1417 | ||
024426ac GH |
1418 | if (epctx->nr_pstreams) { |
1419 | uint32_t err; | |
1420 | sctx = xhci_find_stream(epctx, streamid, &err); | |
1421 | if (sctx == NULL) { | |
1422 | return err; | |
1423 | } | |
1424 | xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); | |
1425 | sctx->ring.ccs = dequeue & 1; | |
1426 | } else { | |
1427 | sctx = NULL; | |
1428 | xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); | |
1429 | epctx->ring.ccs = dequeue & 1; | |
1430 | } | |
62c6ae04 | 1431 | |
024426ac | 1432 | xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); |
62c6ae04 HM |
1433 | |
1434 | return CC_SUCCESS; | |
1435 | } | |
1436 | ||
a6fb2ddb | 1437 | static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) |
62c6ae04 | 1438 | { |
5612564e | 1439 | XHCIState *xhci = xfer->epctx->xhci; |
d5a15814 | 1440 | int i; |
62c6ae04 | 1441 | |
a6fb2ddb | 1442 | xfer->int_req = false; |
9b7d3334 | 1443 | pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); |
62c6ae04 HM |
1444 | for (i = 0; i < xfer->trb_count; i++) { |
1445 | XHCITRB *trb = &xfer->trbs[i]; | |
59a70ccd | 1446 | dma_addr_t addr; |
62c6ae04 HM |
1447 | unsigned int chunk = 0; |
1448 | ||
a6fb2ddb HG |
1449 | if (trb->control & TRB_TR_IOC) { |
1450 | xfer->int_req = true; | |
1451 | } | |
1452 | ||
62c6ae04 HM |
1453 | switch (TRB_TYPE(*trb)) { |
1454 | case TR_DATA: | |
1455 | if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { | |
d6bb65fc | 1456 | DPRINTF("xhci: data direction mismatch for TR_DATA\n"); |
d5a15814 | 1457 | goto err; |
62c6ae04 HM |
1458 | } |
1459 | /* fallthrough */ | |
1460 | case TR_NORMAL: | |
1461 | case TR_ISOCH: | |
1462 | addr = xhci_mask64(trb->parameter); | |
d5a15814 GH |
1463 | chunk = trb->status & 0x1ffff; |
1464 | if (trb->control & TRB_TR_IDT) { | |
1465 | if (chunk > 8 || in_xfer) { | |
d6bb65fc | 1466 | DPRINTF("xhci: invalid immediate data TRB\n"); |
d5a15814 GH |
1467 | goto err; |
1468 | } | |
1469 | qemu_sglist_add(&xfer->sgl, trb->addr, chunk); | |
1470 | } else { | |
1471 | qemu_sglist_add(&xfer->sgl, addr, chunk); | |
1472 | } | |
1473 | break; | |
1474 | } | |
1475 | } | |
1476 | ||
d5a15814 GH |
1477 | return 0; |
1478 | ||
1479 | err: | |
1480 | qemu_sglist_destroy(&xfer->sgl); | |
1481 | xhci_die(xhci); | |
1482 | return -1; | |
1483 | } | |
1484 | ||
1485 | static void xhci_xfer_unmap(XHCITransfer *xfer) | |
1486 | { | |
1487 | usb_packet_unmap(&xfer->packet, &xfer->sgl); | |
1488 | qemu_sglist_destroy(&xfer->sgl); | |
1489 | } | |
1490 | ||
1491 | static void xhci_xfer_report(XHCITransfer *xfer) | |
1492 | { | |
1493 | uint32_t edtla = 0; | |
1494 | unsigned int left; | |
1495 | bool reported = 0; | |
1496 | bool shortpkt = 0; | |
1497 | XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; | |
5612564e | 1498 | XHCIState *xhci = xfer->epctx->xhci; |
d5a15814 GH |
1499 | int i; |
1500 | ||
9b8251c5 | 1501 | left = xfer->packet.actual_length; |
d5a15814 GH |
1502 | |
1503 | for (i = 0; i < xfer->trb_count; i++) { | |
1504 | XHCITRB *trb = &xfer->trbs[i]; | |
1505 | unsigned int chunk = 0; | |
1506 | ||
1507 | switch (TRB_TYPE(*trb)) { | |
b66ad1f1 HPS |
1508 | case TR_SETUP: |
1509 | chunk = trb->status & 0x1ffff; | |
1510 | if (chunk > 8) { | |
1511 | chunk = 8; | |
1512 | } | |
1513 | break; | |
d5a15814 GH |
1514 | case TR_DATA: |
1515 | case TR_NORMAL: | |
1516 | case TR_ISOCH: | |
62c6ae04 HM |
1517 | chunk = trb->status & 0x1ffff; |
1518 | if (chunk > left) { | |
1519 | chunk = left; | |
d5a15814 GH |
1520 | if (xfer->status == CC_SUCCESS) { |
1521 | shortpkt = 1; | |
62c6ae04 HM |
1522 | } |
1523 | } | |
1524 | left -= chunk; | |
62c6ae04 | 1525 | edtla += chunk; |
62c6ae04 HM |
1526 | break; |
1527 | case TR_STATUS: | |
1528 | reported = 0; | |
1529 | shortpkt = 0; | |
1530 | break; | |
1531 | } | |
1532 | ||
88dbed3f GH |
1533 | if (!reported && ((trb->control & TRB_TR_IOC) || |
1534 | (shortpkt && (trb->control & TRB_TR_ISP)) || | |
1535 | (xfer->status != CC_SUCCESS && left == 0))) { | |
d6fcb293 GH |
1536 | event.slotid = xfer->epctx->slotid; |
1537 | event.epid = xfer->epctx->epid; | |
62c6ae04 HM |
1538 | event.length = (trb->status & 0x1ffff) - chunk; |
1539 | event.flags = 0; | |
1540 | event.ptr = trb->addr; | |
1541 | if (xfer->status == CC_SUCCESS) { | |
1542 | event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; | |
1543 | } else { | |
1544 | event.ccode = xfer->status; | |
1545 | } | |
1546 | if (TRB_TYPE(*trb) == TR_EVDATA) { | |
1547 | event.ptr = trb->parameter; | |
1548 | event.flags |= TRB_EV_ED; | |
1549 | event.length = edtla & 0xffffff; | |
1550 | DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); | |
1551 | edtla = 0; | |
1552 | } | |
2d1de850 | 1553 | xhci_event(xhci, &event, TRB_INTR(*trb)); |
62c6ae04 | 1554 | reported = 1; |
d5a15814 GH |
1555 | if (xfer->status != CC_SUCCESS) { |
1556 | return; | |
1557 | } | |
62c6ae04 | 1558 | } |
df0f1692 GH |
1559 | |
1560 | switch (TRB_TYPE(*trb)) { | |
1561 | case TR_SETUP: | |
1562 | reported = 0; | |
1563 | shortpkt = 0; | |
1564 | break; | |
1565 | } | |
1566 | ||
62c6ae04 | 1567 | } |
62c6ae04 HM |
1568 | } |
1569 | ||
1570 | static void xhci_stall_ep(XHCITransfer *xfer) | |
1571 | { | |
5612564e GH |
1572 | XHCIEPContext *epctx = xfer->epctx; |
1573 | XHCIState *xhci = epctx->xhci; | |
024426ac GH |
1574 | uint32_t err; |
1575 | XHCIStreamContext *sctx; | |
62c6ae04 | 1576 | |
a587c832 YB |
1577 | if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) { |
1578 | /* never halt isoch endpoints, 4.10.2 */ | |
1579 | return; | |
1580 | } | |
1581 | ||
024426ac GH |
1582 | if (epctx->nr_pstreams) { |
1583 | sctx = xhci_find_stream(epctx, xfer->streamid, &err); | |
1584 | if (sctx == NULL) { | |
1585 | return; | |
1586 | } | |
1587 | sctx->ring.dequeue = xfer->trbs[0].addr; | |
1588 | sctx->ring.ccs = xfer->trbs[0].ccs; | |
1589 | xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); | |
1590 | } else { | |
1591 | epctx->ring.dequeue = xfer->trbs[0].addr; | |
1592 | epctx->ring.ccs = xfer->trbs[0].ccs; | |
1593 | xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); | |
1594 | } | |
62c6ae04 HM |
1595 | } |
1596 | ||
5c08106f GH |
1597 | static int xhci_setup_packet(XHCITransfer *xfer) |
1598 | { | |
079d0b7f GH |
1599 | USBEndpoint *ep; |
1600 | int dir; | |
1601 | ||
1602 | dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; | |
5c08106f GH |
1603 | |
1604 | if (xfer->packet.ep) { | |
1605 | ep = xfer->packet.ep; | |
5c08106f | 1606 | } else { |
070eeef9 | 1607 | ep = xhci_epid_to_usbep(xfer->epctx); |
518ad5f2 | 1608 | if (!ep) { |
d6bb65fc | 1609 | DPRINTF("xhci: slot %d has no device\n", |
ee56264a | 1610 | xfer->epctx->slotid); |
5c08106f GH |
1611 | return -1; |
1612 | } | |
5c08106f GH |
1613 | } |
1614 | ||
a6fb2ddb | 1615 | xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ |
024426ac | 1616 | usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, |
8550a02d | 1617 | xfer->trbs[0].addr, false, xfer->int_req); |
a6fb2ddb | 1618 | usb_packet_map(&xfer->packet, &xfer->sgl); |
62c6ae04 | 1619 | DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", |
518ad5f2 | 1620 | xfer->packet.pid, ep->dev->addr, ep->nr); |
62c6ae04 HM |
1621 | return 0; |
1622 | } | |
1623 | ||
13e8ff7a | 1624 | static int xhci_try_complete_packet(XHCITransfer *xfer) |
62c6ae04 | 1625 | { |
9a77a0f5 | 1626 | if (xfer->packet.status == USB_RET_ASYNC) { |
97df650b | 1627 | trace_usb_xhci_xfer_async(xfer); |
7c605a23 GH |
1628 | xfer->running_async = 1; |
1629 | xfer->running_retry = 0; | |
1630 | xfer->complete = 0; | |
7c605a23 | 1631 | return 0; |
9a77a0f5 | 1632 | } else if (xfer->packet.status == USB_RET_NAK) { |
97df650b | 1633 | trace_usb_xhci_xfer_nak(xfer); |
7c605a23 GH |
1634 | xfer->running_async = 0; |
1635 | xfer->running_retry = 1; | |
62c6ae04 | 1636 | xfer->complete = 0; |
62c6ae04 HM |
1637 | return 0; |
1638 | } else { | |
7c605a23 GH |
1639 | xfer->running_async = 0; |
1640 | xfer->running_retry = 0; | |
62c6ae04 | 1641 | xfer->complete = 1; |
d5a15814 | 1642 | xhci_xfer_unmap(xfer); |
62c6ae04 HM |
1643 | } |
1644 | ||
9a77a0f5 HG |
1645 | if (xfer->packet.status == USB_RET_SUCCESS) { |
1646 | trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); | |
d5a15814 GH |
1647 | xfer->status = CC_SUCCESS; |
1648 | xhci_xfer_report(xfer); | |
62c6ae04 HM |
1649 | return 0; |
1650 | } | |
1651 | ||
1652 | /* error */ | |
9a77a0f5 HG |
1653 | trace_usb_xhci_xfer_error(xfer, xfer->packet.status); |
1654 | switch (xfer->packet.status) { | |
62c6ae04 | 1655 | case USB_RET_NODEV: |
ed60ff02 | 1656 | case USB_RET_IOERROR: |
62c6ae04 | 1657 | xfer->status = CC_USB_TRANSACTION_ERROR; |
d5a15814 | 1658 | xhci_xfer_report(xfer); |
62c6ae04 HM |
1659 | xhci_stall_ep(xfer); |
1660 | break; | |
1661 | case USB_RET_STALL: | |
1662 | xfer->status = CC_STALL_ERROR; | |
d5a15814 | 1663 | xhci_xfer_report(xfer); |
62c6ae04 HM |
1664 | xhci_stall_ep(xfer); |
1665 | break; | |
4e906d56 GH |
1666 | case USB_RET_BABBLE: |
1667 | xfer->status = CC_BABBLE_DETECTED; | |
1668 | xhci_xfer_report(xfer); | |
1669 | xhci_stall_ep(xfer); | |
1670 | break; | |
62c6ae04 | 1671 | default: |
d6bb65fc | 1672 | DPRINTF("%s: FIXME: status = %d\n", __func__, |
9a77a0f5 | 1673 | xfer->packet.status); |
024426ac | 1674 | FIXME("unhandled USB_RET_*"); |
62c6ae04 HM |
1675 | } |
1676 | return 0; | |
1677 | } | |
1678 | ||
1679 | static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) | |
1680 | { | |
1681 | XHCITRB *trb_setup, *trb_status; | |
2850ca9e | 1682 | uint8_t bmRequestType; |
62c6ae04 | 1683 | |
62c6ae04 HM |
1684 | trb_setup = &xfer->trbs[0]; |
1685 | trb_status = &xfer->trbs[xfer->trb_count-1]; | |
1686 | ||
d6fcb293 GH |
1687 | trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, |
1688 | xfer->epctx->epid, xfer->streamid); | |
97df650b | 1689 | |
62c6ae04 HM |
1690 | /* at most one Event Data TRB allowed after STATUS */ |
1691 | if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { | |
1692 | trb_status--; | |
1693 | } | |
1694 | ||
1695 | /* do some sanity checks */ | |
1696 | if (TRB_TYPE(*trb_setup) != TR_SETUP) { | |
d6bb65fc | 1697 | DPRINTF("xhci: ep0 first TD not SETUP: %d\n", |
62c6ae04 HM |
1698 | TRB_TYPE(*trb_setup)); |
1699 | return -1; | |
1700 | } | |
1701 | if (TRB_TYPE(*trb_status) != TR_STATUS) { | |
d6bb65fc | 1702 | DPRINTF("xhci: ep0 last TD not STATUS: %d\n", |
62c6ae04 HM |
1703 | TRB_TYPE(*trb_status)); |
1704 | return -1; | |
1705 | } | |
1706 | if (!(trb_setup->control & TRB_TR_IDT)) { | |
d6bb65fc | 1707 | DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); |
62c6ae04 HM |
1708 | return -1; |
1709 | } | |
1710 | if ((trb_setup->status & 0x1ffff) != 8) { | |
d6bb65fc | 1711 | DPRINTF("xhci: Setup TRB has bad length (%d)\n", |
62c6ae04 HM |
1712 | (trb_setup->status & 0x1ffff)); |
1713 | return -1; | |
1714 | } | |
1715 | ||
1716 | bmRequestType = trb_setup->parameter; | |
62c6ae04 | 1717 | |
62c6ae04 HM |
1718 | xfer->in_xfer = bmRequestType & USB_DIR_IN; |
1719 | xfer->iso_xfer = false; | |
4d7a81c0 | 1720 | xfer->timed_xfer = false; |
62c6ae04 | 1721 | |
5c08106f GH |
1722 | if (xhci_setup_packet(xfer) < 0) { |
1723 | return -1; | |
1724 | } | |
2850ca9e | 1725 | xfer->packet.parameter = trb_setup->parameter; |
2850ca9e | 1726 | |
9a77a0f5 | 1727 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
13e8ff7a | 1728 | xhci_try_complete_packet(xfer); |
62c6ae04 HM |
1729 | return 0; |
1730 | } | |
1731 | ||
4d7a81c0 GH |
1732 | static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, |
1733 | XHCIEPContext *epctx, uint64_t mfindex) | |
1734 | { | |
1735 | uint64_t asap = ((mfindex + epctx->interval - 1) & | |
1736 | ~(epctx->interval-1)); | |
1737 | uint64_t kick = epctx->mfindex_last + epctx->interval; | |
1738 | ||
1739 | assert(epctx->interval != 0); | |
1740 | xfer->mfindex_kick = MAX(asap, kick); | |
1741 | } | |
1742 | ||
3d139684 GH |
1743 | static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
1744 | XHCIEPContext *epctx, uint64_t mfindex) | |
1745 | { | |
1746 | if (xfer->trbs[0].control & TRB_TR_SIA) { | |
1747 | uint64_t asap = ((mfindex + epctx->interval - 1) & | |
1748 | ~(epctx->interval-1)); | |
1749 | if (asap >= epctx->mfindex_last && | |
1750 | asap <= epctx->mfindex_last + epctx->interval * 4) { | |
1751 | xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; | |
1752 | } else { | |
1753 | xfer->mfindex_kick = asap; | |
1754 | } | |
1755 | } else { | |
786ad214 GH |
1756 | xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) |
1757 | & TRB_TR_FRAMEID_MASK) << 3; | |
3d139684 | 1758 | xfer->mfindex_kick |= mfindex & ~0x3fff; |
cc03ff9d | 1759 | if (xfer->mfindex_kick + 0x100 < mfindex) { |
3d139684 GH |
1760 | xfer->mfindex_kick += 0x4000; |
1761 | } | |
1762 | } | |
1763 | } | |
1764 | ||
4d7a81c0 GH |
1765 | static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
1766 | XHCIEPContext *epctx, uint64_t mfindex) | |
3d139684 GH |
1767 | { |
1768 | if (xfer->mfindex_kick > mfindex) { | |
bc72ad67 | 1769 | timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
3d139684 GH |
1770 | (xfer->mfindex_kick - mfindex) * 125000); |
1771 | xfer->running_retry = 1; | |
1772 | } else { | |
1773 | epctx->mfindex_last = xfer->mfindex_kick; | |
bc72ad67 | 1774 | timer_del(epctx->kick_timer); |
3d139684 GH |
1775 | xfer->running_retry = 0; |
1776 | } | |
1777 | } | |
1778 | ||
1779 | ||
62c6ae04 HM |
1780 | static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
1781 | { | |
3d139684 | 1782 | uint64_t mfindex; |
62c6ae04 | 1783 | |
ee56264a | 1784 | DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid); |
62c6ae04 HM |
1785 | |
1786 | xfer->in_xfer = epctx->type>>2; | |
62c6ae04 | 1787 | |
62c6ae04 HM |
1788 | switch(epctx->type) { |
1789 | case ET_INTR_OUT: | |
1790 | case ET_INTR_IN: | |
4d7a81c0 GH |
1791 | xfer->pkts = 0; |
1792 | xfer->iso_xfer = false; | |
1793 | xfer->timed_xfer = true; | |
1794 | mfindex = xhci_mfindex_get(xhci); | |
1795 | xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); | |
1796 | xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); | |
1797 | if (xfer->running_retry) { | |
1798 | return -1; | |
1799 | } | |
1800 | break; | |
62c6ae04 HM |
1801 | case ET_BULK_OUT: |
1802 | case ET_BULK_IN: | |
3d139684 GH |
1803 | xfer->pkts = 0; |
1804 | xfer->iso_xfer = false; | |
4d7a81c0 | 1805 | xfer->timed_xfer = false; |
62c6ae04 HM |
1806 | break; |
1807 | case ET_ISO_OUT: | |
1808 | case ET_ISO_IN: | |
3d139684 GH |
1809 | xfer->pkts = 1; |
1810 | xfer->iso_xfer = true; | |
4d7a81c0 | 1811 | xfer->timed_xfer = true; |
3d139684 GH |
1812 | mfindex = xhci_mfindex_get(xhci); |
1813 | xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); | |
4d7a81c0 | 1814 | xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); |
3d139684 GH |
1815 | if (xfer->running_retry) { |
1816 | return -1; | |
1817 | } | |
62c6ae04 HM |
1818 | break; |
1819 | default: | |
4f9cc734 | 1820 | trace_usb_xhci_unimplemented("endpoint type", epctx->type); |
62c6ae04 HM |
1821 | return -1; |
1822 | } | |
1823 | ||
5c08106f GH |
1824 | if (xhci_setup_packet(xfer) < 0) { |
1825 | return -1; | |
1826 | } | |
9a77a0f5 | 1827 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
13e8ff7a | 1828 | xhci_try_complete_packet(xfer); |
62c6ae04 HM |
1829 | return 0; |
1830 | } | |
1831 | ||
1832 | static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) | |
1833 | { | |
d6fcb293 GH |
1834 | trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, |
1835 | xfer->epctx->epid, xfer->streamid); | |
331e9406 | 1836 | return xhci_submit(xhci, xfer, epctx); |
62c6ae04 HM |
1837 | } |
1838 | ||
024426ac GH |
1839 | static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
1840 | unsigned int epid, unsigned int streamid) | |
62c6ae04 HM |
1841 | { |
1842 | XHCIEPContext *epctx; | |
62c6ae04 | 1843 | |
91062ae0 | 1844 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 1845 | assert(epid >= 1 && epid <= 31); |
62c6ae04 HM |
1846 | |
1847 | if (!xhci->slots[slotid-1].enabled) { | |
d6bb65fc | 1848 | DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); |
62c6ae04 HM |
1849 | return; |
1850 | } | |
1851 | epctx = xhci->slots[slotid-1].eps[epid-1]; | |
1852 | if (!epctx) { | |
d6bb65fc | 1853 | DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", |
62c6ae04 HM |
1854 | epid, slotid); |
1855 | return; | |
1856 | } | |
1857 | ||
96d87bdd GH |
1858 | if (epctx->kick_active) { |
1859 | return; | |
1860 | } | |
3a533ee8 GH |
1861 | xhci_kick_epctx(epctx, streamid); |
1862 | } | |
1863 | ||
236846a0 GH |
1864 | static bool xhci_slot_ok(XHCIState *xhci, int slotid) |
1865 | { | |
1866 | return (xhci->slots[slotid - 1].uport && | |
1867 | xhci->slots[slotid - 1].uport->dev && | |
1868 | xhci->slots[slotid - 1].uport->dev->attached); | |
1869 | } | |
1870 | ||
3a533ee8 GH |
1871 | static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid) |
1872 | { | |
1873 | XHCIState *xhci = epctx->xhci; | |
243afe85 | 1874 | XHCIStreamContext *stctx = NULL; |
3a533ee8 GH |
1875 | XHCITransfer *xfer; |
1876 | XHCIRing *ring; | |
1877 | USBEndpoint *ep = NULL; | |
1878 | uint64_t mfindex; | |
f89b60f6 | 1879 | unsigned int count = 0; |
3a533ee8 GH |
1880 | int length; |
1881 | int i; | |
1882 | ||
1883 | trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid); | |
96d87bdd | 1884 | assert(!epctx->kick_active); |
3a533ee8 | 1885 | |
de9de157 HG |
1886 | /* If the device has been detached, but the guest has not noticed this |
1887 | yet the 2 above checks will succeed, but we must NOT continue */ | |
236846a0 | 1888 | if (!xhci_slot_ok(xhci, epctx->slotid)) { |
de9de157 HG |
1889 | return; |
1890 | } | |
1891 | ||
7c605a23 | 1892 | if (epctx->retry) { |
7c605a23 | 1893 | XHCITransfer *xfer = epctx->retry; |
7c605a23 | 1894 | |
97df650b | 1895 | trace_usb_xhci_xfer_retry(xfer); |
7c605a23 | 1896 | assert(xfer->running_retry); |
4d7a81c0 GH |
1897 | if (xfer->timed_xfer) { |
1898 | /* time to kick the transfer? */ | |
3d139684 | 1899 | mfindex = xhci_mfindex_get(xhci); |
4d7a81c0 | 1900 | xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); |
3d139684 GH |
1901 | if (xfer->running_retry) { |
1902 | return; | |
1903 | } | |
4d7a81c0 GH |
1904 | xfer->timed_xfer = 0; |
1905 | xfer->running_retry = 1; | |
1906 | } | |
1907 | if (xfer->iso_xfer) { | |
1908 | /* retry iso transfer */ | |
3d139684 GH |
1909 | if (xhci_setup_packet(xfer) < 0) { |
1910 | return; | |
1911 | } | |
9a77a0f5 HG |
1912 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1913 | assert(xfer->packet.status != USB_RET_NAK); | |
13e8ff7a | 1914 | xhci_try_complete_packet(xfer); |
3d139684 GH |
1915 | } else { |
1916 | /* retry nak'ed transfer */ | |
1917 | if (xhci_setup_packet(xfer) < 0) { | |
1918 | return; | |
1919 | } | |
9a77a0f5 HG |
1920 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1921 | if (xfer->packet.status == USB_RET_NAK) { | |
7cec2ed9 | 1922 | xhci_xfer_unmap(xfer); |
3d139684 GH |
1923 | return; |
1924 | } | |
13e8ff7a | 1925 | xhci_try_complete_packet(xfer); |
7c605a23 | 1926 | } |
7c605a23 | 1927 | assert(!xfer->running_retry); |
f94d18d6 | 1928 | if (xfer->complete) { |
d54fddea GH |
1929 | /* update ring dequeue ptr */ |
1930 | xhci_set_ep_state(xhci, epctx, stctx, epctx->state); | |
f94d18d6 GH |
1931 | xhci_ep_free_xfer(epctx->retry); |
1932 | } | |
7c605a23 GH |
1933 | epctx->retry = NULL; |
1934 | } | |
1935 | ||
62c6ae04 HM |
1936 | if (epctx->state == EP_HALTED) { |
1937 | DPRINTF("xhci: ep halted, not running schedule\n"); | |
1938 | return; | |
1939 | } | |
1940 | ||
024426ac GH |
1941 | |
1942 | if (epctx->nr_pstreams) { | |
1943 | uint32_t err; | |
1944 | stctx = xhci_find_stream(epctx, streamid, &err); | |
1945 | if (stctx == NULL) { | |
1946 | return; | |
1947 | } | |
1948 | ring = &stctx->ring; | |
1949 | xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); | |
1950 | } else { | |
1951 | ring = &epctx->ring; | |
1952 | streamid = 0; | |
1953 | xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); | |
1954 | } | |
7d04c2b7 | 1955 | assert(ring->dequeue != 0); |
62c6ae04 | 1956 | |
96d87bdd | 1957 | epctx->kick_active++; |
62c6ae04 | 1958 | while (1) { |
024426ac | 1959 | length = xhci_ring_chain_length(xhci, ring); |
94b037f2 | 1960 | if (length <= 0) { |
b4329d1a YB |
1961 | if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) { |
1962 | /* 4.10.3.1 */ | |
1963 | XHCIEvent ev = { ER_TRANSFER }; | |
1964 | ev.ccode = epctx->type == ET_ISO_IN ? | |
1965 | CC_RING_OVERRUN : CC_RING_UNDERRUN; | |
1966 | ev.slotid = epctx->slotid; | |
1967 | ev.epid = epctx->epid; | |
1968 | ev.ptr = epctx->ring.dequeue; | |
1969 | xhci_event(xhci, &ev, xhci->slots[epctx->slotid-1].intr); | |
1970 | } | |
62c6ae04 | 1971 | break; |
62c6ae04 | 1972 | } |
94b037f2 GH |
1973 | xfer = xhci_ep_alloc_xfer(epctx, length); |
1974 | if (xfer == NULL) { | |
1975 | break; | |
62c6ae04 | 1976 | } |
62c6ae04 HM |
1977 | |
1978 | for (i = 0; i < length; i++) { | |
f81bb347 AK |
1979 | TRBType type; |
1980 | type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL); | |
8f36ec70 GH |
1981 | if (!type) { |
1982 | xhci_die(xhci); | |
1983 | xhci_ep_free_xfer(xfer); | |
1984 | epctx->kick_active--; | |
1985 | return; | |
1986 | } | |
62c6ae04 | 1987 | } |
024426ac | 1988 | xfer->streamid = streamid; |
62c6ae04 | 1989 | |
3a533ee8 | 1990 | if (epctx->epid == 1) { |
94b037f2 | 1991 | xhci_fire_ctl_transfer(xhci, xfer); |
62c6ae04 | 1992 | } else { |
94b037f2 GH |
1993 | xhci_fire_transfer(xhci, xfer, epctx); |
1994 | } | |
236846a0 GH |
1995 | if (!xhci_slot_ok(xhci, epctx->slotid)) { |
1996 | /* surprise removal -> stop processing */ | |
1997 | break; | |
1998 | } | |
94b037f2 | 1999 | if (xfer->complete) { |
d54fddea GH |
2000 | /* update ring dequeue ptr */ |
2001 | xhci_set_ep_state(xhci, epctx, stctx, epctx->state); | |
94b037f2 GH |
2002 | xhci_ep_free_xfer(xfer); |
2003 | xfer = NULL; | |
62c6ae04 HM |
2004 | } |
2005 | ||
3c4866e0 | 2006 | if (epctx->state == EP_HALTED) { |
3c4866e0 GH |
2007 | break; |
2008 | } | |
94b037f2 | 2009 | if (xfer != NULL && xfer->running_retry) { |
7c605a23 GH |
2010 | DPRINTF("xhci: xfer nacked, stopping schedule\n"); |
2011 | epctx->retry = xfer; | |
34b9d6a1 | 2012 | xhci_xfer_unmap(xfer); |
7c605a23 GH |
2013 | break; |
2014 | } | |
f89b60f6 GH |
2015 | if (count++ > TRANSFER_LIMIT) { |
2016 | trace_usb_xhci_enforced_limit("transfers"); | |
2017 | break; | |
2018 | } | |
62c6ae04 | 2019 | } |
96d87bdd | 2020 | epctx->kick_active--; |
518ad5f2 | 2021 | |
070eeef9 | 2022 | ep = xhci_epid_to_usbep(epctx); |
36dfe324 HG |
2023 | if (ep) { |
2024 | usb_device_flush_ep_queue(ep->dev, ep); | |
2025 | } | |
62c6ae04 HM |
2026 | } |
2027 | ||
2028 | static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) | |
2029 | { | |
348f1037 | 2030 | trace_usb_xhci_slot_enable(slotid); |
91062ae0 | 2031 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 2032 | xhci->slots[slotid-1].enabled = 1; |
ccaf87a0 | 2033 | xhci->slots[slotid-1].uport = NULL; |
62c6ae04 HM |
2034 | memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); |
2035 | ||
2036 | return CC_SUCCESS; | |
2037 | } | |
2038 | ||
2039 | static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) | |
2040 | { | |
2041 | int i; | |
2042 | ||
348f1037 | 2043 | trace_usb_xhci_slot_disable(slotid); |
91062ae0 | 2044 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2045 | |
2046 | for (i = 1; i <= 31; i++) { | |
2047 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2048 | xhci_disable_ep(xhci, slotid, i); | |
2049 | } | |
2050 | } | |
2051 | ||
2052 | xhci->slots[slotid-1].enabled = 0; | |
4034e693 | 2053 | xhci->slots[slotid-1].addressed = 0; |
5c67dd7b | 2054 | xhci->slots[slotid-1].uport = NULL; |
b4329d1a | 2055 | xhci->slots[slotid-1].intr = 0; |
62c6ae04 HM |
2056 | return CC_SUCCESS; |
2057 | } | |
2058 | ||
ccaf87a0 GH |
2059 | static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) |
2060 | { | |
2061 | USBPort *uport; | |
2062 | char path[32]; | |
2063 | int i, pos, port; | |
2064 | ||
2065 | port = (slot_ctx[1]>>16) & 0xFF; | |
f2ad97ff GH |
2066 | if (port < 1 || port > xhci->numports) { |
2067 | return NULL; | |
2068 | } | |
ccaf87a0 GH |
2069 | port = xhci->ports[port-1].uport->index+1; |
2070 | pos = snprintf(path, sizeof(path), "%d", port); | |
2071 | for (i = 0; i < 5; i++) { | |
2072 | port = (slot_ctx[0] >> 4*i) & 0x0f; | |
2073 | if (!port) { | |
2074 | break; | |
2075 | } | |
2076 | pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); | |
2077 | } | |
2078 | ||
2079 | QTAILQ_FOREACH(uport, &xhci->bus.used, next) { | |
2080 | if (strcmp(uport->path, path) == 0) { | |
2081 | return uport; | |
2082 | } | |
2083 | } | |
2084 | return NULL; | |
2085 | } | |
2086 | ||
62c6ae04 HM |
2087 | static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, |
2088 | uint64_t pictx, bool bsr) | |
2089 | { | |
2090 | XHCISlot *slot; | |
ccaf87a0 | 2091 | USBPort *uport; |
62c6ae04 | 2092 | USBDevice *dev; |
59a70ccd | 2093 | dma_addr_t ictx, octx, dcbaap; |
62c6ae04 HM |
2094 | uint64_t poctx; |
2095 | uint32_t ictl_ctx[2]; | |
2096 | uint32_t slot_ctx[4]; | |
2097 | uint32_t ep0_ctx[5]; | |
62c6ae04 HM |
2098 | int i; |
2099 | TRBCCode res; | |
2100 | ||
91062ae0 | 2101 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2102 | |
2103 | dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); | |
9b7d3334 | 2104 | poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); |
62c6ae04 | 2105 | ictx = xhci_mask64(pictx); |
616b5d53 | 2106 | octx = xhci_mask64(poctx); |
62c6ae04 | 2107 | |
59a70ccd DG |
2108 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2109 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 | 2110 | |
616b5d53 | 2111 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2112 | |
2113 | if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { | |
d6bb65fc | 2114 | DPRINTF("xhci: invalid input context control %08x %08x\n", |
62c6ae04 HM |
2115 | ictl_ctx[0], ictl_ctx[1]); |
2116 | return CC_TRB_ERROR; | |
2117 | } | |
2118 | ||
616b5d53 DG |
2119 | xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); |
2120 | xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); | |
62c6ae04 HM |
2121 | |
2122 | DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", | |
2123 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2124 | ||
2125 | DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", | |
2126 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2127 | ||
ccaf87a0 GH |
2128 | uport = xhci_lookup_uport(xhci, slot_ctx); |
2129 | if (uport == NULL) { | |
d6bb65fc | 2130 | DPRINTF("xhci: port not found\n"); |
62c6ae04 | 2131 | return CC_TRB_ERROR; |
ccaf87a0 | 2132 | } |
65d81ed4 | 2133 | trace_usb_xhci_slot_address(slotid, uport->path); |
ccaf87a0 GH |
2134 | |
2135 | dev = uport->dev; | |
de9de157 | 2136 | if (!dev || !dev->attached) { |
d6bb65fc | 2137 | DPRINTF("xhci: port %s not connected\n", uport->path); |
62c6ae04 HM |
2138 | return CC_USB_TRANSACTION_ERROR; |
2139 | } | |
2140 | ||
91062ae0 | 2141 | for (i = 0; i < xhci->numslots; i++) { |
0bc85da6 GH |
2142 | if (i == slotid-1) { |
2143 | continue; | |
2144 | } | |
ccaf87a0 | 2145 | if (xhci->slots[i].uport == uport) { |
d6bb65fc | 2146 | DPRINTF("xhci: port %s already assigned to slot %d\n", |
ccaf87a0 | 2147 | uport->path, i+1); |
62c6ae04 HM |
2148 | return CC_TRB_ERROR; |
2149 | } | |
2150 | } | |
2151 | ||
2152 | slot = &xhci->slots[slotid-1]; | |
ccaf87a0 | 2153 | slot->uport = uport; |
62c6ae04 | 2154 | slot->ctx = octx; |
b4329d1a | 2155 | slot->intr = get_field(slot_ctx[2], TRB_INTR); |
62c6ae04 | 2156 | |
a4055d85 ZS |
2157 | /* Make sure device is in USB_STATE_DEFAULT state */ |
2158 | usb_device_reset(dev); | |
62c6ae04 HM |
2159 | if (bsr) { |
2160 | slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; | |
2161 | } else { | |
a820b575 | 2162 | USBPacket p; |
a6718874 GH |
2163 | uint8_t buf[1]; |
2164 | ||
af203be3 | 2165 | slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; |
a6718874 GH |
2166 | memset(&p, 0, sizeof(p)); |
2167 | usb_packet_addbuf(&p, buf, sizeof(buf)); | |
a820b575 | 2168 | usb_packet_setup(&p, USB_TOKEN_OUT, |
8550a02d | 2169 | usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, |
a820b575 GH |
2170 | 0, false, false); |
2171 | usb_device_handle_control(dev, &p, | |
62c6ae04 | 2172 | DeviceOutRequest | USB_REQ_SET_ADDRESS, |
af203be3 | 2173 | slotid, 0, 0, NULL); |
a820b575 | 2174 | assert(p.status != USB_RET_ASYNC); |
c9e38592 | 2175 | usb_packet_cleanup(&p); |
62c6ae04 HM |
2176 | } |
2177 | ||
2178 | res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); | |
2179 | ||
2180 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2181 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2182 | DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", | |
2183 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2184 | ||
616b5d53 DG |
2185 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
2186 | xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); | |
62c6ae04 | 2187 | |
4034e693 | 2188 | xhci->slots[slotid-1].addressed = 1; |
62c6ae04 HM |
2189 | return res; |
2190 | } | |
2191 | ||
2192 | ||
2193 | static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, | |
2194 | uint64_t pictx, bool dc) | |
2195 | { | |
59a70ccd | 2196 | dma_addr_t ictx, octx; |
62c6ae04 HM |
2197 | uint32_t ictl_ctx[2]; |
2198 | uint32_t slot_ctx[4]; | |
2199 | uint32_t islot_ctx[4]; | |
2200 | uint32_t ep_ctx[5]; | |
2201 | int i; | |
2202 | TRBCCode res; | |
2203 | ||
348f1037 | 2204 | trace_usb_xhci_slot_configure(slotid); |
91062ae0 | 2205 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2206 | |
2207 | ictx = xhci_mask64(pictx); | |
2208 | octx = xhci->slots[slotid-1].ctx; | |
2209 | ||
59a70ccd DG |
2210 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2211 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 HM |
2212 | |
2213 | if (dc) { | |
2214 | for (i = 2; i <= 31; i++) { | |
2215 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2216 | xhci_disable_ep(xhci, slotid, i); | |
2217 | } | |
2218 | } | |
2219 | ||
616b5d53 | 2220 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2221 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2222 | slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; | |
2223 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2224 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
616b5d53 | 2225 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2226 | |
2227 | return CC_SUCCESS; | |
2228 | } | |
2229 | ||
616b5d53 | 2230 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2231 | |
2232 | if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { | |
d6bb65fc | 2233 | DPRINTF("xhci: invalid input context control %08x %08x\n", |
62c6ae04 HM |
2234 | ictl_ctx[0], ictl_ctx[1]); |
2235 | return CC_TRB_ERROR; | |
2236 | } | |
2237 | ||
616b5d53 DG |
2238 | xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); |
2239 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); | |
62c6ae04 HM |
2240 | |
2241 | if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { | |
d6bb65fc | 2242 | DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); |
62c6ae04 HM |
2243 | return CC_CONTEXT_STATE_ERROR; |
2244 | } | |
2245 | ||
72391da5 HG |
2246 | xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); |
2247 | ||
62c6ae04 HM |
2248 | for (i = 2; i <= 31; i++) { |
2249 | if (ictl_ctx[0] & (1<<i)) { | |
2250 | xhci_disable_ep(xhci, slotid, i); | |
2251 | } | |
2252 | if (ictl_ctx[1] & (1<<i)) { | |
616b5d53 | 2253 | xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); |
62c6ae04 HM |
2254 | DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", |
2255 | i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], | |
2256 | ep_ctx[3], ep_ctx[4]); | |
2257 | xhci_disable_ep(xhci, slotid, i); | |
2258 | res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); | |
2259 | if (res != CC_SUCCESS) { | |
2260 | return res; | |
2261 | } | |
2262 | DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", | |
2263 | i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], | |
2264 | ep_ctx[3], ep_ctx[4]); | |
616b5d53 | 2265 | xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); |
62c6ae04 HM |
2266 | } |
2267 | } | |
2268 | ||
72391da5 HG |
2269 | res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); |
2270 | if (res != CC_SUCCESS) { | |
2271 | for (i = 2; i <= 31; i++) { | |
3d80365b | 2272 | if (ictl_ctx[1] & (1u << i)) { |
72391da5 HG |
2273 | xhci_disable_ep(xhci, slotid, i); |
2274 | } | |
2275 | } | |
2276 | return res; | |
2277 | } | |
2278 | ||
62c6ae04 HM |
2279 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2280 | slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; | |
2281 | slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); | |
2282 | slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << | |
2283 | SLOT_CONTEXT_ENTRIES_SHIFT); | |
2284 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2285 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2286 | ||
616b5d53 | 2287 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2288 | |
2289 | return CC_SUCCESS; | |
2290 | } | |
2291 | ||
2292 | ||
2293 | static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, | |
2294 | uint64_t pictx) | |
2295 | { | |
59a70ccd | 2296 | dma_addr_t ictx, octx; |
62c6ae04 HM |
2297 | uint32_t ictl_ctx[2]; |
2298 | uint32_t iep0_ctx[5]; | |
2299 | uint32_t ep0_ctx[5]; | |
2300 | uint32_t islot_ctx[4]; | |
2301 | uint32_t slot_ctx[4]; | |
2302 | ||
348f1037 | 2303 | trace_usb_xhci_slot_evaluate(slotid); |
91062ae0 | 2304 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2305 | |
2306 | ictx = xhci_mask64(pictx); | |
2307 | octx = xhci->slots[slotid-1].ctx; | |
2308 | ||
59a70ccd DG |
2309 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2310 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 | 2311 | |
616b5d53 | 2312 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2313 | |
2314 | if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { | |
d6bb65fc | 2315 | DPRINTF("xhci: invalid input context control %08x %08x\n", |
62c6ae04 HM |
2316 | ictl_ctx[0], ictl_ctx[1]); |
2317 | return CC_TRB_ERROR; | |
2318 | } | |
2319 | ||
2320 | if (ictl_ctx[1] & 0x1) { | |
616b5d53 | 2321 | xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); |
62c6ae04 HM |
2322 | |
2323 | DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", | |
2324 | islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); | |
2325 | ||
616b5d53 | 2326 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2327 | |
2328 | slot_ctx[1] &= ~0xFFFF; /* max exit latency */ | |
2329 | slot_ctx[1] |= islot_ctx[1] & 0xFFFF; | |
b4329d1a YB |
2330 | /* update interrupter target field */ |
2331 | xhci->slots[slotid-1].intr = get_field(islot_ctx[2], TRB_INTR); | |
2332 | set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR); | |
62c6ae04 HM |
2333 | |
2334 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2335 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2336 | ||
616b5d53 | 2337 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2338 | } |
2339 | ||
2340 | if (ictl_ctx[1] & 0x2) { | |
616b5d53 | 2341 | xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); |
62c6ae04 HM |
2342 | |
2343 | DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", | |
2344 | iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], | |
2345 | iep0_ctx[3], iep0_ctx[4]); | |
2346 | ||
616b5d53 | 2347 | xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
62c6ae04 HM |
2348 | |
2349 | ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ | |
2350 | ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; | |
2351 | ||
2352 | DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", | |
2353 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2354 | ||
616b5d53 | 2355 | xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
62c6ae04 HM |
2356 | } |
2357 | ||
2358 | return CC_SUCCESS; | |
2359 | } | |
2360 | ||
2361 | static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) | |
2362 | { | |
2363 | uint32_t slot_ctx[4]; | |
59a70ccd | 2364 | dma_addr_t octx; |
62c6ae04 HM |
2365 | int i; |
2366 | ||
348f1037 | 2367 | trace_usb_xhci_slot_reset(slotid); |
91062ae0 | 2368 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2369 | |
2370 | octx = xhci->slots[slotid-1].ctx; | |
2371 | ||
59a70ccd | 2372 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
62c6ae04 HM |
2373 | |
2374 | for (i = 2; i <= 31; i++) { | |
2375 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2376 | xhci_disable_ep(xhci, slotid, i); | |
2377 | } | |
2378 | } | |
2379 | ||
616b5d53 | 2380 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2381 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2382 | slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; | |
2383 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2384 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
616b5d53 | 2385 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2386 | |
2387 | return CC_SUCCESS; | |
2388 | } | |
2389 | ||
2390 | static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) | |
2391 | { | |
2392 | unsigned int slotid; | |
2393 | slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; | |
91062ae0 | 2394 | if (slotid < 1 || slotid > xhci->numslots) { |
d6bb65fc | 2395 | DPRINTF("xhci: bad slot id %d\n", slotid); |
62c6ae04 HM |
2396 | event->ccode = CC_TRB_ERROR; |
2397 | return 0; | |
2398 | } else if (!xhci->slots[slotid-1].enabled) { | |
d6bb65fc | 2399 | DPRINTF("xhci: slot id %d not enabled\n", slotid); |
62c6ae04 HM |
2400 | event->ccode = CC_SLOT_NOT_ENABLED_ERROR; |
2401 | return 0; | |
2402 | } | |
2403 | return slotid; | |
2404 | } | |
2405 | ||
81251841 GH |
2406 | /* cleanup slot state on usb device detach */ |
2407 | static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) | |
2408 | { | |
0cb41e2c | 2409 | int slot, ep; |
81251841 GH |
2410 | |
2411 | for (slot = 0; slot < xhci->numslots; slot++) { | |
2412 | if (xhci->slots[slot].uport == uport) { | |
2413 | break; | |
2414 | } | |
2415 | } | |
2416 | if (slot == xhci->numslots) { | |
2417 | return; | |
2418 | } | |
2419 | ||
0cb41e2c GH |
2420 | for (ep = 0; ep < 31; ep++) { |
2421 | if (xhci->slots[slot].eps[ep]) { | |
582d6f4a | 2422 | xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); |
0cb41e2c GH |
2423 | } |
2424 | } | |
81251841 GH |
2425 | xhci->slots[slot].uport = NULL; |
2426 | } | |
2427 | ||
62c6ae04 HM |
2428 | static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) |
2429 | { | |
59a70ccd | 2430 | dma_addr_t ctx; |
0846e635 | 2431 | uint8_t bw_ctx[xhci->numports+1]; |
62c6ae04 HM |
2432 | |
2433 | DPRINTF("xhci_get_port_bandwidth()\n"); | |
2434 | ||
2435 | ctx = xhci_mask64(pctx); | |
2436 | ||
59a70ccd | 2437 | DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); |
62c6ae04 HM |
2438 | |
2439 | /* TODO: actually implement real values here */ | |
2440 | bw_ctx[0] = 0; | |
0846e635 | 2441 | memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ |
9b7d3334 | 2442 | pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); |
62c6ae04 HM |
2443 | |
2444 | return CC_SUCCESS; | |
2445 | } | |
2446 | ||
2447 | static uint32_t rotl(uint32_t v, unsigned count) | |
2448 | { | |
2449 | count &= 31; | |
2450 | return (v << count) | (v >> (32 - count)); | |
2451 | } | |
2452 | ||
2453 | ||
2454 | static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) | |
2455 | { | |
2456 | uint32_t val; | |
2457 | val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); | |
2458 | val += rotl(lo + 0x49434878, hi & 0x1F); | |
2459 | val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); | |
2460 | return ~val; | |
2461 | } | |
2462 | ||
62c6ae04 HM |
2463 | static void xhci_process_commands(XHCIState *xhci) |
2464 | { | |
2465 | XHCITRB trb; | |
2466 | TRBType type; | |
2467 | XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; | |
59a70ccd | 2468 | dma_addr_t addr; |
f89b60f6 | 2469 | unsigned int i, slotid = 0, count = 0; |
62c6ae04 HM |
2470 | |
2471 | DPRINTF("xhci_process_commands()\n"); | |
2472 | if (!xhci_running(xhci)) { | |
2473 | DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); | |
2474 | return; | |
2475 | } | |
2476 | ||
2477 | xhci->crcr_low |= CRCR_CRR; | |
2478 | ||
2479 | while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { | |
2480 | event.ptr = addr; | |
2481 | switch (type) { | |
2482 | case CR_ENABLE_SLOT: | |
91062ae0 | 2483 | for (i = 0; i < xhci->numslots; i++) { |
62c6ae04 HM |
2484 | if (!xhci->slots[i].enabled) { |
2485 | break; | |
2486 | } | |
2487 | } | |
91062ae0 | 2488 | if (i >= xhci->numslots) { |
d6bb65fc | 2489 | DPRINTF("xhci: no device slots available\n"); |
62c6ae04 HM |
2490 | event.ccode = CC_NO_SLOTS_ERROR; |
2491 | } else { | |
2492 | slotid = i+1; | |
2493 | event.ccode = xhci_enable_slot(xhci, slotid); | |
2494 | } | |
2495 | break; | |
2496 | case CR_DISABLE_SLOT: | |
2497 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2498 | if (slotid) { | |
2499 | event.ccode = xhci_disable_slot(xhci, slotid); | |
2500 | } | |
2501 | break; | |
2502 | case CR_ADDRESS_DEVICE: | |
2503 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2504 | if (slotid) { | |
2505 | event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, | |
2506 | trb.control & TRB_CR_BSR); | |
2507 | } | |
2508 | break; | |
2509 | case CR_CONFIGURE_ENDPOINT: | |
2510 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2511 | if (slotid) { | |
2512 | event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, | |
2513 | trb.control & TRB_CR_DC); | |
2514 | } | |
2515 | break; | |
2516 | case CR_EVALUATE_CONTEXT: | |
2517 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2518 | if (slotid) { | |
2519 | event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); | |
2520 | } | |
2521 | break; | |
2522 | case CR_STOP_ENDPOINT: | |
2523 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2524 | if (slotid) { | |
2525 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2526 | & TRB_CR_EPID_MASK; | |
2527 | event.ccode = xhci_stop_ep(xhci, slotid, epid); | |
2528 | } | |
2529 | break; | |
2530 | case CR_RESET_ENDPOINT: | |
2531 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2532 | if (slotid) { | |
2533 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2534 | & TRB_CR_EPID_MASK; | |
2535 | event.ccode = xhci_reset_ep(xhci, slotid, epid); | |
2536 | } | |
2537 | break; | |
2538 | case CR_SET_TR_DEQUEUE: | |
2539 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2540 | if (slotid) { | |
2541 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2542 | & TRB_CR_EPID_MASK; | |
024426ac GH |
2543 | unsigned int streamid = (trb.status >> 16) & 0xffff; |
2544 | event.ccode = xhci_set_ep_dequeue(xhci, slotid, | |
2545 | epid, streamid, | |
62c6ae04 HM |
2546 | trb.parameter); |
2547 | } | |
2548 | break; | |
2549 | case CR_RESET_DEVICE: | |
2550 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2551 | if (slotid) { | |
2552 | event.ccode = xhci_reset_slot(xhci, slotid); | |
2553 | } | |
2554 | break; | |
2555 | case CR_GET_PORT_BANDWIDTH: | |
2556 | event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); | |
2557 | break; | |
dc2c037f HN |
2558 | case CR_NOOP: |
2559 | event.ccode = CC_SUCCESS; | |
2560 | break; | |
62c6ae04 | 2561 | case CR_VENDOR_NEC_FIRMWARE_REVISION: |
2992d6b4 GH |
2562 | if (xhci->nec_quirks) { |
2563 | event.type = 48; /* NEC reply */ | |
2564 | event.length = 0x3025; | |
2565 | } else { | |
2566 | event.ccode = CC_TRB_ERROR; | |
2567 | } | |
62c6ae04 HM |
2568 | break; |
2569 | case CR_VENDOR_NEC_CHALLENGE_RESPONSE: | |
2992d6b4 GH |
2570 | if (xhci->nec_quirks) { |
2571 | uint32_t chi = trb.parameter >> 32; | |
2572 | uint32_t clo = trb.parameter; | |
2573 | uint32_t val = xhci_nec_challenge(chi, clo); | |
2574 | event.length = val & 0xFFFF; | |
2575 | event.epid = val >> 16; | |
2576 | slotid = val >> 24; | |
2577 | event.type = 48; /* NEC reply */ | |
2578 | } else { | |
2579 | event.ccode = CC_TRB_ERROR; | |
2580 | } | |
2581 | break; | |
62c6ae04 | 2582 | default: |
0ab966cf | 2583 | trace_usb_xhci_unimplemented("command", type); |
62c6ae04 HM |
2584 | event.ccode = CC_TRB_ERROR; |
2585 | break; | |
2586 | } | |
2587 | event.slotid = slotid; | |
2d1de850 | 2588 | xhci_event(xhci, &event, 0); |
f89b60f6 GH |
2589 | |
2590 | if (count++ > COMMAND_LIMIT) { | |
2591 | trace_usb_xhci_enforced_limit("commands"); | |
2592 | return; | |
2593 | } | |
62c6ae04 HM |
2594 | } |
2595 | } | |
2596 | ||
6a32f80f GH |
2597 | static bool xhci_port_have_device(XHCIPort *port) |
2598 | { | |
2599 | if (!port->uport->dev || !port->uport->dev->attached) { | |
2600 | return false; /* no device present */ | |
2601 | } | |
2602 | if (!((1 << port->uport->dev->speed) & port->speedmask)) { | |
2603 | return false; /* speed mismatch */ | |
2604 | } | |
2605 | return true; | |
2606 | } | |
2607 | ||
f705a362 GH |
2608 | static void xhci_port_notify(XHCIPort *port, uint32_t bits) |
2609 | { | |
2610 | XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, | |
2611 | port->portnr << 24 }; | |
2612 | ||
2613 | if ((port->portsc & bits) == bits) { | |
2614 | return; | |
2615 | } | |
bdfce20d | 2616 | trace_usb_xhci_port_notify(port->portnr, bits); |
f705a362 GH |
2617 | port->portsc |= bits; |
2618 | if (!xhci_running(port->xhci)) { | |
2619 | return; | |
2620 | } | |
2621 | xhci_event(port->xhci, &ev, 0); | |
2622 | } | |
2623 | ||
f3214027 | 2624 | static void xhci_port_update(XHCIPort *port, int is_detach) |
62c6ae04 | 2625 | { |
b62b0828 GH |
2626 | uint32_t pls = PLS_RX_DETECT; |
2627 | ||
92cf3427 | 2628 | assert(port); |
62c6ae04 | 2629 | port->portsc = PORTSC_PP; |
6a32f80f | 2630 | if (!is_detach && xhci_port_have_device(port)) { |
62c6ae04 | 2631 | port->portsc |= PORTSC_CCS; |
0846e635 | 2632 | switch (port->uport->dev->speed) { |
62c6ae04 HM |
2633 | case USB_SPEED_LOW: |
2634 | port->portsc |= PORTSC_SPEED_LOW; | |
b62b0828 | 2635 | pls = PLS_POLLING; |
62c6ae04 HM |
2636 | break; |
2637 | case USB_SPEED_FULL: | |
2638 | port->portsc |= PORTSC_SPEED_FULL; | |
b62b0828 | 2639 | pls = PLS_POLLING; |
62c6ae04 HM |
2640 | break; |
2641 | case USB_SPEED_HIGH: | |
2642 | port->portsc |= PORTSC_SPEED_HIGH; | |
b62b0828 | 2643 | pls = PLS_POLLING; |
62c6ae04 | 2644 | break; |
0846e635 GH |
2645 | case USB_SPEED_SUPER: |
2646 | port->portsc |= PORTSC_SPEED_SUPER; | |
b62b0828 GH |
2647 | port->portsc |= PORTSC_PED; |
2648 | pls = PLS_U0; | |
0846e635 | 2649 | break; |
62c6ae04 HM |
2650 | } |
2651 | } | |
b62b0828 | 2652 | set_field(&port->portsc, pls, PORTSC_PLS); |
4f47f0f8 | 2653 | trace_usb_xhci_port_link(port->portnr, pls); |
f705a362 | 2654 | xhci_port_notify(port, PORTSC_CSC); |
62c6ae04 HM |
2655 | } |
2656 | ||
dad5b9ea | 2657 | static void xhci_port_reset(XHCIPort *port, bool warm_reset) |
40030130 | 2658 | { |
7bd3055f | 2659 | trace_usb_xhci_port_reset(port->portnr, warm_reset); |
4f47f0f8 | 2660 | |
b62b0828 GH |
2661 | if (!xhci_port_have_device(port)) { |
2662 | return; | |
2663 | } | |
2664 | ||
40030130 | 2665 | usb_device_reset(port->uport->dev); |
b62b0828 GH |
2666 | |
2667 | switch (port->uport->dev->speed) { | |
dad5b9ea GH |
2668 | case USB_SPEED_SUPER: |
2669 | if (warm_reset) { | |
2670 | port->portsc |= PORTSC_WRC; | |
2671 | } | |
2672 | /* fall through */ | |
b62b0828 GH |
2673 | case USB_SPEED_LOW: |
2674 | case USB_SPEED_FULL: | |
2675 | case USB_SPEED_HIGH: | |
2676 | set_field(&port->portsc, PLS_U0, PORTSC_PLS); | |
4f47f0f8 | 2677 | trace_usb_xhci_port_link(port->portnr, PLS_U0); |
b62b0828 GH |
2678 | port->portsc |= PORTSC_PED; |
2679 | break; | |
2680 | } | |
2681 | ||
2682 | port->portsc &= ~PORTSC_PR; | |
2683 | xhci_port_notify(port, PORTSC_PRC); | |
40030130 GH |
2684 | } |
2685 | ||
64619739 | 2686 | static void xhci_reset(DeviceState *dev) |
62c6ae04 | 2687 | { |
37034575 | 2688 | XHCIState *xhci = XHCI(dev); |
62c6ae04 HM |
2689 | int i; |
2690 | ||
2d754a10 | 2691 | trace_usb_xhci_reset(); |
62c6ae04 | 2692 | if (!(xhci->usbsts & USBSTS_HCH)) { |
d6bb65fc | 2693 | DPRINTF("xhci: reset while running!\n"); |
62c6ae04 HM |
2694 | } |
2695 | ||
2696 | xhci->usbcmd = 0; | |
2697 | xhci->usbsts = USBSTS_HCH; | |
2698 | xhci->dnctrl = 0; | |
2699 | xhci->crcr_low = 0; | |
2700 | xhci->crcr_high = 0; | |
2701 | xhci->dcbaap_low = 0; | |
2702 | xhci->dcbaap_high = 0; | |
2703 | xhci->config = 0; | |
62c6ae04 | 2704 | |
91062ae0 | 2705 | for (i = 0; i < xhci->numslots; i++) { |
62c6ae04 HM |
2706 | xhci_disable_slot(xhci, i+1); |
2707 | } | |
2708 | ||
0846e635 | 2709 | for (i = 0; i < xhci->numports; i++) { |
f3214027 | 2710 | xhci_port_update(xhci->ports + i, 0); |
62c6ae04 HM |
2711 | } |
2712 | ||
91062ae0 | 2713 | for (i = 0; i < xhci->numintrs; i++) { |
962d11e1 GH |
2714 | xhci->intr[i].iman = 0; |
2715 | xhci->intr[i].imod = 0; | |
2716 | xhci->intr[i].erstsz = 0; | |
2717 | xhci->intr[i].erstba_low = 0; | |
2718 | xhci->intr[i].erstba_high = 0; | |
2719 | xhci->intr[i].erdp_low = 0; | |
2720 | xhci->intr[i].erdp_high = 0; | |
2721 | xhci->intr[i].msix_used = 0; | |
62c6ae04 | 2722 | |
962d11e1 GH |
2723 | xhci->intr[i].er_ep_idx = 0; |
2724 | xhci->intr[i].er_pcs = 1; | |
962d11e1 GH |
2725 | xhci->intr[i].ev_buffer_put = 0; |
2726 | xhci->intr[i].ev_buffer_get = 0; | |
2727 | } | |
01546fa6 | 2728 | |
bc72ad67 | 2729 | xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
01546fa6 | 2730 | xhci_mfwrap_update(xhci); |
62c6ae04 HM |
2731 | } |
2732 | ||
a8170e5e | 2733 | static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2734 | { |
1b067564 | 2735 | XHCIState *xhci = ptr; |
2d754a10 | 2736 | uint32_t ret; |
62c6ae04 HM |
2737 | |
2738 | switch (reg) { | |
2739 | case 0x00: /* HCIVERSION, CAPLENGTH */ | |
2d754a10 GH |
2740 | ret = 0x01000000 | LEN_CAP; |
2741 | break; | |
62c6ae04 | 2742 | case 0x04: /* HCSPARAMS 1 */ |
0846e635 | 2743 | ret = ((xhci->numports_2+xhci->numports_3)<<24) |
91062ae0 | 2744 | | (xhci->numintrs<<8) | xhci->numslots; |
2d754a10 | 2745 | break; |
62c6ae04 | 2746 | case 0x08: /* HCSPARAMS 2 */ |
2d754a10 GH |
2747 | ret = 0x0000000f; |
2748 | break; | |
62c6ae04 | 2749 | case 0x0c: /* HCSPARAMS 3 */ |
2d754a10 GH |
2750 | ret = 0x00000000; |
2751 | break; | |
62c6ae04 | 2752 | case 0x10: /* HCCPARAMS */ |
2d754a10 | 2753 | if (sizeof(dma_addr_t) == 4) { |
2aa6bfcb | 2754 | ret = 0x00080000 | (xhci->max_pstreams_mask << 12); |
2d754a10 | 2755 | } else { |
2aa6bfcb | 2756 | ret = 0x00080001 | (xhci->max_pstreams_mask << 12); |
2d754a10 GH |
2757 | } |
2758 | break; | |
62c6ae04 | 2759 | case 0x14: /* DBOFF */ |
2d754a10 GH |
2760 | ret = OFF_DOORBELL; |
2761 | break; | |
62c6ae04 | 2762 | case 0x18: /* RTSOFF */ |
2d754a10 GH |
2763 | ret = OFF_RUNTIME; |
2764 | break; | |
62c6ae04 HM |
2765 | |
2766 | /* extended capabilities */ | |
2767 | case 0x20: /* Supported Protocol:00 */ | |
2d754a10 GH |
2768 | ret = 0x02000402; /* USB 2.0 */ |
2769 | break; | |
62c6ae04 | 2770 | case 0x24: /* Supported Protocol:04 */ |
0ebfb144 | 2771 | ret = 0x20425355; /* "USB " */ |
2d754a10 | 2772 | break; |
62c6ae04 | 2773 | case 0x28: /* Supported Protocol:08 */ |
7bafd888 GH |
2774 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
2775 | ret = (xhci->numports_2<<8) | (xhci->numports_3+1); | |
2776 | } else { | |
2777 | ret = (xhci->numports_2<<8) | 1; | |
2778 | } | |
2d754a10 | 2779 | break; |
62c6ae04 | 2780 | case 0x2c: /* Supported Protocol:0c */ |
2d754a10 GH |
2781 | ret = 0x00000000; /* reserved */ |
2782 | break; | |
62c6ae04 | 2783 | case 0x30: /* Supported Protocol:00 */ |
2d754a10 GH |
2784 | ret = 0x03000002; /* USB 3.0 */ |
2785 | break; | |
62c6ae04 | 2786 | case 0x34: /* Supported Protocol:04 */ |
0ebfb144 | 2787 | ret = 0x20425355; /* "USB " */ |
2d754a10 | 2788 | break; |
62c6ae04 | 2789 | case 0x38: /* Supported Protocol:08 */ |
7bafd888 GH |
2790 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
2791 | ret = (xhci->numports_3<<8) | 1; | |
2792 | } else { | |
2793 | ret = (xhci->numports_3<<8) | (xhci->numports_2+1); | |
2794 | } | |
2d754a10 | 2795 | break; |
62c6ae04 | 2796 | case 0x3c: /* Supported Protocol:0c */ |
2d754a10 GH |
2797 | ret = 0x00000000; /* reserved */ |
2798 | break; | |
62c6ae04 | 2799 | default: |
0ab966cf | 2800 | trace_usb_xhci_unimplemented("cap read", reg); |
2d754a10 | 2801 | ret = 0; |
62c6ae04 | 2802 | } |
2d754a10 GH |
2803 | |
2804 | trace_usb_xhci_cap_read(reg, ret); | |
2805 | return ret; | |
62c6ae04 HM |
2806 | } |
2807 | ||
a8170e5e | 2808 | static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2809 | { |
1d8a4e69 | 2810 | XHCIPort *port = ptr; |
2d754a10 GH |
2811 | uint32_t ret; |
2812 | ||
1d8a4e69 | 2813 | switch (reg) { |
62c6ae04 | 2814 | case 0x00: /* PORTSC */ |
1d8a4e69 | 2815 | ret = port->portsc; |
2d754a10 | 2816 | break; |
62c6ae04 HM |
2817 | case 0x04: /* PORTPMSC */ |
2818 | case 0x08: /* PORTLI */ | |
2d754a10 GH |
2819 | ret = 0; |
2820 | break; | |
62c6ae04 HM |
2821 | case 0x0c: /* reserved */ |
2822 | default: | |
0ab966cf | 2823 | trace_usb_xhci_unimplemented("port read", reg); |
2d754a10 | 2824 | ret = 0; |
62c6ae04 | 2825 | } |
2d754a10 | 2826 | |
1d8a4e69 | 2827 | trace_usb_xhci_port_read(port->portnr, reg, ret); |
2d754a10 | 2828 | return ret; |
62c6ae04 HM |
2829 | } |
2830 | ||
a8170e5e | 2831 | static void xhci_port_write(void *ptr, hwaddr reg, |
1d8a4e69 | 2832 | uint64_t val, unsigned size) |
62c6ae04 | 2833 | { |
1d8a4e69 | 2834 | XHCIPort *port = ptr; |
bdfce20d | 2835 | uint32_t portsc, notify; |
62c6ae04 | 2836 | |
1d8a4e69 | 2837 | trace_usb_xhci_port_write(port->portnr, reg, val); |
2d754a10 | 2838 | |
1d8a4e69 | 2839 | switch (reg) { |
62c6ae04 | 2840 | case 0x00: /* PORTSC */ |
bdfce20d | 2841 | /* write-1-to-start bits */ |
dad5b9ea GH |
2842 | if (val & PORTSC_WPR) { |
2843 | xhci_port_reset(port, true); | |
2844 | break; | |
2845 | } | |
bdfce20d | 2846 | if (val & PORTSC_PR) { |
dad5b9ea | 2847 | xhci_port_reset(port, false); |
bdfce20d GH |
2848 | break; |
2849 | } | |
2850 | ||
1d8a4e69 | 2851 | portsc = port->portsc; |
bdfce20d | 2852 | notify = 0; |
62c6ae04 HM |
2853 | /* write-1-to-clear bits*/ |
2854 | portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| | |
2855 | PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); | |
2856 | if (val & PORTSC_LWS) { | |
2857 | /* overwrite PLS only when LWS=1 */ | |
bdfce20d GH |
2858 | uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); |
2859 | uint32_t new_pls = get_field(val, PORTSC_PLS); | |
2860 | switch (new_pls) { | |
2861 | case PLS_U0: | |
2862 | if (old_pls != PLS_U0) { | |
2863 | set_field(&portsc, new_pls, PORTSC_PLS); | |
2864 | trace_usb_xhci_port_link(port->portnr, new_pls); | |
2865 | notify = PORTSC_PLC; | |
2866 | } | |
2867 | break; | |
2868 | case PLS_U3: | |
2869 | if (old_pls < PLS_U3) { | |
2870 | set_field(&portsc, new_pls, PORTSC_PLS); | |
2871 | trace_usb_xhci_port_link(port->portnr, new_pls); | |
2872 | } | |
2873 | break; | |
2874 | case PLS_RESUME: | |
2875 | /* windows does this for some reason, don't spam stderr */ | |
2876 | break; | |
2877 | default: | |
d6bb65fc | 2878 | DPRINTF("%s: ignore pls write (old %d, new %d)\n", |
bdfce20d GH |
2879 | __func__, old_pls, new_pls); |
2880 | break; | |
2881 | } | |
62c6ae04 HM |
2882 | } |
2883 | /* read/write bits */ | |
2884 | portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); | |
2885 | portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); | |
40030130 | 2886 | port->portsc = portsc; |
bdfce20d GH |
2887 | if (notify) { |
2888 | xhci_port_notify(port, notify); | |
62c6ae04 | 2889 | } |
62c6ae04 HM |
2890 | break; |
2891 | case 0x04: /* PORTPMSC */ | |
2892 | case 0x08: /* PORTLI */ | |
2893 | default: | |
0ab966cf | 2894 | trace_usb_xhci_unimplemented("port write", reg); |
62c6ae04 HM |
2895 | } |
2896 | } | |
2897 | ||
a8170e5e | 2898 | static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2899 | { |
1b067564 | 2900 | XHCIState *xhci = ptr; |
2d754a10 | 2901 | uint32_t ret; |
62c6ae04 | 2902 | |
62c6ae04 HM |
2903 | switch (reg) { |
2904 | case 0x00: /* USBCMD */ | |
2d754a10 GH |
2905 | ret = xhci->usbcmd; |
2906 | break; | |
62c6ae04 | 2907 | case 0x04: /* USBSTS */ |
2d754a10 GH |
2908 | ret = xhci->usbsts; |
2909 | break; | |
62c6ae04 | 2910 | case 0x08: /* PAGESIZE */ |
2d754a10 GH |
2911 | ret = 1; /* 4KiB */ |
2912 | break; | |
62c6ae04 | 2913 | case 0x14: /* DNCTRL */ |
2d754a10 GH |
2914 | ret = xhci->dnctrl; |
2915 | break; | |
62c6ae04 | 2916 | case 0x18: /* CRCR low */ |
2d754a10 GH |
2917 | ret = xhci->crcr_low & ~0xe; |
2918 | break; | |
62c6ae04 | 2919 | case 0x1c: /* CRCR high */ |
2d754a10 GH |
2920 | ret = xhci->crcr_high; |
2921 | break; | |
62c6ae04 | 2922 | case 0x30: /* DCBAAP low */ |
2d754a10 GH |
2923 | ret = xhci->dcbaap_low; |
2924 | break; | |
62c6ae04 | 2925 | case 0x34: /* DCBAAP high */ |
2d754a10 GH |
2926 | ret = xhci->dcbaap_high; |
2927 | break; | |
62c6ae04 | 2928 | case 0x38: /* CONFIG */ |
2d754a10 GH |
2929 | ret = xhci->config; |
2930 | break; | |
62c6ae04 | 2931 | default: |
0ab966cf | 2932 | trace_usb_xhci_unimplemented("oper read", reg); |
2d754a10 | 2933 | ret = 0; |
62c6ae04 | 2934 | } |
2d754a10 GH |
2935 | |
2936 | trace_usb_xhci_oper_read(reg, ret); | |
2937 | return ret; | |
62c6ae04 HM |
2938 | } |
2939 | ||
a8170e5e | 2940 | static void xhci_oper_write(void *ptr, hwaddr reg, |
1b067564 | 2941 | uint64_t val, unsigned size) |
62c6ae04 | 2942 | { |
1b067564 | 2943 | XHCIState *xhci = ptr; |
37034575 | 2944 | DeviceState *d = DEVICE(ptr); |
1b067564 | 2945 | |
2d754a10 GH |
2946 | trace_usb_xhci_oper_write(reg, val); |
2947 | ||
62c6ae04 HM |
2948 | switch (reg) { |
2949 | case 0x00: /* USBCMD */ | |
2950 | if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { | |
2951 | xhci_run(xhci); | |
2952 | } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { | |
2953 | xhci_stop(xhci); | |
2954 | } | |
f1f8bc21 GH |
2955 | if (val & USBCMD_CSS) { |
2956 | /* save state */ | |
2957 | xhci->usbsts &= ~USBSTS_SRE; | |
2958 | } | |
2959 | if (val & USBCMD_CRS) { | |
2960 | /* restore state */ | |
2961 | xhci->usbsts |= USBSTS_SRE; | |
2962 | } | |
62c6ae04 | 2963 | xhci->usbcmd = val & 0xc0f; |
01546fa6 | 2964 | xhci_mfwrap_update(xhci); |
62c6ae04 | 2965 | if (val & USBCMD_HCRST) { |
37034575 | 2966 | xhci_reset(d); |
62c6ae04 | 2967 | } |
4c4abe7c | 2968 | xhci_intx_update(xhci); |
62c6ae04 HM |
2969 | break; |
2970 | ||
2971 | case 0x04: /* USBSTS */ | |
2972 | /* these bits are write-1-to-clear */ | |
2973 | xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); | |
4c4abe7c | 2974 | xhci_intx_update(xhci); |
62c6ae04 HM |
2975 | break; |
2976 | ||
2977 | case 0x14: /* DNCTRL */ | |
2978 | xhci->dnctrl = val & 0xffff; | |
2979 | break; | |
2980 | case 0x18: /* CRCR low */ | |
2981 | xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); | |
2982 | break; | |
2983 | case 0x1c: /* CRCR high */ | |
2984 | xhci->crcr_high = val; | |
2985 | if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { | |
2986 | XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; | |
2987 | xhci->crcr_low &= ~CRCR_CRR; | |
2d1de850 | 2988 | xhci_event(xhci, &event, 0); |
62c6ae04 HM |
2989 | DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); |
2990 | } else { | |
59a70ccd | 2991 | dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); |
62c6ae04 HM |
2992 | xhci_ring_init(xhci, &xhci->cmd_ring, base); |
2993 | } | |
2994 | xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); | |
2995 | break; | |
2996 | case 0x30: /* DCBAAP low */ | |
2997 | xhci->dcbaap_low = val & 0xffffffc0; | |
2998 | break; | |
2999 | case 0x34: /* DCBAAP high */ | |
3000 | xhci->dcbaap_high = val; | |
3001 | break; | |
3002 | case 0x38: /* CONFIG */ | |
3003 | xhci->config = val & 0xff; | |
3004 | break; | |
3005 | default: | |
0ab966cf | 3006 | trace_usb_xhci_unimplemented("oper write", reg); |
62c6ae04 HM |
3007 | } |
3008 | } | |
3009 | ||
a8170e5e | 3010 | static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, |
1b067564 | 3011 | unsigned size) |
62c6ae04 | 3012 | { |
1b067564 | 3013 | XHCIState *xhci = ptr; |
43d9d604 | 3014 | uint32_t ret = 0; |
62c6ae04 | 3015 | |
43d9d604 GH |
3016 | if (reg < 0x20) { |
3017 | switch (reg) { | |
3018 | case 0x00: /* MFINDEX */ | |
3019 | ret = xhci_mfindex_get(xhci) & 0x3fff; | |
3020 | break; | |
3021 | default: | |
0ab966cf | 3022 | trace_usb_xhci_unimplemented("runtime read", reg); |
43d9d604 GH |
3023 | break; |
3024 | } | |
3025 | } else { | |
3026 | int v = (reg - 0x20) / 0x20; | |
3027 | XHCIInterrupter *intr = &xhci->intr[v]; | |
3028 | switch (reg & 0x1f) { | |
3029 | case 0x00: /* IMAN */ | |
3030 | ret = intr->iman; | |
3031 | break; | |
3032 | case 0x04: /* IMOD */ | |
3033 | ret = intr->imod; | |
3034 | break; | |
3035 | case 0x08: /* ERSTSZ */ | |
3036 | ret = intr->erstsz; | |
3037 | break; | |
3038 | case 0x10: /* ERSTBA low */ | |
3039 | ret = intr->erstba_low; | |
3040 | break; | |
3041 | case 0x14: /* ERSTBA high */ | |
3042 | ret = intr->erstba_high; | |
3043 | break; | |
3044 | case 0x18: /* ERDP low */ | |
3045 | ret = intr->erdp_low; | |
3046 | break; | |
3047 | case 0x1c: /* ERDP high */ | |
3048 | ret = intr->erdp_high; | |
3049 | break; | |
3050 | } | |
62c6ae04 | 3051 | } |
2d754a10 GH |
3052 | |
3053 | trace_usb_xhci_runtime_read(reg, ret); | |
3054 | return ret; | |
62c6ae04 HM |
3055 | } |
3056 | ||
a8170e5e | 3057 | static void xhci_runtime_write(void *ptr, hwaddr reg, |
1b067564 | 3058 | uint64_t val, unsigned size) |
62c6ae04 | 3059 | { |
1b067564 | 3060 | XHCIState *xhci = ptr; |
43d9d604 GH |
3061 | int v = (reg - 0x20) / 0x20; |
3062 | XHCIInterrupter *intr = &xhci->intr[v]; | |
8e9f18b6 | 3063 | trace_usb_xhci_runtime_write(reg, val); |
62c6ae04 | 3064 | |
43d9d604 | 3065 | if (reg < 0x20) { |
0ab966cf | 3066 | trace_usb_xhci_unimplemented("runtime write", reg); |
43d9d604 GH |
3067 | return; |
3068 | } | |
3069 | ||
3070 | switch (reg & 0x1f) { | |
3071 | case 0x00: /* IMAN */ | |
62c6ae04 | 3072 | if (val & IMAN_IP) { |
962d11e1 | 3073 | intr->iman &= ~IMAN_IP; |
62c6ae04 | 3074 | } |
962d11e1 GH |
3075 | intr->iman &= ~IMAN_IE; |
3076 | intr->iman |= val & IMAN_IE; | |
43d9d604 GH |
3077 | if (v == 0) { |
3078 | xhci_intx_update(xhci); | |
3079 | } | |
3080 | xhci_msix_update(xhci, v); | |
62c6ae04 | 3081 | break; |
43d9d604 | 3082 | case 0x04: /* IMOD */ |
962d11e1 | 3083 | intr->imod = val; |
62c6ae04 | 3084 | break; |
43d9d604 | 3085 | case 0x08: /* ERSTSZ */ |
962d11e1 | 3086 | intr->erstsz = val & 0xffff; |
62c6ae04 | 3087 | break; |
43d9d604 | 3088 | case 0x10: /* ERSTBA low */ |
2992d6b4 GH |
3089 | if (xhci->nec_quirks) { |
3090 | /* NEC driver bug: it doesn't align this to 64 bytes */ | |
3091 | intr->erstba_low = val & 0xfffffff0; | |
3092 | } else { | |
3093 | intr->erstba_low = val & 0xffffffc0; | |
3094 | } | |
62c6ae04 | 3095 | break; |
43d9d604 | 3096 | case 0x14: /* ERSTBA high */ |
962d11e1 | 3097 | intr->erstba_high = val; |
43d9d604 | 3098 | xhci_er_reset(xhci, v); |
62c6ae04 | 3099 | break; |
43d9d604 | 3100 | case 0x18: /* ERDP low */ |
62c6ae04 | 3101 | if (val & ERDP_EHB) { |
962d11e1 | 3102 | intr->erdp_low &= ~ERDP_EHB; |
62c6ae04 | 3103 | } |
962d11e1 | 3104 | intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); |
7da76e12 GH |
3105 | if (val & ERDP_EHB) { |
3106 | dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); | |
3107 | unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE; | |
3108 | if (erdp >= intr->er_start && | |
3109 | erdp < (intr->er_start + TRB_SIZE * intr->er_size) && | |
3110 | dp_idx != intr->er_ep_idx) { | |
3111 | xhci_intr_raise(xhci, v); | |
3112 | } | |
3113 | } | |
62c6ae04 | 3114 | break; |
43d9d604 | 3115 | case 0x1c: /* ERDP high */ |
962d11e1 | 3116 | intr->erdp_high = val; |
62c6ae04 HM |
3117 | break; |
3118 | default: | |
0ab966cf | 3119 | trace_usb_xhci_unimplemented("oper write", reg); |
62c6ae04 HM |
3120 | } |
3121 | } | |
3122 | ||
a8170e5e | 3123 | static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, |
1b067564 | 3124 | unsigned size) |
62c6ae04 | 3125 | { |
62c6ae04 | 3126 | /* doorbells always read as 0 */ |
2d754a10 | 3127 | trace_usb_xhci_doorbell_read(reg, 0); |
62c6ae04 HM |
3128 | return 0; |
3129 | } | |
3130 | ||
a8170e5e | 3131 | static void xhci_doorbell_write(void *ptr, hwaddr reg, |
1b067564 | 3132 | uint64_t val, unsigned size) |
62c6ae04 | 3133 | { |
1b067564 | 3134 | XHCIState *xhci = ptr; |
024426ac | 3135 | unsigned int epid, streamid; |
1b067564 | 3136 | |
2d754a10 | 3137 | trace_usb_xhci_doorbell_write(reg, val); |
62c6ae04 HM |
3138 | |
3139 | if (!xhci_running(xhci)) { | |
d6bb65fc | 3140 | DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); |
62c6ae04 HM |
3141 | return; |
3142 | } | |
3143 | ||
3144 | reg >>= 2; | |
3145 | ||
3146 | if (reg == 0) { | |
3147 | if (val == 0) { | |
3148 | xhci_process_commands(xhci); | |
3149 | } else { | |
d6bb65fc | 3150 | DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", |
1b067564 | 3151 | (uint32_t)val); |
62c6ae04 HM |
3152 | } |
3153 | } else { | |
024426ac GH |
3154 | epid = val & 0xff; |
3155 | streamid = (val >> 16) & 0xffff; | |
91062ae0 | 3156 | if (reg > xhci->numslots) { |
d6bb65fc | 3157 | DPRINTF("xhci: bad doorbell %d\n", (int)reg); |
0a076730 | 3158 | } else if (epid == 0 || epid > 31) { |
d6bb65fc | 3159 | DPRINTF("xhci: bad doorbell %d write: 0x%x\n", |
1b067564 | 3160 | (int)reg, (uint32_t)val); |
62c6ae04 | 3161 | } else { |
024426ac | 3162 | xhci_kick_ep(xhci, reg, epid, streamid); |
62c6ae04 HM |
3163 | } |
3164 | } | |
3165 | } | |
3166 | ||
6d3bc22e GH |
3167 | static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, |
3168 | unsigned width) | |
3169 | { | |
3170 | /* nothing */ | |
3171 | } | |
3172 | ||
1b067564 GH |
3173 | static const MemoryRegionOps xhci_cap_ops = { |
3174 | .read = xhci_cap_read, | |
6d3bc22e | 3175 | .write = xhci_cap_write, |
6ee021d4 | 3176 | .valid.min_access_size = 1, |
1b067564 | 3177 | .valid.max_access_size = 4, |
6ee021d4 GH |
3178 | .impl.min_access_size = 4, |
3179 | .impl.max_access_size = 4, | |
1b067564 GH |
3180 | .endianness = DEVICE_LITTLE_ENDIAN, |
3181 | }; | |
62c6ae04 | 3182 | |
1b067564 GH |
3183 | static const MemoryRegionOps xhci_oper_ops = { |
3184 | .read = xhci_oper_read, | |
3185 | .write = xhci_oper_write, | |
3186 | .valid.min_access_size = 4, | |
3187 | .valid.max_access_size = 4, | |
3188 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3189 | }; | |
62c6ae04 | 3190 | |
1d8a4e69 GH |
3191 | static const MemoryRegionOps xhci_port_ops = { |
3192 | .read = xhci_port_read, | |
3193 | .write = xhci_port_write, | |
3194 | .valid.min_access_size = 4, | |
3195 | .valid.max_access_size = 4, | |
3196 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3197 | }; | |
3198 | ||
1b067564 GH |
3199 | static const MemoryRegionOps xhci_runtime_ops = { |
3200 | .read = xhci_runtime_read, | |
3201 | .write = xhci_runtime_write, | |
3202 | .valid.min_access_size = 4, | |
3203 | .valid.max_access_size = 4, | |
3204 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3205 | }; | |
62c6ae04 | 3206 | |
1b067564 GH |
3207 | static const MemoryRegionOps xhci_doorbell_ops = { |
3208 | .read = xhci_doorbell_read, | |
3209 | .write = xhci_doorbell_write, | |
62c6ae04 HM |
3210 | .valid.min_access_size = 4, |
3211 | .valid.max_access_size = 4, | |
3212 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3213 | }; | |
3214 | ||
3215 | static void xhci_attach(USBPort *usbport) | |
3216 | { | |
3217 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3218 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
62c6ae04 | 3219 | |
f3214027 | 3220 | xhci_port_update(port, 0); |
62c6ae04 HM |
3221 | } |
3222 | ||
3223 | static void xhci_detach(USBPort *usbport) | |
3224 | { | |
3225 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3226 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
62c6ae04 | 3227 | |
f3dcf638 | 3228 | xhci_detach_slot(xhci, usbport); |
f3214027 | 3229 | xhci_port_update(port, 1); |
62c6ae04 HM |
3230 | } |
3231 | ||
8c735e43 GH |
3232 | static void xhci_wakeup(USBPort *usbport) |
3233 | { | |
3234 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3235 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
8c735e43 | 3236 | |
92cf3427 | 3237 | assert(port); |
85e05d82 | 3238 | if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { |
8c735e43 GH |
3239 | return; |
3240 | } | |
85e05d82 | 3241 | set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); |
f705a362 | 3242 | xhci_port_notify(port, PORTSC_PLC); |
8c735e43 GH |
3243 | } |
3244 | ||
62c6ae04 HM |
3245 | static void xhci_complete(USBPort *port, USBPacket *packet) |
3246 | { | |
3247 | XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); | |
3248 | ||
9a77a0f5 | 3249 | if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { |
582d6f4a | 3250 | xhci_ep_nuke_one_xfer(xfer, 0); |
0cae7b1a HG |
3251 | return; |
3252 | } | |
13e8ff7a | 3253 | xhci_try_complete_packet(xfer); |
3a533ee8 | 3254 | xhci_kick_epctx(xfer->epctx, xfer->streamid); |
94b037f2 GH |
3255 | if (xfer->complete) { |
3256 | xhci_ep_free_xfer(xfer); | |
3257 | } | |
62c6ae04 HM |
3258 | } |
3259 | ||
ccaf87a0 | 3260 | static void xhci_child_detach(USBPort *uport, USBDevice *child) |
62c6ae04 | 3261 | { |
ccaf87a0 GH |
3262 | USBBus *bus = usb_bus_from_device(child); |
3263 | XHCIState *xhci = container_of(bus, XHCIState, bus); | |
ccaf87a0 | 3264 | |
463c534d | 3265 | xhci_detach_slot(xhci, child->port); |
62c6ae04 HM |
3266 | } |
3267 | ||
1d8a4e69 | 3268 | static USBPortOps xhci_uport_ops = { |
62c6ae04 HM |
3269 | .attach = xhci_attach, |
3270 | .detach = xhci_detach, | |
8c735e43 | 3271 | .wakeup = xhci_wakeup, |
62c6ae04 HM |
3272 | .complete = xhci_complete, |
3273 | .child_detach = xhci_child_detach, | |
3274 | }; | |
3275 | ||
7c605a23 GH |
3276 | static int xhci_find_epid(USBEndpoint *ep) |
3277 | { | |
3278 | if (ep->nr == 0) { | |
3279 | return 1; | |
3280 | } | |
3281 | if (ep->pid == USB_TOKEN_IN) { | |
3282 | return ep->nr * 2 + 1; | |
3283 | } else { | |
3284 | return ep->nr * 2; | |
3285 | } | |
3286 | } | |
3287 | ||
070eeef9 | 3288 | static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx) |
518ad5f2 | 3289 | { |
070eeef9 GH |
3290 | USBPort *uport; |
3291 | uint32_t token; | |
518ad5f2 | 3292 | |
070eeef9 | 3293 | if (!epctx) { |
518ad5f2 HG |
3294 | return NULL; |
3295 | } | |
070eeef9 | 3296 | uport = epctx->xhci->slots[epctx->slotid - 1].uport; |
7cb513aa | 3297 | if (!uport || !uport->dev) { |
070eeef9 GH |
3298 | return NULL; |
3299 | } | |
7cb513aa | 3300 | token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT; |
070eeef9 | 3301 | return usb_ep_get(uport->dev, token, epctx->epid >> 1); |
518ad5f2 HG |
3302 | } |
3303 | ||
8550a02d GH |
3304 | static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, |
3305 | unsigned int stream) | |
7c605a23 GH |
3306 | { |
3307 | XHCIState *xhci = container_of(bus, XHCIState, bus); | |
3308 | int slotid; | |
3309 | ||
3310 | DPRINTF("%s\n", __func__); | |
af203be3 | 3311 | slotid = ep->dev->addr; |
7c605a23 GH |
3312 | if (slotid == 0 || !xhci->slots[slotid-1].enabled) { |
3313 | DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); | |
3314 | return; | |
3315 | } | |
024426ac | 3316 | xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); |
7c605a23 GH |
3317 | } |
3318 | ||
62c6ae04 | 3319 | static USBBusOps xhci_bus_ops = { |
7c605a23 | 3320 | .wakeup_endpoint = xhci_wakeup_endpoint, |
62c6ae04 HM |
3321 | }; |
3322 | ||
37034575 | 3323 | static void usb_xhci_init(XHCIState *xhci) |
62c6ae04 | 3324 | { |
37034575 | 3325 | DeviceState *dev = DEVICE(xhci); |
0846e635 | 3326 | XHCIPort *port; |
ccb79931 | 3327 | unsigned int i, usbports, speedmask; |
62c6ae04 HM |
3328 | |
3329 | xhci->usbsts = USBSTS_HCH; | |
3330 | ||
0846e635 GH |
3331 | if (xhci->numports_2 > MAXPORTS_2) { |
3332 | xhci->numports_2 = MAXPORTS_2; | |
3333 | } | |
3334 | if (xhci->numports_3 > MAXPORTS_3) { | |
3335 | xhci->numports_3 = MAXPORTS_3; | |
3336 | } | |
3337 | usbports = MAX(xhci->numports_2, xhci->numports_3); | |
3338 | xhci->numports = xhci->numports_2 + xhci->numports_3; | |
3339 | ||
c889b3a5 | 3340 | usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); |
62c6ae04 | 3341 | |
0846e635 GH |
3342 | for (i = 0; i < usbports; i++) { |
3343 | speedmask = 0; | |
3344 | if (i < xhci->numports_2) { | |
7bafd888 GH |
3345 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
3346 | port = &xhci->ports[i + xhci->numports_3]; | |
3347 | port->portnr = i + 1 + xhci->numports_3; | |
3348 | } else { | |
3349 | port = &xhci->ports[i]; | |
3350 | port->portnr = i + 1; | |
3351 | } | |
0846e635 GH |
3352 | port->uport = &xhci->uports[i]; |
3353 | port->speedmask = | |
3354 | USB_SPEED_MASK_LOW | | |
3355 | USB_SPEED_MASK_FULL | | |
3356 | USB_SPEED_MASK_HIGH; | |
ccb79931 | 3357 | assert(i < MAXPORTS); |
1d8a4e69 | 3358 | snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); |
0846e635 GH |
3359 | speedmask |= port->speedmask; |
3360 | } | |
3361 | if (i < xhci->numports_3) { | |
7bafd888 GH |
3362 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
3363 | port = &xhci->ports[i]; | |
3364 | port->portnr = i + 1; | |
3365 | } else { | |
3366 | port = &xhci->ports[i + xhci->numports_2]; | |
3367 | port->portnr = i + 1 + xhci->numports_2; | |
3368 | } | |
0846e635 GH |
3369 | port->uport = &xhci->uports[i]; |
3370 | port->speedmask = USB_SPEED_MASK_SUPER; | |
ccb79931 | 3371 | assert(i < MAXPORTS); |
1d8a4e69 | 3372 | snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); |
0846e635 GH |
3373 | speedmask |= port->speedmask; |
3374 | } | |
3375 | usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, | |
1d8a4e69 | 3376 | &xhci_uport_ops, speedmask); |
62c6ae04 | 3377 | } |
62c6ae04 HM |
3378 | } |
3379 | ||
9af21dbe | 3380 | static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) |
62c6ae04 | 3381 | { |
1d8a4e69 | 3382 | int i, ret; |
1108b2f8 | 3383 | Error *err = NULL; |
62c6ae04 | 3384 | |
37034575 | 3385 | XHCIState *xhci = XHCI(dev); |
62c6ae04 | 3386 | |
9b7d3334 AF |
3387 | dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ |
3388 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ | |
3389 | dev->config[PCI_CACHE_LINE_SIZE] = 0x10; | |
3390 | dev->config[0x60] = 0x30; /* release number */ | |
62c6ae04 | 3391 | |
2992d6b4 GH |
3392 | if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { |
3393 | xhci->nec_quirks = true; | |
3394 | } | |
91062ae0 GH |
3395 | if (xhci->numintrs > MAXINTRS) { |
3396 | xhci->numintrs = MAXINTRS; | |
3397 | } | |
c94a7c69 GH |
3398 | while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ |
3399 | xhci->numintrs++; | |
3400 | } | |
91062ae0 GH |
3401 | if (xhci->numintrs < 1) { |
3402 | xhci->numintrs = 1; | |
3403 | } | |
3404 | if (xhci->numslots > MAXSLOTS) { | |
3405 | xhci->numslots = MAXSLOTS; | |
3406 | } | |
3407 | if (xhci->numslots < 1) { | |
3408 | xhci->numslots = 1; | |
3409 | } | |
2aa6bfcb GH |
3410 | if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { |
3411 | xhci->max_pstreams_mask = 7; /* == 256 primary streams */ | |
3412 | } else { | |
3413 | xhci->max_pstreams_mask = 0; | |
3414 | } | |
91062ae0 | 3415 | |
20729dbd C |
3416 | if (xhci->msi != ON_OFF_AUTO_OFF) { |
3417 | ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err); | |
3418 | /* Any error other than -ENOTSUP(board's MSI support is broken) | |
3419 | * is a programming error */ | |
3420 | assert(!ret || ret == -ENOTSUP); | |
3421 | if (ret && xhci->msi == ON_OFF_AUTO_ON) { | |
3422 | /* Can't satisfy user's explicit msi=on request, fail */ | |
3423 | error_append_hint(&err, "You have to use msi=auto (default) or " | |
3424 | "msi=off with this machine type.\n"); | |
3425 | error_propagate(errp, err); | |
3426 | return; | |
3427 | } | |
3428 | assert(!err || xhci->msi == ON_OFF_AUTO_AUTO); | |
3429 | /* With msi=auto, we fall back to MSI off silently */ | |
3430 | error_free(err); | |
3431 | } | |
3432 | ||
3433 | usb_xhci_init(xhci); | |
bc72ad67 | 3434 | xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); |
01546fa6 | 3435 | |
22fc860b PB |
3436 | memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); |
3437 | memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, | |
1b067564 | 3438 | "capabilities", LEN_CAP); |
22fc860b | 3439 | memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, |
1d8a4e69 | 3440 | "operational", 0x400); |
22fc860b | 3441 | memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, |
1b067564 | 3442 | "runtime", LEN_RUNTIME); |
22fc860b | 3443 | memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, |
1b067564 GH |
3444 | "doorbell", LEN_DOORBELL); |
3445 | ||
3446 | memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); | |
3447 | memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); | |
3448 | memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); | |
3449 | memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); | |
3450 | ||
1d8a4e69 GH |
3451 | for (i = 0; i < xhci->numports; i++) { |
3452 | XHCIPort *port = &xhci->ports[i]; | |
3453 | uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; | |
3454 | port->xhci = xhci; | |
22fc860b | 3455 | memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, |
1d8a4e69 GH |
3456 | port->name, 0x10); |
3457 | memory_region_add_subregion(&xhci->mem, offset, &port->mem); | |
3458 | } | |
3459 | ||
9b7d3334 | 3460 | pci_register_bar(dev, 0, |
62c6ae04 HM |
3461 | PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, |
3462 | &xhci->mem); | |
3463 | ||
fd56e061 | 3464 | if (pci_bus_is_express(pci_get_bus(dev)) || |
e6043e92 | 3465 | xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { |
058fdcf5 | 3466 | ret = pcie_endpoint_cap_init(dev, 0xa0); |
9a815774 | 3467 | assert(ret > 0); |
058fdcf5 | 3468 | } |
62c6ae04 | 3469 | |
290fd20d | 3470 | if (xhci->msix != ON_OFF_AUTO_OFF) { |
ee640c62 | 3471 | /* TODO check for errors, and should fail when msix=on */ |
9b7d3334 | 3472 | msix_init(dev, xhci->numintrs, |
4c47f800 GH |
3473 | &xhci->mem, 0, OFF_MSIX_TABLE, |
3474 | &xhci->mem, 0, OFF_MSIX_PBA, | |
ee640c62 | 3475 | 0x90, NULL); |
4c47f800 | 3476 | } |
62c6ae04 HM |
3477 | } |
3478 | ||
53c30545 GA |
3479 | static void usb_xhci_exit(PCIDevice *dev) |
3480 | { | |
3481 | int i; | |
3482 | XHCIState *xhci = XHCI(dev); | |
3483 | ||
d733f74c GA |
3484 | trace_usb_xhci_exit(); |
3485 | ||
53c30545 GA |
3486 | for (i = 0; i < xhci->numslots; i++) { |
3487 | xhci_disable_slot(xhci, i + 1); | |
3488 | } | |
3489 | ||
3490 | if (xhci->mfwrap_timer) { | |
3491 | timer_del(xhci->mfwrap_timer); | |
3492 | timer_free(xhci->mfwrap_timer); | |
3493 | xhci->mfwrap_timer = NULL; | |
3494 | } | |
3495 | ||
3496 | memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); | |
3497 | memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); | |
3498 | memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); | |
3499 | memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); | |
3500 | ||
3501 | for (i = 0; i < xhci->numports; i++) { | |
3502 | XHCIPort *port = &xhci->ports[i]; | |
3503 | memory_region_del_subregion(&xhci->mem, &port->mem); | |
3504 | } | |
3505 | ||
3506 | /* destroy msix memory region */ | |
3507 | if (dev->msix_table && dev->msix_pba | |
3508 | && dev->msix_entry_used) { | |
b53dd449 | 3509 | msix_uninit(dev, &xhci->mem, &xhci->mem); |
53c30545 GA |
3510 | } |
3511 | ||
3512 | usb_bus_release(&xhci->bus); | |
3513 | } | |
3514 | ||
37352df3 GH |
3515 | static int usb_xhci_post_load(void *opaque, int version_id) |
3516 | { | |
3517 | XHCIState *xhci = opaque; | |
9b7d3334 | 3518 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
37352df3 GH |
3519 | XHCISlot *slot; |
3520 | XHCIEPContext *epctx; | |
3521 | dma_addr_t dcbaap, pctx; | |
3522 | uint32_t slot_ctx[4]; | |
3523 | uint32_t ep_ctx[5]; | |
3524 | int slotid, epid, state, intr; | |
3525 | ||
3526 | dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); | |
3527 | ||
3528 | for (slotid = 1; slotid <= xhci->numslots; slotid++) { | |
3529 | slot = &xhci->slots[slotid-1]; | |
3530 | if (!slot->addressed) { | |
3531 | continue; | |
3532 | } | |
3533 | slot->ctx = | |
9b7d3334 | 3534 | xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); |
37352df3 GH |
3535 | xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); |
3536 | slot->uport = xhci_lookup_uport(xhci, slot_ctx); | |
f2ad97ff GH |
3537 | if (!slot->uport) { |
3538 | /* should not happen, but may trigger on guest bugs */ | |
3539 | slot->enabled = 0; | |
3540 | slot->addressed = 0; | |
3541 | continue; | |
3542 | } | |
37352df3 GH |
3543 | assert(slot->uport && slot->uport->dev); |
3544 | ||
f6969b9f | 3545 | for (epid = 1; epid <= 31; epid++) { |
37352df3 GH |
3546 | pctx = slot->ctx + 32 * epid; |
3547 | xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); | |
3548 | state = ep_ctx[0] & EP_STATE_MASK; | |
3549 | if (state == EP_DISABLED) { | |
3550 | continue; | |
3551 | } | |
3552 | epctx = xhci_alloc_epctx(xhci, slotid, epid); | |
3553 | slot->eps[epid-1] = epctx; | |
3554 | xhci_init_epctx(epctx, pctx, ep_ctx); | |
3555 | epctx->state = state; | |
3556 | if (state == EP_RUNNING) { | |
3557 | /* kick endpoint after vmload is finished */ | |
bc72ad67 | 3558 | timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
37352df3 GH |
3559 | } |
3560 | } | |
3561 | } | |
3562 | ||
3563 | for (intr = 0; intr < xhci->numintrs; intr++) { | |
3564 | if (xhci->intr[intr].msix_used) { | |
9b7d3334 | 3565 | msix_vector_use(pci_dev, intr); |
37352df3 | 3566 | } else { |
9b7d3334 | 3567 | msix_vector_unuse(pci_dev, intr); |
37352df3 GH |
3568 | } |
3569 | } | |
3570 | ||
3571 | return 0; | |
3572 | } | |
3573 | ||
3574 | static const VMStateDescription vmstate_xhci_ring = { | |
3575 | .name = "xhci-ring", | |
3576 | .version_id = 1, | |
3577 | .fields = (VMStateField[]) { | |
3578 | VMSTATE_UINT64(dequeue, XHCIRing), | |
3579 | VMSTATE_BOOL(ccs, XHCIRing), | |
3580 | VMSTATE_END_OF_LIST() | |
3581 | } | |
3582 | }; | |
3583 | ||
3584 | static const VMStateDescription vmstate_xhci_port = { | |
3585 | .name = "xhci-port", | |
3586 | .version_id = 1, | |
3587 | .fields = (VMStateField[]) { | |
3588 | VMSTATE_UINT32(portsc, XHCIPort), | |
3589 | VMSTATE_END_OF_LIST() | |
3590 | } | |
3591 | }; | |
3592 | ||
3593 | static const VMStateDescription vmstate_xhci_slot = { | |
3594 | .name = "xhci-slot", | |
3595 | .version_id = 1, | |
3596 | .fields = (VMStateField[]) { | |
3597 | VMSTATE_BOOL(enabled, XHCISlot), | |
3598 | VMSTATE_BOOL(addressed, XHCISlot), | |
3599 | VMSTATE_END_OF_LIST() | |
3600 | } | |
3601 | }; | |
3602 | ||
3603 | static const VMStateDescription vmstate_xhci_event = { | |
3604 | .name = "xhci-event", | |
3605 | .version_id = 1, | |
3606 | .fields = (VMStateField[]) { | |
3607 | VMSTATE_UINT32(type, XHCIEvent), | |
3608 | VMSTATE_UINT32(ccode, XHCIEvent), | |
3609 | VMSTATE_UINT64(ptr, XHCIEvent), | |
3610 | VMSTATE_UINT32(length, XHCIEvent), | |
3611 | VMSTATE_UINT32(flags, XHCIEvent), | |
3612 | VMSTATE_UINT8(slotid, XHCIEvent), | |
3613 | VMSTATE_UINT8(epid, XHCIEvent), | |
3afca1d6 | 3614 | VMSTATE_END_OF_LIST() |
37352df3 GH |
3615 | } |
3616 | }; | |
3617 | ||
3618 | static bool xhci_er_full(void *opaque, int version_id) | |
3619 | { | |
898248a3 | 3620 | return false; |
37352df3 GH |
3621 | } |
3622 | ||
3623 | static const VMStateDescription vmstate_xhci_intr = { | |
3624 | .name = "xhci-intr", | |
3625 | .version_id = 1, | |
3626 | .fields = (VMStateField[]) { | |
3627 | /* registers */ | |
3628 | VMSTATE_UINT32(iman, XHCIInterrupter), | |
3629 | VMSTATE_UINT32(imod, XHCIInterrupter), | |
3630 | VMSTATE_UINT32(erstsz, XHCIInterrupter), | |
3631 | VMSTATE_UINT32(erstba_low, XHCIInterrupter), | |
3632 | VMSTATE_UINT32(erstba_high, XHCIInterrupter), | |
3633 | VMSTATE_UINT32(erdp_low, XHCIInterrupter), | |
3634 | VMSTATE_UINT32(erdp_high, XHCIInterrupter), | |
3635 | ||
3636 | /* state */ | |
3637 | VMSTATE_BOOL(msix_used, XHCIInterrupter), | |
3638 | VMSTATE_BOOL(er_pcs, XHCIInterrupter), | |
3639 | VMSTATE_UINT64(er_start, XHCIInterrupter), | |
3640 | VMSTATE_UINT32(er_size, XHCIInterrupter), | |
3641 | VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), | |
3642 | ||
3643 | /* event queue (used if ring is full) */ | |
898248a3 | 3644 | VMSTATE_BOOL(er_full_unused, XHCIInterrupter), |
37352df3 GH |
3645 | VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), |
3646 | VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), | |
3647 | VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, | |
3648 | xhci_er_full, 1, | |
3649 | vmstate_xhci_event, XHCIEvent), | |
3650 | ||
3651 | VMSTATE_END_OF_LIST() | |
3652 | } | |
3653 | }; | |
3654 | ||
62c6ae04 HM |
3655 | static const VMStateDescription vmstate_xhci = { |
3656 | .name = "xhci", | |
37352df3 GH |
3657 | .version_id = 1, |
3658 | .post_load = usb_xhci_post_load, | |
3659 | .fields = (VMStateField[]) { | |
20daa90a | 3660 | VMSTATE_PCI_DEVICE(parent_obj, XHCIState), |
9b7d3334 | 3661 | VMSTATE_MSIX(parent_obj, XHCIState), |
37352df3 GH |
3662 | |
3663 | VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, | |
3664 | vmstate_xhci_port, XHCIPort), | |
3665 | VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, | |
3666 | vmstate_xhci_slot, XHCISlot), | |
3667 | VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, | |
3668 | vmstate_xhci_intr, XHCIInterrupter), | |
3669 | ||
3670 | /* Operational Registers */ | |
3671 | VMSTATE_UINT32(usbcmd, XHCIState), | |
3672 | VMSTATE_UINT32(usbsts, XHCIState), | |
3673 | VMSTATE_UINT32(dnctrl, XHCIState), | |
3674 | VMSTATE_UINT32(crcr_low, XHCIState), | |
3675 | VMSTATE_UINT32(crcr_high, XHCIState), | |
3676 | VMSTATE_UINT32(dcbaap_low, XHCIState), | |
3677 | VMSTATE_UINT32(dcbaap_high, XHCIState), | |
3678 | VMSTATE_UINT32(config, XHCIState), | |
3679 | ||
3680 | /* Runtime Registers & state */ | |
3681 | VMSTATE_INT64(mfindex_start, XHCIState), | |
e720677e | 3682 | VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), |
37352df3 GH |
3683 | VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), |
3684 | ||
3685 | VMSTATE_END_OF_LIST() | |
3686 | } | |
62c6ae04 HM |
3687 | }; |
3688 | ||
4f72b8d2 GH |
3689 | static Property xhci_properties[] = { |
3690 | DEFINE_PROP_BIT("streams", XHCIState, flags, | |
3691 | XHCI_FLAG_ENABLE_STREAMS, true), | |
91062ae0 GH |
3692 | DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), |
3693 | DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), | |
39bffca2 AL |
3694 | DEFINE_PROP_END_OF_LIST(), |
3695 | }; | |
3696 | ||
d61a363d YB |
3697 | static void xhci_instance_init(Object *obj) |
3698 | { | |
3699 | /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command | |
3700 | * line, therefore, no need to wait to realize like other devices */ | |
3701 | PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
3702 | } | |
3703 | ||
40021f08 AL |
3704 | static void xhci_class_init(ObjectClass *klass, void *data) |
3705 | { | |
3706 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 3707 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 3708 | |
39bffca2 | 3709 | dc->vmsd = &vmstate_xhci; |
4f67d30b | 3710 | device_class_set_props(dc, xhci_properties); |
64619739 | 3711 | dc->reset = xhci_reset; |
125ee0ed | 3712 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
9af21dbe | 3713 | k->realize = usb_xhci_realize; |
53c30545 | 3714 | k->exit = usb_xhci_exit; |
40021f08 | 3715 | k->class_id = PCI_CLASS_SERIAL_USB; |
40021f08 AL |
3716 | } |
3717 | ||
8c43a6f0 | 3718 | static const TypeInfo xhci_info = { |
37034575 | 3719 | .name = TYPE_XHCI, |
39bffca2 AL |
3720 | .parent = TYPE_PCI_DEVICE, |
3721 | .instance_size = sizeof(XHCIState), | |
3722 | .class_init = xhci_class_init, | |
d61a363d | 3723 | .instance_init = xhci_instance_init, |
72a810f4 | 3724 | .abstract = true, |
a5fa336f EH |
3725 | .interfaces = (InterfaceInfo[]) { |
3726 | { INTERFACE_PCIE_DEVICE }, | |
3727 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
3728 | { } | |
3729 | }, | |
72a810f4 GH |
3730 | }; |
3731 | ||
72a810f4 GH |
3732 | static void qemu_xhci_class_init(ObjectClass *klass, void *data) |
3733 | { | |
3734 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
3735 | ||
3736 | k->vendor_id = PCI_VENDOR_ID_REDHAT; | |
3737 | k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; | |
3738 | k->revision = 0x01; | |
3739 | } | |
3740 | ||
4f72b8d2 GH |
3741 | static void qemu_xhci_instance_init(Object *obj) |
3742 | { | |
3743 | XHCIState *xhci = XHCI(obj); | |
3744 | ||
3745 | xhci->msi = ON_OFF_AUTO_OFF; | |
3746 | xhci->msix = ON_OFF_AUTO_AUTO; | |
3747 | xhci->numintrs = MAXINTRS; | |
3748 | xhci->numslots = MAXSLOTS; | |
3749 | xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST); | |
3750 | } | |
3751 | ||
72a810f4 GH |
3752 | static const TypeInfo qemu_xhci_info = { |
3753 | .name = TYPE_QEMU_XHCI, | |
3754 | .parent = TYPE_XHCI, | |
3755 | .class_init = qemu_xhci_class_init, | |
4f72b8d2 | 3756 | .instance_init = qemu_xhci_instance_init, |
62c6ae04 HM |
3757 | }; |
3758 | ||
83f7d43a | 3759 | static void xhci_register_types(void) |
62c6ae04 | 3760 | { |
39bffca2 | 3761 | type_register_static(&xhci_info); |
72a810f4 | 3762 | type_register_static(&qemu_xhci_info); |
62c6ae04 | 3763 | } |
83f7d43a AF |
3764 | |
3765 | type_init(xhci_register_types) |