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xhci: emulate intr endpoint intervals correctly
[mirror_qemu.git] / hw / usb / hcd-xhci.c
CommitLineData
62c6ae04
HM		 1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
f1ae32a1 21#include "hw/hw.h"
1de7afc9 22#include "qemu/timer.h"
f1ae32a1 23#include "hw/usb.h"
a2cb15b0
MT		 24#include "hw/pci/pci.h"
25#include "hw/pci/msi.h"
26#include "hw/pci/msix.h"
2d754a10 27#include "trace.h"
62c6ae04
HM		 28
29//#define DEBUG_XHCI
30//#define DEBUG_DATA
31
32#ifdef DEBUG_XHCI
33#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34#else
35#define DPRINTF(...) do {} while (0)
36#endif
024426ac
GH		 37#define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
62c6ae04 39
d95e74ea
GH		 40#define MAXPORTS_2 15
41#define MAXPORTS_3 15
62c6ae04 42
0846e635 43#define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
d95e74ea
GH		 44#define MAXSLOTS 64
45#define MAXINTRS 16
62c6ae04
HM		 46
47#define TD_QUEUE 24
62c6ae04
HM		 48
49/* Very pessimistic, let's hope it's enough for all cases */
50#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51/* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53#define ER_FULL_HACK
54
55#define LEN_CAP 0x40
62c6ae04 56#define LEN_OPER (0x400 + 0x10 * MAXPORTS)
106b214c 57#define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
62c6ae04
HM		 58#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
106b214c
GH		 60#define OFF_OPER LEN_CAP
61#define OFF_RUNTIME 0x1000
62#define OFF_DOORBELL 0x2000
4c47f800
GH		 63#define OFF_MSIX_TABLE 0x3000
64#define OFF_MSIX_PBA 0x3800
62c6ae04 65/* must be power of 2 */
106b214c 66#define LEN_REGS 0x4000
62c6ae04 67
106b214c
GH		 68#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69#error Increase OFF_RUNTIME
70#endif
71#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72#error Increase OFF_DOORBELL
73#endif
62c6ae04
HM		 74#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75# error Increase LEN_REGS
76#endif
77
62c6ae04
HM		 78/* bit definitions */
79#define USBCMD_RS (1<<0)
80#define USBCMD_HCRST (1<<1)
81#define USBCMD_INTE (1<<2)
82#define USBCMD_HSEE (1<<3)
83#define USBCMD_LHCRST (1<<7)
84#define USBCMD_CSS (1<<8)
85#define USBCMD_CRS (1<<9)
86#define USBCMD_EWE (1<<10)
87#define USBCMD_EU3S (1<<11)
88
89#define USBSTS_HCH (1<<0)
90#define USBSTS_HSE (1<<2)
91#define USBSTS_EINT (1<<3)
92#define USBSTS_PCD (1<<4)
93#define USBSTS_SSS (1<<8)
94#define USBSTS_RSS (1<<9)
95#define USBSTS_SRE (1<<10)
96#define USBSTS_CNR (1<<11)
97#define USBSTS_HCE (1<<12)
98
99
100#define PORTSC_CCS (1<<0)
101#define PORTSC_PED (1<<1)
102#define PORTSC_OCA (1<<3)
103#define PORTSC_PR (1<<4)
104#define PORTSC_PLS_SHIFT 5
105#define PORTSC_PLS_MASK 0xf
106#define PORTSC_PP (1<<9)
107#define PORTSC_SPEED_SHIFT 10
108#define PORTSC_SPEED_MASK 0xf
109#define PORTSC_SPEED_FULL (1<<10)
110#define PORTSC_SPEED_LOW (2<<10)
111#define PORTSC_SPEED_HIGH (3<<10)
112#define PORTSC_SPEED_SUPER (4<<10)
113#define PORTSC_PIC_SHIFT 14
114#define PORTSC_PIC_MASK 0x3
115#define PORTSC_LWS (1<<16)
116#define PORTSC_CSC (1<<17)
117#define PORTSC_PEC (1<<18)
118#define PORTSC_WRC (1<<19)
119#define PORTSC_OCC (1<<20)
120#define PORTSC_PRC (1<<21)
121#define PORTSC_PLC (1<<22)
122#define PORTSC_CEC (1<<23)
123#define PORTSC_CAS (1<<24)
124#define PORTSC_WCE (1<<25)
125#define PORTSC_WDE (1<<26)
126#define PORTSC_WOE (1<<27)
127#define PORTSC_DR (1<<30)
128#define PORTSC_WPR (1<<31)
129
130#define CRCR_RCS (1<<0)
131#define CRCR_CS (1<<1)
132#define CRCR_CA (1<<2)
133#define CRCR_CRR (1<<3)
134
135#define IMAN_IP (1<<0)
136#define IMAN_IE (1<<1)
137
138#define ERDP_EHB (1<<3)
139
140#define TRB_SIZE 16
141typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
59a70ccd 145 dma_addr_t addr;
62c6ae04
HM		 146 bool ccs;
147} XHCITRB;
148
85e05d82
GH		 149enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163};
62c6ae04
HM		 164
165typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202} TRBType;
203
204#define CR_LINK TR_LINK
205
206typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242} TRBCCode;
243
244#define TRB_C (1<<0)
245#define TRB_TYPE_SHIFT 10
246#define TRB_TYPE_MASK 0x3f
247#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
248
249#define TRB_EV_ED (1<<2)
250
251#define TRB_TR_ENT (1<<1)
252#define TRB_TR_ISP (1<<2)
253#define TRB_TR_NS (1<<3)
254#define TRB_TR_CH (1<<4)
255#define TRB_TR_IOC (1<<5)
256#define TRB_TR_IDT (1<<6)
257#define TRB_TR_TBC_SHIFT 7
258#define TRB_TR_TBC_MASK 0x3
259#define TRB_TR_BEI (1<<9)
260#define TRB_TR_TLBPC_SHIFT 16
261#define TRB_TR_TLBPC_MASK 0xf
262#define TRB_TR_FRAMEID_SHIFT 20
263#define TRB_TR_FRAMEID_MASK 0x7ff
264#define TRB_TR_SIA (1<<31)
265
266#define TRB_TR_DIR (1<<16)
267
268#define TRB_CR_SLOTID_SHIFT 24
269#define TRB_CR_SLOTID_MASK 0xff
270#define TRB_CR_EPID_SHIFT 16
271#define TRB_CR_EPID_MASK 0x1f
272
273#define TRB_CR_BSR (1<<9)
274#define TRB_CR_DC (1<<9)
275
276#define TRB_LK_TC (1<<1)
277
2d1de850
GH		 278#define TRB_INTR_SHIFT 22
279#define TRB_INTR_MASK 0x3ff
280#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
281
62c6ae04
HM		 282#define EP_TYPE_MASK 0x7
283#define EP_TYPE_SHIFT 3
284
285#define EP_STATE_MASK 0x7
286#define EP_DISABLED (0<<0)
287#define EP_RUNNING (1<<0)
288#define EP_HALTED (2<<0)
289#define EP_STOPPED (3<<0)
290#define EP_ERROR (4<<0)
291
292#define SLOT_STATE_MASK 0x1f
293#define SLOT_STATE_SHIFT 27
294#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295#define SLOT_ENABLED 0
296#define SLOT_DEFAULT 1
297#define SLOT_ADDRESSED 2
298#define SLOT_CONFIGURED 3
299
300#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301#define SLOT_CONTEXT_ENTRIES_SHIFT 27
302
1d8a4e69 303typedef struct XHCIState XHCIState;
024426ac
GH		 304typedef struct XHCIStreamContext XHCIStreamContext;
305typedef struct XHCIEPContext XHCIEPContext;
1d8a4e69 306
85e05d82
GH		 307#define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310#define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
62c6ae04
HM		 317typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326} EPType;
327
328typedef struct XHCIRing {
59a70ccd 329 dma_addr_t dequeue;
62c6ae04
HM		 330 bool ccs;
331} XHCIRing;
332
333typedef struct XHCIPort {
1d8a4e69 334 XHCIState *xhci;
62c6ae04 335 uint32_t portsc;
0846e635
GH		 336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
1d8a4e69
GH		 339 char name[16];
340 MemoryRegion mem;
62c6ae04
HM		 341} XHCIPort;
342
62c6ae04
HM		 343typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
d5a15814 346 QEMUSGList sgl;
7c605a23
GH		 347 bool running_async;
348 bool running_retry;
62c6ae04
HM		 349 bool cancelled;
350 bool complete;
a6fb2ddb 351 bool int_req;
62c6ae04
HM		 352 unsigned int iso_pkts;
353 unsigned int slotid;
354 unsigned int epid;
024426ac 355 unsigned int streamid;
62c6ae04
HM		 356 bool in_xfer;
357 bool iso_xfer;
4d7a81c0 358 bool timed_xfer;
62c6ae04
HM		 359
360 unsigned int trb_count;
361 unsigned int trb_alloced;
362 XHCITRB *trbs;
363
62c6ae04
HM		 364 TRBCCode status;
365
366 unsigned int pkts;
367 unsigned int pktsize;
368 unsigned int cur_pkt;
3d139684
GH		 369
370 uint64_t mfindex_kick;
62c6ae04
HM		 371} XHCITransfer;
372
024426ac
GH		 373struct XHCIStreamContext {
374 dma_addr_t pctx;
375 unsigned int sct;
376 XHCIRing ring;
377 XHCIStreamContext *sstreams;
378};
379
380struct XHCIEPContext {
3d139684
GH		 381 XHCIState *xhci;
382 unsigned int slotid;
383 unsigned int epid;
384
62c6ae04
HM		 385 XHCIRing ring;
386 unsigned int next_xfer;
387 unsigned int comp_xfer;
388 XHCITransfer transfers[TD_QUEUE];
7c605a23 389 XHCITransfer *retry;
62c6ae04 390 EPType type;
59a70ccd 391 dma_addr_t pctx;
62c6ae04 392 unsigned int max_psize;
62c6ae04 393 uint32_t state;
3d139684 394
024426ac
GH		 395 /* streams */
396 unsigned int max_pstreams;
397 bool lsa;
398 unsigned int nr_pstreams;
399 XHCIStreamContext *pstreams;
400
3d139684
GH		 401 /* iso xfer scheduling */
402 unsigned int interval;
403 int64_t mfindex_last;
404 QEMUTimer *kick_timer;
024426ac 405};
62c6ae04
HM		 406
407typedef struct XHCISlot {
408 bool enabled;
4034e693 409 bool addressed;
59a70ccd 410 dma_addr_t ctx;
ccaf87a0 411 USBPort *uport;
62c6ae04
HM		 412 XHCIEPContext * eps[31];
413} XHCISlot;
414
415typedef struct XHCIEvent {
416 TRBType type;
417 TRBCCode ccode;
418 uint64_t ptr;
419 uint32_t length;
420 uint32_t flags;
421 uint8_t slotid;
422 uint8_t epid;
423} XHCIEvent;
424
962d11e1
GH		 425typedef struct XHCIInterrupter {
426 uint32_t iman;
427 uint32_t imod;
428 uint32_t erstsz;
429 uint32_t erstba_low;
430 uint32_t erstba_high;
431 uint32_t erdp_low;
432 uint32_t erdp_high;
433
434 bool msix_used, er_pcs, er_full;
435
436 dma_addr_t er_start;
437 uint32_t er_size;
438 unsigned int er_ep_idx;
439
440 XHCIEvent ev_buffer[EV_QUEUE];
441 unsigned int ev_buffer_put;
442 unsigned int ev_buffer_get;
443
444} XHCIInterrupter;
445
62c6ae04 446struct XHCIState {
9b7d3334
AF		 447 /*< private >*/
448 PCIDevice parent_obj;
449 /*< public >*/
450
62c6ae04
HM		 451 USBBus bus;
452 qemu_irq irq;
453 MemoryRegion mem;
1b067564
GH		 454 MemoryRegion mem_cap;
455 MemoryRegion mem_oper;
456 MemoryRegion mem_runtime;
457 MemoryRegion mem_doorbell;
62c6ae04 458
0846e635
GH		 459 /* properties */
460 uint32_t numports_2;
461 uint32_t numports_3;
91062ae0
GH		 462 uint32_t numintrs;
463 uint32_t numslots;
c5e9b02d 464 uint32_t flags;
0846e635 465
62c6ae04
HM		 466 /* Operational Registers */
467 uint32_t usbcmd;
468 uint32_t usbsts;
469 uint32_t dnctrl;
470 uint32_t crcr_low;
471 uint32_t crcr_high;
472 uint32_t dcbaap_low;
473 uint32_t dcbaap_high;
474 uint32_t config;
475
0846e635 476 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
62c6ae04
HM		 477 XHCIPort ports[MAXPORTS];
478 XHCISlot slots[MAXSLOTS];
0846e635 479 uint32_t numports;
62c6ae04
HM		 480
481 /* Runtime Registers */
01546fa6
GH		 482 int64_t mfindex_start;
483 QEMUTimer *mfwrap_timer;
962d11e1 484 XHCIInterrupter intr[MAXINTRS];
62c6ae04
HM		 485
486 XHCIRing cmd_ring;
487};
488
37034575
PC		 489#define TYPE_XHCI "nec-usb-xhci"
490
491#define XHCI(obj) \
492 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
493
62c6ae04
HM		 494typedef struct XHCIEvRingSeg {
495 uint32_t addr_low;
496 uint32_t addr_high;
497 uint32_t size;
498 uint32_t rsvd;
499} XHCIEvRingSeg;
500
c5e9b02d
GH		 501enum xhci_flags {
502 XHCI_FLAG_USE_MSI = 1,
4c47f800 503 XHCI_FLAG_USE_MSI_X,
c5e9b02d
GH		 504};
505
01546fa6 506static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
024426ac 507 unsigned int epid, unsigned int streamid);
0bc85da6
GH		 508static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
509 unsigned int epid);
962d11e1
GH		 510static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
511static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
01546fa6 512
f10de44e
GH		 513static const char *TRBType_names[] = {
514 [TRB_RESERVED] = "TRB_RESERVED",
515 [TR_NORMAL] = "TR_NORMAL",
516 [TR_SETUP] = "TR_SETUP",
517 [TR_DATA] = "TR_DATA",
518 [TR_STATUS] = "TR_STATUS",
519 [TR_ISOCH] = "TR_ISOCH",
520 [TR_LINK] = "TR_LINK",
521 [TR_EVDATA] = "TR_EVDATA",
522 [TR_NOOP] = "TR_NOOP",
523 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
524 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
525 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
526 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
527 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
528 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
529 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
530 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
531 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
532 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
533 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
534 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
535 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
536 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
537 [CR_NOOP] = "CR_NOOP",
538 [ER_TRANSFER] = "ER_TRANSFER",
539 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
540 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
541 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
542 [ER_DOORBELL] = "ER_DOORBELL",
543 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
544 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
545 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
546 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
547 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
548 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
549};
550
873123fe
GH		 551static const char *TRBCCode_names[] = {
552 [CC_INVALID] = "CC_INVALID",
553 [CC_SUCCESS] = "CC_SUCCESS",
554 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
555 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
556 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
557 [CC_TRB_ERROR] = "CC_TRB_ERROR",
558 [CC_STALL_ERROR] = "CC_STALL_ERROR",
559 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
560 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
561 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
562 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
563 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
564 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
565 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
566 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
567 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
568 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
569 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
570 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
571 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
572 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
573 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
574 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
575 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
576 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
577 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
578 [CC_STOPPED] = "CC_STOPPED",
579 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
580 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
581 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
582 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
583 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
584 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
585 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
586 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
587 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
588};
589
1c82392a
GH		 590static const char *ep_state_names[] = {
591 [EP_DISABLED] = "disabled",
592 [EP_RUNNING] = "running",
593 [EP_HALTED] = "halted",
594 [EP_STOPPED] = "stopped",
595 [EP_ERROR] = "error",
596};
597
f10de44e
GH		 598static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
599{
600 if (index >= llen || list[index] == NULL) {
601 return "???";
602 }
603 return list[index];
604}
605
606static const char *trb_name(XHCITRB *trb)
607{
608 return lookup_name(TRB_TYPE(*trb), TRBType_names,
609 ARRAY_SIZE(TRBType_names));
610}
f10de44e 611
873123fe
GH		 612static const char *event_name(XHCIEvent *event)
613{
614 return lookup_name(event->ccode, TRBCCode_names,
615 ARRAY_SIZE(TRBCCode_names));
616}
617
1c82392a
GH		 618static const char *ep_state_name(uint32_t state)
619{
620 return lookup_name(state, ep_state_names,
621 ARRAY_SIZE(ep_state_names));
622}
623
01546fa6
GH		 624static uint64_t xhci_mfindex_get(XHCIState *xhci)
625{
bc72ad67 626 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
01546fa6
GH		 627 return (now - xhci->mfindex_start) / 125000;
628}
629
630static void xhci_mfwrap_update(XHCIState *xhci)
631{
632 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
633 uint32_t mfindex, left;
634 int64_t now;
635
636 if ((xhci->usbcmd & bits) == bits) {
bc72ad67 637 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
01546fa6
GH		 638 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
639 left = 0x4000 - mfindex;
bc72ad67 640 timer_mod(xhci->mfwrap_timer, now + left * 125000);
01546fa6 641 } else {
bc72ad67 642 timer_del(xhci->mfwrap_timer);
01546fa6
GH		 643 }
644}
645
646static void xhci_mfwrap_timer(void *opaque)
647{
648 XHCIState *xhci = opaque;
649 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
650
962d11e1 651 xhci_event(xhci, &wrap, 0);
01546fa6
GH		 652 xhci_mfwrap_update(xhci);
653}
62c6ae04 654
59a70ccd 655static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
62c6ae04 656{
59a70ccd
DG		 657 if (sizeof(dma_addr_t) == 4) {
658 return low;
659 } else {
660 return low | (((dma_addr_t)high << 16) << 16);
661 }
62c6ae04
HM		 662}
663
59a70ccd 664static inline dma_addr_t xhci_mask64(uint64_t addr)
62c6ae04 665{
59a70ccd
DG		 666 if (sizeof(dma_addr_t) == 4) {
667 return addr & 0xffffffff;
668 } else {
669 return addr;
670 }
62c6ae04
HM		 671}
672
616b5d53
DG		 673static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
674 uint32_t *buf, size_t len)
675{
676 int i;
677
678 assert((len % sizeof(uint32_t)) == 0);
679
9b7d3334 680 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
616b5d53
DG		 681
682 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
683 buf[i] = le32_to_cpu(buf[i]);
684 }
685}
686
687static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
688 uint32_t *buf, size_t len)
689{
690 int i;
691 uint32_t tmp[len / sizeof(uint32_t)];
692
693 assert((len % sizeof(uint32_t)) == 0);
694
695 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
696 tmp[i] = cpu_to_le32(buf[i]);
697 }
9b7d3334 698 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
616b5d53
DG		 699}
700
0846e635
GH		 701static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
702{
703 int index;
704
705 if (!uport->dev) {
706 return NULL;
707 }
708 switch (uport->dev->speed) {
709 case USB_SPEED_LOW:
710 case USB_SPEED_FULL:
711 case USB_SPEED_HIGH:
712 index = uport->index;
713 break;
714 case USB_SPEED_SUPER:
715 index = uport->index + xhci->numports_2;
716 break;
717 default:
718 return NULL;
719 }
720 return &xhci->ports[index];
721}
722
4c4abe7c 723static void xhci_intx_update(XHCIState *xhci)
62c6ae04 724{
9b7d3334 725 PCIDevice *pci_dev = PCI_DEVICE(xhci);
62c6ae04
HM		 726 int level = 0;
727
9b7d3334
AF		 728 if (msix_enabled(pci_dev) ||
729 msi_enabled(pci_dev)) {
4c4abe7c
GH		 730 return;
731 }
732
962d11e1
GH		 733 if (xhci->intr[0].iman & IMAN_IP &&
734 xhci->intr[0].iman & IMAN_IE &&
215bff17 735 xhci->usbcmd & USBCMD_INTE) {
62c6ae04
HM		 736 level = 1;
737 }
738
4c4abe7c
GH		 739 trace_usb_xhci_irq_intx(level);
740 qemu_set_irq(xhci->irq, level);
741}
742
962d11e1 743static void xhci_msix_update(XHCIState *xhci, int v)
4c47f800 744{
9b7d3334 745 PCIDevice *pci_dev = PCI_DEVICE(xhci);
4c47f800
GH		 746 bool enabled;
747
9b7d3334 748 if (!msix_enabled(pci_dev)) {
4c47f800
GH		 749 return;
750 }
751
962d11e1
GH		 752 enabled = xhci->intr[v].iman & IMAN_IE;
753 if (enabled == xhci->intr[v].msix_used) {
4c47f800
GH		 754 return;
755 }
756
757 if (enabled) {
962d11e1 758 trace_usb_xhci_irq_msix_use(v);
9b7d3334 759 msix_vector_use(pci_dev, v);
962d11e1 760 xhci->intr[v].msix_used = true;
4c47f800 761 } else {
962d11e1 762 trace_usb_xhci_irq_msix_unuse(v);
9b7d3334 763 msix_vector_unuse(pci_dev, v);
962d11e1 764 xhci->intr[v].msix_used = false;
4c47f800
GH		 765 }
766}
767
962d11e1 768static void xhci_intr_raise(XHCIState *xhci, int v)
4c4abe7c 769{
9b7d3334
AF		 770 PCIDevice *pci_dev = PCI_DEVICE(xhci);
771
962d11e1
GH		 772 xhci->intr[v].erdp_low |= ERDP_EHB;
773 xhci->intr[v].iman |= IMAN_IP;
2cae4119
GH		 774 xhci->usbsts |= USBSTS_EINT;
775
962d11e1 776 if (!(xhci->intr[v].iman & IMAN_IE)) {
4c4abe7c
GH		 777 return;
778 }
779
780 if (!(xhci->usbcmd & USBCMD_INTE)) {
781 return;
782 }
783
9b7d3334 784 if (msix_enabled(pci_dev)) {
962d11e1 785 trace_usb_xhci_irq_msix(v);
9b7d3334 786 msix_notify(pci_dev, v);
4c47f800
GH		 787 return;
788 }
789
9b7d3334 790 if (msi_enabled(pci_dev)) {
962d11e1 791 trace_usb_xhci_irq_msi(v);
9b7d3334 792 msi_notify(pci_dev, v);
4c4abe7c 793 return;
62c6ae04 794 }
4c4abe7c 795
962d11e1
GH		 796 if (v == 0) {
797 trace_usb_xhci_irq_intx(1);
798 qemu_set_irq(xhci->irq, 1);
799 }
62c6ae04
HM		 800}
801
802static inline int xhci_running(XHCIState *xhci)
803{
962d11e1 804 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
62c6ae04
HM		 805}
806
807static void xhci_die(XHCIState *xhci)
808{
809 xhci->usbsts |= USBSTS_HCE;
810 fprintf(stderr, "xhci: asserted controller error\n");
811}
812
962d11e1 813static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
62c6ae04 814{
9b7d3334 815 PCIDevice *pci_dev = PCI_DEVICE(xhci);
962d11e1 816 XHCIInterrupter *intr = &xhci->intr[v];
62c6ae04 817 XHCITRB ev_trb;
59a70ccd 818 dma_addr_t addr;
62c6ae04
HM		 819
820 ev_trb.parameter = cpu_to_le64(event->ptr);
821 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
822 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
823 event->flags | (event->type << TRB_TYPE_SHIFT);
962d11e1 824 if (intr->er_pcs) {
62c6ae04
HM		 825 ev_trb.control |= TRB_C;
826 }
827 ev_trb.control = cpu_to_le32(ev_trb.control);
828
962d11e1 829 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
873123fe
GH		 830 event_name(event), ev_trb.parameter,
831 ev_trb.status, ev_trb.control);
62c6ae04 832
962d11e1 833 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
9b7d3334 834 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
62c6ae04 835
962d11e1
GH		 836 intr->er_ep_idx++;
837 if (intr->er_ep_idx >= intr->er_size) {
838 intr->er_ep_idx = 0;
839 intr->er_pcs = !intr->er_pcs;
62c6ae04
HM		 840 }
841}
842
962d11e1 843static void xhci_events_update(XHCIState *xhci, int v)
62c6ae04 844{
962d11e1 845 XHCIInterrupter *intr = &xhci->intr[v];
59a70ccd 846 dma_addr_t erdp;
62c6ae04
HM		 847 unsigned int dp_idx;
848 bool do_irq = 0;
849
850 if (xhci->usbsts & USBSTS_HCH) {
851 return;
852 }
853
962d11e1
GH		 854 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
855 if (erdp < intr->er_start ||
856 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
59a70ccd 857 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
962d11e1
GH		 858 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
859 v, intr->er_start, intr->er_size);
62c6ae04
HM		 860 xhci_die(xhci);
861 return;
862 }
962d11e1
GH		 863 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
864 assert(dp_idx < intr->er_size);
62c6ae04
HM		 865
866 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
867 * deadlocks when the ER is full. Hack it by holding off events until
868 * the driver decides to free at least half of the ring */
962d11e1
GH		 869 if (intr->er_full) {
870 int er_free = dp_idx - intr->er_ep_idx;
62c6ae04 871 if (er_free <= 0) {
962d11e1 872 er_free += intr->er_size;
62c6ae04 873 }
962d11e1 874 if (er_free < (intr->er_size/2)) {
62c6ae04
HM		 875 DPRINTF("xhci_events_update(): event ring still "
876 "more than half full (hack)\n");
877 return;
878 }
879 }
880
962d11e1
GH		 881 while (intr->ev_buffer_put != intr->ev_buffer_get) {
882 assert(intr->er_full);
883 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
62c6ae04
HM		 884 DPRINTF("xhci_events_update(): event ring full again\n");
885#ifndef ER_FULL_HACK
886 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
962d11e1 887 xhci_write_event(xhci, &full, v);
62c6ae04
HM		 888#endif
889 do_irq = 1;
890 break;
891 }
962d11e1
GH		 892 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
893 xhci_write_event(xhci, event, v);
894 intr->ev_buffer_get++;
62c6ae04 895 do_irq = 1;
962d11e1
GH		 896 if (intr->ev_buffer_get == EV_QUEUE) {
897 intr->ev_buffer_get = 0;
62c6ae04
HM		 898 }
899 }
900
901 if (do_irq) {
962d11e1 902 xhci_intr_raise(xhci, v);
62c6ae04
HM		 903 }
904
962d11e1 905 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
62c6ae04 906 DPRINTF("xhci_events_update(): event ring no longer full\n");
962d11e1 907 intr->er_full = 0;
62c6ae04 908 }
62c6ae04
HM		 909}
910
962d11e1 911static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
62c6ae04 912{
2d1de850 913 XHCIInterrupter *intr;
59a70ccd 914 dma_addr_t erdp;
62c6ae04
HM		 915 unsigned int dp_idx;
916
91062ae0
GH		 917 if (v >= xhci->numintrs) {
918 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
2d1de850
GH		 919 return;
920 }
921 intr = &xhci->intr[v];
922
962d11e1 923 if (intr->er_full) {
62c6ae04 924 DPRINTF("xhci_event(): ER full, queueing\n");
962d11e1 925 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
62c6ae04
HM		 926 fprintf(stderr, "xhci: event queue full, dropping event!\n");
927 return;
928 }
962d11e1
GH		 929 intr->ev_buffer[intr->ev_buffer_put++] = *event;
930 if (intr->ev_buffer_put == EV_QUEUE) {
931 intr->ev_buffer_put = 0;
62c6ae04
HM		 932 }
933 return;
934 }
935
962d11e1
GH		 936 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
937 if (erdp < intr->er_start ||
938 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
59a70ccd 939 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
962d11e1
GH		 940 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
941 v, intr->er_start, intr->er_size);
62c6ae04
HM		 942 xhci_die(xhci);
943 return;
944 }
945
962d11e1
GH		 946 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
947 assert(dp_idx < intr->er_size);
62c6ae04 948
962d11e1 949 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
62c6ae04
HM		 950 DPRINTF("xhci_event(): ER full, queueing\n");
951#ifndef ER_FULL_HACK
952 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
953 xhci_write_event(xhci, &full);
954#endif
962d11e1
GH		 955 intr->er_full = 1;
956 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
62c6ae04
HM		 957 fprintf(stderr, "xhci: event queue full, dropping event!\n");
958 return;
959 }
962d11e1
GH		 960 intr->ev_buffer[intr->ev_buffer_put++] = *event;
961 if (intr->ev_buffer_put == EV_QUEUE) {
962 intr->ev_buffer_put = 0;
62c6ae04
HM		 963 }
964 } else {
962d11e1 965 xhci_write_event(xhci, event, v);
62c6ae04
HM		 966 }
967
962d11e1 968 xhci_intr_raise(xhci, v);
62c6ae04
HM		 969}
970
971static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
59a70ccd 972 dma_addr_t base)
62c6ae04 973{
62c6ae04
HM		 974 ring->dequeue = base;
975 ring->ccs = 1;
976}
977
978static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
59a70ccd 979 dma_addr_t *addr)
62c6ae04 980{
9b7d3334
AF		 981 PCIDevice *pci_dev = PCI_DEVICE(xhci);
982
62c6ae04
HM		 983 while (1) {
984 TRBType type;
9b7d3334 985 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
62c6ae04
HM		 986 trb->addr = ring->dequeue;
987 trb->ccs = ring->ccs;
988 le64_to_cpus(&trb->parameter);
989 le32_to_cpus(&trb->status);
990 le32_to_cpus(&trb->control);
991
0703a4a7
GH		 992 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
993 trb->parameter, trb->status, trb->control);
62c6ae04
HM		 994
995 if ((trb->control & TRB_C) != ring->ccs) {
996 return 0;
997 }
998
999 type = TRB_TYPE(*trb);
1000
1001 if (type != TR_LINK) {
1002 if (addr) {
1003 *addr = ring->dequeue;
1004 }
1005 ring->dequeue += TRB_SIZE;
1006 return type;
1007 } else {
1008 ring->dequeue = xhci_mask64(trb->parameter);
1009 if (trb->control & TRB_LK_TC) {
1010 ring->ccs = !ring->ccs;
1011 }
1012 }
1013 }
1014}
1015
1016static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1017{
9b7d3334 1018 PCIDevice *pci_dev = PCI_DEVICE(xhci);
62c6ae04
HM		 1019 XHCITRB trb;
1020 int length = 0;
59a70ccd 1021 dma_addr_t dequeue = ring->dequeue;
62c6ae04
HM		 1022 bool ccs = ring->ccs;
1023 /* hack to bundle together the two/three TDs that make a setup transfer */
1024 bool control_td_set = 0;
1025
1026 while (1) {
1027 TRBType type;
9b7d3334 1028 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
62c6ae04
HM		 1029 le64_to_cpus(&trb.parameter);
1030 le32_to_cpus(&trb.status);
1031 le32_to_cpus(&trb.control);
1032
62c6ae04
HM		 1033 if ((trb.control & TRB_C) != ccs) {
1034 return -length;
1035 }
1036
1037 type = TRB_TYPE(trb);
1038
1039 if (type == TR_LINK) {
1040 dequeue = xhci_mask64(trb.parameter);
1041 if (trb.control & TRB_LK_TC) {
1042 ccs = !ccs;
1043 }
1044 continue;
1045 }
1046
1047 length += 1;
1048 dequeue += TRB_SIZE;
1049
1050 if (type == TR_SETUP) {
1051 control_td_set = 1;
1052 } else if (type == TR_STATUS) {
1053 control_td_set = 0;
1054 }
1055
1056 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1057 return length;
1058 }
1059 }
1060}
1061
962d11e1 1062static void xhci_er_reset(XHCIState *xhci, int v)
62c6ae04 1063{
962d11e1 1064 XHCIInterrupter *intr = &xhci->intr[v];
62c6ae04
HM		 1065 XHCIEvRingSeg seg;
1066
e099ad4b
GH		 1067 if (intr->erstsz == 0) {
1068 /* disabled */
1069 intr->er_start = 0;
1070 intr->er_size = 0;
1071 return;
1072 }
62c6ae04 1073 /* cache the (sole) event ring segment location */
962d11e1
GH		 1074 if (intr->erstsz != 1) {
1075 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
62c6ae04
HM		 1076 xhci_die(xhci);
1077 return;
1078 }
962d11e1 1079 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
9b7d3334 1080 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
62c6ae04
HM		 1081 le32_to_cpus(&seg.addr_low);
1082 le32_to_cpus(&seg.addr_high);
1083 le32_to_cpus(&seg.size);
1084 if (seg.size < 16 || seg.size > 4096) {
1085 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
1086 xhci_die(xhci);
1087 return;
1088 }
962d11e1
GH		 1089 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1090 intr->er_size = seg.size;
62c6ae04 1091
962d11e1
GH		 1092 intr->er_ep_idx = 0;
1093 intr->er_pcs = 1;
1094 intr->er_full = 0;
62c6ae04 1095
962d11e1
GH		 1096 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1097 v, intr->er_start, intr->er_size);
62c6ae04
HM		 1098}
1099
1100static void xhci_run(XHCIState *xhci)
1101{
fc0ddaca 1102 trace_usb_xhci_run();
62c6ae04 1103 xhci->usbsts &= ~USBSTS_HCH;
bc72ad67 1104 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
62c6ae04
HM		 1105}
1106
1107static void xhci_stop(XHCIState *xhci)
1108{
fc0ddaca 1109 trace_usb_xhci_stop();
62c6ae04
HM		 1110 xhci->usbsts |= USBSTS_HCH;
1111 xhci->crcr_low &= ~CRCR_CRR;
1112}
1113
024426ac
GH		 1114static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1115 dma_addr_t base)
1116{
1117 XHCIStreamContext *stctx;
1118 unsigned int i;
1119
1120 stctx = g_new0(XHCIStreamContext, count);
1121 for (i = 0; i < count; i++) {
1122 stctx[i].pctx = base + i * 16;
1123 stctx[i].sct = -1;
1124 }
1125 return stctx;
1126}
1127
1128static void xhci_reset_streams(XHCIEPContext *epctx)
1129{
1130 unsigned int i;
1131
1132 for (i = 0; i < epctx->nr_pstreams; i++) {
1133 epctx->pstreams[i].sct = -1;
1134 g_free(epctx->pstreams[i].sstreams);
1135 }
1136}
1137
1138static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1139{
1140 assert(epctx->pstreams == NULL);
1141 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1142 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1143}
1144
1145static void xhci_free_streams(XHCIEPContext *epctx)
1146{
1147 int i;
1148
1149 assert(epctx->pstreams != NULL);
1150
1151 if (!epctx->lsa) {
1152 for (i = 0; i < epctx->nr_pstreams; i++) {
1153 g_free(epctx->pstreams[i].sstreams);
1154 }
1155 }
1156 g_free(epctx->pstreams);
1157 epctx->pstreams = NULL;
1158 epctx->nr_pstreams = 0;
1159}
1160
1161static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1162 unsigned int streamid,
1163 uint32_t *cc_error)
1164{
1165 XHCIStreamContext *sctx;
1166 dma_addr_t base;
1167 uint32_t ctx[2], sct;
1168
1169 assert(streamid != 0);
1170 if (epctx->lsa) {
1171 if (streamid >= epctx->nr_pstreams) {
1172 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1173 return NULL;
1174 }
1175 sctx = epctx->pstreams + streamid;
1176 } else {
1177 FIXME("secondary streams not implemented yet");
1178 }
1179
1180 if (sctx->sct == -1) {
1181 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
024426ac
GH		 1182 sct = (ctx[0] >> 1) & 0x07;
1183 if (epctx->lsa && sct != 1) {
1184 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1185 return NULL;
1186 }
1187 sctx->sct = sct;
1188 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1189 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1190 }
1191 return sctx;
1192}
1193
62c6ae04 1194static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
024426ac 1195 XHCIStreamContext *sctx, uint32_t state)
62c6ae04
HM		 1196{
1197 uint32_t ctx[5];
024426ac 1198 uint32_t ctx2[2];
62c6ae04 1199
616b5d53 1200 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
62c6ae04
HM		 1201 ctx[0] &= ~EP_STATE_MASK;
1202 ctx[0] |= state;
024426ac
GH		 1203
1204 /* update ring dequeue ptr */
1205 if (epctx->nr_pstreams) {
1206 if (sctx != NULL) {
1207 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1208 ctx2[0] &= 0xe;
1209 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1210 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1211 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1212 }
1213 } else {
1214 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
1215 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
1216 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1217 epctx->pctx, state, ctx[3], ctx[2]);
1218 }
1219
616b5d53 1220 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1c82392a
GH		 1221 if (epctx->state != state) {
1222 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1223 ep_state_name(epctx->state),
1224 ep_state_name(state));
1225 }
62c6ae04
HM		 1226 epctx->state = state;
1227}
1228
3d139684
GH		 1229static void xhci_ep_kick_timer(void *opaque)
1230{
1231 XHCIEPContext *epctx = opaque;
024426ac 1232 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
3d139684
GH		 1233}
1234
492b21f6
GH		 1235static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1236 unsigned int slotid,
1237 unsigned int epid)
1238{
1239 XHCIEPContext *epctx;
1240 int i;
1241
1242 epctx = g_new0(XHCIEPContext, 1);
1243 epctx->xhci = xhci;
1244 epctx->slotid = slotid;
1245 epctx->epid = epid;
1246
1247 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1248 usb_packet_init(&epctx->transfers[i].packet);
1249 }
bc72ad67 1250 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
492b21f6
GH		 1251
1252 return epctx;
1253}
1254
003e15a1
GH		 1255static void xhci_init_epctx(XHCIEPContext *epctx,
1256 dma_addr_t pctx, uint32_t *ctx)
62c6ae04 1257{
59a70ccd 1258 dma_addr_t dequeue;
62c6ae04 1259
62c6ae04 1260 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
62c6ae04
HM		 1261
1262 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1263 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
1264 epctx->pctx = pctx;
1265 epctx->max_psize = ctx[1]>>16;
1266 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
024426ac
GH		 1267 epctx->max_pstreams = (ctx[0] >> 10) & 0xf;
1268 epctx->lsa = (ctx[0] >> 15) & 1;
62c6ae04
HM		 1269 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1270 epid/2, epid%2, epctx->max_psize);
024426ac
GH		 1271 if (epctx->max_pstreams) {
1272 xhci_alloc_streams(epctx, dequeue);
1273 } else {
003e15a1 1274 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
024426ac
GH		 1275 epctx->ring.ccs = ctx[2] & 1;
1276 }
62c6ae04 1277
ca716278 1278 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
003e15a1
GH		 1279}
1280
1281static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1282 unsigned int epid, dma_addr_t pctx,
1283 uint32_t *ctx)
1284{
1285 XHCISlot *slot;
1286 XHCIEPContext *epctx;
1287
1288 trace_usb_xhci_ep_enable(slotid, epid);
1289 assert(slotid >= 1 && slotid <= xhci->numslots);
1290 assert(epid >= 1 && epid <= 31);
1291
1292 slot = &xhci->slots[slotid-1];
1293 if (slot->eps[epid-1]) {
1294 xhci_disable_ep(xhci, slotid, epid);
1295 }
1296
1297 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1298 slot->eps[epid-1] = epctx;
1299 xhci_init_epctx(epctx, pctx, ctx);
1300
3d139684 1301 epctx->mfindex_last = 0;
3d139684 1302
62c6ae04
HM		 1303 epctx->state = EP_RUNNING;
1304 ctx[0] &= ~EP_STATE_MASK;
1305 ctx[0] |= EP_RUNNING;
1306
1307 return CC_SUCCESS;
1308}
1309
3151f209
HG		 1310static int xhci_ep_nuke_one_xfer(XHCITransfer *t)
1311{
1312 int killed = 0;
1313
1314 if (t->running_async) {
1315 usb_cancel_packet(&t->packet);
1316 t->running_async = 0;
1317 t->cancelled = 1;
1318 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n");
1319 killed = 1;
1320 }
1321 if (t->running_retry) {
1322 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1323 if (epctx) {
1324 epctx->retry = NULL;
bc72ad67 1325 timer_del(epctx->kick_timer);
3151f209
HG		 1326 }
1327 t->running_retry = 0;
1328 }
1329 if (t->trbs) {
1330 g_free(t->trbs);
1331 }
1332
1333 t->trbs = NULL;
1334 t->trb_count = t->trb_alloced = 0;
1335
1336 return killed;
1337}
1338
62c6ae04
HM		 1339static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1340 unsigned int epid)
1341{
1342 XHCISlot *slot;
1343 XHCIEPContext *epctx;
1344 int i, xferi, killed = 0;
f79738b0 1345 USBEndpoint *ep = NULL;
91062ae0 1346 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1347 assert(epid >= 1 && epid <= 31);
1348
1349 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1350
1351 slot = &xhci->slots[slotid-1];
1352
1353 if (!slot->eps[epid-1]) {
1354 return 0;
1355 }
1356
1357 epctx = slot->eps[epid-1];
1358
1359 xferi = epctx->next_xfer;
1360 for (i = 0; i < TD_QUEUE; i++) {
f79738b0
HG		 1361 if (epctx->transfers[xferi].packet.ep) {
1362 ep = epctx->transfers[xferi].packet.ep;
1363 }
3151f209 1364 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]);
0cb41e2c 1365 epctx->transfers[xferi].packet.ep = NULL;
62c6ae04
HM		 1366 xferi = (xferi + 1) % TD_QUEUE;
1367 }
f79738b0
HG		 1368 if (ep) {
1369 usb_device_ep_stopped(ep->dev, ep);
1370 }
62c6ae04
HM		 1371 return killed;
1372}
1373
1374static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1375 unsigned int epid)
1376{
1377 XHCISlot *slot;
1378 XHCIEPContext *epctx;
1379
c1f6b493 1380 trace_usb_xhci_ep_disable(slotid, epid);
91062ae0 1381 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1382 assert(epid >= 1 && epid <= 31);
1383
62c6ae04
HM		 1384 slot = &xhci->slots[slotid-1];
1385
1386 if (!slot->eps[epid-1]) {
1387 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1388 return CC_SUCCESS;
1389 }
1390
1391 xhci_ep_nuke_xfers(xhci, slotid, epid);
1392
1393 epctx = slot->eps[epid-1];
1394
024426ac
GH		 1395 if (epctx->nr_pstreams) {
1396 xhci_free_streams(epctx);
1397 }
1398
1399 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
62c6ae04 1400
bc72ad67 1401 timer_free(epctx->kick_timer);
62c6ae04
HM		 1402 g_free(epctx);
1403 slot->eps[epid-1] = NULL;
1404
1405 return CC_SUCCESS;
1406}
1407
1408static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1409 unsigned int epid)
1410{
1411 XHCISlot *slot;
1412 XHCIEPContext *epctx;
1413
c1f6b493 1414 trace_usb_xhci_ep_stop(slotid, epid);
91062ae0 1415 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1416
1417 if (epid < 1 || epid > 31) {
1418 fprintf(stderr, "xhci: bad ep %d\n", epid);
1419 return CC_TRB_ERROR;
1420 }
1421
1422 slot = &xhci->slots[slotid-1];
1423
1424 if (!slot->eps[epid-1]) {
1425 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1426 return CC_EP_NOT_ENABLED_ERROR;
1427 }
1428
1429 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1430 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1431 "data might be lost\n");
1432 }
1433
1434 epctx = slot->eps[epid-1];
1435
024426ac
GH		 1436 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1437
1438 if (epctx->nr_pstreams) {
1439 xhci_reset_streams(epctx);
1440 }
62c6ae04
HM		 1441
1442 return CC_SUCCESS;
1443}
1444
1445static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1446 unsigned int epid)
1447{
1448 XHCISlot *slot;
1449 XHCIEPContext *epctx;
62c6ae04 1450
c1f6b493 1451 trace_usb_xhci_ep_reset(slotid, epid);
91062ae0 1452 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04 1453
62c6ae04
HM		 1454 if (epid < 1 || epid > 31) {
1455 fprintf(stderr, "xhci: bad ep %d\n", epid);
1456 return CC_TRB_ERROR;
1457 }
1458
1459 slot = &xhci->slots[slotid-1];
1460
1461 if (!slot->eps[epid-1]) {
1462 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1463 return CC_EP_NOT_ENABLED_ERROR;
1464 }
1465
1466 epctx = slot->eps[epid-1];
1467
1468 if (epctx->state != EP_HALTED) {
1469 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1470 epid, epctx->state);
1471 return CC_CONTEXT_STATE_ERROR;
1472 }
1473
1474 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1475 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1476 "data might be lost\n");
1477 }
1478
1479 uint8_t ep = epid>>1;
1480
1481 if (epid & 1) {
1482 ep |= 0x80;
1483 }
1484
75cc1c1f
GH		 1485 if (!xhci->slots[slotid-1].uport ||
1486 !xhci->slots[slotid-1].uport->dev) {
62c6ae04
HM		 1487 return CC_USB_TRANSACTION_ERROR;
1488 }
1489
024426ac
GH		 1490 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1491
1492 if (epctx->nr_pstreams) {
1493 xhci_reset_streams(epctx);
1494 }
62c6ae04
HM		 1495
1496 return CC_SUCCESS;
1497}
1498
1499static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
024426ac
GH		 1500 unsigned int epid, unsigned int streamid,
1501 uint64_t pdequeue)
62c6ae04
HM		 1502{
1503 XHCISlot *slot;
1504 XHCIEPContext *epctx;
024426ac 1505 XHCIStreamContext *sctx;
59a70ccd 1506 dma_addr_t dequeue;
62c6ae04 1507
91062ae0 1508 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 1509
1510 if (epid < 1 || epid > 31) {
1511 fprintf(stderr, "xhci: bad ep %d\n", epid);
1512 return CC_TRB_ERROR;
1513 }
1514
024426ac 1515 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
62c6ae04
HM		 1516 dequeue = xhci_mask64(pdequeue);
1517
1518 slot = &xhci->slots[slotid-1];
1519
1520 if (!slot->eps[epid-1]) {
1521 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1522 return CC_EP_NOT_ENABLED_ERROR;
1523 }
1524
1525 epctx = slot->eps[epid-1];
1526
62c6ae04
HM		 1527 if (epctx->state != EP_STOPPED) {
1528 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1529 return CC_CONTEXT_STATE_ERROR;
1530 }
1531
024426ac
GH		 1532 if (epctx->nr_pstreams) {
1533 uint32_t err;
1534 sctx = xhci_find_stream(epctx, streamid, &err);
1535 if (sctx == NULL) {
1536 return err;
1537 }
1538 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1539 sctx->ring.ccs = dequeue & 1;
1540 } else {
1541 sctx = NULL;
1542 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1543 epctx->ring.ccs = dequeue & 1;
1544 }
62c6ae04 1545
024426ac 1546 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
62c6ae04
HM		 1547
1548 return CC_SUCCESS;
1549}
1550
a6fb2ddb 1551static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
62c6ae04 1552{
62c6ae04 1553 XHCIState *xhci = xfer->xhci;
d5a15814 1554 int i;
62c6ae04 1555
a6fb2ddb 1556 xfer->int_req = false;
9b7d3334 1557 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
62c6ae04
HM		 1558 for (i = 0; i < xfer->trb_count; i++) {
1559 XHCITRB *trb = &xfer->trbs[i];
59a70ccd 1560 dma_addr_t addr;
62c6ae04
HM		 1561 unsigned int chunk = 0;
1562
a6fb2ddb
HG		 1563 if (trb->control & TRB_TR_IOC) {
1564 xfer->int_req = true;
1565 }
1566
62c6ae04
HM		 1567 switch (TRB_TYPE(*trb)) {
1568 case TR_DATA:
1569 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1570 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
d5a15814 1571 goto err;
62c6ae04
HM		 1572 }
1573 /* fallthrough */
1574 case TR_NORMAL:
1575 case TR_ISOCH:
1576 addr = xhci_mask64(trb->parameter);
d5a15814
GH		 1577 chunk = trb->status & 0x1ffff;
1578 if (trb->control & TRB_TR_IDT) {
1579 if (chunk > 8 || in_xfer) {
1580 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1581 goto err;
1582 }
1583 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1584 } else {
1585 qemu_sglist_add(&xfer->sgl, addr, chunk);
1586 }
1587 break;
1588 }
1589 }
1590
d5a15814
GH		 1591 return 0;
1592
1593err:
1594 qemu_sglist_destroy(&xfer->sgl);
1595 xhci_die(xhci);
1596 return -1;
1597}
1598
1599static void xhci_xfer_unmap(XHCITransfer *xfer)
1600{
1601 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1602 qemu_sglist_destroy(&xfer->sgl);
1603}
1604
1605static void xhci_xfer_report(XHCITransfer *xfer)
1606{
1607 uint32_t edtla = 0;
1608 unsigned int left;
1609 bool reported = 0;
1610 bool shortpkt = 0;
1611 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1612 XHCIState *xhci = xfer->xhci;
1613 int i;
1614
9b8251c5 1615 left = xfer->packet.actual_length;
d5a15814
GH		 1616
1617 for (i = 0; i < xfer->trb_count; i++) {
1618 XHCITRB *trb = &xfer->trbs[i];
1619 unsigned int chunk = 0;
1620
1621 switch (TRB_TYPE(*trb)) {
1622 case TR_DATA:
1623 case TR_NORMAL:
1624 case TR_ISOCH:
62c6ae04
HM		 1625 chunk = trb->status & 0x1ffff;
1626 if (chunk > left) {
1627 chunk = left;
d5a15814
GH		 1628 if (xfer->status == CC_SUCCESS) {
1629 shortpkt = 1;
62c6ae04
HM		 1630 }
1631 }
1632 left -= chunk;
62c6ae04 1633 edtla += chunk;
62c6ae04
HM		 1634 break;
1635 case TR_STATUS:
1636 reported = 0;
1637 shortpkt = 0;
1638 break;
1639 }
1640
d5a15814
GH		 1641 if (!reported && ((trb->control & TRB_TR_IOC) ||
1642 (shortpkt && (trb->control & TRB_TR_ISP)) ||
9b8251c5 1643 (xfer->status != CC_SUCCESS && left == 0))) {
62c6ae04
HM		 1644 event.slotid = xfer->slotid;
1645 event.epid = xfer->epid;
1646 event.length = (trb->status & 0x1ffff) - chunk;
1647 event.flags = 0;
1648 event.ptr = trb->addr;
1649 if (xfer->status == CC_SUCCESS) {
1650 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1651 } else {
1652 event.ccode = xfer->status;
1653 }
1654 if (TRB_TYPE(*trb) == TR_EVDATA) {
1655 event.ptr = trb->parameter;
1656 event.flags |= TRB_EV_ED;
1657 event.length = edtla & 0xffffff;
1658 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1659 edtla = 0;
1660 }
2d1de850 1661 xhci_event(xhci, &event, TRB_INTR(*trb));
62c6ae04 1662 reported = 1;
d5a15814
GH		 1663 if (xfer->status != CC_SUCCESS) {
1664 return;
1665 }
62c6ae04
HM		 1666 }
1667 }
62c6ae04
HM		 1668}
1669
1670static void xhci_stall_ep(XHCITransfer *xfer)
1671{
1672 XHCIState *xhci = xfer->xhci;
1673 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1674 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
024426ac
GH		 1675 uint32_t err;
1676 XHCIStreamContext *sctx;
62c6ae04 1677
024426ac
GH		 1678 if (epctx->nr_pstreams) {
1679 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1680 if (sctx == NULL) {
1681 return;
1682 }
1683 sctx->ring.dequeue = xfer->trbs[0].addr;
1684 sctx->ring.ccs = xfer->trbs[0].ccs;
1685 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1686 } else {
1687 epctx->ring.dequeue = xfer->trbs[0].addr;
1688 epctx->ring.ccs = xfer->trbs[0].ccs;
1689 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1690 }
62c6ae04
HM		 1691}
1692
1693static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1694 XHCIEPContext *epctx);
1695
5c08106f
GH		 1696static int xhci_setup_packet(XHCITransfer *xfer)
1697{
1698 XHCIState *xhci = xfer->xhci;
5c08106f 1699 USBDevice *dev;
079d0b7f
GH		 1700 USBEndpoint *ep;
1701 int dir;
1702
1703 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
5c08106f
GH		 1704
1705 if (xfer->packet.ep) {
1706 ep = xfer->packet.ep;
1707 dev = ep->dev;
1708 } else {
ccaf87a0
GH		 1709 if (!xhci->slots[xfer->slotid-1].uport) {
1710 fprintf(stderr, "xhci: slot %d has no device\n",
1711 xfer->slotid);
5c08106f
GH		 1712 return -1;
1713 }
ccaf87a0 1714 dev = xhci->slots[xfer->slotid-1].uport->dev;
5c08106f
GH		 1715 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1716 }
1717
a6fb2ddb 1718 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
024426ac 1719 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
8550a02d 1720 xfer->trbs[0].addr, false, xfer->int_req);
a6fb2ddb 1721 usb_packet_map(&xfer->packet, &xfer->sgl);
62c6ae04 1722 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
079d0b7f 1723 xfer->packet.pid, dev->addr, ep->nr);
62c6ae04
HM		 1724 return 0;
1725}
1726
9a77a0f5 1727static int xhci_complete_packet(XHCITransfer *xfer)
62c6ae04 1728{
9a77a0f5 1729 if (xfer->packet.status == USB_RET_ASYNC) {
97df650b 1730 trace_usb_xhci_xfer_async(xfer);
7c605a23
GH		 1731 xfer->running_async = 1;
1732 xfer->running_retry = 0;
1733 xfer->complete = 0;
1734 xfer->cancelled = 0;
1735 return 0;
9a77a0f5 1736 } else if (xfer->packet.status == USB_RET_NAK) {
97df650b 1737 trace_usb_xhci_xfer_nak(xfer);
7c605a23
GH		 1738 xfer->running_async = 0;
1739 xfer->running_retry = 1;
62c6ae04
HM		 1740 xfer->complete = 0;
1741 xfer->cancelled = 0;
1742 return 0;
1743 } else {
7c605a23
GH		 1744 xfer->running_async = 0;
1745 xfer->running_retry = 0;
62c6ae04 1746 xfer->complete = 1;
d5a15814 1747 xhci_xfer_unmap(xfer);
62c6ae04
HM		 1748 }
1749
9a77a0f5
HG		 1750 if (xfer->packet.status == USB_RET_SUCCESS) {
1751 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
d5a15814
GH		 1752 xfer->status = CC_SUCCESS;
1753 xhci_xfer_report(xfer);
62c6ae04
HM		 1754 return 0;
1755 }
1756
1757 /* error */
9a77a0f5
HG		 1758 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1759 switch (xfer->packet.status) {
62c6ae04 1760 case USB_RET_NODEV:
ed60ff02 1761 case USB_RET_IOERROR:
62c6ae04 1762 xfer->status = CC_USB_TRANSACTION_ERROR;
d5a15814 1763 xhci_xfer_report(xfer);
62c6ae04
HM		 1764 xhci_stall_ep(xfer);
1765 break;
1766 case USB_RET_STALL:
1767 xfer->status = CC_STALL_ERROR;
d5a15814 1768 xhci_xfer_report(xfer);
62c6ae04
HM		 1769 xhci_stall_ep(xfer);
1770 break;
4e906d56
GH		 1771 case USB_RET_BABBLE:
1772 xfer->status = CC_BABBLE_DETECTED;
1773 xhci_xfer_report(xfer);
1774 xhci_stall_ep(xfer);
1775 break;
62c6ae04 1776 default:
9a77a0f5
HG		 1777 fprintf(stderr, "%s: FIXME: status = %d\n", __func__,
1778 xfer->packet.status);
024426ac 1779 FIXME("unhandled USB_RET_*");
62c6ae04
HM		 1780 }
1781 return 0;
1782}
1783
1784static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1785{
1786 XHCITRB *trb_setup, *trb_status;
2850ca9e 1787 uint8_t bmRequestType;
62c6ae04 1788
62c6ae04
HM		 1789 trb_setup = &xfer->trbs[0];
1790 trb_status = &xfer->trbs[xfer->trb_count-1];
1791
024426ac 1792 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
97df650b 1793
62c6ae04
HM		 1794 /* at most one Event Data TRB allowed after STATUS */
1795 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1796 trb_status--;
1797 }
1798
1799 /* do some sanity checks */
1800 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1801 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1802 TRB_TYPE(*trb_setup));
1803 return -1;
1804 }
1805 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1806 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1807 TRB_TYPE(*trb_status));
1808 return -1;
1809 }
1810 if (!(trb_setup->control & TRB_TR_IDT)) {
1811 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1812 return -1;
1813 }
1814 if ((trb_setup->status & 0x1ffff) != 8) {
1815 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1816 (trb_setup->status & 0x1ffff));
1817 return -1;
1818 }
1819
1820 bmRequestType = trb_setup->parameter;
62c6ae04 1821
62c6ae04
HM		 1822 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1823 xfer->iso_xfer = false;
4d7a81c0 1824 xfer->timed_xfer = false;
62c6ae04 1825
5c08106f
GH		 1826 if (xhci_setup_packet(xfer) < 0) {
1827 return -1;
1828 }
2850ca9e 1829 xfer->packet.parameter = trb_setup->parameter;
2850ca9e 1830
9a77a0f5 1831 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
62c6ae04 1832
9a77a0f5 1833 xhci_complete_packet(xfer);
7c605a23 1834 if (!xfer->running_async && !xfer->running_retry) {
024426ac 1835 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
62c6ae04
HM		 1836 }
1837 return 0;
1838}
1839
4d7a81c0
GH		 1840static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1841 XHCIEPContext *epctx, uint64_t mfindex)
1842{
1843 uint64_t asap = ((mfindex + epctx->interval - 1) &
1844 ~(epctx->interval-1));
1845 uint64_t kick = epctx->mfindex_last + epctx->interval;
1846
1847 assert(epctx->interval != 0);
1848 xfer->mfindex_kick = MAX(asap, kick);
1849}
1850
3d139684
GH		 1851static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1852 XHCIEPContext *epctx, uint64_t mfindex)
1853{
1854 if (xfer->trbs[0].control & TRB_TR_SIA) {
1855 uint64_t asap = ((mfindex + epctx->interval - 1) &
1856 ~(epctx->interval-1));
1857 if (asap >= epctx->mfindex_last &&
1858 asap <= epctx->mfindex_last + epctx->interval * 4) {
1859 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1860 } else {
1861 xfer->mfindex_kick = asap;
1862 }
1863 } else {
1864 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1865 & TRB_TR_FRAMEID_MASK;
1866 xfer->mfindex_kick |= mfindex & ~0x3fff;
1867 if (xfer->mfindex_kick < mfindex) {
1868 xfer->mfindex_kick += 0x4000;
1869 }
1870 }
1871}
1872
4d7a81c0
GH		 1873static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1874 XHCIEPContext *epctx, uint64_t mfindex)
3d139684
GH		 1875{
1876 if (xfer->mfindex_kick > mfindex) {
bc72ad67 1877 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
3d139684
GH		 1878 (xfer->mfindex_kick - mfindex) * 125000);
1879 xfer->running_retry = 1;
1880 } else {
1881 epctx->mfindex_last = xfer->mfindex_kick;
bc72ad67 1882 timer_del(epctx->kick_timer);
3d139684
GH		 1883 xfer->running_retry = 0;
1884 }
1885}
1886
1887
62c6ae04
HM		 1888static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1889{
3d139684 1890 uint64_t mfindex;
62c6ae04
HM		 1891
1892 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
62c6ae04
HM		 1893
1894 xfer->in_xfer = epctx->type>>2;
62c6ae04 1895
62c6ae04
HM		 1896 switch(epctx->type) {
1897 case ET_INTR_OUT:
1898 case ET_INTR_IN:
4d7a81c0
GH		 1899 xfer->pkts = 0;
1900 xfer->iso_xfer = false;
1901 xfer->timed_xfer = true;
1902 mfindex = xhci_mfindex_get(xhci);
1903 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1904 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1905 if (xfer->running_retry) {
1906 return -1;
1907 }
1908 break;
62c6ae04
HM		 1909 case ET_BULK_OUT:
1910 case ET_BULK_IN:
3d139684
GH		 1911 xfer->pkts = 0;
1912 xfer->iso_xfer = false;
4d7a81c0 1913 xfer->timed_xfer = false;
62c6ae04
HM		 1914 break;
1915 case ET_ISO_OUT:
1916 case ET_ISO_IN:
3d139684
GH		 1917 xfer->pkts = 1;
1918 xfer->iso_xfer = true;
4d7a81c0 1919 xfer->timed_xfer = true;
3d139684
GH		 1920 mfindex = xhci_mfindex_get(xhci);
1921 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
4d7a81c0 1922 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
3d139684
GH		 1923 if (xfer->running_retry) {
1924 return -1;
1925 }
62c6ae04
HM		 1926 break;
1927 default:
079d0b7f
GH		 1928 fprintf(stderr, "xhci: unknown or unhandled EP "
1929 "(type %d, in %d, ep %02x)\n",
1930 epctx->type, xfer->in_xfer, xfer->epid);
62c6ae04
HM		 1931 return -1;
1932 }
1933
5c08106f
GH		 1934 if (xhci_setup_packet(xfer) < 0) {
1935 return -1;
1936 }
9a77a0f5 1937 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
62c6ae04 1938
9a77a0f5 1939 xhci_complete_packet(xfer);
7c605a23 1940 if (!xfer->running_async && !xfer->running_retry) {
024426ac 1941 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
62c6ae04
HM		 1942 }
1943 return 0;
1944}
1945
1946static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1947{
024426ac 1948 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
331e9406 1949 return xhci_submit(xhci, xfer, epctx);
62c6ae04
HM		 1950}
1951
024426ac
GH		 1952static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1953 unsigned int epid, unsigned int streamid)
62c6ae04 1954{
024426ac 1955 XHCIStreamContext *stctx;
62c6ae04 1956 XHCIEPContext *epctx;
024426ac 1957 XHCIRing *ring;
36dfe324 1958 USBEndpoint *ep = NULL;
3d139684 1959 uint64_t mfindex;
62c6ae04
HM		 1960 int length;
1961 int i;
1962
024426ac 1963 trace_usb_xhci_ep_kick(slotid, epid, streamid);
91062ae0 1964 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04 1965 assert(epid >= 1 && epid <= 31);
62c6ae04
HM		 1966
1967 if (!xhci->slots[slotid-1].enabled) {
1968 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1969 return;
1970 }
1971 epctx = xhci->slots[slotid-1].eps[epid-1];
1972 if (!epctx) {
1973 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1974 epid, slotid);
1975 return;
1976 }
1977
7c605a23 1978 if (epctx->retry) {
7c605a23 1979 XHCITransfer *xfer = epctx->retry;
7c605a23 1980
97df650b 1981 trace_usb_xhci_xfer_retry(xfer);
7c605a23 1982 assert(xfer->running_retry);
4d7a81c0
GH		 1983 if (xfer->timed_xfer) {
1984 /* time to kick the transfer? */
3d139684 1985 mfindex = xhci_mfindex_get(xhci);
4d7a81c0 1986 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
3d139684
GH		 1987 if (xfer->running_retry) {
1988 return;
1989 }
4d7a81c0
GH		 1990 xfer->timed_xfer = 0;
1991 xfer->running_retry = 1;
1992 }
1993 if (xfer->iso_xfer) {
1994 /* retry iso transfer */
3d139684
GH		 1995 if (xhci_setup_packet(xfer) < 0) {
1996 return;
1997 }
9a77a0f5
HG		 1998 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1999 assert(xfer->packet.status != USB_RET_NAK);
2000 xhci_complete_packet(xfer);
3d139684
GH		 2001 } else {
2002 /* retry nak'ed transfer */
2003 if (xhci_setup_packet(xfer) < 0) {
2004 return;
2005 }
9a77a0f5
HG		 2006 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2007 if (xfer->packet.status == USB_RET_NAK) {
3d139684
GH		 2008 return;
2009 }
9a77a0f5 2010 xhci_complete_packet(xfer);
7c605a23 2011 }
7c605a23
GH		 2012 assert(!xfer->running_retry);
2013 epctx->retry = NULL;
2014 }
2015
62c6ae04
HM		 2016 if (epctx->state == EP_HALTED) {
2017 DPRINTF("xhci: ep halted, not running schedule\n");
2018 return;
2019 }
2020
024426ac
GH		 2021
2022 if (epctx->nr_pstreams) {
2023 uint32_t err;
2024 stctx = xhci_find_stream(epctx, streamid, &err);
2025 if (stctx == NULL) {
2026 return;
2027 }
2028 ring = &stctx->ring;
2029 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2030 } else {
2031 ring = &epctx->ring;
2032 streamid = 0;
2033 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2034 }
7d04c2b7 2035 assert(ring->dequeue != 0);
62c6ae04
HM		 2036
2037 while (1) {
2038 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
331e9406 2039 if (xfer->running_async || xfer->running_retry) {
62c6ae04
HM		 2040 break;
2041 }
024426ac 2042 length = xhci_ring_chain_length(xhci, ring);
62c6ae04 2043 if (length < 0) {
62c6ae04
HM		 2044 break;
2045 } else if (length == 0) {
2046 break;
2047 }
62c6ae04
HM		 2048 if (xfer->trbs && xfer->trb_alloced < length) {
2049 xfer->trb_count = 0;
2050 xfer->trb_alloced = 0;
2051 g_free(xfer->trbs);
2052 xfer->trbs = NULL;
2053 }
2054 if (!xfer->trbs) {
2055 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
2056 xfer->trb_alloced = length;
2057 }
2058 xfer->trb_count = length;
2059
2060 for (i = 0; i < length; i++) {
024426ac 2061 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL));
62c6ae04
HM		 2062 }
2063 xfer->xhci = xhci;
2064 xfer->epid = epid;
2065 xfer->slotid = slotid;
024426ac 2066 xfer->streamid = streamid;
62c6ae04
HM		 2067
2068 if (epid == 1) {
2069 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2070 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
36dfe324 2071 ep = xfer->packet.ep;
62c6ae04
HM		 2072 } else {
2073 fprintf(stderr, "xhci: error firing CTL transfer\n");
2074 }
2075 } else {
2076 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2077 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
36dfe324 2078 ep = xfer->packet.ep;
62c6ae04 2079 } else {
4d7a81c0 2080 if (!xfer->timed_xfer) {
3d139684
GH		 2081 fprintf(stderr, "xhci: error firing data transfer\n");
2082 }
62c6ae04
HM		 2083 }
2084 }
2085
3c4866e0 2086 if (epctx->state == EP_HALTED) {
3c4866e0
GH		 2087 break;
2088 }
7c605a23
GH		 2089 if (xfer->running_retry) {
2090 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2091 epctx->retry = xfer;
2092 break;
2093 }
62c6ae04 2094 }
36dfe324
HG		 2095 if (ep) {
2096 usb_device_flush_ep_queue(ep->dev, ep);
2097 }
62c6ae04
HM		 2098}
2099
2100static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2101{
348f1037 2102 trace_usb_xhci_slot_enable(slotid);
91062ae0 2103 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04 2104 xhci->slots[slotid-1].enabled = 1;
ccaf87a0 2105 xhci->slots[slotid-1].uport = NULL;
62c6ae04
HM		 2106 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2107
2108 return CC_SUCCESS;
2109}
2110
2111static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2112{
2113 int i;
2114
348f1037 2115 trace_usb_xhci_slot_disable(slotid);
91062ae0 2116 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2117
2118 for (i = 1; i <= 31; i++) {
2119 if (xhci->slots[slotid-1].eps[i-1]) {
2120 xhci_disable_ep(xhci, slotid, i);
2121 }
2122 }
2123
2124 xhci->slots[slotid-1].enabled = 0;
4034e693 2125 xhci->slots[slotid-1].addressed = 0;
62c6ae04
HM		 2126 return CC_SUCCESS;
2127}
2128
ccaf87a0
GH		 2129static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2130{
2131 USBPort *uport;
2132 char path[32];
2133 int i, pos, port;
2134
2135 port = (slot_ctx[1]>>16) & 0xFF;
2136 port = xhci->ports[port-1].uport->index+1;
2137 pos = snprintf(path, sizeof(path), "%d", port);
2138 for (i = 0; i < 5; i++) {
2139 port = (slot_ctx[0] >> 4*i) & 0x0f;
2140 if (!port) {
2141 break;
2142 }
2143 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2144 }
2145
2146 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2147 if (strcmp(uport->path, path) == 0) {
2148 return uport;
2149 }
2150 }
2151 return NULL;
2152}
2153
62c6ae04
HM		 2154static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2155 uint64_t pictx, bool bsr)
2156{
2157 XHCISlot *slot;
ccaf87a0 2158 USBPort *uport;
62c6ae04 2159 USBDevice *dev;
59a70ccd 2160 dma_addr_t ictx, octx, dcbaap;
62c6ae04
HM		 2161 uint64_t poctx;
2162 uint32_t ictl_ctx[2];
2163 uint32_t slot_ctx[4];
2164 uint32_t ep0_ctx[5];
62c6ae04
HM		 2165 int i;
2166 TRBCCode res;
2167
91062ae0 2168 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2169
2170 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
9b7d3334 2171 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
62c6ae04 2172 ictx = xhci_mask64(pictx);
616b5d53 2173 octx = xhci_mask64(poctx);
62c6ae04 2174
59a70ccd
DG		 2175 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2176 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 2177
616b5d53 2178 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 2179
2180 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2181 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2182 ictl_ctx[0], ictl_ctx[1]);
2183 return CC_TRB_ERROR;
2184 }
2185
616b5d53
DG		 2186 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2187 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2188
2189 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2190 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2191
2192 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2193 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2194
ccaf87a0
GH		 2195 uport = xhci_lookup_uport(xhci, slot_ctx);
2196 if (uport == NULL) {
2197 fprintf(stderr, "xhci: port not found\n");
62c6ae04 2198 return CC_TRB_ERROR;
ccaf87a0 2199 }
65d81ed4 2200 trace_usb_xhci_slot_address(slotid, uport->path);
ccaf87a0
GH		 2201
2202 dev = uport->dev;
2203 if (!dev) {
2204 fprintf(stderr, "xhci: port %s not connected\n", uport->path);
62c6ae04
HM		 2205 return CC_USB_TRANSACTION_ERROR;
2206 }
2207
91062ae0 2208 for (i = 0; i < xhci->numslots; i++) {
0bc85da6
GH		 2209 if (i == slotid-1) {
2210 continue;
2211 }
ccaf87a0
GH		 2212 if (xhci->slots[i].uport == uport) {
2213 fprintf(stderr, "xhci: port %s already assigned to slot %d\n",
2214 uport->path, i+1);
62c6ae04
HM		 2215 return CC_TRB_ERROR;
2216 }
2217 }
2218
2219 slot = &xhci->slots[slotid-1];
ccaf87a0 2220 slot->uport = uport;
62c6ae04
HM		 2221 slot->ctx = octx;
2222
2223 if (bsr) {
2224 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2225 } else {
a820b575 2226 USBPacket p;
a6718874
GH		 2227 uint8_t buf[1];
2228
af203be3 2229 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
0bc85da6 2230 usb_device_reset(dev);
a6718874
GH		 2231 memset(&p, 0, sizeof(p));
2232 usb_packet_addbuf(&p, buf, sizeof(buf));
a820b575 2233 usb_packet_setup(&p, USB_TOKEN_OUT,
8550a02d 2234 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
a820b575
GH		 2235 0, false, false);
2236 usb_device_handle_control(dev, &p,
62c6ae04 2237 DeviceOutRequest | USB_REQ_SET_ADDRESS,
af203be3 2238 slotid, 0, 0, NULL);
a820b575 2239 assert(p.status != USB_RET_ASYNC);
62c6ae04
HM		 2240 }
2241
2242 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2243
2244 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2245 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2246 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2247 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2248
616b5d53
DG		 2249 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2250 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04 2251
4034e693 2252 xhci->slots[slotid-1].addressed = 1;
62c6ae04
HM		 2253 return res;
2254}
2255
2256
2257static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2258 uint64_t pictx, bool dc)
2259{
59a70ccd 2260 dma_addr_t ictx, octx;
62c6ae04
HM		 2261 uint32_t ictl_ctx[2];
2262 uint32_t slot_ctx[4];
2263 uint32_t islot_ctx[4];
2264 uint32_t ep_ctx[5];
2265 int i;
2266 TRBCCode res;
2267
348f1037 2268 trace_usb_xhci_slot_configure(slotid);
91062ae0 2269 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2270
2271 ictx = xhci_mask64(pictx);
2272 octx = xhci->slots[slotid-1].ctx;
2273
59a70ccd
DG		 2274 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2275 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 2276
2277 if (dc) {
2278 for (i = 2; i <= 31; i++) {
2279 if (xhci->slots[slotid-1].eps[i-1]) {
2280 xhci_disable_ep(xhci, slotid, i);
2281 }
2282 }
2283
616b5d53 2284 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2285 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2286 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2287 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2288 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
616b5d53 2289 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2290
2291 return CC_SUCCESS;
2292 }
2293
616b5d53 2294 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 2295
2296 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2297 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2298 ictl_ctx[0], ictl_ctx[1]);
2299 return CC_TRB_ERROR;
2300 }
2301
616b5d53
DG		 2302 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2303 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2304
2305 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2306 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
2307 return CC_CONTEXT_STATE_ERROR;
2308 }
2309
2310 for (i = 2; i <= 31; i++) {
2311 if (ictl_ctx[0] & (1<<i)) {
2312 xhci_disable_ep(xhci, slotid, i);
2313 }
2314 if (ictl_ctx[1] & (1<<i)) {
616b5d53 2315 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
62c6ae04
HM		 2316 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2317 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2318 ep_ctx[3], ep_ctx[4]);
2319 xhci_disable_ep(xhci, slotid, i);
2320 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2321 if (res != CC_SUCCESS) {
2322 return res;
2323 }
2324 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2325 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2326 ep_ctx[3], ep_ctx[4]);
616b5d53 2327 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
62c6ae04
HM		 2328 }
2329 }
2330
2331 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2332 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2333 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2334 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2335 SLOT_CONTEXT_ENTRIES_SHIFT);
2336 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2337 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2338
616b5d53 2339 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2340
2341 return CC_SUCCESS;
2342}
2343
2344
2345static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2346 uint64_t pictx)
2347{
59a70ccd 2348 dma_addr_t ictx, octx;
62c6ae04
HM		 2349 uint32_t ictl_ctx[2];
2350 uint32_t iep0_ctx[5];
2351 uint32_t ep0_ctx[5];
2352 uint32_t islot_ctx[4];
2353 uint32_t slot_ctx[4];
2354
348f1037 2355 trace_usb_xhci_slot_evaluate(slotid);
91062ae0 2356 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2357
2358 ictx = xhci_mask64(pictx);
2359 octx = xhci->slots[slotid-1].ctx;
2360
59a70ccd
DG		 2361 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2362 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 2363
616b5d53 2364 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 2365
2366 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2367 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2368 ictl_ctx[0], ictl_ctx[1]);
2369 return CC_TRB_ERROR;
2370 }
2371
2372 if (ictl_ctx[1] & 0x1) {
616b5d53 2373 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
62c6ae04
HM		 2374
2375 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2376 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2377
616b5d53 2378 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2379
2380 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2381 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2382 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2383 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2384
2385 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2386 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2387
616b5d53 2388 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2389 }
2390
2391 if (ictl_ctx[1] & 0x2) {
616b5d53 2392 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
62c6ae04
HM		 2393
2394 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2395 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2396 iep0_ctx[3], iep0_ctx[4]);
2397
616b5d53 2398 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2399
2400 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2401 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2402
2403 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2404 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2405
616b5d53 2406 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2407 }
2408
2409 return CC_SUCCESS;
2410}
2411
2412static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2413{
2414 uint32_t slot_ctx[4];
59a70ccd 2415 dma_addr_t octx;
62c6ae04
HM		 2416 int i;
2417
348f1037 2418 trace_usb_xhci_slot_reset(slotid);
91062ae0 2419 assert(slotid >= 1 && slotid <= xhci->numslots);
62c6ae04
HM		 2420
2421 octx = xhci->slots[slotid-1].ctx;
2422
59a70ccd 2423 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 2424
2425 for (i = 2; i <= 31; i++) {
2426 if (xhci->slots[slotid-1].eps[i-1]) {
2427 xhci_disable_ep(xhci, slotid, i);
2428 }
2429 }
2430
616b5d53 2431 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2432 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2433 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2434 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2435 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
616b5d53 2436 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2437
2438 return CC_SUCCESS;
2439}
2440
2441static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2442{
2443 unsigned int slotid;
2444 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
91062ae0 2445 if (slotid < 1 || slotid > xhci->numslots) {
62c6ae04
HM		 2446 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2447 event->ccode = CC_TRB_ERROR;
2448 return 0;
2449 } else if (!xhci->slots[slotid-1].enabled) {
2450 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2451 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2452 return 0;
2453 }
2454 return slotid;
2455}
2456
81251841
GH		 2457/* cleanup slot state on usb device detach */
2458static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2459{
0cb41e2c 2460 int slot, ep;
81251841
GH		 2461
2462 for (slot = 0; slot < xhci->numslots; slot++) {
2463 if (xhci->slots[slot].uport == uport) {
2464 break;
2465 }
2466 }
2467 if (slot == xhci->numslots) {
2468 return;
2469 }
2470
0cb41e2c
GH		 2471 for (ep = 0; ep < 31; ep++) {
2472 if (xhci->slots[slot].eps[ep]) {
2473 xhci_ep_nuke_xfers(xhci, slot+1, ep+1);
2474 }
2475 }
81251841
GH		 2476 xhci->slots[slot].uport = NULL;
2477}
2478
62c6ae04
HM		 2479static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2480{
59a70ccd 2481 dma_addr_t ctx;
0846e635 2482 uint8_t bw_ctx[xhci->numports+1];
62c6ae04
HM		 2483
2484 DPRINTF("xhci_get_port_bandwidth()\n");
2485
2486 ctx = xhci_mask64(pctx);
2487
59a70ccd 2488 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
62c6ae04
HM		 2489
2490 /* TODO: actually implement real values here */
2491 bw_ctx[0] = 0;
0846e635 2492 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
9b7d3334 2493 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
62c6ae04
HM		 2494
2495 return CC_SUCCESS;
2496}
2497
2498static uint32_t rotl(uint32_t v, unsigned count)
2499{
2500 count &= 31;
2501 return (v << count) | (v >> (32 - count));
2502}
2503
2504
2505static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2506{
2507 uint32_t val;
2508 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2509 val += rotl(lo + 0x49434878, hi & 0x1F);
2510 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2511 return ~val;
2512}
2513
59a70ccd 2514static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
62c6ae04 2515{
9b7d3334 2516 PCIDevice *pci_dev = PCI_DEVICE(xhci);
62c6ae04
HM		 2517 uint32_t buf[8];
2518 uint32_t obuf[8];
59a70ccd 2519 dma_addr_t paddr = xhci_mask64(addr);
62c6ae04 2520
9b7d3334 2521 pci_dma_read(pci_dev, paddr, &buf, 32);
62c6ae04
HM		 2522
2523 memcpy(obuf, buf, sizeof(obuf));
2524
2525 if ((buf[0] & 0xff) == 2) {
2526 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2527 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2528 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2529 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2530 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2531 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2532 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2533 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2534 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2535 }
2536
9b7d3334 2537 pci_dma_write(pci_dev, paddr, &obuf, 32);
62c6ae04
HM		 2538}
2539
2540static void xhci_process_commands(XHCIState *xhci)
2541{
2542 XHCITRB trb;
2543 TRBType type;
2544 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
59a70ccd 2545 dma_addr_t addr;
62c6ae04
HM		 2546 unsigned int i, slotid = 0;
2547
2548 DPRINTF("xhci_process_commands()\n");
2549 if (!xhci_running(xhci)) {
2550 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2551 return;
2552 }
2553
2554 xhci->crcr_low |= CRCR_CRR;
2555
2556 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2557 event.ptr = addr;
2558 switch (type) {
2559 case CR_ENABLE_SLOT:
91062ae0 2560 for (i = 0; i < xhci->numslots; i++) {
62c6ae04
HM		 2561 if (!xhci->slots[i].enabled) {
2562 break;
2563 }
2564 }
91062ae0 2565 if (i >= xhci->numslots) {
62c6ae04
HM		 2566 fprintf(stderr, "xhci: no device slots available\n");
2567 event.ccode = CC_NO_SLOTS_ERROR;
2568 } else {
2569 slotid = i+1;
2570 event.ccode = xhci_enable_slot(xhci, slotid);
2571 }
2572 break;
2573 case CR_DISABLE_SLOT:
2574 slotid = xhci_get_slot(xhci, &event, &trb);
2575 if (slotid) {
2576 event.ccode = xhci_disable_slot(xhci, slotid);
2577 }
2578 break;
2579 case CR_ADDRESS_DEVICE:
2580 slotid = xhci_get_slot(xhci, &event, &trb);
2581 if (slotid) {
2582 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2583 trb.control & TRB_CR_BSR);
2584 }
2585 break;
2586 case CR_CONFIGURE_ENDPOINT:
2587 slotid = xhci_get_slot(xhci, &event, &trb);
2588 if (slotid) {
2589 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2590 trb.control & TRB_CR_DC);
2591 }
2592 break;
2593 case CR_EVALUATE_CONTEXT:
2594 slotid = xhci_get_slot(xhci, &event, &trb);
2595 if (slotid) {
2596 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2597 }
2598 break;
2599 case CR_STOP_ENDPOINT:
2600 slotid = xhci_get_slot(xhci, &event, &trb);
2601 if (slotid) {
2602 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2603 & TRB_CR_EPID_MASK;
2604 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2605 }
2606 break;
2607 case CR_RESET_ENDPOINT:
2608 slotid = xhci_get_slot(xhci, &event, &trb);
2609 if (slotid) {
2610 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2611 & TRB_CR_EPID_MASK;
2612 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2613 }
2614 break;
2615 case CR_SET_TR_DEQUEUE:
2616 slotid = xhci_get_slot(xhci, &event, &trb);
2617 if (slotid) {
2618 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2619 & TRB_CR_EPID_MASK;
024426ac
GH		 2620 unsigned int streamid = (trb.status >> 16) & 0xffff;
2621 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2622 epid, streamid,
62c6ae04
HM		 2623 trb.parameter);
2624 }
2625 break;
2626 case CR_RESET_DEVICE:
2627 slotid = xhci_get_slot(xhci, &event, &trb);
2628 if (slotid) {
2629 event.ccode = xhci_reset_slot(xhci, slotid);
2630 }
2631 break;
2632 case CR_GET_PORT_BANDWIDTH:
2633 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2634 break;
2635 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
59a70ccd 2636 xhci_via_challenge(xhci, trb.parameter);
62c6ae04
HM		 2637 break;
2638 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2639 event.type = 48; /* NEC reply */
2640 event.length = 0x3025;
2641 break;
2642 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2643 {
2644 uint32_t chi = trb.parameter >> 32;
2645 uint32_t clo = trb.parameter;
2646 uint32_t val = xhci_nec_challenge(chi, clo);
2647 event.length = val & 0xFFFF;
2648 event.epid = val >> 16;
2649 slotid = val >> 24;
2650 event.type = 48; /* NEC reply */
2651 }
2652 break;
2653 default:
0ab966cf 2654 trace_usb_xhci_unimplemented("command", type);
62c6ae04
HM		 2655 event.ccode = CC_TRB_ERROR;
2656 break;
2657 }
2658 event.slotid = slotid;
2d1de850 2659 xhci_event(xhci, &event, 0);
62c6ae04
HM		 2660 }
2661}
2662
6a32f80f
GH		 2663static bool xhci_port_have_device(XHCIPort *port)
2664{
2665 if (!port->uport->dev || !port->uport->dev->attached) {
2666 return false; /* no device present */
2667 }
2668 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2669 return false; /* speed mismatch */
2670 }
2671 return true;
2672}
2673
f705a362
GH		 2674static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2675{
2676 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2677 port->portnr << 24 };
2678
2679 if ((port->portsc & bits) == bits) {
2680 return;
2681 }
bdfce20d 2682 trace_usb_xhci_port_notify(port->portnr, bits);
f705a362
GH		 2683 port->portsc |= bits;
2684 if (!xhci_running(port->xhci)) {
2685 return;
2686 }
2687 xhci_event(port->xhci, &ev, 0);
2688}
2689
f3214027 2690static void xhci_port_update(XHCIPort *port, int is_detach)
62c6ae04 2691{
b62b0828
GH		 2692 uint32_t pls = PLS_RX_DETECT;
2693
62c6ae04 2694 port->portsc = PORTSC_PP;
6a32f80f 2695 if (!is_detach && xhci_port_have_device(port)) {
62c6ae04 2696 port->portsc |= PORTSC_CCS;
0846e635 2697 switch (port->uport->dev->speed) {
62c6ae04
HM		 2698 case USB_SPEED_LOW:
2699 port->portsc |= PORTSC_SPEED_LOW;
b62b0828 2700 pls = PLS_POLLING;
62c6ae04
HM		 2701 break;
2702 case USB_SPEED_FULL:
2703 port->portsc |= PORTSC_SPEED_FULL;
b62b0828 2704 pls = PLS_POLLING;
62c6ae04
HM		 2705 break;
2706 case USB_SPEED_HIGH:
2707 port->portsc |= PORTSC_SPEED_HIGH;
b62b0828 2708 pls = PLS_POLLING;
62c6ae04 2709 break;
0846e635
GH		 2710 case USB_SPEED_SUPER:
2711 port->portsc |= PORTSC_SPEED_SUPER;
b62b0828
GH		 2712 port->portsc |= PORTSC_PED;
2713 pls = PLS_U0;
0846e635 2714 break;
62c6ae04
HM		 2715 }
2716 }
b62b0828 2717 set_field(&port->portsc, pls, PORTSC_PLS);
4f47f0f8 2718 trace_usb_xhci_port_link(port->portnr, pls);
f705a362 2719 xhci_port_notify(port, PORTSC_CSC);
62c6ae04
HM		 2720}
2721
dad5b9ea 2722static void xhci_port_reset(XHCIPort *port, bool warm_reset)
40030130 2723{
4f47f0f8
GH		 2724 trace_usb_xhci_port_reset(port->portnr);
2725
b62b0828
GH		 2726 if (!xhci_port_have_device(port)) {
2727 return;
2728 }
2729
40030130 2730 usb_device_reset(port->uport->dev);
b62b0828
GH		 2731
2732 switch (port->uport->dev->speed) {
dad5b9ea
GH		 2733 case USB_SPEED_SUPER:
2734 if (warm_reset) {
2735 port->portsc |= PORTSC_WRC;
2736 }
2737 /* fall through */
b62b0828
GH		 2738 case USB_SPEED_LOW:
2739 case USB_SPEED_FULL:
2740 case USB_SPEED_HIGH:
2741 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
4f47f0f8 2742 trace_usb_xhci_port_link(port->portnr, PLS_U0);
b62b0828
GH		 2743 port->portsc |= PORTSC_PED;
2744 break;
2745 }
2746
2747 port->portsc &= ~PORTSC_PR;
2748 xhci_port_notify(port, PORTSC_PRC);
40030130
GH		 2749}
2750
64619739 2751static void xhci_reset(DeviceState *dev)
62c6ae04 2752{
37034575 2753 XHCIState *xhci = XHCI(dev);
62c6ae04
HM		 2754 int i;
2755
2d754a10 2756 trace_usb_xhci_reset();
62c6ae04
HM		 2757 if (!(xhci->usbsts & USBSTS_HCH)) {
2758 fprintf(stderr, "xhci: reset while running!\n");
2759 }
2760
2761 xhci->usbcmd = 0;
2762 xhci->usbsts = USBSTS_HCH;
2763 xhci->dnctrl = 0;
2764 xhci->crcr_low = 0;
2765 xhci->crcr_high = 0;
2766 xhci->dcbaap_low = 0;
2767 xhci->dcbaap_high = 0;
2768 xhci->config = 0;
62c6ae04 2769
91062ae0 2770 for (i = 0; i < xhci->numslots; i++) {
62c6ae04
HM		 2771 xhci_disable_slot(xhci, i+1);
2772 }
2773
0846e635 2774 for (i = 0; i < xhci->numports; i++) {
f3214027 2775 xhci_port_update(xhci->ports + i, 0);
62c6ae04
HM		 2776 }
2777
91062ae0 2778 for (i = 0; i < xhci->numintrs; i++) {
962d11e1
GH		 2779 xhci->intr[i].iman = 0;
2780 xhci->intr[i].imod = 0;
2781 xhci->intr[i].erstsz = 0;
2782 xhci->intr[i].erstba_low = 0;
2783 xhci->intr[i].erstba_high = 0;
2784 xhci->intr[i].erdp_low = 0;
2785 xhci->intr[i].erdp_high = 0;
2786 xhci->intr[i].msix_used = 0;
62c6ae04 2787
962d11e1
GH		 2788 xhci->intr[i].er_ep_idx = 0;
2789 xhci->intr[i].er_pcs = 1;
2790 xhci->intr[i].er_full = 0;
2791 xhci->intr[i].ev_buffer_put = 0;
2792 xhci->intr[i].ev_buffer_get = 0;
2793 }
01546fa6 2794
bc72ad67 2795 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
01546fa6 2796 xhci_mfwrap_update(xhci);
62c6ae04
HM		 2797}
2798
a8170e5e 2799static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
62c6ae04 2800{
1b067564 2801 XHCIState *xhci = ptr;
2d754a10 2802 uint32_t ret;
62c6ae04
HM		 2803
2804 switch (reg) {
2805 case 0x00: /* HCIVERSION, CAPLENGTH */
2d754a10
GH		 2806 ret = 0x01000000 | LEN_CAP;
2807 break;
62c6ae04 2808 case 0x04: /* HCSPARAMS 1 */
0846e635 2809 ret = ((xhci->numports_2+xhci->numports_3)<<24)
91062ae0 2810 | (xhci->numintrs<<8) | xhci->numslots;
2d754a10 2811 break;
62c6ae04 2812 case 0x08: /* HCSPARAMS 2 */
2d754a10
GH		 2813 ret = 0x0000000f;
2814 break;
62c6ae04 2815 case 0x0c: /* HCSPARAMS 3 */
2d754a10
GH		 2816 ret = 0x00000000;
2817 break;
62c6ae04 2818 case 0x10: /* HCCPARAMS */
2d754a10 2819 if (sizeof(dma_addr_t) == 4) {
024426ac 2820 ret = 0x00087000;
2d754a10 2821 } else {
024426ac 2822 ret = 0x00087001;
2d754a10
GH		 2823 }
2824 break;
62c6ae04 2825 case 0x14: /* DBOFF */
2d754a10
GH		 2826 ret = OFF_DOORBELL;
2827 break;
62c6ae04 2828 case 0x18: /* RTSOFF */
2d754a10
GH		 2829 ret = OFF_RUNTIME;
2830 break;
62c6ae04
HM		 2831
2832 /* extended capabilities */
2833 case 0x20: /* Supported Protocol:00 */
2d754a10
GH		 2834 ret = 0x02000402; /* USB 2.0 */
2835 break;
62c6ae04 2836 case 0x24: /* Supported Protocol:04 */
0ebfb144 2837 ret = 0x20425355; /* "USB " */
2d754a10 2838 break;
62c6ae04 2839 case 0x28: /* Supported Protocol:08 */
0846e635 2840 ret = 0x00000001 | (xhci->numports_2<<8);
2d754a10 2841 break;
62c6ae04 2842 case 0x2c: /* Supported Protocol:0c */
2d754a10
GH		 2843 ret = 0x00000000; /* reserved */
2844 break;
62c6ae04 2845 case 0x30: /* Supported Protocol:00 */
2d754a10
GH		 2846 ret = 0x03000002; /* USB 3.0 */
2847 break;
62c6ae04 2848 case 0x34: /* Supported Protocol:04 */
0ebfb144 2849 ret = 0x20425355; /* "USB " */
2d754a10 2850 break;
62c6ae04 2851 case 0x38: /* Supported Protocol:08 */
0846e635 2852 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2d754a10 2853 break;
62c6ae04 2854 case 0x3c: /* Supported Protocol:0c */
2d754a10
GH		 2855 ret = 0x00000000; /* reserved */
2856 break;
62c6ae04 2857 default:
0ab966cf 2858 trace_usb_xhci_unimplemented("cap read", reg);
2d754a10 2859 ret = 0;
62c6ae04 2860 }
2d754a10
GH		 2861
2862 trace_usb_xhci_cap_read(reg, ret);
2863 return ret;
62c6ae04
HM		 2864}
2865
a8170e5e 2866static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
62c6ae04 2867{
1d8a4e69 2868 XHCIPort *port = ptr;
2d754a10
GH		 2869 uint32_t ret;
2870
1d8a4e69 2871 switch (reg) {
62c6ae04 2872 case 0x00: /* PORTSC */
1d8a4e69 2873 ret = port->portsc;
2d754a10 2874 break;
62c6ae04
HM		 2875 case 0x04: /* PORTPMSC */
2876 case 0x08: /* PORTLI */
2d754a10
GH		 2877 ret = 0;
2878 break;
62c6ae04
HM		 2879 case 0x0c: /* reserved */
2880 default:
0ab966cf 2881 trace_usb_xhci_unimplemented("port read", reg);
2d754a10 2882 ret = 0;
62c6ae04 2883 }
2d754a10 2884
1d8a4e69 2885 trace_usb_xhci_port_read(port->portnr, reg, ret);
2d754a10 2886 return ret;
62c6ae04
HM		 2887}
2888
a8170e5e 2889static void xhci_port_write(void *ptr, hwaddr reg,
1d8a4e69 2890 uint64_t val, unsigned size)
62c6ae04 2891{
1d8a4e69 2892 XHCIPort *port = ptr;
bdfce20d 2893 uint32_t portsc, notify;
62c6ae04 2894
1d8a4e69 2895 trace_usb_xhci_port_write(port->portnr, reg, val);
2d754a10 2896
1d8a4e69 2897 switch (reg) {
62c6ae04 2898 case 0x00: /* PORTSC */
bdfce20d 2899 /* write-1-to-start bits */
dad5b9ea
GH		 2900 if (val & PORTSC_WPR) {
2901 xhci_port_reset(port, true);
2902 break;
2903 }
bdfce20d 2904 if (val & PORTSC_PR) {
dad5b9ea 2905 xhci_port_reset(port, false);
bdfce20d
GH		 2906 break;
2907 }
2908
1d8a4e69 2909 portsc = port->portsc;
bdfce20d 2910 notify = 0;
62c6ae04
HM		 2911 /* write-1-to-clear bits*/
2912 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2913 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2914 if (val & PORTSC_LWS) {
2915 /* overwrite PLS only when LWS=1 */
bdfce20d
GH		 2916 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2917 uint32_t new_pls = get_field(val, PORTSC_PLS);
2918 switch (new_pls) {
2919 case PLS_U0:
2920 if (old_pls != PLS_U0) {
2921 set_field(&portsc, new_pls, PORTSC_PLS);
2922 trace_usb_xhci_port_link(port->portnr, new_pls);
2923 notify = PORTSC_PLC;
2924 }
2925 break;
2926 case PLS_U3:
2927 if (old_pls < PLS_U3) {
2928 set_field(&portsc, new_pls, PORTSC_PLS);
2929 trace_usb_xhci_port_link(port->portnr, new_pls);
2930 }
2931 break;
2932 case PLS_RESUME:
2933 /* windows does this for some reason, don't spam stderr */
2934 break;
2935 default:
2936 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n",
2937 __func__, old_pls, new_pls);
2938 break;
2939 }
62c6ae04
HM		 2940 }
2941 /* read/write bits */
2942 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2943 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
40030130 2944 port->portsc = portsc;
bdfce20d
GH		 2945 if (notify) {
2946 xhci_port_notify(port, notify);
62c6ae04 2947 }
62c6ae04
HM		 2948 break;
2949 case 0x04: /* PORTPMSC */
2950 case 0x08: /* PORTLI */
2951 default:
0ab966cf 2952 trace_usb_xhci_unimplemented("port write", reg);
62c6ae04
HM		 2953 }
2954}
2955
a8170e5e 2956static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
62c6ae04 2957{
1b067564 2958 XHCIState *xhci = ptr;
2d754a10 2959 uint32_t ret;
62c6ae04 2960
62c6ae04
HM		 2961 switch (reg) {
2962 case 0x00: /* USBCMD */
2d754a10
GH		 2963 ret = xhci->usbcmd;
2964 break;
62c6ae04 2965 case 0x04: /* USBSTS */
2d754a10
GH		 2966 ret = xhci->usbsts;
2967 break;
62c6ae04 2968 case 0x08: /* PAGESIZE */
2d754a10
GH		 2969 ret = 1; /* 4KiB */
2970 break;
62c6ae04 2971 case 0x14: /* DNCTRL */
2d754a10
GH		 2972 ret = xhci->dnctrl;
2973 break;
62c6ae04 2974 case 0x18: /* CRCR low */
2d754a10
GH		 2975 ret = xhci->crcr_low & ~0xe;
2976 break;
62c6ae04 2977 case 0x1c: /* CRCR high */
2d754a10
GH		 2978 ret = xhci->crcr_high;
2979 break;
62c6ae04 2980 case 0x30: /* DCBAAP low */
2d754a10
GH		 2981 ret = xhci->dcbaap_low;
2982 break;
62c6ae04 2983 case 0x34: /* DCBAAP high */
2d754a10
GH		 2984 ret = xhci->dcbaap_high;
2985 break;
62c6ae04 2986 case 0x38: /* CONFIG */
2d754a10
GH		 2987 ret = xhci->config;
2988 break;
62c6ae04 2989 default:
0ab966cf 2990 trace_usb_xhci_unimplemented("oper read", reg);
2d754a10 2991 ret = 0;
62c6ae04 2992 }
2d754a10
GH		 2993
2994 trace_usb_xhci_oper_read(reg, ret);
2995 return ret;
62c6ae04
HM		 2996}
2997
a8170e5e 2998static void xhci_oper_write(void *ptr, hwaddr reg,
1b067564 2999 uint64_t val, unsigned size)
62c6ae04 3000{
1b067564 3001 XHCIState *xhci = ptr;
37034575 3002 DeviceState *d = DEVICE(ptr);
1b067564 3003
2d754a10
GH		 3004 trace_usb_xhci_oper_write(reg, val);
3005
62c6ae04
HM		 3006 switch (reg) {
3007 case 0x00: /* USBCMD */
3008 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3009 xhci_run(xhci);
3010 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3011 xhci_stop(xhci);
3012 }
3013 xhci->usbcmd = val & 0xc0f;
01546fa6 3014 xhci_mfwrap_update(xhci);
62c6ae04 3015 if (val & USBCMD_HCRST) {
37034575 3016 xhci_reset(d);
62c6ae04 3017 }
4c4abe7c 3018 xhci_intx_update(xhci);
62c6ae04
HM		 3019 break;
3020
3021 case 0x04: /* USBSTS */
3022 /* these bits are write-1-to-clear */
3023 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
4c4abe7c 3024 xhci_intx_update(xhci);
62c6ae04
HM		 3025 break;
3026
3027 case 0x14: /* DNCTRL */
3028 xhci->dnctrl = val & 0xffff;
3029 break;
3030 case 0x18: /* CRCR low */
3031 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3032 break;
3033 case 0x1c: /* CRCR high */
3034 xhci->crcr_high = val;
3035 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3036 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3037 xhci->crcr_low &= ~CRCR_CRR;
2d1de850 3038 xhci_event(xhci, &event, 0);
62c6ae04
HM		 3039 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3040 } else {
59a70ccd 3041 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
62c6ae04
HM		 3042 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3043 }
3044 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3045 break;
3046 case 0x30: /* DCBAAP low */
3047 xhci->dcbaap_low = val & 0xffffffc0;
3048 break;
3049 case 0x34: /* DCBAAP high */
3050 xhci->dcbaap_high = val;
3051 break;
3052 case 0x38: /* CONFIG */
3053 xhci->config = val & 0xff;
3054 break;
3055 default:
0ab966cf 3056 trace_usb_xhci_unimplemented("oper write", reg);
62c6ae04
HM		 3057 }
3058}
3059
a8170e5e 3060static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
1b067564 3061 unsigned size)
62c6ae04 3062{
1b067564 3063 XHCIState *xhci = ptr;
43d9d604 3064 uint32_t ret = 0;
62c6ae04 3065
43d9d604
GH		 3066 if (reg < 0x20) {
3067 switch (reg) {
3068 case 0x00: /* MFINDEX */
3069 ret = xhci_mfindex_get(xhci) & 0x3fff;
3070 break;
3071 default:
0ab966cf 3072 trace_usb_xhci_unimplemented("runtime read", reg);
43d9d604
GH		 3073 break;
3074 }
3075 } else {
3076 int v = (reg - 0x20) / 0x20;
3077 XHCIInterrupter *intr = &xhci->intr[v];
3078 switch (reg & 0x1f) {
3079 case 0x00: /* IMAN */
3080 ret = intr->iman;
3081 break;
3082 case 0x04: /* IMOD */
3083 ret = intr->imod;
3084 break;
3085 case 0x08: /* ERSTSZ */
3086 ret = intr->erstsz;
3087 break;
3088 case 0x10: /* ERSTBA low */
3089 ret = intr->erstba_low;
3090 break;
3091 case 0x14: /* ERSTBA high */
3092 ret = intr->erstba_high;
3093 break;
3094 case 0x18: /* ERDP low */
3095 ret = intr->erdp_low;
3096 break;
3097 case 0x1c: /* ERDP high */
3098 ret = intr->erdp_high;
3099 break;
3100 }
62c6ae04 3101 }
2d754a10
GH		 3102
3103 trace_usb_xhci_runtime_read(reg, ret);
3104 return ret;
62c6ae04
HM		 3105}
3106
a8170e5e 3107static void xhci_runtime_write(void *ptr, hwaddr reg,
1b067564 3108 uint64_t val, unsigned size)
62c6ae04 3109{
1b067564 3110 XHCIState *xhci = ptr;
43d9d604
GH		 3111 int v = (reg - 0x20) / 0x20;
3112 XHCIInterrupter *intr = &xhci->intr[v];
8e9f18b6 3113 trace_usb_xhci_runtime_write(reg, val);
62c6ae04 3114
43d9d604 3115 if (reg < 0x20) {
0ab966cf 3116 trace_usb_xhci_unimplemented("runtime write", reg);
43d9d604
GH		 3117 return;
3118 }
3119
3120 switch (reg & 0x1f) {
3121 case 0x00: /* IMAN */
62c6ae04 3122 if (val & IMAN_IP) {
962d11e1 3123 intr->iman &= ~IMAN_IP;
62c6ae04 3124 }
962d11e1
GH		 3125 intr->iman &= ~IMAN_IE;
3126 intr->iman |= val & IMAN_IE;
43d9d604
GH		 3127 if (v == 0) {
3128 xhci_intx_update(xhci);
3129 }
3130 xhci_msix_update(xhci, v);
62c6ae04 3131 break;
43d9d604 3132 case 0x04: /* IMOD */
962d11e1 3133 intr->imod = val;
62c6ae04 3134 break;
43d9d604 3135 case 0x08: /* ERSTSZ */
962d11e1 3136 intr->erstsz = val & 0xffff;
62c6ae04 3137 break;
43d9d604 3138 case 0x10: /* ERSTBA low */
62c6ae04 3139 /* XXX NEC driver bug: it doesn't align this to 64 bytes
962d11e1
GH		 3140 intr->erstba_low = val & 0xffffffc0; */
3141 intr->erstba_low = val & 0xfffffff0;
62c6ae04 3142 break;
43d9d604 3143 case 0x14: /* ERSTBA high */
962d11e1 3144 intr->erstba_high = val;
43d9d604 3145 xhci_er_reset(xhci, v);
62c6ae04 3146 break;
43d9d604 3147 case 0x18: /* ERDP low */
62c6ae04 3148 if (val & ERDP_EHB) {
962d11e1 3149 intr->erdp_low &= ~ERDP_EHB;
62c6ae04 3150 }
962d11e1 3151 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
62c6ae04 3152 break;
43d9d604 3153 case 0x1c: /* ERDP high */
962d11e1 3154 intr->erdp_high = val;
43d9d604 3155 xhci_events_update(xhci, v);
62c6ae04
HM		 3156 break;
3157 default:
0ab966cf 3158 trace_usb_xhci_unimplemented("oper write", reg);
62c6ae04
HM		 3159 }
3160}
3161
a8170e5e 3162static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
1b067564 3163 unsigned size)
62c6ae04 3164{
62c6ae04 3165 /* doorbells always read as 0 */
2d754a10 3166 trace_usb_xhci_doorbell_read(reg, 0);
62c6ae04
HM		 3167 return 0;
3168}
3169
a8170e5e 3170static void xhci_doorbell_write(void *ptr, hwaddr reg,
1b067564 3171 uint64_t val, unsigned size)
62c6ae04 3172{
1b067564 3173 XHCIState *xhci = ptr;
024426ac 3174 unsigned int epid, streamid;
1b067564 3175
2d754a10 3176 trace_usb_xhci_doorbell_write(reg, val);
62c6ae04
HM		 3177
3178 if (!xhci_running(xhci)) {
3179 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
3180 return;
3181 }
3182
3183 reg >>= 2;
3184
3185 if (reg == 0) {
3186 if (val == 0) {
3187 xhci_process_commands(xhci);
3188 } else {
1b067564
GH		 3189 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n",
3190 (uint32_t)val);
62c6ae04
HM		 3191 }
3192 } else {
024426ac
GH		 3193 epid = val & 0xff;
3194 streamid = (val >> 16) & 0xffff;
91062ae0 3195 if (reg > xhci->numslots) {
1b067564 3196 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg);
024426ac 3197 } else if (epid > 31) {
1b067564
GH		 3198 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n",
3199 (int)reg, (uint32_t)val);
62c6ae04 3200 } else {
024426ac 3201 xhci_kick_ep(xhci, reg, epid, streamid);
62c6ae04
HM		 3202 }
3203 }
3204}
3205
6d3bc22e
GH		 3206static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3207 unsigned width)
3208{
3209 /* nothing */
3210}
3211
1b067564
GH		 3212static const MemoryRegionOps xhci_cap_ops = {
3213 .read = xhci_cap_read,
6d3bc22e 3214 .write = xhci_cap_write,
6ee021d4 3215 .valid.min_access_size = 1,
1b067564 3216 .valid.max_access_size = 4,
6ee021d4
GH		 3217 .impl.min_access_size = 4,
3218 .impl.max_access_size = 4,
1b067564
GH		 3219 .endianness = DEVICE_LITTLE_ENDIAN,
3220};
62c6ae04 3221
1b067564
GH		 3222static const MemoryRegionOps xhci_oper_ops = {
3223 .read = xhci_oper_read,
3224 .write = xhci_oper_write,
3225 .valid.min_access_size = 4,
3226 .valid.max_access_size = 4,
3227 .endianness = DEVICE_LITTLE_ENDIAN,
3228};
62c6ae04 3229
1d8a4e69
GH		 3230static const MemoryRegionOps xhci_port_ops = {
3231 .read = xhci_port_read,
3232 .write = xhci_port_write,
3233 .valid.min_access_size = 4,
3234 .valid.max_access_size = 4,
3235 .endianness = DEVICE_LITTLE_ENDIAN,
3236};
3237
1b067564
GH		 3238static const MemoryRegionOps xhci_runtime_ops = {
3239 .read = xhci_runtime_read,
3240 .write = xhci_runtime_write,
3241 .valid.min_access_size = 4,
3242 .valid.max_access_size = 4,
3243 .endianness = DEVICE_LITTLE_ENDIAN,
3244};
62c6ae04 3245
1b067564
GH		 3246static const MemoryRegionOps xhci_doorbell_ops = {
3247 .read = xhci_doorbell_read,
3248 .write = xhci_doorbell_write,
62c6ae04
HM		 3249 .valid.min_access_size = 4,
3250 .valid.max_access_size = 4,
3251 .endianness = DEVICE_LITTLE_ENDIAN,
3252};
3253
3254static void xhci_attach(USBPort *usbport)
3255{
3256 XHCIState *xhci = usbport->opaque;
0846e635 3257 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04 3258
f3214027 3259 xhci_port_update(port, 0);
62c6ae04
HM		 3260}
3261
3262static void xhci_detach(USBPort *usbport)
3263{
3264 XHCIState *xhci = usbport->opaque;
0846e635 3265 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04 3266
f3dcf638 3267 xhci_detach_slot(xhci, usbport);
f3214027 3268 xhci_port_update(port, 1);
62c6ae04
HM		 3269}
3270
8c735e43
GH		 3271static void xhci_wakeup(USBPort *usbport)
3272{
3273 XHCIState *xhci = usbport->opaque;
0846e635 3274 XHCIPort *port = xhci_lookup_port(xhci, usbport);
8c735e43 3275
85e05d82 3276 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
8c735e43
GH		 3277 return;
3278 }
85e05d82 3279 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
f705a362 3280 xhci_port_notify(port, PORTSC_PLC);
8c735e43
GH		 3281}
3282
62c6ae04
HM		 3283static void xhci_complete(USBPort *port, USBPacket *packet)
3284{
3285 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3286
9a77a0f5 3287 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
0cae7b1a
HG		 3288 xhci_ep_nuke_one_xfer(xfer);
3289 return;
3290 }
9a77a0f5 3291 xhci_complete_packet(xfer);
024426ac 3292 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
62c6ae04
HM		 3293}
3294
ccaf87a0 3295static void xhci_child_detach(USBPort *uport, USBDevice *child)
62c6ae04 3296{
ccaf87a0
GH		 3297 USBBus *bus = usb_bus_from_device(child);
3298 XHCIState *xhci = container_of(bus, XHCIState, bus);
ccaf87a0 3299
81251841 3300 xhci_detach_slot(xhci, uport);
62c6ae04
HM		 3301}
3302
1d8a4e69 3303static USBPortOps xhci_uport_ops = {
62c6ae04
HM		 3304 .attach = xhci_attach,
3305 .detach = xhci_detach,
8c735e43 3306 .wakeup = xhci_wakeup,
62c6ae04
HM		 3307 .complete = xhci_complete,
3308 .child_detach = xhci_child_detach,
3309};
3310
7c605a23
GH		 3311static int xhci_find_epid(USBEndpoint *ep)
3312{
3313 if (ep->nr == 0) {
3314 return 1;
3315 }
3316 if (ep->pid == USB_TOKEN_IN) {
3317 return ep->nr * 2 + 1;
3318 } else {
3319 return ep->nr * 2;
3320 }
3321}
3322
8550a02d
GH		 3323static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3324 unsigned int stream)
7c605a23
GH		 3325{
3326 XHCIState *xhci = container_of(bus, XHCIState, bus);
3327 int slotid;
3328
3329 DPRINTF("%s\n", __func__);
af203be3 3330 slotid = ep->dev->addr;
7c605a23
GH		 3331 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3332 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3333 return;
3334 }
024426ac 3335 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
7c605a23
GH		 3336}
3337
62c6ae04 3338static USBBusOps xhci_bus_ops = {
7c605a23 3339 .wakeup_endpoint = xhci_wakeup_endpoint,
62c6ae04
HM		 3340};
3341
37034575 3342static void usb_xhci_init(XHCIState *xhci)
62c6ae04 3343{
37034575 3344 DeviceState *dev = DEVICE(xhci);
0846e635
GH		 3345 XHCIPort *port;
3346 int i, usbports, speedmask;
62c6ae04
HM		 3347
3348 xhci->usbsts = USBSTS_HCH;
3349
0846e635
GH		 3350 if (xhci->numports_2 > MAXPORTS_2) {
3351 xhci->numports_2 = MAXPORTS_2;
3352 }
3353 if (xhci->numports_3 > MAXPORTS_3) {
3354 xhci->numports_3 = MAXPORTS_3;
3355 }
3356 usbports = MAX(xhci->numports_2, xhci->numports_3);
3357 xhci->numports = xhci->numports_2 + xhci->numports_3;
3358
37034575 3359 usb_bus_new(&xhci->bus, &xhci_bus_ops, dev);
62c6ae04 3360
0846e635
GH		 3361 for (i = 0; i < usbports; i++) {
3362 speedmask = 0;
3363 if (i < xhci->numports_2) {
3364 port = &xhci->ports[i];
3365 port->portnr = i + 1;
3366 port->uport = &xhci->uports[i];
3367 port->speedmask =
3368 USB_SPEED_MASK_LOW |
3369 USB_SPEED_MASK_FULL |
3370 USB_SPEED_MASK_HIGH;
1d8a4e69 3371 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
0846e635
GH		 3372 speedmask |= port->speedmask;
3373 }
3374 if (i < xhci->numports_3) {
3375 port = &xhci->ports[i + xhci->numports_2];
3376 port->portnr = i + 1 + xhci->numports_2;
3377 port->uport = &xhci->uports[i];
3378 port->speedmask = USB_SPEED_MASK_SUPER;
1d8a4e69 3379 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
0846e635
GH		 3380 speedmask |= port->speedmask;
3381 }
3382 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
1d8a4e69 3383 &xhci_uport_ops, speedmask);
62c6ae04 3384 }
62c6ae04
HM		 3385}
3386
3387static int usb_xhci_initfn(struct PCIDevice *dev)
3388{
1d8a4e69 3389 int i, ret;
62c6ae04 3390
37034575 3391 XHCIState *xhci = XHCI(dev);
62c6ae04 3392
9b7d3334
AF		 3393 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3394 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3395 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3396 dev->config[0x60] = 0x30; /* release number */
62c6ae04 3397
37034575 3398 usb_xhci_init(xhci);
62c6ae04 3399
91062ae0
GH		 3400 if (xhci->numintrs > MAXINTRS) {
3401 xhci->numintrs = MAXINTRS;
3402 }
c94a7c69
GH		 3403 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3404 xhci->numintrs++;
3405 }
91062ae0
GH		 3406 if (xhci->numintrs < 1) {
3407 xhci->numintrs = 1;
3408 }
3409 if (xhci->numslots > MAXSLOTS) {
3410 xhci->numslots = MAXSLOTS;
3411 }
3412 if (xhci->numslots < 1) {
3413 xhci->numslots = 1;
3414 }
3415
bc72ad67 3416 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
01546fa6 3417
9b7d3334 3418 xhci->irq = dev->irq[0];
62c6ae04 3419
22fc860b
PB		 3420 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3421 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
1b067564 3422 "capabilities", LEN_CAP);
22fc860b 3423 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
1d8a4e69 3424 "operational", 0x400);
22fc860b 3425 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
1b067564 3426 "runtime", LEN_RUNTIME);
22fc860b 3427 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
1b067564
GH		 3428 "doorbell", LEN_DOORBELL);
3429
3430 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3431 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3432 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3433 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3434
1d8a4e69
GH		 3435 for (i = 0; i < xhci->numports; i++) {
3436 XHCIPort *port = &xhci->ports[i];
3437 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3438 port->xhci = xhci;
22fc860b 3439 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
1d8a4e69
GH		 3440 port->name, 0x10);
3441 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3442 }
3443
9b7d3334 3444 pci_register_bar(dev, 0,
62c6ae04
HM		 3445 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3446 &xhci->mem);
3447
9b7d3334 3448 ret = pcie_endpoint_cap_init(dev, 0xa0);
62c6ae04
HM		 3449 assert(ret >= 0);
3450
c5e9b02d 3451 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
9b7d3334 3452 msi_init(dev, 0x70, xhci->numintrs, true, false);
62c6ae04 3453 }
4c47f800 3454 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
9b7d3334 3455 msix_init(dev, xhci->numintrs,
4c47f800
GH		 3456 &xhci->mem, 0, OFF_MSIX_TABLE,
3457 &xhci->mem, 0, OFF_MSIX_PBA,
3458 0x90);
3459 }
62c6ae04
HM		 3460
3461 return 0;
3462}
3463
37352df3
GH		 3464static int usb_xhci_post_load(void *opaque, int version_id)
3465{
3466 XHCIState *xhci = opaque;
9b7d3334 3467 PCIDevice *pci_dev = PCI_DEVICE(xhci);
37352df3
GH		 3468 XHCISlot *slot;
3469 XHCIEPContext *epctx;
3470 dma_addr_t dcbaap, pctx;
3471 uint32_t slot_ctx[4];
3472 uint32_t ep_ctx[5];
3473 int slotid, epid, state, intr;
3474
3475 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3476
3477 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3478 slot = &xhci->slots[slotid-1];
3479 if (!slot->addressed) {
3480 continue;
3481 }
3482 slot->ctx =
9b7d3334 3483 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
37352df3
GH		 3484 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3485 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3486 assert(slot->uport && slot->uport->dev);
3487
3488 for (epid = 1; epid <= 32; epid++) {
3489 pctx = slot->ctx + 32 * epid;
3490 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3491 state = ep_ctx[0] & EP_STATE_MASK;
3492 if (state == EP_DISABLED) {
3493 continue;
3494 }
3495 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3496 slot->eps[epid-1] = epctx;
3497 xhci_init_epctx(epctx, pctx, ep_ctx);
3498 epctx->state = state;
3499 if (state == EP_RUNNING) {
3500 /* kick endpoint after vmload is finished */
bc72ad67 3501 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
37352df3
GH		 3502 }
3503 }
3504 }
3505
3506 for (intr = 0; intr < xhci->numintrs; intr++) {
3507 if (xhci->intr[intr].msix_used) {
9b7d3334 3508 msix_vector_use(pci_dev, intr);
37352df3 3509 } else {
9b7d3334 3510 msix_vector_unuse(pci_dev, intr);
37352df3
GH		 3511 }
3512 }
3513
3514 return 0;
3515}
3516
3517static const VMStateDescription vmstate_xhci_ring = {
3518 .name = "xhci-ring",
3519 .version_id = 1,
3520 .fields = (VMStateField[]) {
3521 VMSTATE_UINT64(dequeue, XHCIRing),
3522 VMSTATE_BOOL(ccs, XHCIRing),
3523 VMSTATE_END_OF_LIST()
3524 }
3525};
3526
3527static const VMStateDescription vmstate_xhci_port = {
3528 .name = "xhci-port",
3529 .version_id = 1,
3530 .fields = (VMStateField[]) {
3531 VMSTATE_UINT32(portsc, XHCIPort),
3532 VMSTATE_END_OF_LIST()
3533 }
3534};
3535
3536static const VMStateDescription vmstate_xhci_slot = {
3537 .name = "xhci-slot",
3538 .version_id = 1,
3539 .fields = (VMStateField[]) {
3540 VMSTATE_BOOL(enabled, XHCISlot),
3541 VMSTATE_BOOL(addressed, XHCISlot),
3542 VMSTATE_END_OF_LIST()
3543 }
3544};
3545
3546static const VMStateDescription vmstate_xhci_event = {
3547 .name = "xhci-event",
3548 .version_id = 1,
3549 .fields = (VMStateField[]) {
3550 VMSTATE_UINT32(type, XHCIEvent),
3551 VMSTATE_UINT32(ccode, XHCIEvent),
3552 VMSTATE_UINT64(ptr, XHCIEvent),
3553 VMSTATE_UINT32(length, XHCIEvent),
3554 VMSTATE_UINT32(flags, XHCIEvent),
3555 VMSTATE_UINT8(slotid, XHCIEvent),
3556 VMSTATE_UINT8(epid, XHCIEvent),
3557 }
3558};
3559
3560static bool xhci_er_full(void *opaque, int version_id)
3561{
3562 struct XHCIInterrupter *intr = opaque;
3563 return intr->er_full;
3564}
3565
3566static const VMStateDescription vmstate_xhci_intr = {
3567 .name = "xhci-intr",
3568 .version_id = 1,
3569 .fields = (VMStateField[]) {
3570 /* registers */
3571 VMSTATE_UINT32(iman, XHCIInterrupter),
3572 VMSTATE_UINT32(imod, XHCIInterrupter),
3573 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3574 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3575 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3576 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3577 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3578
3579 /* state */
3580 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3581 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3582 VMSTATE_UINT64(er_start, XHCIInterrupter),
3583 VMSTATE_UINT32(er_size, XHCIInterrupter),
3584 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3585
3586 /* event queue (used if ring is full) */
3587 VMSTATE_BOOL(er_full, XHCIInterrupter),
3588 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3589 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3590 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3591 xhci_er_full, 1,
3592 vmstate_xhci_event, XHCIEvent),
3593
3594 VMSTATE_END_OF_LIST()
3595 }
3596};
3597
62c6ae04
HM		 3598static const VMStateDescription vmstate_xhci = {
3599 .name = "xhci",
37352df3
GH		 3600 .version_id = 1,
3601 .post_load = usb_xhci_post_load,
3602 .fields = (VMStateField[]) {
9b7d3334
AF		 3603 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
3604 VMSTATE_MSIX(parent_obj, XHCIState),
37352df3
GH		 3605
3606 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3607 vmstate_xhci_port, XHCIPort),
3608 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3609 vmstate_xhci_slot, XHCISlot),
3610 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3611 vmstate_xhci_intr, XHCIInterrupter),
3612
3613 /* Operational Registers */
3614 VMSTATE_UINT32(usbcmd, XHCIState),
3615 VMSTATE_UINT32(usbsts, XHCIState),
3616 VMSTATE_UINT32(dnctrl, XHCIState),
3617 VMSTATE_UINT32(crcr_low, XHCIState),
3618 VMSTATE_UINT32(crcr_high, XHCIState),
3619 VMSTATE_UINT32(dcbaap_low, XHCIState),
3620 VMSTATE_UINT32(dcbaap_high, XHCIState),
3621 VMSTATE_UINT32(config, XHCIState),
3622
3623 /* Runtime Registers & state */
3624 VMSTATE_INT64(mfindex_start, XHCIState),
3625 VMSTATE_TIMER(mfwrap_timer, XHCIState),
3626 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3627
3628 VMSTATE_END_OF_LIST()
3629 }
62c6ae04
HM		 3630};
3631
39bffca2 3632static Property xhci_properties[] = {
91062ae0
GH		 3633 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
3634 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
3635 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3636 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3637 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3638 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
39bffca2
AL		 3639 DEFINE_PROP_END_OF_LIST(),
3640};
3641
40021f08
AL		 3642static void xhci_class_init(ObjectClass *klass, void *data)
3643{
3644 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2 3645 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 3646
39bffca2
AL		 3647 dc->vmsd = &vmstate_xhci;
3648 dc->props = xhci_properties;
64619739 3649 dc->reset = xhci_reset;
125ee0ed 3650 set_bit(DEVICE_CATEGORY_USB, dc->categories);
40021f08
AL		 3651 k->init = usb_xhci_initfn;
3652 k->vendor_id = PCI_VENDOR_ID_NEC;
3653 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3654 k->class_id = PCI_CLASS_SERIAL_USB;
3655 k->revision = 0x03;
3656 k->is_express = 1;
6c2d1c32 3657 k->no_hotplug = 1;
40021f08
AL		 3658}
3659
8c43a6f0 3660static const TypeInfo xhci_info = {
37034575 3661 .name = TYPE_XHCI,
39bffca2
AL		 3662 .parent = TYPE_PCI_DEVICE,
3663 .instance_size = sizeof(XHCIState),
3664 .class_init = xhci_class_init,
62c6ae04
HM		 3665};
3666
83f7d43a 3667static void xhci_register_types(void)
62c6ae04 3668{
39bffca2 3669 type_register_static(&xhci_info);
62c6ae04 3670}
83f7d43a
AF		 3671
3672type_init(xhci_register_types)
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