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xhci: add XHCIInterrupter
[mirror_qemu.git] / hw / usb / hcd-xhci.c
CommitLineData
62c6ae04
HM		 1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
f1ae32a1 21#include "hw/hw.h"
62c6ae04 22#include "qemu-timer.h"
f1ae32a1
GH		 23#include "hw/usb.h"
24#include "hw/pci.h"
f1ae32a1 25#include "hw/msi.h"
4c47f800 26#include "hw/msix.h"
2d754a10 27#include "trace.h"
62c6ae04
HM		 28
29//#define DEBUG_XHCI
30//#define DEBUG_DATA
31
32#ifdef DEBUG_XHCI
33#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34#else
35#define DPRINTF(...) do {} while (0)
36#endif
37#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
38 __func__, __LINE__); abort(); } while (0)
39
0846e635
GH		 40#define MAXPORTS_2 8
41#define MAXPORTS_3 8
62c6ae04 42
0846e635 43#define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
106b214c
GH		 44#define MAXSLOTS MAXPORTS
45#define MAXINTRS 1 /* MAXPORTS */
62c6ae04
HM		 46
47#define TD_QUEUE 24
62c6ae04
HM		 48
49/* Very pessimistic, let's hope it's enough for all cases */
50#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51/* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53#define ER_FULL_HACK
54
55#define LEN_CAP 0x40
62c6ae04 56#define LEN_OPER (0x400 + 0x10 * MAXPORTS)
106b214c 57#define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
62c6ae04
HM		 58#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
106b214c
GH		 60#define OFF_OPER LEN_CAP
61#define OFF_RUNTIME 0x1000
62#define OFF_DOORBELL 0x2000
4c47f800
GH		 63#define OFF_MSIX_TABLE 0x3000
64#define OFF_MSIX_PBA 0x3800
62c6ae04 65/* must be power of 2 */
106b214c 66#define LEN_REGS 0x4000
62c6ae04 67
106b214c
GH		 68#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69#error Increase OFF_RUNTIME
70#endif
71#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72#error Increase OFF_DOORBELL
73#endif
62c6ae04
HM		 74#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75# error Increase LEN_REGS
76#endif
77
78#if MAXINTRS > 1
79# error TODO: only one interrupter supported
80#endif
81
82/* bit definitions */
83#define USBCMD_RS (1<<0)
84#define USBCMD_HCRST (1<<1)
85#define USBCMD_INTE (1<<2)
86#define USBCMD_HSEE (1<<3)
87#define USBCMD_LHCRST (1<<7)
88#define USBCMD_CSS (1<<8)
89#define USBCMD_CRS (1<<9)
90#define USBCMD_EWE (1<<10)
91#define USBCMD_EU3S (1<<11)
92
93#define USBSTS_HCH (1<<0)
94#define USBSTS_HSE (1<<2)
95#define USBSTS_EINT (1<<3)
96#define USBSTS_PCD (1<<4)
97#define USBSTS_SSS (1<<8)
98#define USBSTS_RSS (1<<9)
99#define USBSTS_SRE (1<<10)
100#define USBSTS_CNR (1<<11)
101#define USBSTS_HCE (1<<12)
102
103
104#define PORTSC_CCS (1<<0)
105#define PORTSC_PED (1<<1)
106#define PORTSC_OCA (1<<3)
107#define PORTSC_PR (1<<4)
108#define PORTSC_PLS_SHIFT 5
109#define PORTSC_PLS_MASK 0xf
110#define PORTSC_PP (1<<9)
111#define PORTSC_SPEED_SHIFT 10
112#define PORTSC_SPEED_MASK 0xf
113#define PORTSC_SPEED_FULL (1<<10)
114#define PORTSC_SPEED_LOW (2<<10)
115#define PORTSC_SPEED_HIGH (3<<10)
116#define PORTSC_SPEED_SUPER (4<<10)
117#define PORTSC_PIC_SHIFT 14
118#define PORTSC_PIC_MASK 0x3
119#define PORTSC_LWS (1<<16)
120#define PORTSC_CSC (1<<17)
121#define PORTSC_PEC (1<<18)
122#define PORTSC_WRC (1<<19)
123#define PORTSC_OCC (1<<20)
124#define PORTSC_PRC (1<<21)
125#define PORTSC_PLC (1<<22)
126#define PORTSC_CEC (1<<23)
127#define PORTSC_CAS (1<<24)
128#define PORTSC_WCE (1<<25)
129#define PORTSC_WDE (1<<26)
130#define PORTSC_WOE (1<<27)
131#define PORTSC_DR (1<<30)
132#define PORTSC_WPR (1<<31)
133
134#define CRCR_RCS (1<<0)
135#define CRCR_CS (1<<1)
136#define CRCR_CA (1<<2)
137#define CRCR_CRR (1<<3)
138
139#define IMAN_IP (1<<0)
140#define IMAN_IE (1<<1)
141
142#define ERDP_EHB (1<<3)
143
144#define TRB_SIZE 16
145typedef struct XHCITRB {
146 uint64_t parameter;
147 uint32_t status;
148 uint32_t control;
59a70ccd 149 dma_addr_t addr;
62c6ae04
HM		 150 bool ccs;
151} XHCITRB;
152
153
154typedef enum TRBType {
155 TRB_RESERVED = 0,
156 TR_NORMAL,
157 TR_SETUP,
158 TR_DATA,
159 TR_STATUS,
160 TR_ISOCH,
161 TR_LINK,
162 TR_EVDATA,
163 TR_NOOP,
164 CR_ENABLE_SLOT,
165 CR_DISABLE_SLOT,
166 CR_ADDRESS_DEVICE,
167 CR_CONFIGURE_ENDPOINT,
168 CR_EVALUATE_CONTEXT,
169 CR_RESET_ENDPOINT,
170 CR_STOP_ENDPOINT,
171 CR_SET_TR_DEQUEUE,
172 CR_RESET_DEVICE,
173 CR_FORCE_EVENT,
174 CR_NEGOTIATE_BW,
175 CR_SET_LATENCY_TOLERANCE,
176 CR_GET_PORT_BANDWIDTH,
177 CR_FORCE_HEADER,
178 CR_NOOP,
179 ER_TRANSFER = 32,
180 ER_COMMAND_COMPLETE,
181 ER_PORT_STATUS_CHANGE,
182 ER_BANDWIDTH_REQUEST,
183 ER_DOORBELL,
184 ER_HOST_CONTROLLER,
185 ER_DEVICE_NOTIFICATION,
186 ER_MFINDEX_WRAP,
187 /* vendor specific bits */
188 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
189 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
190 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
191} TRBType;
192
193#define CR_LINK TR_LINK
194
195typedef enum TRBCCode {
196 CC_INVALID = 0,
197 CC_SUCCESS,
198 CC_DATA_BUFFER_ERROR,
199 CC_BABBLE_DETECTED,
200 CC_USB_TRANSACTION_ERROR,
201 CC_TRB_ERROR,
202 CC_STALL_ERROR,
203 CC_RESOURCE_ERROR,
204 CC_BANDWIDTH_ERROR,
205 CC_NO_SLOTS_ERROR,
206 CC_INVALID_STREAM_TYPE_ERROR,
207 CC_SLOT_NOT_ENABLED_ERROR,
208 CC_EP_NOT_ENABLED_ERROR,
209 CC_SHORT_PACKET,
210 CC_RING_UNDERRUN,
211 CC_RING_OVERRUN,
212 CC_VF_ER_FULL,
213 CC_PARAMETER_ERROR,
214 CC_BANDWIDTH_OVERRUN,
215 CC_CONTEXT_STATE_ERROR,
216 CC_NO_PING_RESPONSE_ERROR,
217 CC_EVENT_RING_FULL_ERROR,
218 CC_INCOMPATIBLE_DEVICE_ERROR,
219 CC_MISSED_SERVICE_ERROR,
220 CC_COMMAND_RING_STOPPED,
221 CC_COMMAND_ABORTED,
222 CC_STOPPED,
223 CC_STOPPED_LENGTH_INVALID,
224 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
225 CC_ISOCH_BUFFER_OVERRUN = 31,
226 CC_EVENT_LOST_ERROR,
227 CC_UNDEFINED_ERROR,
228 CC_INVALID_STREAM_ID_ERROR,
229 CC_SECONDARY_BANDWIDTH_ERROR,
230 CC_SPLIT_TRANSACTION_ERROR
231} TRBCCode;
232
233#define TRB_C (1<<0)
234#define TRB_TYPE_SHIFT 10
235#define TRB_TYPE_MASK 0x3f
236#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
237
238#define TRB_EV_ED (1<<2)
239
240#define TRB_TR_ENT (1<<1)
241#define TRB_TR_ISP (1<<2)
242#define TRB_TR_NS (1<<3)
243#define TRB_TR_CH (1<<4)
244#define TRB_TR_IOC (1<<5)
245#define TRB_TR_IDT (1<<6)
246#define TRB_TR_TBC_SHIFT 7
247#define TRB_TR_TBC_MASK 0x3
248#define TRB_TR_BEI (1<<9)
249#define TRB_TR_TLBPC_SHIFT 16
250#define TRB_TR_TLBPC_MASK 0xf
251#define TRB_TR_FRAMEID_SHIFT 20
252#define TRB_TR_FRAMEID_MASK 0x7ff
253#define TRB_TR_SIA (1<<31)
254
255#define TRB_TR_DIR (1<<16)
256
257#define TRB_CR_SLOTID_SHIFT 24
258#define TRB_CR_SLOTID_MASK 0xff
259#define TRB_CR_EPID_SHIFT 16
260#define TRB_CR_EPID_MASK 0x1f
261
262#define TRB_CR_BSR (1<<9)
263#define TRB_CR_DC (1<<9)
264
265#define TRB_LK_TC (1<<1)
266
267#define EP_TYPE_MASK 0x7
268#define EP_TYPE_SHIFT 3
269
270#define EP_STATE_MASK 0x7
271#define EP_DISABLED (0<<0)
272#define EP_RUNNING (1<<0)
273#define EP_HALTED (2<<0)
274#define EP_STOPPED (3<<0)
275#define EP_ERROR (4<<0)
276
277#define SLOT_STATE_MASK 0x1f
278#define SLOT_STATE_SHIFT 27
279#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
280#define SLOT_ENABLED 0
281#define SLOT_DEFAULT 1
282#define SLOT_ADDRESSED 2
283#define SLOT_CONFIGURED 3
284
285#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
286#define SLOT_CONTEXT_ENTRIES_SHIFT 27
287
288typedef enum EPType {
289 ET_INVALID = 0,
290 ET_ISO_OUT,
291 ET_BULK_OUT,
292 ET_INTR_OUT,
293 ET_CONTROL,
294 ET_ISO_IN,
295 ET_BULK_IN,
296 ET_INTR_IN,
297} EPType;
298
299typedef struct XHCIRing {
59a70ccd
DG		 300 dma_addr_t base;
301 dma_addr_t dequeue;
62c6ae04
HM		 302 bool ccs;
303} XHCIRing;
304
305typedef struct XHCIPort {
62c6ae04 306 uint32_t portsc;
0846e635
GH		 307 uint32_t portnr;
308 USBPort *uport;
309 uint32_t speedmask;
62c6ae04
HM		 310} XHCIPort;
311
312struct XHCIState;
313typedef struct XHCIState XHCIState;
314
315typedef struct XHCITransfer {
316 XHCIState *xhci;
317 USBPacket packet;
d5a15814 318 QEMUSGList sgl;
7c605a23
GH		 319 bool running_async;
320 bool running_retry;
62c6ae04
HM		 321 bool cancelled;
322 bool complete;
62c6ae04
HM		 323 unsigned int iso_pkts;
324 unsigned int slotid;
325 unsigned int epid;
326 bool in_xfer;
327 bool iso_xfer;
62c6ae04
HM		 328
329 unsigned int trb_count;
330 unsigned int trb_alloced;
331 XHCITRB *trbs;
332
62c6ae04
HM		 333 TRBCCode status;
334
335 unsigned int pkts;
336 unsigned int pktsize;
337 unsigned int cur_pkt;
3d139684
GH		 338
339 uint64_t mfindex_kick;
62c6ae04
HM		 340} XHCITransfer;
341
342typedef struct XHCIEPContext {
3d139684
GH		 343 XHCIState *xhci;
344 unsigned int slotid;
345 unsigned int epid;
346
62c6ae04
HM		 347 XHCIRing ring;
348 unsigned int next_xfer;
349 unsigned int comp_xfer;
350 XHCITransfer transfers[TD_QUEUE];
7c605a23 351 XHCITransfer *retry;
62c6ae04 352 EPType type;
59a70ccd 353 dma_addr_t pctx;
62c6ae04 354 unsigned int max_psize;
62c6ae04 355 uint32_t state;
3d139684
GH		 356
357 /* iso xfer scheduling */
358 unsigned int interval;
359 int64_t mfindex_last;
360 QEMUTimer *kick_timer;
62c6ae04
HM		 361} XHCIEPContext;
362
363typedef struct XHCISlot {
364 bool enabled;
59a70ccd 365 dma_addr_t ctx;
62c6ae04
HM		 366 unsigned int port;
367 unsigned int devaddr;
368 XHCIEPContext * eps[31];
369} XHCISlot;
370
371typedef struct XHCIEvent {
372 TRBType type;
373 TRBCCode ccode;
374 uint64_t ptr;
375 uint32_t length;
376 uint32_t flags;
377 uint8_t slotid;
378 uint8_t epid;
379} XHCIEvent;
380
962d11e1
GH		 381typedef struct XHCIInterrupter {
382 uint32_t iman;
383 uint32_t imod;
384 uint32_t erstsz;
385 uint32_t erstba_low;
386 uint32_t erstba_high;
387 uint32_t erdp_low;
388 uint32_t erdp_high;
389
390 bool msix_used, er_pcs, er_full;
391
392 dma_addr_t er_start;
393 uint32_t er_size;
394 unsigned int er_ep_idx;
395
396 XHCIEvent ev_buffer[EV_QUEUE];
397 unsigned int ev_buffer_put;
398 unsigned int ev_buffer_get;
399
400} XHCIInterrupter;
401
62c6ae04
HM		 402struct XHCIState {
403 PCIDevice pci_dev;
404 USBBus bus;
405 qemu_irq irq;
406 MemoryRegion mem;
407 const char *name;
62c6ae04
HM		 408 unsigned int devaddr;
409
0846e635
GH		 410 /* properties */
411 uint32_t numports_2;
412 uint32_t numports_3;
c5e9b02d 413 uint32_t flags;
0846e635 414
62c6ae04
HM		 415 /* Operational Registers */
416 uint32_t usbcmd;
417 uint32_t usbsts;
418 uint32_t dnctrl;
419 uint32_t crcr_low;
420 uint32_t crcr_high;
421 uint32_t dcbaap_low;
422 uint32_t dcbaap_high;
423 uint32_t config;
424
0846e635 425 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
62c6ae04
HM		 426 XHCIPort ports[MAXPORTS];
427 XHCISlot slots[MAXSLOTS];
0846e635 428 uint32_t numports;
62c6ae04
HM		 429
430 /* Runtime Registers */
01546fa6
GH		 431 int64_t mfindex_start;
432 QEMUTimer *mfwrap_timer;
962d11e1 433 XHCIInterrupter intr[MAXINTRS];
62c6ae04
HM		 434
435 XHCIRing cmd_ring;
436};
437
438typedef struct XHCIEvRingSeg {
439 uint32_t addr_low;
440 uint32_t addr_high;
441 uint32_t size;
442 uint32_t rsvd;
443} XHCIEvRingSeg;
444
c5e9b02d
GH		 445enum xhci_flags {
446 XHCI_FLAG_USE_MSI = 1,
4c47f800 447 XHCI_FLAG_USE_MSI_X,
c5e9b02d
GH		 448};
449
01546fa6
GH		 450static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
451 unsigned int epid);
962d11e1
GH		 452static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
453static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
01546fa6 454
f10de44e
GH		 455static const char *TRBType_names[] = {
456 [TRB_RESERVED] = "TRB_RESERVED",
457 [TR_NORMAL] = "TR_NORMAL",
458 [TR_SETUP] = "TR_SETUP",
459 [TR_DATA] = "TR_DATA",
460 [TR_STATUS] = "TR_STATUS",
461 [TR_ISOCH] = "TR_ISOCH",
462 [TR_LINK] = "TR_LINK",
463 [TR_EVDATA] = "TR_EVDATA",
464 [TR_NOOP] = "TR_NOOP",
465 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
466 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
467 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
468 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
469 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
470 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
471 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
472 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
473 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
474 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
475 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
476 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
477 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
478 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
479 [CR_NOOP] = "CR_NOOP",
480 [ER_TRANSFER] = "ER_TRANSFER",
481 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
482 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
483 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
484 [ER_DOORBELL] = "ER_DOORBELL",
485 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
486 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
487 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
488 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
489 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
490 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
491};
492
873123fe
GH		 493static const char *TRBCCode_names[] = {
494 [CC_INVALID] = "CC_INVALID",
495 [CC_SUCCESS] = "CC_SUCCESS",
496 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
497 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
498 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
499 [CC_TRB_ERROR] = "CC_TRB_ERROR",
500 [CC_STALL_ERROR] = "CC_STALL_ERROR",
501 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
502 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
503 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
504 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
505 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
506 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
507 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
508 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
509 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
510 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
511 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
512 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
513 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
514 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
515 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
516 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
517 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
518 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
519 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
520 [CC_STOPPED] = "CC_STOPPED",
521 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
522 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
523 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
524 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
525 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
526 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
527 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
528 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
529 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
530};
531
f10de44e
GH		 532static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
533{
534 if (index >= llen || list[index] == NULL) {
535 return "???";
536 }
537 return list[index];
538}
539
540static const char *trb_name(XHCITRB *trb)
541{
542 return lookup_name(TRB_TYPE(*trb), TRBType_names,
543 ARRAY_SIZE(TRBType_names));
544}
f10de44e 545
873123fe
GH		 546static const char *event_name(XHCIEvent *event)
547{
548 return lookup_name(event->ccode, TRBCCode_names,
549 ARRAY_SIZE(TRBCCode_names));
550}
551
01546fa6
GH		 552static uint64_t xhci_mfindex_get(XHCIState *xhci)
553{
554 int64_t now = qemu_get_clock_ns(vm_clock);
555 return (now - xhci->mfindex_start) / 125000;
556}
557
558static void xhci_mfwrap_update(XHCIState *xhci)
559{
560 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
561 uint32_t mfindex, left;
562 int64_t now;
563
564 if ((xhci->usbcmd & bits) == bits) {
565 now = qemu_get_clock_ns(vm_clock);
566 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
567 left = 0x4000 - mfindex;
568 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
569 } else {
570 qemu_del_timer(xhci->mfwrap_timer);
571 }
572}
573
574static void xhci_mfwrap_timer(void *opaque)
575{
576 XHCIState *xhci = opaque;
577 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
578
962d11e1 579 xhci_event(xhci, &wrap, 0);
01546fa6
GH		 580 xhci_mfwrap_update(xhci);
581}
62c6ae04 582
59a70ccd 583static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
62c6ae04 584{
59a70ccd
DG		 585 if (sizeof(dma_addr_t) == 4) {
586 return low;
587 } else {
588 return low | (((dma_addr_t)high << 16) << 16);
589 }
62c6ae04
HM		 590}
591
59a70ccd 592static inline dma_addr_t xhci_mask64(uint64_t addr)
62c6ae04 593{
59a70ccd
DG		 594 if (sizeof(dma_addr_t) == 4) {
595 return addr & 0xffffffff;
596 } else {
597 return addr;
598 }
62c6ae04
HM		 599}
600
0846e635
GH		 601static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
602{
603 int index;
604
605 if (!uport->dev) {
606 return NULL;
607 }
608 switch (uport->dev->speed) {
609 case USB_SPEED_LOW:
610 case USB_SPEED_FULL:
611 case USB_SPEED_HIGH:
612 index = uport->index;
613 break;
614 case USB_SPEED_SUPER:
615 index = uport->index + xhci->numports_2;
616 break;
617 default:
618 return NULL;
619 }
620 return &xhci->ports[index];
621}
622
4c4abe7c 623static void xhci_intx_update(XHCIState *xhci)
62c6ae04
HM		 624{
625 int level = 0;
626
4c47f800
GH		 627 if (msix_enabled(&xhci->pci_dev) ||
628 msi_enabled(&xhci->pci_dev)) {
4c4abe7c
GH		 629 return;
630 }
631
962d11e1
GH		 632 if (xhci->intr[0].iman & IMAN_IP &&
633 xhci->intr[0].iman & IMAN_IE &&
215bff17 634 xhci->usbcmd & USBCMD_INTE) {
62c6ae04
HM		 635 level = 1;
636 }
637
4c4abe7c
GH		 638 trace_usb_xhci_irq_intx(level);
639 qemu_set_irq(xhci->irq, level);
640}
641
962d11e1 642static void xhci_msix_update(XHCIState *xhci, int v)
4c47f800
GH		 643{
644 bool enabled;
645
646 if (!msix_enabled(&xhci->pci_dev)) {
647 return;
648 }
649
962d11e1
GH		 650 enabled = xhci->intr[v].iman & IMAN_IE;
651 if (enabled == xhci->intr[v].msix_used) {
4c47f800
GH		 652 return;
653 }
654
655 if (enabled) {
962d11e1
GH		 656 trace_usb_xhci_irq_msix_use(v);
657 msix_vector_use(&xhci->pci_dev, v);
658 xhci->intr[v].msix_used = true;
4c47f800 659 } else {
962d11e1
GH		 660 trace_usb_xhci_irq_msix_unuse(v);
661 msix_vector_unuse(&xhci->pci_dev, v);
662 xhci->intr[v].msix_used = false;
4c47f800
GH		 663 }
664}
665
962d11e1 666static void xhci_intr_raise(XHCIState *xhci, int v)
4c4abe7c 667{
962d11e1
GH		 668 xhci->intr[v].erdp_low |= ERDP_EHB;
669 xhci->intr[v].iman |= IMAN_IP;
2cae4119
GH		 670 xhci->usbsts |= USBSTS_EINT;
671
962d11e1 672 if (!(xhci->intr[v].iman & IMAN_IE)) {
4c4abe7c
GH		 673 return;
674 }
675
676 if (!(xhci->usbcmd & USBCMD_INTE)) {
677 return;
678 }
679
4c47f800 680 if (msix_enabled(&xhci->pci_dev)) {
962d11e1
GH		 681 trace_usb_xhci_irq_msix(v);
682 msix_notify(&xhci->pci_dev, v);
4c47f800
GH		 683 return;
684 }
685
c5e9b02d 686 if (msi_enabled(&xhci->pci_dev)) {
962d11e1
GH		 687 trace_usb_xhci_irq_msi(v);
688 msi_notify(&xhci->pci_dev, v);
4c4abe7c 689 return;
62c6ae04 690 }
4c4abe7c 691
962d11e1
GH		 692 if (v == 0) {
693 trace_usb_xhci_irq_intx(1);
694 qemu_set_irq(xhci->irq, 1);
695 }
62c6ae04
HM		 696}
697
698static inline int xhci_running(XHCIState *xhci)
699{
962d11e1 700 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
62c6ae04
HM		 701}
702
703static void xhci_die(XHCIState *xhci)
704{
705 xhci->usbsts |= USBSTS_HCE;
706 fprintf(stderr, "xhci: asserted controller error\n");
707}
708
962d11e1 709static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
62c6ae04 710{
962d11e1 711 XHCIInterrupter *intr = &xhci->intr[v];
62c6ae04 712 XHCITRB ev_trb;
59a70ccd 713 dma_addr_t addr;
62c6ae04
HM		 714
715 ev_trb.parameter = cpu_to_le64(event->ptr);
716 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
717 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
718 event->flags | (event->type << TRB_TYPE_SHIFT);
962d11e1 719 if (intr->er_pcs) {
62c6ae04
HM		 720 ev_trb.control |= TRB_C;
721 }
722 ev_trb.control = cpu_to_le32(ev_trb.control);
723
962d11e1 724 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
873123fe
GH		 725 event_name(event), ev_trb.parameter,
726 ev_trb.status, ev_trb.control);
62c6ae04 727
962d11e1 728 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
59a70ccd 729 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
62c6ae04 730
962d11e1
GH		 731 intr->er_ep_idx++;
732 if (intr->er_ep_idx >= intr->er_size) {
733 intr->er_ep_idx = 0;
734 intr->er_pcs = !intr->er_pcs;
62c6ae04
HM		 735 }
736}
737
962d11e1 738static void xhci_events_update(XHCIState *xhci, int v)
62c6ae04 739{
962d11e1 740 XHCIInterrupter *intr = &xhci->intr[v];
59a70ccd 741 dma_addr_t erdp;
62c6ae04
HM		 742 unsigned int dp_idx;
743 bool do_irq = 0;
744
745 if (xhci->usbsts & USBSTS_HCH) {
746 return;
747 }
748
962d11e1
GH		 749 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
750 if (erdp < intr->er_start ||
751 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
59a70ccd 752 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
962d11e1
GH		 753 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
754 v, intr->er_start, intr->er_size);
62c6ae04
HM		 755 xhci_die(xhci);
756 return;
757 }
962d11e1
GH		 758 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
759 assert(dp_idx < intr->er_size);
62c6ae04
HM		 760
761 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
762 * deadlocks when the ER is full. Hack it by holding off events until
763 * the driver decides to free at least half of the ring */
962d11e1
GH		 764 if (intr->er_full) {
765 int er_free = dp_idx - intr->er_ep_idx;
62c6ae04 766 if (er_free <= 0) {
962d11e1 767 er_free += intr->er_size;
62c6ae04 768 }
962d11e1 769 if (er_free < (intr->er_size/2)) {
62c6ae04
HM		 770 DPRINTF("xhci_events_update(): event ring still "
771 "more than half full (hack)\n");
772 return;
773 }
774 }
775
962d11e1
GH		 776 while (intr->ev_buffer_put != intr->ev_buffer_get) {
777 assert(intr->er_full);
778 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
62c6ae04
HM		 779 DPRINTF("xhci_events_update(): event ring full again\n");
780#ifndef ER_FULL_HACK
781 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
962d11e1 782 xhci_write_event(xhci, &full, v);
62c6ae04
HM		 783#endif
784 do_irq = 1;
785 break;
786 }
962d11e1
GH		 787 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
788 xhci_write_event(xhci, event, v);
789 intr->ev_buffer_get++;
62c6ae04 790 do_irq = 1;
962d11e1
GH		 791 if (intr->ev_buffer_get == EV_QUEUE) {
792 intr->ev_buffer_get = 0;
62c6ae04
HM		 793 }
794 }
795
796 if (do_irq) {
962d11e1 797 xhci_intr_raise(xhci, v);
62c6ae04
HM		 798 }
799
962d11e1 800 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
62c6ae04 801 DPRINTF("xhci_events_update(): event ring no longer full\n");
962d11e1 802 intr->er_full = 0;
62c6ae04
HM		 803 }
804 return;
805}
806
962d11e1 807static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
62c6ae04 808{
962d11e1 809 XHCIInterrupter *intr = &xhci->intr[v];
59a70ccd 810 dma_addr_t erdp;
62c6ae04
HM		 811 unsigned int dp_idx;
812
962d11e1 813 if (intr->er_full) {
62c6ae04 814 DPRINTF("xhci_event(): ER full, queueing\n");
962d11e1 815 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
62c6ae04
HM		 816 fprintf(stderr, "xhci: event queue full, dropping event!\n");
817 return;
818 }
962d11e1
GH		 819 intr->ev_buffer[intr->ev_buffer_put++] = *event;
820 if (intr->ev_buffer_put == EV_QUEUE) {
821 intr->ev_buffer_put = 0;
62c6ae04
HM		 822 }
823 return;
824 }
825
962d11e1
GH		 826 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
827 if (erdp < intr->er_start ||
828 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
59a70ccd 829 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
962d11e1
GH		 830 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
831 v, intr->er_start, intr->er_size);
62c6ae04
HM		 832 xhci_die(xhci);
833 return;
834 }
835
962d11e1
GH		 836 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
837 assert(dp_idx < intr->er_size);
62c6ae04 838
962d11e1 839 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
62c6ae04
HM		 840 DPRINTF("xhci_event(): ER full, queueing\n");
841#ifndef ER_FULL_HACK
842 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
843 xhci_write_event(xhci, &full);
844#endif
962d11e1
GH		 845 intr->er_full = 1;
846 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
62c6ae04
HM		 847 fprintf(stderr, "xhci: event queue full, dropping event!\n");
848 return;
849 }
962d11e1
GH		 850 intr->ev_buffer[intr->ev_buffer_put++] = *event;
851 if (intr->ev_buffer_put == EV_QUEUE) {
852 intr->ev_buffer_put = 0;
62c6ae04
HM		 853 }
854 } else {
962d11e1 855 xhci_write_event(xhci, event, v);
62c6ae04
HM		 856 }
857
962d11e1 858 xhci_intr_raise(xhci, v);
62c6ae04
HM		 859}
860
861static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
59a70ccd 862 dma_addr_t base)
62c6ae04
HM		 863{
864 ring->base = base;
865 ring->dequeue = base;
866 ring->ccs = 1;
867}
868
869static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
59a70ccd 870 dma_addr_t *addr)
62c6ae04
HM		 871{
872 while (1) {
873 TRBType type;
59a70ccd 874 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
62c6ae04
HM		 875 trb->addr = ring->dequeue;
876 trb->ccs = ring->ccs;
877 le64_to_cpus(&trb->parameter);
878 le32_to_cpus(&trb->status);
879 le32_to_cpus(&trb->control);
880
0703a4a7
GH		 881 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
882 trb->parameter, trb->status, trb->control);
62c6ae04
HM		 883
884 if ((trb->control & TRB_C) != ring->ccs) {
885 return 0;
886 }
887
888 type = TRB_TYPE(*trb);
889
890 if (type != TR_LINK) {
891 if (addr) {
892 *addr = ring->dequeue;
893 }
894 ring->dequeue += TRB_SIZE;
895 return type;
896 } else {
897 ring->dequeue = xhci_mask64(trb->parameter);
898 if (trb->control & TRB_LK_TC) {
899 ring->ccs = !ring->ccs;
900 }
901 }
902 }
903}
904
905static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
906{
907 XHCITRB trb;
908 int length = 0;
59a70ccd 909 dma_addr_t dequeue = ring->dequeue;
62c6ae04
HM		 910 bool ccs = ring->ccs;
911 /* hack to bundle together the two/three TDs that make a setup transfer */
912 bool control_td_set = 0;
913
914 while (1) {
915 TRBType type;
59a70ccd 916 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
62c6ae04
HM		 917 le64_to_cpus(&trb.parameter);
918 le32_to_cpus(&trb.status);
919 le32_to_cpus(&trb.control);
920
62c6ae04
HM		 921 if ((trb.control & TRB_C) != ccs) {
922 return -length;
923 }
924
925 type = TRB_TYPE(trb);
926
927 if (type == TR_LINK) {
928 dequeue = xhci_mask64(trb.parameter);
929 if (trb.control & TRB_LK_TC) {
930 ccs = !ccs;
931 }
932 continue;
933 }
934
935 length += 1;
936 dequeue += TRB_SIZE;
937
938 if (type == TR_SETUP) {
939 control_td_set = 1;
940 } else if (type == TR_STATUS) {
941 control_td_set = 0;
942 }
943
944 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
945 return length;
946 }
947 }
948}
949
962d11e1 950static void xhci_er_reset(XHCIState *xhci, int v)
62c6ae04 951{
962d11e1 952 XHCIInterrupter *intr = &xhci->intr[v];
62c6ae04
HM		 953 XHCIEvRingSeg seg;
954
955 /* cache the (sole) event ring segment location */
962d11e1
GH		 956 if (intr->erstsz != 1) {
957 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
62c6ae04
HM		 958 xhci_die(xhci);
959 return;
960 }
962d11e1 961 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
59a70ccd 962 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
62c6ae04
HM		 963 le32_to_cpus(&seg.addr_low);
964 le32_to_cpus(&seg.addr_high);
965 le32_to_cpus(&seg.size);
966 if (seg.size < 16 || seg.size > 4096) {
967 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
968 xhci_die(xhci);
969 return;
970 }
962d11e1
GH		 971 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
972 intr->er_size = seg.size;
62c6ae04 973
962d11e1
GH		 974 intr->er_ep_idx = 0;
975 intr->er_pcs = 1;
976 intr->er_full = 0;
62c6ae04 977
962d11e1
GH		 978 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
979 v, intr->er_start, intr->er_size);
62c6ae04
HM		 980}
981
982static void xhci_run(XHCIState *xhci)
983{
fc0ddaca 984 trace_usb_xhci_run();
62c6ae04 985 xhci->usbsts &= ~USBSTS_HCH;
01546fa6 986 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
62c6ae04
HM		 987}
988
989static void xhci_stop(XHCIState *xhci)
990{
fc0ddaca 991 trace_usb_xhci_stop();
62c6ae04
HM		 992 xhci->usbsts |= USBSTS_HCH;
993 xhci->crcr_low &= ~CRCR_CRR;
994}
995
996static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
997 uint32_t state)
998{
999 uint32_t ctx[5];
1000 if (epctx->state == state) {
1001 return;
1002 }
1003
59a70ccd 1004 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
62c6ae04
HM		 1005 ctx[0] &= ~EP_STATE_MASK;
1006 ctx[0] |= state;
1007 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
1008 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
59a70ccd 1009 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
62c6ae04 1010 epctx->pctx, state, ctx[3], ctx[2]);
59a70ccd 1011 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
62c6ae04
HM		 1012 epctx->state = state;
1013}
1014
3d139684
GH		 1015static void xhci_ep_kick_timer(void *opaque)
1016{
1017 XHCIEPContext *epctx = opaque;
1018 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid);
1019}
1020
62c6ae04 1021static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
59a70ccd 1022 unsigned int epid, dma_addr_t pctx,
62c6ae04
HM		 1023 uint32_t *ctx)
1024{
1025 XHCISlot *slot;
1026 XHCIEPContext *epctx;
59a70ccd 1027 dma_addr_t dequeue;
62c6ae04
HM		 1028 int i;
1029
c1f6b493 1030 trace_usb_xhci_ep_enable(slotid, epid);
62c6ae04
HM		 1031 assert(slotid >= 1 && slotid <= MAXSLOTS);
1032 assert(epid >= 1 && epid <= 31);
1033
62c6ae04
HM		 1034 slot = &xhci->slots[slotid-1];
1035 if (slot->eps[epid-1]) {
1036 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
1037 return CC_TRB_ERROR;
1038 }
1039
1040 epctx = g_malloc(sizeof(XHCIEPContext));
1041 memset(epctx, 0, sizeof(XHCIEPContext));
3d139684
GH		 1042 epctx->xhci = xhci;
1043 epctx->slotid = slotid;
1044 epctx->epid = epid;
62c6ae04
HM		 1045
1046 slot->eps[epid-1] = epctx;
1047
1048 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1049 xhci_ring_init(xhci, &epctx->ring, dequeue);
1050 epctx->ring.ccs = ctx[2] & 1;
1051
1052 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1053 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
1054 epctx->pctx = pctx;
1055 epctx->max_psize = ctx[1]>>16;
1056 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
62c6ae04
HM		 1057 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1058 epid/2, epid%2, epctx->max_psize);
1059 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1060 usb_packet_init(&epctx->transfers[i].packet);
1061 }
1062
3d139684
GH		 1063 epctx->interval = 1 << (ctx[0] >> 16) & 0xff;
1064 epctx->mfindex_last = 0;
1065 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx);
1066
62c6ae04
HM		 1067 epctx->state = EP_RUNNING;
1068 ctx[0] &= ~EP_STATE_MASK;
1069 ctx[0] |= EP_RUNNING;
1070
1071 return CC_SUCCESS;
1072}
1073
1074static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1075 unsigned int epid)
1076{
1077 XHCISlot *slot;
1078 XHCIEPContext *epctx;
1079 int i, xferi, killed = 0;
1080 assert(slotid >= 1 && slotid <= MAXSLOTS);
1081 assert(epid >= 1 && epid <= 31);
1082
1083 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1084
1085 slot = &xhci->slots[slotid-1];
1086
1087 if (!slot->eps[epid-1]) {
1088 return 0;
1089 }
1090
1091 epctx = slot->eps[epid-1];
1092
1093 xferi = epctx->next_xfer;
1094 for (i = 0; i < TD_QUEUE; i++) {
1095 XHCITransfer *t = &epctx->transfers[xferi];
7c605a23
GH		 1096 if (t->running_async) {
1097 usb_cancel_packet(&t->packet);
1098 t->running_async = 0;
62c6ae04 1099 t->cancelled = 1;
62c6ae04
HM		 1100 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
1101 killed++;
1102 }
7c605a23
GH		 1103 if (t->running_retry) {
1104 t->running_retry = 0;
1105 epctx->retry = NULL;
3d139684 1106 qemu_del_timer(epctx->kick_timer);
7c605a23 1107 }
62c6ae04
HM		 1108 if (t->trbs) {
1109 g_free(t->trbs);
1110 }
62c6ae04
HM		 1111
1112 t->trbs = NULL;
62c6ae04 1113 t->trb_count = t->trb_alloced = 0;
62c6ae04
HM		 1114 xferi = (xferi + 1) % TD_QUEUE;
1115 }
62c6ae04
HM		 1116 return killed;
1117}
1118
1119static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1120 unsigned int epid)
1121{
1122 XHCISlot *slot;
1123 XHCIEPContext *epctx;
1124
c1f6b493 1125 trace_usb_xhci_ep_disable(slotid, epid);
62c6ae04
HM		 1126 assert(slotid >= 1 && slotid <= MAXSLOTS);
1127 assert(epid >= 1 && epid <= 31);
1128
62c6ae04
HM		 1129 slot = &xhci->slots[slotid-1];
1130
1131 if (!slot->eps[epid-1]) {
1132 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1133 return CC_SUCCESS;
1134 }
1135
1136 xhci_ep_nuke_xfers(xhci, slotid, epid);
1137
1138 epctx = slot->eps[epid-1];
1139
1140 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
1141
3d139684 1142 qemu_free_timer(epctx->kick_timer);
62c6ae04
HM		 1143 g_free(epctx);
1144 slot->eps[epid-1] = NULL;
1145
1146 return CC_SUCCESS;
1147}
1148
1149static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1150 unsigned int epid)
1151{
1152 XHCISlot *slot;
1153 XHCIEPContext *epctx;
1154
c1f6b493 1155 trace_usb_xhci_ep_stop(slotid, epid);
62c6ae04
HM		 1156 assert(slotid >= 1 && slotid <= MAXSLOTS);
1157
1158 if (epid < 1 || epid > 31) {
1159 fprintf(stderr, "xhci: bad ep %d\n", epid);
1160 return CC_TRB_ERROR;
1161 }
1162
1163 slot = &xhci->slots[slotid-1];
1164
1165 if (!slot->eps[epid-1]) {
1166 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1167 return CC_EP_NOT_ENABLED_ERROR;
1168 }
1169
1170 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1171 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1172 "data might be lost\n");
1173 }
1174
1175 epctx = slot->eps[epid-1];
1176
1177 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1178
1179 return CC_SUCCESS;
1180}
1181
1182static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1183 unsigned int epid)
1184{
1185 XHCISlot *slot;
1186 XHCIEPContext *epctx;
1187 USBDevice *dev;
1188
c1f6b493 1189 trace_usb_xhci_ep_reset(slotid, epid);
62c6ae04
HM		 1190 assert(slotid >= 1 && slotid <= MAXSLOTS);
1191
62c6ae04
HM		 1192 if (epid < 1 || epid > 31) {
1193 fprintf(stderr, "xhci: bad ep %d\n", epid);
1194 return CC_TRB_ERROR;
1195 }
1196
1197 slot = &xhci->slots[slotid-1];
1198
1199 if (!slot->eps[epid-1]) {
1200 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1201 return CC_EP_NOT_ENABLED_ERROR;
1202 }
1203
1204 epctx = slot->eps[epid-1];
1205
1206 if (epctx->state != EP_HALTED) {
1207 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1208 epid, epctx->state);
1209 return CC_CONTEXT_STATE_ERROR;
1210 }
1211
1212 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1213 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1214 "data might be lost\n");
1215 }
1216
1217 uint8_t ep = epid>>1;
1218
1219 if (epid & 1) {
1220 ep |= 0x80;
1221 }
1222
0846e635 1223 dev = xhci->ports[xhci->slots[slotid-1].port-1].uport->dev;
62c6ae04
HM		 1224 if (!dev) {
1225 return CC_USB_TRANSACTION_ERROR;
1226 }
1227
1228 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1229
1230 return CC_SUCCESS;
1231}
1232
1233static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1234 unsigned int epid, uint64_t pdequeue)
1235{
1236 XHCISlot *slot;
1237 XHCIEPContext *epctx;
59a70ccd 1238 dma_addr_t dequeue;
62c6ae04
HM		 1239
1240 assert(slotid >= 1 && slotid <= MAXSLOTS);
1241
1242 if (epid < 1 || epid > 31) {
1243 fprintf(stderr, "xhci: bad ep %d\n", epid);
1244 return CC_TRB_ERROR;
1245 }
1246
d829fde9 1247 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue);
62c6ae04
HM		 1248 dequeue = xhci_mask64(pdequeue);
1249
1250 slot = &xhci->slots[slotid-1];
1251
1252 if (!slot->eps[epid-1]) {
1253 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1254 return CC_EP_NOT_ENABLED_ERROR;
1255 }
1256
1257 epctx = slot->eps[epid-1];
1258
1259
1260 if (epctx->state != EP_STOPPED) {
1261 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1262 return CC_CONTEXT_STATE_ERROR;
1263 }
1264
1265 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1266 epctx->ring.ccs = dequeue & 1;
1267
1268 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1269
1270 return CC_SUCCESS;
1271}
1272
d5a15814 1273static int xhci_xfer_map(XHCITransfer *xfer)
62c6ae04 1274{
d5a15814 1275 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN);
62c6ae04 1276 XHCIState *xhci = xfer->xhci;
d5a15814 1277 int i;
62c6ae04 1278
d5a15814 1279 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
62c6ae04
HM		 1280 for (i = 0; i < xfer->trb_count; i++) {
1281 XHCITRB *trb = &xfer->trbs[i];
59a70ccd 1282 dma_addr_t addr;
62c6ae04
HM		 1283 unsigned int chunk = 0;
1284
1285 switch (TRB_TYPE(*trb)) {
1286 case TR_DATA:
1287 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1288 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
d5a15814 1289 goto err;
62c6ae04
HM		 1290 }
1291 /* fallthrough */
1292 case TR_NORMAL:
1293 case TR_ISOCH:
1294 addr = xhci_mask64(trb->parameter);
d5a15814
GH		 1295 chunk = trb->status & 0x1ffff;
1296 if (trb->control & TRB_TR_IDT) {
1297 if (chunk > 8 || in_xfer) {
1298 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1299 goto err;
1300 }
1301 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1302 } else {
1303 qemu_sglist_add(&xfer->sgl, addr, chunk);
1304 }
1305 break;
1306 }
1307 }
1308
1309 usb_packet_map(&xfer->packet, &xfer->sgl);
1310 return 0;
1311
1312err:
1313 qemu_sglist_destroy(&xfer->sgl);
1314 xhci_die(xhci);
1315 return -1;
1316}
1317
1318static void xhci_xfer_unmap(XHCITransfer *xfer)
1319{
1320 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1321 qemu_sglist_destroy(&xfer->sgl);
1322}
1323
1324static void xhci_xfer_report(XHCITransfer *xfer)
1325{
1326 uint32_t edtla = 0;
1327 unsigned int left;
1328 bool reported = 0;
1329 bool shortpkt = 0;
1330 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1331 XHCIState *xhci = xfer->xhci;
1332 int i;
1333
1334 left = xfer->packet.result < 0 ? 0 : xfer->packet.result;
1335
1336 for (i = 0; i < xfer->trb_count; i++) {
1337 XHCITRB *trb = &xfer->trbs[i];
1338 unsigned int chunk = 0;
1339
1340 switch (TRB_TYPE(*trb)) {
1341 case TR_DATA:
1342 case TR_NORMAL:
1343 case TR_ISOCH:
62c6ae04
HM		 1344 chunk = trb->status & 0x1ffff;
1345 if (chunk > left) {
1346 chunk = left;
d5a15814
GH		 1347 if (xfer->status == CC_SUCCESS) {
1348 shortpkt = 1;
62c6ae04
HM		 1349 }
1350 }
1351 left -= chunk;
62c6ae04 1352 edtla += chunk;
62c6ae04
HM		 1353 break;
1354 case TR_STATUS:
1355 reported = 0;
1356 shortpkt = 0;
1357 break;
1358 }
1359
d5a15814
GH		 1360 if (!reported && ((trb->control & TRB_TR_IOC) ||
1361 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1362 (xfer->status != CC_SUCCESS))) {
62c6ae04
HM		 1363 event.slotid = xfer->slotid;
1364 event.epid = xfer->epid;
1365 event.length = (trb->status & 0x1ffff) - chunk;
1366 event.flags = 0;
1367 event.ptr = trb->addr;
1368 if (xfer->status == CC_SUCCESS) {
1369 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1370 } else {
1371 event.ccode = xfer->status;
1372 }
1373 if (TRB_TYPE(*trb) == TR_EVDATA) {
1374 event.ptr = trb->parameter;
1375 event.flags |= TRB_EV_ED;
1376 event.length = edtla & 0xffffff;
1377 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1378 edtla = 0;
1379 }
962d11e1 1380 xhci_event(xhci, &event, 0 /* FIXME */);
62c6ae04 1381 reported = 1;
d5a15814
GH		 1382 if (xfer->status != CC_SUCCESS) {
1383 return;
1384 }
62c6ae04
HM		 1385 }
1386 }
62c6ae04
HM		 1387}
1388
1389static void xhci_stall_ep(XHCITransfer *xfer)
1390{
1391 XHCIState *xhci = xfer->xhci;
1392 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1393 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1394
1395 epctx->ring.dequeue = xfer->trbs[0].addr;
1396 epctx->ring.ccs = xfer->trbs[0].ccs;
1397 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1398 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
59a70ccd 1399 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue);
62c6ae04
HM		 1400}
1401
1402static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1403 XHCIEPContext *epctx);
1404
5c08106f 1405static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
62c6ae04 1406{
5c08106f
GH		 1407 if (!(port->portsc & PORTSC_PED)) {
1408 return NULL;
1409 }
0846e635 1410 return usb_find_device(port->uport, addr);
5c08106f
GH		 1411}
1412
1413static int xhci_setup_packet(XHCITransfer *xfer)
1414{
1415 XHCIState *xhci = xfer->xhci;
1416 XHCIPort *port;
1417 USBDevice *dev;
079d0b7f
GH		 1418 USBEndpoint *ep;
1419 int dir;
1420
1421 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
5c08106f
GH		 1422
1423 if (xfer->packet.ep) {
1424 ep = xfer->packet.ep;
1425 dev = ep->dev;
1426 } else {
1427 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1428 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1429 if (!dev) {
1430 fprintf(stderr, "xhci: slot %d port %d has no device\n",
1431 xfer->slotid, xhci->slots[xfer->slotid-1].port);
1432 return -1;
1433 }
1434 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1435 }
1436
e983395d 1437 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr);
d5a15814 1438 xhci_xfer_map(xfer);
62c6ae04 1439 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
079d0b7f 1440 xfer->packet.pid, dev->addr, ep->nr);
62c6ae04
HM		 1441 return 0;
1442}
1443
1444static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1445{
1446 if (ret == USB_RET_ASYNC) {
97df650b 1447 trace_usb_xhci_xfer_async(xfer);
7c605a23
GH		 1448 xfer->running_async = 1;
1449 xfer->running_retry = 0;
1450 xfer->complete = 0;
1451 xfer->cancelled = 0;
1452 return 0;
1453 } else if (ret == USB_RET_NAK) {
97df650b 1454 trace_usb_xhci_xfer_nak(xfer);
7c605a23
GH		 1455 xfer->running_async = 0;
1456 xfer->running_retry = 1;
62c6ae04
HM		 1457 xfer->complete = 0;
1458 xfer->cancelled = 0;
1459 return 0;
1460 } else {
7c605a23
GH		 1461 xfer->running_async = 0;
1462 xfer->running_retry = 0;
62c6ae04 1463 xfer->complete = 1;
d5a15814 1464 xhci_xfer_unmap(xfer);
62c6ae04
HM		 1465 }
1466
1467 if (ret >= 0) {
97df650b 1468 trace_usb_xhci_xfer_success(xfer, ret);
d5a15814
GH		 1469 xfer->status = CC_SUCCESS;
1470 xhci_xfer_report(xfer);
62c6ae04
HM		 1471 return 0;
1472 }
1473
1474 /* error */
97df650b 1475 trace_usb_xhci_xfer_error(xfer, ret);
62c6ae04
HM		 1476 switch (ret) {
1477 case USB_RET_NODEV:
1478 xfer->status = CC_USB_TRANSACTION_ERROR;
d5a15814 1479 xhci_xfer_report(xfer);
62c6ae04
HM		 1480 xhci_stall_ep(xfer);
1481 break;
1482 case USB_RET_STALL:
1483 xfer->status = CC_STALL_ERROR;
d5a15814 1484 xhci_xfer_report(xfer);
62c6ae04
HM		 1485 xhci_stall_ep(xfer);
1486 break;
1487 default:
1488 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1489 FIXME();
1490 }
1491 return 0;
1492}
1493
1494static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1495{
1496 XHCITRB *trb_setup, *trb_status;
2850ca9e 1497 uint8_t bmRequestType;
62c6ae04
HM		 1498 int ret;
1499
62c6ae04
HM		 1500 trb_setup = &xfer->trbs[0];
1501 trb_status = &xfer->trbs[xfer->trb_count-1];
1502
d5a15814 1503 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
97df650b 1504
62c6ae04
HM		 1505 /* at most one Event Data TRB allowed after STATUS */
1506 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1507 trb_status--;
1508 }
1509
1510 /* do some sanity checks */
1511 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1512 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1513 TRB_TYPE(*trb_setup));
1514 return -1;
1515 }
1516 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1517 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1518 TRB_TYPE(*trb_status));
1519 return -1;
1520 }
1521 if (!(trb_setup->control & TRB_TR_IDT)) {
1522 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1523 return -1;
1524 }
1525 if ((trb_setup->status & 0x1ffff) != 8) {
1526 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1527 (trb_setup->status & 0x1ffff));
1528 return -1;
1529 }
1530
1531 bmRequestType = trb_setup->parameter;
62c6ae04 1532
62c6ae04
HM		 1533 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1534 xfer->iso_xfer = false;
1535
5c08106f
GH		 1536 if (xhci_setup_packet(xfer) < 0) {
1537 return -1;
1538 }
2850ca9e 1539 xfer->packet.parameter = trb_setup->parameter;
2850ca9e 1540
5c08106f 1541 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
62c6ae04
HM		 1542
1543 xhci_complete_packet(xfer, ret);
7c605a23 1544 if (!xfer->running_async && !xfer->running_retry) {
62c6ae04
HM		 1545 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1546 }
1547 return 0;
1548}
1549
3d139684
GH		 1550static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1551 XHCIEPContext *epctx, uint64_t mfindex)
1552{
1553 if (xfer->trbs[0].control & TRB_TR_SIA) {
1554 uint64_t asap = ((mfindex + epctx->interval - 1) &
1555 ~(epctx->interval-1));
1556 if (asap >= epctx->mfindex_last &&
1557 asap <= epctx->mfindex_last + epctx->interval * 4) {
1558 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1559 } else {
1560 xfer->mfindex_kick = asap;
1561 }
1562 } else {
1563 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1564 & TRB_TR_FRAMEID_MASK;
1565 xfer->mfindex_kick |= mfindex & ~0x3fff;
1566 if (xfer->mfindex_kick < mfindex) {
1567 xfer->mfindex_kick += 0x4000;
1568 }
1569 }
1570}
1571
1572static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1573 XHCIEPContext *epctx, uint64_t mfindex)
1574{
1575 if (xfer->mfindex_kick > mfindex) {
1576 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) +
1577 (xfer->mfindex_kick - mfindex) * 125000);
1578 xfer->running_retry = 1;
1579 } else {
1580 epctx->mfindex_last = xfer->mfindex_kick;
1581 qemu_del_timer(epctx->kick_timer);
1582 xfer->running_retry = 0;
1583 }
1584}
1585
1586
62c6ae04
HM		 1587static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1588{
3d139684 1589 uint64_t mfindex;
62c6ae04
HM		 1590 int ret;
1591
1592 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
62c6ae04
HM		 1593
1594 xfer->in_xfer = epctx->type>>2;
62c6ae04 1595
62c6ae04
HM		 1596 switch(epctx->type) {
1597 case ET_INTR_OUT:
1598 case ET_INTR_IN:
1599 case ET_BULK_OUT:
1600 case ET_BULK_IN:
3d139684
GH		 1601 xfer->pkts = 0;
1602 xfer->iso_xfer = false;
62c6ae04
HM		 1603 break;
1604 case ET_ISO_OUT:
1605 case ET_ISO_IN:
3d139684
GH		 1606 xfer->pkts = 1;
1607 xfer->iso_xfer = true;
1608 mfindex = xhci_mfindex_get(xhci);
1609 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1610 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1611 if (xfer->running_retry) {
1612 return -1;
1613 }
62c6ae04
HM		 1614 break;
1615 default:
079d0b7f
GH		 1616 fprintf(stderr, "xhci: unknown or unhandled EP "
1617 "(type %d, in %d, ep %02x)\n",
1618 epctx->type, xfer->in_xfer, xfer->epid);
62c6ae04
HM		 1619 return -1;
1620 }
1621
5c08106f
GH		 1622 if (xhci_setup_packet(xfer) < 0) {
1623 return -1;
1624 }
1625 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
62c6ae04
HM		 1626
1627 xhci_complete_packet(xfer, ret);
7c605a23 1628 if (!xfer->running_async && !xfer->running_retry) {
62c6ae04
HM		 1629 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1630 }
1631 return 0;
1632}
1633
1634static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1635{
d5a15814 1636 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
331e9406 1637 return xhci_submit(xhci, xfer, epctx);
62c6ae04
HM		 1638}
1639
1640static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1641{
1642 XHCIEPContext *epctx;
3d139684 1643 uint64_t mfindex;
62c6ae04
HM		 1644 int length;
1645 int i;
1646
c1f6b493 1647 trace_usb_xhci_ep_kick(slotid, epid);
62c6ae04
HM		 1648 assert(slotid >= 1 && slotid <= MAXSLOTS);
1649 assert(epid >= 1 && epid <= 31);
62c6ae04
HM		 1650
1651 if (!xhci->slots[slotid-1].enabled) {
1652 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1653 return;
1654 }
1655 epctx = xhci->slots[slotid-1].eps[epid-1];
1656 if (!epctx) {
1657 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1658 epid, slotid);
1659 return;
1660 }
1661
7c605a23 1662 if (epctx->retry) {
7c605a23
GH		 1663 XHCITransfer *xfer = epctx->retry;
1664 int result;
1665
97df650b 1666 trace_usb_xhci_xfer_retry(xfer);
7c605a23 1667 assert(xfer->running_retry);
3d139684
GH		 1668 if (xfer->iso_xfer) {
1669 /* retry delayed iso transfer */
1670 mfindex = xhci_mfindex_get(xhci);
1671 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1672 if (xfer->running_retry) {
1673 return;
1674 }
1675 if (xhci_setup_packet(xfer) < 0) {
1676 return;
1677 }
1678 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1679 assert(result != USB_RET_NAK);
1680 xhci_complete_packet(xfer, result);
1681 } else {
1682 /* retry nak'ed transfer */
1683 if (xhci_setup_packet(xfer) < 0) {
1684 return;
1685 }
1686 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1687 if (result == USB_RET_NAK) {
1688 return;
1689 }
1690 xhci_complete_packet(xfer, result);
7c605a23 1691 }
7c605a23
GH		 1692 assert(!xfer->running_retry);
1693 epctx->retry = NULL;
1694 }
1695
62c6ae04
HM		 1696 if (epctx->state == EP_HALTED) {
1697 DPRINTF("xhci: ep halted, not running schedule\n");
1698 return;
1699 }
1700
1701 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1702
1703 while (1) {
1704 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
331e9406 1705 if (xfer->running_async || xfer->running_retry) {
62c6ae04
HM		 1706 break;
1707 }
1708 length = xhci_ring_chain_length(xhci, &epctx->ring);
1709 if (length < 0) {
62c6ae04
HM		 1710 break;
1711 } else if (length == 0) {
1712 break;
1713 }
62c6ae04
HM		 1714 if (xfer->trbs && xfer->trb_alloced < length) {
1715 xfer->trb_count = 0;
1716 xfer->trb_alloced = 0;
1717 g_free(xfer->trbs);
1718 xfer->trbs = NULL;
1719 }
1720 if (!xfer->trbs) {
1721 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1722 xfer->trb_alloced = length;
1723 }
1724 xfer->trb_count = length;
1725
1726 for (i = 0; i < length; i++) {
1727 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1728 }
1729 xfer->xhci = xhci;
1730 xfer->epid = epid;
1731 xfer->slotid = slotid;
1732
1733 if (epid == 1) {
1734 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1735 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1736 } else {
1737 fprintf(stderr, "xhci: error firing CTL transfer\n");
1738 }
1739 } else {
1740 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1741 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1742 } else {
3d139684
GH		 1743 if (!xfer->iso_xfer) {
1744 fprintf(stderr, "xhci: error firing data transfer\n");
1745 }
62c6ae04
HM		 1746 }
1747 }
1748
3c4866e0 1749 if (epctx->state == EP_HALTED) {
3c4866e0
GH		 1750 break;
1751 }
7c605a23
GH		 1752 if (xfer->running_retry) {
1753 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1754 epctx->retry = xfer;
1755 break;
1756 }
62c6ae04
HM		 1757 }
1758}
1759
1760static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1761{
348f1037 1762 trace_usb_xhci_slot_enable(slotid);
62c6ae04 1763 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1764 xhci->slots[slotid-1].enabled = 1;
1765 xhci->slots[slotid-1].port = 0;
1766 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1767
1768 return CC_SUCCESS;
1769}
1770
1771static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1772{
1773 int i;
1774
348f1037 1775 trace_usb_xhci_slot_disable(slotid);
62c6ae04 1776 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1777
1778 for (i = 1; i <= 31; i++) {
1779 if (xhci->slots[slotid-1].eps[i-1]) {
1780 xhci_disable_ep(xhci, slotid, i);
1781 }
1782 }
1783
1784 xhci->slots[slotid-1].enabled = 0;
1785 return CC_SUCCESS;
1786}
1787
1788static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1789 uint64_t pictx, bool bsr)
1790{
1791 XHCISlot *slot;
1792 USBDevice *dev;
59a70ccd 1793 dma_addr_t ictx, octx, dcbaap;
62c6ae04
HM		 1794 uint64_t poctx;
1795 uint32_t ictl_ctx[2];
1796 uint32_t slot_ctx[4];
1797 uint32_t ep0_ctx[5];
1798 unsigned int port;
1799 int i;
1800 TRBCCode res;
1801
348f1037 1802 trace_usb_xhci_slot_address(slotid);
62c6ae04 1803 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1804
1805 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
59a70ccd 1806 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx));
62c6ae04
HM		 1807 ictx = xhci_mask64(pictx);
1808 octx = xhci_mask64(le64_to_cpu(poctx));
1809
59a70ccd
DG		 1810 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1811 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 1812
59a70ccd 1813 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 1814
1815 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1816 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1817 ictl_ctx[0], ictl_ctx[1]);
1818 return CC_TRB_ERROR;
1819 }
1820
59a70ccd
DG		 1821 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx));
1822 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 1823
1824 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1825 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1826
1827 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1828 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1829
1830 port = (slot_ctx[1]>>16) & 0xFF;
0846e635 1831 dev = xhci->ports[port-1].uport->dev;
62c6ae04 1832
0846e635 1833 if (port < 1 || port > xhci->numports) {
62c6ae04
HM		 1834 fprintf(stderr, "xhci: bad port %d\n", port);
1835 return CC_TRB_ERROR;
1836 } else if (!dev) {
1837 fprintf(stderr, "xhci: port %d not connected\n", port);
1838 return CC_USB_TRANSACTION_ERROR;
1839 }
1840
1841 for (i = 0; i < MAXSLOTS; i++) {
1842 if (xhci->slots[i].port == port) {
1843 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1844 port, i+1);
1845 return CC_TRB_ERROR;
1846 }
1847 }
1848
1849 slot = &xhci->slots[slotid-1];
1850 slot->port = port;
1851 slot->ctx = octx;
1852
1853 if (bsr) {
1854 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1855 } else {
1856 slot->devaddr = xhci->devaddr++;
1857 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1858 DPRINTF("xhci: device address is %d\n", slot->devaddr);
62aed765 1859 usb_device_handle_control(dev, NULL,
62c6ae04
HM		 1860 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1861 slot->devaddr, 0, 0, NULL);
1862 }
1863
1864 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1865
1866 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1867 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1868 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1869 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1870
59a70ccd
DG		 1871 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1872 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 1873
1874 return res;
1875}
1876
1877
1878static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1879 uint64_t pictx, bool dc)
1880{
59a70ccd 1881 dma_addr_t ictx, octx;
62c6ae04
HM		 1882 uint32_t ictl_ctx[2];
1883 uint32_t slot_ctx[4];
1884 uint32_t islot_ctx[4];
1885 uint32_t ep_ctx[5];
1886 int i;
1887 TRBCCode res;
1888
348f1037 1889 trace_usb_xhci_slot_configure(slotid);
62c6ae04 1890 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1891
1892 ictx = xhci_mask64(pictx);
1893 octx = xhci->slots[slotid-1].ctx;
1894
59a70ccd
DG		 1895 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1896 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 1897
1898 if (dc) {
1899 for (i = 2; i <= 31; i++) {
1900 if (xhci->slots[slotid-1].eps[i-1]) {
1901 xhci_disable_ep(xhci, slotid, i);
1902 }
1903 }
1904
59a70ccd 1905 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1906 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1907 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1908 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1909 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
59a70ccd 1910 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1911
1912 return CC_SUCCESS;
1913 }
1914
59a70ccd 1915 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 1916
1917 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1918 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1919 ictl_ctx[0], ictl_ctx[1]);
1920 return CC_TRB_ERROR;
1921 }
1922
59a70ccd
DG		 1923 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1924 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1925
1926 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1927 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1928 return CC_CONTEXT_STATE_ERROR;
1929 }
1930
1931 for (i = 2; i <= 31; i++) {
1932 if (ictl_ctx[0] & (1<<i)) {
1933 xhci_disable_ep(xhci, slotid, i);
1934 }
1935 if (ictl_ctx[1] & (1<<i)) {
59a70ccd
DG		 1936 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx,
1937 sizeof(ep_ctx));
62c6ae04
HM		 1938 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1939 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1940 ep_ctx[3], ep_ctx[4]);
1941 xhci_disable_ep(xhci, slotid, i);
1942 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1943 if (res != CC_SUCCESS) {
1944 return res;
1945 }
1946 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1947 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1948 ep_ctx[3], ep_ctx[4]);
59a70ccd 1949 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx));
62c6ae04
HM		 1950 }
1951 }
1952
1953 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1954 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1955 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1956 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1957 SLOT_CONTEXT_ENTRIES_SHIFT);
1958 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1959 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1960
59a70ccd 1961 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1962
1963 return CC_SUCCESS;
1964}
1965
1966
1967static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1968 uint64_t pictx)
1969{
59a70ccd 1970 dma_addr_t ictx, octx;
62c6ae04
HM		 1971 uint32_t ictl_ctx[2];
1972 uint32_t iep0_ctx[5];
1973 uint32_t ep0_ctx[5];
1974 uint32_t islot_ctx[4];
1975 uint32_t slot_ctx[4];
1976
348f1037 1977 trace_usb_xhci_slot_evaluate(slotid);
62c6ae04 1978 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1979
1980 ictx = xhci_mask64(pictx);
1981 octx = xhci->slots[slotid-1].ctx;
1982
59a70ccd
DG		 1983 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1984 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 1985
59a70ccd 1986 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 1987
1988 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1989 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1990 ictl_ctx[0], ictl_ctx[1]);
1991 return CC_TRB_ERROR;
1992 }
1993
1994 if (ictl_ctx[1] & 0x1) {
59a70ccd 1995 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
62c6ae04
HM		 1996
1997 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1998 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1999
59a70ccd 2000 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2001
2002 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2003 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2004 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2005 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2006
2007 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2008 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2009
59a70ccd 2010 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2011 }
2012
2013 if (ictl_ctx[1] & 0x2) {
59a70ccd 2014 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx));
62c6ae04
HM		 2015
2016 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2017 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2018 iep0_ctx[3], iep0_ctx[4]);
2019
59a70ccd 2020 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2021
2022 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2023 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2024
2025 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2026 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2027
59a70ccd 2028 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 2029 }
2030
2031 return CC_SUCCESS;
2032}
2033
2034static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2035{
2036 uint32_t slot_ctx[4];
59a70ccd 2037 dma_addr_t octx;
62c6ae04
HM		 2038 int i;
2039
348f1037 2040 trace_usb_xhci_slot_reset(slotid);
62c6ae04 2041 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 2042
2043 octx = xhci->slots[slotid-1].ctx;
2044
59a70ccd 2045 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 2046
2047 for (i = 2; i <= 31; i++) {
2048 if (xhci->slots[slotid-1].eps[i-1]) {
2049 xhci_disable_ep(xhci, slotid, i);
2050 }
2051 }
2052
59a70ccd 2053 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2054 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2055 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2056 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2057 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
59a70ccd 2058 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 2059
2060 return CC_SUCCESS;
2061}
2062
2063static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2064{
2065 unsigned int slotid;
2066 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2067 if (slotid < 1 || slotid > MAXSLOTS) {
2068 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2069 event->ccode = CC_TRB_ERROR;
2070 return 0;
2071 } else if (!xhci->slots[slotid-1].enabled) {
2072 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2073 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2074 return 0;
2075 }
2076 return slotid;
2077}
2078
2079static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2080{
59a70ccd 2081 dma_addr_t ctx;
0846e635 2082 uint8_t bw_ctx[xhci->numports+1];
62c6ae04
HM		 2083
2084 DPRINTF("xhci_get_port_bandwidth()\n");
2085
2086 ctx = xhci_mask64(pctx);
2087
59a70ccd 2088 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
62c6ae04
HM		 2089
2090 /* TODO: actually implement real values here */
2091 bw_ctx[0] = 0;
0846e635 2092 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
59a70ccd 2093 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
62c6ae04
HM		 2094
2095 return CC_SUCCESS;
2096}
2097
2098static uint32_t rotl(uint32_t v, unsigned count)
2099{
2100 count &= 31;
2101 return (v << count) | (v >> (32 - count));
2102}
2103
2104
2105static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2106{
2107 uint32_t val;
2108 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2109 val += rotl(lo + 0x49434878, hi & 0x1F);
2110 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2111 return ~val;
2112}
2113
59a70ccd 2114static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
62c6ae04
HM		 2115{
2116 uint32_t buf[8];
2117 uint32_t obuf[8];
59a70ccd 2118 dma_addr_t paddr = xhci_mask64(addr);
62c6ae04 2119
59a70ccd 2120 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
62c6ae04
HM		 2121
2122 memcpy(obuf, buf, sizeof(obuf));
2123
2124 if ((buf[0] & 0xff) == 2) {
2125 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2126 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2127 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2128 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2129 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2130 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2131 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2132 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2133 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2134 }
2135
59a70ccd 2136 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
62c6ae04
HM		 2137}
2138
2139static void xhci_process_commands(XHCIState *xhci)
2140{
2141 XHCITRB trb;
2142 TRBType type;
2143 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
59a70ccd 2144 dma_addr_t addr;
62c6ae04
HM		 2145 unsigned int i, slotid = 0;
2146
2147 DPRINTF("xhci_process_commands()\n");
2148 if (!xhci_running(xhci)) {
2149 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2150 return;
2151 }
2152
2153 xhci->crcr_low |= CRCR_CRR;
2154
2155 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2156 event.ptr = addr;
2157 switch (type) {
2158 case CR_ENABLE_SLOT:
2159 for (i = 0; i < MAXSLOTS; i++) {
2160 if (!xhci->slots[i].enabled) {
2161 break;
2162 }
2163 }
2164 if (i >= MAXSLOTS) {
2165 fprintf(stderr, "xhci: no device slots available\n");
2166 event.ccode = CC_NO_SLOTS_ERROR;
2167 } else {
2168 slotid = i+1;
2169 event.ccode = xhci_enable_slot(xhci, slotid);
2170 }
2171 break;
2172 case CR_DISABLE_SLOT:
2173 slotid = xhci_get_slot(xhci, &event, &trb);
2174 if (slotid) {
2175 event.ccode = xhci_disable_slot(xhci, slotid);
2176 }
2177 break;
2178 case CR_ADDRESS_DEVICE:
2179 slotid = xhci_get_slot(xhci, &event, &trb);
2180 if (slotid) {
2181 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2182 trb.control & TRB_CR_BSR);
2183 }
2184 break;
2185 case CR_CONFIGURE_ENDPOINT:
2186 slotid = xhci_get_slot(xhci, &event, &trb);
2187 if (slotid) {
2188 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2189 trb.control & TRB_CR_DC);
2190 }
2191 break;
2192 case CR_EVALUATE_CONTEXT:
2193 slotid = xhci_get_slot(xhci, &event, &trb);
2194 if (slotid) {
2195 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2196 }
2197 break;
2198 case CR_STOP_ENDPOINT:
2199 slotid = xhci_get_slot(xhci, &event, &trb);
2200 if (slotid) {
2201 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2202 & TRB_CR_EPID_MASK;
2203 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2204 }
2205 break;
2206 case CR_RESET_ENDPOINT:
2207 slotid = xhci_get_slot(xhci, &event, &trb);
2208 if (slotid) {
2209 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2210 & TRB_CR_EPID_MASK;
2211 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2212 }
2213 break;
2214 case CR_SET_TR_DEQUEUE:
2215 slotid = xhci_get_slot(xhci, &event, &trb);
2216 if (slotid) {
2217 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2218 & TRB_CR_EPID_MASK;
2219 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2220 trb.parameter);
2221 }
2222 break;
2223 case CR_RESET_DEVICE:
2224 slotid = xhci_get_slot(xhci, &event, &trb);
2225 if (slotid) {
2226 event.ccode = xhci_reset_slot(xhci, slotid);
2227 }
2228 break;
2229 case CR_GET_PORT_BANDWIDTH:
2230 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2231 break;
2232 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
59a70ccd 2233 xhci_via_challenge(xhci, trb.parameter);
62c6ae04
HM		 2234 break;
2235 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2236 event.type = 48; /* NEC reply */
2237 event.length = 0x3025;
2238 break;
2239 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2240 {
2241 uint32_t chi = trb.parameter >> 32;
2242 uint32_t clo = trb.parameter;
2243 uint32_t val = xhci_nec_challenge(chi, clo);
2244 event.length = val & 0xFFFF;
2245 event.epid = val >> 16;
2246 slotid = val >> 24;
2247 event.type = 48; /* NEC reply */
2248 }
2249 break;
2250 default:
2251 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2252 event.ccode = CC_TRB_ERROR;
2253 break;
2254 }
2255 event.slotid = slotid;
962d11e1 2256 xhci_event(xhci, &event, 0 /* FIXME */);
62c6ae04
HM		 2257 }
2258}
2259
2260static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2261{
62c6ae04 2262 port->portsc = PORTSC_PP;
0846e635
GH		 2263 if (port->uport->dev && port->uport->dev->attached && !is_detach &&
2264 (1 << port->uport->dev->speed) & port->speedmask) {
62c6ae04 2265 port->portsc |= PORTSC_CCS;
0846e635 2266 switch (port->uport->dev->speed) {
62c6ae04
HM		 2267 case USB_SPEED_LOW:
2268 port->portsc |= PORTSC_SPEED_LOW;
2269 break;
2270 case USB_SPEED_FULL:
2271 port->portsc |= PORTSC_SPEED_FULL;
2272 break;
2273 case USB_SPEED_HIGH:
2274 port->portsc |= PORTSC_SPEED_HIGH;
2275 break;
0846e635
GH		 2276 case USB_SPEED_SUPER:
2277 port->portsc |= PORTSC_SPEED_SUPER;
2278 break;
62c6ae04
HM		 2279 }
2280 }
2281
2282 if (xhci_running(xhci)) {
2283 port->portsc |= PORTSC_CSC;
0846e635
GH		 2284 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2285 port->portnr << 24};
962d11e1 2286 xhci_event(xhci, &ev, 0 /* FIXME */);
0846e635 2287 DPRINTF("xhci: port change event for port %d\n", port->portnr);
62c6ae04
HM		 2288 }
2289}
2290
64619739 2291static void xhci_reset(DeviceState *dev)
62c6ae04 2292{
64619739 2293 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
62c6ae04
HM		 2294 int i;
2295
2d754a10 2296 trace_usb_xhci_reset();
62c6ae04
HM		 2297 if (!(xhci->usbsts & USBSTS_HCH)) {
2298 fprintf(stderr, "xhci: reset while running!\n");
2299 }
2300
2301 xhci->usbcmd = 0;
2302 xhci->usbsts = USBSTS_HCH;
2303 xhci->dnctrl = 0;
2304 xhci->crcr_low = 0;
2305 xhci->crcr_high = 0;
2306 xhci->dcbaap_low = 0;
2307 xhci->dcbaap_high = 0;
2308 xhci->config = 0;
2309 xhci->devaddr = 2;
2310
2311 for (i = 0; i < MAXSLOTS; i++) {
2312 xhci_disable_slot(xhci, i+1);
2313 }
2314
0846e635 2315 for (i = 0; i < xhci->numports; i++) {
62c6ae04
HM		 2316 xhci_update_port(xhci, xhci->ports + i, 0);
2317 }
2318
962d11e1
GH		 2319 for (i = 0; i < MAXINTRS; i++) {
2320 xhci->intr[i].iman = 0;
2321 xhci->intr[i].imod = 0;
2322 xhci->intr[i].erstsz = 0;
2323 xhci->intr[i].erstba_low = 0;
2324 xhci->intr[i].erstba_high = 0;
2325 xhci->intr[i].erdp_low = 0;
2326 xhci->intr[i].erdp_high = 0;
2327 xhci->intr[i].msix_used = 0;
62c6ae04 2328
962d11e1
GH		 2329 xhci->intr[i].er_ep_idx = 0;
2330 xhci->intr[i].er_pcs = 1;
2331 xhci->intr[i].er_full = 0;
2332 xhci->intr[i].ev_buffer_put = 0;
2333 xhci->intr[i].ev_buffer_get = 0;
2334 }
01546fa6
GH		 2335
2336 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
2337 xhci_mfwrap_update(xhci);
62c6ae04
HM		 2338}
2339
2340static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2341{
2d754a10 2342 uint32_t ret;
62c6ae04
HM		 2343
2344 switch (reg) {
2345 case 0x00: /* HCIVERSION, CAPLENGTH */
2d754a10
GH		 2346 ret = 0x01000000 | LEN_CAP;
2347 break;
62c6ae04 2348 case 0x04: /* HCSPARAMS 1 */
0846e635
GH		 2349 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2350 | (MAXINTRS<<8) | MAXSLOTS;
2d754a10 2351 break;
62c6ae04 2352 case 0x08: /* HCSPARAMS 2 */
2d754a10
GH		 2353 ret = 0x0000000f;
2354 break;
62c6ae04 2355 case 0x0c: /* HCSPARAMS 3 */
2d754a10
GH		 2356 ret = 0x00000000;
2357 break;
62c6ae04 2358 case 0x10: /* HCCPARAMS */
2d754a10
GH		 2359 if (sizeof(dma_addr_t) == 4) {
2360 ret = 0x00081000;
2361 } else {
2362 ret = 0x00081001;
2363 }
2364 break;
62c6ae04 2365 case 0x14: /* DBOFF */
2d754a10
GH		 2366 ret = OFF_DOORBELL;
2367 break;
62c6ae04 2368 case 0x18: /* RTSOFF */
2d754a10
GH		 2369 ret = OFF_RUNTIME;
2370 break;
62c6ae04
HM		 2371
2372 /* extended capabilities */
2373 case 0x20: /* Supported Protocol:00 */
2d754a10
GH		 2374 ret = 0x02000402; /* USB 2.0 */
2375 break;
62c6ae04 2376 case 0x24: /* Supported Protocol:04 */
2d754a10
GH		 2377 ret = 0x20425455; /* "USB " */
2378 break;
62c6ae04 2379 case 0x28: /* Supported Protocol:08 */
0846e635 2380 ret = 0x00000001 | (xhci->numports_2<<8);
2d754a10 2381 break;
62c6ae04 2382 case 0x2c: /* Supported Protocol:0c */
2d754a10
GH		 2383 ret = 0x00000000; /* reserved */
2384 break;
62c6ae04 2385 case 0x30: /* Supported Protocol:00 */
2d754a10
GH		 2386 ret = 0x03000002; /* USB 3.0 */
2387 break;
62c6ae04 2388 case 0x34: /* Supported Protocol:04 */
2d754a10
GH		 2389 ret = 0x20425455; /* "USB " */
2390 break;
62c6ae04 2391 case 0x38: /* Supported Protocol:08 */
0846e635 2392 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2d754a10 2393 break;
62c6ae04 2394 case 0x3c: /* Supported Protocol:0c */
2d754a10
GH		 2395 ret = 0x00000000; /* reserved */
2396 break;
62c6ae04
HM		 2397 default:
2398 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2d754a10 2399 ret = 0;
62c6ae04 2400 }
2d754a10
GH		 2401
2402 trace_usb_xhci_cap_read(reg, ret);
2403 return ret;
62c6ae04
HM		 2404}
2405
2406static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2407{
2408 uint32_t port = reg >> 4;
2d754a10
GH		 2409 uint32_t ret;
2410
0846e635 2411 if (port >= xhci->numports) {
62c6ae04 2412 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2d754a10
GH		 2413 ret = 0;
2414 goto out;
62c6ae04
HM		 2415 }
2416
2417 switch (reg & 0xf) {
2418 case 0x00: /* PORTSC */
2d754a10
GH		 2419 ret = xhci->ports[port].portsc;
2420 break;
62c6ae04
HM		 2421 case 0x04: /* PORTPMSC */
2422 case 0x08: /* PORTLI */
2d754a10
GH		 2423 ret = 0;
2424 break;
62c6ae04
HM		 2425 case 0x0c: /* reserved */
2426 default:
2427 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2428 port, reg);
2d754a10 2429 ret = 0;
62c6ae04 2430 }
2d754a10
GH		 2431
2432out:
2433 trace_usb_xhci_port_read(port, reg & 0x0f, ret);
2434 return ret;
62c6ae04
HM		 2435}
2436
2437static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2438{
2439 uint32_t port = reg >> 4;
2440 uint32_t portsc;
2441
2d754a10
GH		 2442 trace_usb_xhci_port_write(port, reg & 0x0f, val);
2443
0846e635 2444 if (port >= xhci->numports) {
62c6ae04
HM		 2445 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2446 return;
2447 }
2448
2449 switch (reg & 0xf) {
2450 case 0x00: /* PORTSC */
2451 portsc = xhci->ports[port].portsc;
2452 /* write-1-to-clear bits*/
2453 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2454 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2455 if (val & PORTSC_LWS) {
2456 /* overwrite PLS only when LWS=1 */
2457 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2458 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2459 }
2460 /* read/write bits */
2461 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2462 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2463 /* write-1-to-start bits */
2464 if (val & PORTSC_PR) {
2465 DPRINTF("xhci: port %d reset\n", port);
0846e635 2466 usb_device_reset(xhci->ports[port].uport->dev);
62c6ae04
HM		 2467 portsc |= PORTSC_PRC | PORTSC_PED;
2468 }
2469 xhci->ports[port].portsc = portsc;
2470 break;
2471 case 0x04: /* PORTPMSC */
2472 case 0x08: /* PORTLI */
2473 default:
2474 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2475 port, reg);
2476 }
2477}
2478
2479static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2480{
2d754a10 2481 uint32_t ret;
62c6ae04
HM		 2482
2483 if (reg >= 0x400) {
2484 return xhci_port_read(xhci, reg - 0x400);
2485 }
2486
2487 switch (reg) {
2488 case 0x00: /* USBCMD */
2d754a10
GH		 2489 ret = xhci->usbcmd;
2490 break;
62c6ae04 2491 case 0x04: /* USBSTS */
2d754a10
GH		 2492 ret = xhci->usbsts;
2493 break;
62c6ae04 2494 case 0x08: /* PAGESIZE */
2d754a10
GH		 2495 ret = 1; /* 4KiB */
2496 break;
62c6ae04 2497 case 0x14: /* DNCTRL */
2d754a10
GH		 2498 ret = xhci->dnctrl;
2499 break;
62c6ae04 2500 case 0x18: /* CRCR low */
2d754a10
GH		 2501 ret = xhci->crcr_low & ~0xe;
2502 break;
62c6ae04 2503 case 0x1c: /* CRCR high */
2d754a10
GH		 2504 ret = xhci->crcr_high;
2505 break;
62c6ae04 2506 case 0x30: /* DCBAAP low */
2d754a10
GH		 2507 ret = xhci->dcbaap_low;
2508 break;
62c6ae04 2509 case 0x34: /* DCBAAP high */
2d754a10
GH		 2510 ret = xhci->dcbaap_high;
2511 break;
62c6ae04 2512 case 0x38: /* CONFIG */
2d754a10
GH		 2513 ret = xhci->config;
2514 break;
62c6ae04
HM		 2515 default:
2516 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2d754a10 2517 ret = 0;
62c6ae04 2518 }
2d754a10
GH		 2519
2520 trace_usb_xhci_oper_read(reg, ret);
2521 return ret;
62c6ae04
HM		 2522}
2523
2524static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2525{
62c6ae04
HM		 2526 if (reg >= 0x400) {
2527 xhci_port_write(xhci, reg - 0x400, val);
2528 return;
2529 }
2530
2d754a10
GH		 2531 trace_usb_xhci_oper_write(reg, val);
2532
62c6ae04
HM		 2533 switch (reg) {
2534 case 0x00: /* USBCMD */
2535 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2536 xhci_run(xhci);
2537 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2538 xhci_stop(xhci);
2539 }
2540 xhci->usbcmd = val & 0xc0f;
01546fa6 2541 xhci_mfwrap_update(xhci);
62c6ae04 2542 if (val & USBCMD_HCRST) {
64619739 2543 xhci_reset(&xhci->pci_dev.qdev);
62c6ae04 2544 }
4c4abe7c 2545 xhci_intx_update(xhci);
62c6ae04
HM		 2546 break;
2547
2548 case 0x04: /* USBSTS */
2549 /* these bits are write-1-to-clear */
2550 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
4c4abe7c 2551 xhci_intx_update(xhci);
62c6ae04
HM		 2552 break;
2553
2554 case 0x14: /* DNCTRL */
2555 xhci->dnctrl = val & 0xffff;
2556 break;
2557 case 0x18: /* CRCR low */
2558 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2559 break;
2560 case 0x1c: /* CRCR high */
2561 xhci->crcr_high = val;
2562 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2563 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2564 xhci->crcr_low &= ~CRCR_CRR;
962d11e1 2565 xhci_event(xhci, &event, 0 /* FIXME */);
62c6ae04
HM		 2566 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2567 } else {
59a70ccd 2568 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
62c6ae04
HM		 2569 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2570 }
2571 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2572 break;
2573 case 0x30: /* DCBAAP low */
2574 xhci->dcbaap_low = val & 0xffffffc0;
2575 break;
2576 case 0x34: /* DCBAAP high */
2577 xhci->dcbaap_high = val;
2578 break;
2579 case 0x38: /* CONFIG */
2580 xhci->config = val & 0xff;
2581 break;
2582 default:
2583 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2584 }
2585}
2586
2587static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2588{
962d11e1 2589 XHCIInterrupter *intr = &xhci->intr[0];
2d754a10 2590 uint32_t ret;
62c6ae04
HM		 2591
2592 switch (reg) {
2593 case 0x00: /* MFINDEX */
01546fa6 2594 ret = xhci_mfindex_get(xhci) & 0x3fff;
2d754a10 2595 break;
62c6ae04 2596 case 0x20: /* IMAN */
962d11e1 2597 ret = intr->iman;
2d754a10 2598 break;
62c6ae04 2599 case 0x24: /* IMOD */
962d11e1 2600 ret = intr->imod;
2d754a10 2601 break;
62c6ae04 2602 case 0x28: /* ERSTSZ */
962d11e1 2603 ret = intr->erstsz;
2d754a10 2604 break;
62c6ae04 2605 case 0x30: /* ERSTBA low */
962d11e1 2606 ret = intr->erstba_low;
2d754a10 2607 break;
62c6ae04 2608 case 0x34: /* ERSTBA high */
962d11e1 2609 ret = intr->erstba_high;
2d754a10 2610 break;
62c6ae04 2611 case 0x38: /* ERDP low */
962d11e1 2612 ret = intr->erdp_low;
2d754a10 2613 break;
62c6ae04 2614 case 0x3c: /* ERDP high */
962d11e1 2615 ret = intr->erdp_high;
2d754a10 2616 break;
62c6ae04
HM		 2617 default:
2618 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2d754a10 2619 ret = 0;
62c6ae04 2620 }
2d754a10
GH		 2621
2622 trace_usb_xhci_runtime_read(reg, ret);
2623 return ret;
62c6ae04
HM		 2624}
2625
2626static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2627{
962d11e1 2628 XHCIInterrupter *intr = &xhci->intr[0];
8e9f18b6 2629 trace_usb_xhci_runtime_write(reg, val);
62c6ae04
HM		 2630
2631 switch (reg) {
2632 case 0x20: /* IMAN */
2633 if (val & IMAN_IP) {
962d11e1 2634 intr->iman &= ~IMAN_IP;
62c6ae04 2635 }
962d11e1
GH		 2636 intr->iman &= ~IMAN_IE;
2637 intr->iman |= val & IMAN_IE;
4c4abe7c 2638 xhci_intx_update(xhci);
962d11e1 2639 xhci_msix_update(xhci, 0);
62c6ae04
HM		 2640 break;
2641 case 0x24: /* IMOD */
962d11e1 2642 intr->imod = val;
62c6ae04
HM		 2643 break;
2644 case 0x28: /* ERSTSZ */
962d11e1 2645 intr->erstsz = val & 0xffff;
62c6ae04
HM		 2646 break;
2647 case 0x30: /* ERSTBA low */
2648 /* XXX NEC driver bug: it doesn't align this to 64 bytes
962d11e1
GH		 2649 intr->erstba_low = val & 0xffffffc0; */
2650 intr->erstba_low = val & 0xfffffff0;
62c6ae04
HM		 2651 break;
2652 case 0x34: /* ERSTBA high */
962d11e1
GH		 2653 intr->erstba_high = val;
2654 xhci_er_reset(xhci, 0);
62c6ae04
HM		 2655 break;
2656 case 0x38: /* ERDP low */
2657 if (val & ERDP_EHB) {
962d11e1 2658 intr->erdp_low &= ~ERDP_EHB;
62c6ae04 2659 }
962d11e1 2660 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
62c6ae04
HM		 2661 break;
2662 case 0x3c: /* ERDP high */
962d11e1
GH		 2663 intr->erdp_high = val;
2664 xhci_events_update(xhci, 0);
62c6ae04
HM		 2665 break;
2666 default:
2667 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2668 }
2669}
2670
2671static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2672{
62c6ae04 2673 /* doorbells always read as 0 */
2d754a10 2674 trace_usb_xhci_doorbell_read(reg, 0);
62c6ae04
HM		 2675 return 0;
2676}
2677
2678static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2679{
2d754a10 2680 trace_usb_xhci_doorbell_write(reg, val);
62c6ae04
HM		 2681
2682 if (!xhci_running(xhci)) {
2683 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2684 return;
2685 }
2686
2687 reg >>= 2;
2688
2689 if (reg == 0) {
2690 if (val == 0) {
2691 xhci_process_commands(xhci);
2692 } else {
2693 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2694 }
2695 } else {
2696 if (reg > MAXSLOTS) {
2697 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2698 } else if (val > 31) {
2699 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2700 } else {
2701 xhci_kick_ep(xhci, reg, val);
2702 }
2703 }
2704}
2705
2706static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2707 unsigned size)
2708{
2709 XHCIState *xhci = ptr;
2710
2711 /* Only aligned reads are allowed on xHCI */
2712 if (addr & 3) {
2713 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2714 return 0;
2715 }
2716
2717 if (addr < LEN_CAP) {
2718 return xhci_cap_read(xhci, addr);
2719 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2720 return xhci_oper_read(xhci, addr - OFF_OPER);
2721 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2722 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2723 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2724 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2725 } else {
2726 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2727 return 0;
2728 }
2729}
2730
2731static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2732 uint64_t val, unsigned size)
2733{
2734 XHCIState *xhci = ptr;
2735
2736 /* Only aligned writes are allowed on xHCI */
2737 if (addr & 3) {
2738 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2739 return;
2740 }
2741
2742 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2743 xhci_oper_write(xhci, addr - OFF_OPER, val);
2744 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2745 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2746 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2747 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2748 } else {
2749 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2750 }
2751}
2752
2753static const MemoryRegionOps xhci_mem_ops = {
2754 .read = xhci_mem_read,
2755 .write = xhci_mem_write,
2756 .valid.min_access_size = 4,
2757 .valid.max_access_size = 4,
2758 .endianness = DEVICE_LITTLE_ENDIAN,
2759};
2760
2761static void xhci_attach(USBPort *usbport)
2762{
2763 XHCIState *xhci = usbport->opaque;
0846e635 2764 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04
HM		 2765
2766 xhci_update_port(xhci, port, 0);
2767}
2768
2769static void xhci_detach(USBPort *usbport)
2770{
2771 XHCIState *xhci = usbport->opaque;
0846e635 2772 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04
HM		 2773
2774 xhci_update_port(xhci, port, 1);
2775}
2776
8c735e43
GH		 2777static void xhci_wakeup(USBPort *usbport)
2778{
2779 XHCIState *xhci = usbport->opaque;
0846e635
GH		 2780 XHCIPort *port = xhci_lookup_port(xhci, usbport);
2781 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2782 port->portnr << 24};
8c735e43
GH		 2783 uint32_t pls;
2784
2785 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
2786 if (pls != 3) {
2787 return;
2788 }
2789 port->portsc |= 0xf << PORTSC_PLS_SHIFT;
2790 if (port->portsc & PORTSC_PLC) {
2791 return;
2792 }
2793 port->portsc |= PORTSC_PLC;
962d11e1 2794 xhci_event(xhci, &ev, 0 /* FIXME */);
8c735e43
GH		 2795}
2796
62c6ae04
HM		 2797static void xhci_complete(USBPort *port, USBPacket *packet)
2798{
2799 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2800
2801 xhci_complete_packet(xfer, packet->result);
2802 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2803}
2804
2805static void xhci_child_detach(USBPort *port, USBDevice *child)
2806{
2807 FIXME();
2808}
2809
2810static USBPortOps xhci_port_ops = {
2811 .attach = xhci_attach,
2812 .detach = xhci_detach,
8c735e43 2813 .wakeup = xhci_wakeup,
62c6ae04
HM		 2814 .complete = xhci_complete,
2815 .child_detach = xhci_child_detach,
2816};
2817
7c605a23
GH		 2818static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev)
2819{
2820 XHCISlot *slot;
2821 int slotid;
2822
2823 for (slotid = 1; slotid <= MAXSLOTS; slotid++) {
2824 slot = &xhci->slots[slotid-1];
2825 if (slot->devaddr == dev->addr) {
2826 return slotid;
2827 }
2828 }
2829 return 0;
2830}
2831
2832static int xhci_find_epid(USBEndpoint *ep)
2833{
2834 if (ep->nr == 0) {
2835 return 1;
2836 }
2837 if (ep->pid == USB_TOKEN_IN) {
2838 return ep->nr * 2 + 1;
2839 } else {
2840 return ep->nr * 2;
2841 }
2842}
2843
2844static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
2845{
2846 XHCIState *xhci = container_of(bus, XHCIState, bus);
2847 int slotid;
2848
2849 DPRINTF("%s\n", __func__);
2850 slotid = xhci_find_slotid(xhci, ep->dev);
2851 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
2852 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
2853 return;
2854 }
2855 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep));
2856}
2857
62c6ae04 2858static USBBusOps xhci_bus_ops = {
7c605a23 2859 .wakeup_endpoint = xhci_wakeup_endpoint,
62c6ae04
HM		 2860};
2861
2862static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2863{
0846e635
GH		 2864 XHCIPort *port;
2865 int i, usbports, speedmask;
62c6ae04
HM		 2866
2867 xhci->usbsts = USBSTS_HCH;
2868
0846e635
GH		 2869 if (xhci->numports_2 > MAXPORTS_2) {
2870 xhci->numports_2 = MAXPORTS_2;
2871 }
2872 if (xhci->numports_3 > MAXPORTS_3) {
2873 xhci->numports_3 = MAXPORTS_3;
2874 }
2875 usbports = MAX(xhci->numports_2, xhci->numports_3);
2876 xhci->numports = xhci->numports_2 + xhci->numports_3;
2877
62c6ae04
HM		 2878 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2879
0846e635
GH		 2880 for (i = 0; i < usbports; i++) {
2881 speedmask = 0;
2882 if (i < xhci->numports_2) {
2883 port = &xhci->ports[i];
2884 port->portnr = i + 1;
2885 port->uport = &xhci->uports[i];
2886 port->speedmask =
2887 USB_SPEED_MASK_LOW |
2888 USB_SPEED_MASK_FULL |
2889 USB_SPEED_MASK_HIGH;
2890 speedmask |= port->speedmask;
2891 }
2892 if (i < xhci->numports_3) {
2893 port = &xhci->ports[i + xhci->numports_2];
2894 port->portnr = i + 1 + xhci->numports_2;
2895 port->uport = &xhci->uports[i];
2896 port->speedmask = USB_SPEED_MASK_SUPER;
2897 speedmask |= port->speedmask;
2898 }
2899 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
2900 &xhci_port_ops, speedmask);
62c6ae04 2901 }
62c6ae04
HM		 2902}
2903
2904static int usb_xhci_initfn(struct PCIDevice *dev)
2905{
2906 int ret;
2907
2908 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2909
2910 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2911 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2912 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2913 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2914
2915 usb_xhci_init(xhci, &dev->qdev);
2916
01546fa6
GH		 2917 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
2918
62c6ae04
HM		 2919 xhci->irq = xhci->pci_dev.irq[0];
2920
2921 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2922 "xhci", LEN_REGS);
2923 pci_register_bar(&xhci->pci_dev, 0,
2924 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2925 &xhci->mem);
2926
2927 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2928 assert(ret >= 0);
2929
c5e9b02d
GH		 2930 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
2931 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false);
62c6ae04 2932 }
4c47f800
GH		 2933 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
2934 msix_init(&xhci->pci_dev, MAXINTRS,
2935 &xhci->mem, 0, OFF_MSIX_TABLE,
2936 &xhci->mem, 0, OFF_MSIX_PBA,
2937 0x90);
2938 }
62c6ae04
HM		 2939
2940 return 0;
2941}
2942
62c6ae04
HM		 2943static const VMStateDescription vmstate_xhci = {
2944 .name = "xhci",
2945 .unmigratable = 1,
2946};
2947
39bffca2 2948static Property xhci_properties[] = {
c5e9b02d 2949 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
4c47f800 2950 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
0846e635
GH		 2951 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
2952 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
39bffca2
AL		 2953 DEFINE_PROP_END_OF_LIST(),
2954};
2955
40021f08
AL		 2956static void xhci_class_init(ObjectClass *klass, void *data)
2957{
2958 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2 2959 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 2960
39bffca2
AL		 2961 dc->vmsd = &vmstate_xhci;
2962 dc->props = xhci_properties;
64619739 2963 dc->reset = xhci_reset;
40021f08
AL		 2964 k->init = usb_xhci_initfn;
2965 k->vendor_id = PCI_VENDOR_ID_NEC;
2966 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2967 k->class_id = PCI_CLASS_SERIAL_USB;
2968 k->revision = 0x03;
2969 k->is_express = 1;
40021f08
AL		 2970}
2971
39bffca2
AL		 2972static TypeInfo xhci_info = {
2973 .name = "nec-usb-xhci",
2974 .parent = TYPE_PCI_DEVICE,
2975 .instance_size = sizeof(XHCIState),
2976 .class_init = xhci_class_init,
62c6ae04
HM		 2977};
2978
83f7d43a 2979static void xhci_register_types(void)
62c6ae04 2980{
39bffca2 2981 type_register_static(&xhci_info);
62c6ae04 2982}
83f7d43a
AF		 2983
2984type_init(xhci_register_types)
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