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xhci: fix & cleanup msi.
[mirror_qemu.git] / hw / usb / hcd-xhci.c
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62c6ae04
HM		 1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
f1ae32a1 21#include "hw/hw.h"
62c6ae04 22#include "qemu-timer.h"
f1ae32a1
GH		 23#include "hw/usb.h"
24#include "hw/pci.h"
f1ae32a1 25#include "hw/msi.h"
2d754a10 26#include "trace.h"
62c6ae04
HM		 27
28//#define DEBUG_XHCI
29//#define DEBUG_DATA
30
31#ifdef DEBUG_XHCI
32#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33#else
34#define DPRINTF(...) do {} while (0)
35#endif
36#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
38
0846e635
GH		 39#define MAXPORTS_2 8
40#define MAXPORTS_3 8
62c6ae04 41
0846e635 42#define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
106b214c
GH		 43#define MAXSLOTS MAXPORTS
44#define MAXINTRS 1 /* MAXPORTS */
62c6ae04
HM		 45
46#define TD_QUEUE 24
62c6ae04
HM		 47
48/* Very pessimistic, let's hope it's enough for all cases */
49#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
50/* Do not deliver ER Full events. NEC's driver does some things not bound
51 * to the specs when it gets them */
52#define ER_FULL_HACK
53
54#define LEN_CAP 0x40
62c6ae04 55#define LEN_OPER (0x400 + 0x10 * MAXPORTS)
106b214c 56#define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
62c6ae04
HM		 57#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
58
106b214c
GH		 59#define OFF_OPER LEN_CAP
60#define OFF_RUNTIME 0x1000
61#define OFF_DOORBELL 0x2000
62c6ae04 62/* must be power of 2 */
106b214c 63#define LEN_REGS 0x4000
62c6ae04 64
106b214c
GH		 65#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
66#error Increase OFF_RUNTIME
67#endif
68#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
69#error Increase OFF_DOORBELL
70#endif
62c6ae04
HM		 71#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
72# error Increase LEN_REGS
73#endif
74
75#if MAXINTRS > 1
76# error TODO: only one interrupter supported
77#endif
78
79/* bit definitions */
80#define USBCMD_RS (1<<0)
81#define USBCMD_HCRST (1<<1)
82#define USBCMD_INTE (1<<2)
83#define USBCMD_HSEE (1<<3)
84#define USBCMD_LHCRST (1<<7)
85#define USBCMD_CSS (1<<8)
86#define USBCMD_CRS (1<<9)
87#define USBCMD_EWE (1<<10)
88#define USBCMD_EU3S (1<<11)
89
90#define USBSTS_HCH (1<<0)
91#define USBSTS_HSE (1<<2)
92#define USBSTS_EINT (1<<3)
93#define USBSTS_PCD (1<<4)
94#define USBSTS_SSS (1<<8)
95#define USBSTS_RSS (1<<9)
96#define USBSTS_SRE (1<<10)
97#define USBSTS_CNR (1<<11)
98#define USBSTS_HCE (1<<12)
99
100
101#define PORTSC_CCS (1<<0)
102#define PORTSC_PED (1<<1)
103#define PORTSC_OCA (1<<3)
104#define PORTSC_PR (1<<4)
105#define PORTSC_PLS_SHIFT 5
106#define PORTSC_PLS_MASK 0xf
107#define PORTSC_PP (1<<9)
108#define PORTSC_SPEED_SHIFT 10
109#define PORTSC_SPEED_MASK 0xf
110#define PORTSC_SPEED_FULL (1<<10)
111#define PORTSC_SPEED_LOW (2<<10)
112#define PORTSC_SPEED_HIGH (3<<10)
113#define PORTSC_SPEED_SUPER (4<<10)
114#define PORTSC_PIC_SHIFT 14
115#define PORTSC_PIC_MASK 0x3
116#define PORTSC_LWS (1<<16)
117#define PORTSC_CSC (1<<17)
118#define PORTSC_PEC (1<<18)
119#define PORTSC_WRC (1<<19)
120#define PORTSC_OCC (1<<20)
121#define PORTSC_PRC (1<<21)
122#define PORTSC_PLC (1<<22)
123#define PORTSC_CEC (1<<23)
124#define PORTSC_CAS (1<<24)
125#define PORTSC_WCE (1<<25)
126#define PORTSC_WDE (1<<26)
127#define PORTSC_WOE (1<<27)
128#define PORTSC_DR (1<<30)
129#define PORTSC_WPR (1<<31)
130
131#define CRCR_RCS (1<<0)
132#define CRCR_CS (1<<1)
133#define CRCR_CA (1<<2)
134#define CRCR_CRR (1<<3)
135
136#define IMAN_IP (1<<0)
137#define IMAN_IE (1<<1)
138
139#define ERDP_EHB (1<<3)
140
141#define TRB_SIZE 16
142typedef struct XHCITRB {
143 uint64_t parameter;
144 uint32_t status;
145 uint32_t control;
59a70ccd 146 dma_addr_t addr;
62c6ae04
HM		 147 bool ccs;
148} XHCITRB;
149
150
151typedef enum TRBType {
152 TRB_RESERVED = 0,
153 TR_NORMAL,
154 TR_SETUP,
155 TR_DATA,
156 TR_STATUS,
157 TR_ISOCH,
158 TR_LINK,
159 TR_EVDATA,
160 TR_NOOP,
161 CR_ENABLE_SLOT,
162 CR_DISABLE_SLOT,
163 CR_ADDRESS_DEVICE,
164 CR_CONFIGURE_ENDPOINT,
165 CR_EVALUATE_CONTEXT,
166 CR_RESET_ENDPOINT,
167 CR_STOP_ENDPOINT,
168 CR_SET_TR_DEQUEUE,
169 CR_RESET_DEVICE,
170 CR_FORCE_EVENT,
171 CR_NEGOTIATE_BW,
172 CR_SET_LATENCY_TOLERANCE,
173 CR_GET_PORT_BANDWIDTH,
174 CR_FORCE_HEADER,
175 CR_NOOP,
176 ER_TRANSFER = 32,
177 ER_COMMAND_COMPLETE,
178 ER_PORT_STATUS_CHANGE,
179 ER_BANDWIDTH_REQUEST,
180 ER_DOORBELL,
181 ER_HOST_CONTROLLER,
182 ER_DEVICE_NOTIFICATION,
183 ER_MFINDEX_WRAP,
184 /* vendor specific bits */
185 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
186 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
187 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
188} TRBType;
189
190#define CR_LINK TR_LINK
191
192typedef enum TRBCCode {
193 CC_INVALID = 0,
194 CC_SUCCESS,
195 CC_DATA_BUFFER_ERROR,
196 CC_BABBLE_DETECTED,
197 CC_USB_TRANSACTION_ERROR,
198 CC_TRB_ERROR,
199 CC_STALL_ERROR,
200 CC_RESOURCE_ERROR,
201 CC_BANDWIDTH_ERROR,
202 CC_NO_SLOTS_ERROR,
203 CC_INVALID_STREAM_TYPE_ERROR,
204 CC_SLOT_NOT_ENABLED_ERROR,
205 CC_EP_NOT_ENABLED_ERROR,
206 CC_SHORT_PACKET,
207 CC_RING_UNDERRUN,
208 CC_RING_OVERRUN,
209 CC_VF_ER_FULL,
210 CC_PARAMETER_ERROR,
211 CC_BANDWIDTH_OVERRUN,
212 CC_CONTEXT_STATE_ERROR,
213 CC_NO_PING_RESPONSE_ERROR,
214 CC_EVENT_RING_FULL_ERROR,
215 CC_INCOMPATIBLE_DEVICE_ERROR,
216 CC_MISSED_SERVICE_ERROR,
217 CC_COMMAND_RING_STOPPED,
218 CC_COMMAND_ABORTED,
219 CC_STOPPED,
220 CC_STOPPED_LENGTH_INVALID,
221 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
222 CC_ISOCH_BUFFER_OVERRUN = 31,
223 CC_EVENT_LOST_ERROR,
224 CC_UNDEFINED_ERROR,
225 CC_INVALID_STREAM_ID_ERROR,
226 CC_SECONDARY_BANDWIDTH_ERROR,
227 CC_SPLIT_TRANSACTION_ERROR
228} TRBCCode;
229
230#define TRB_C (1<<0)
231#define TRB_TYPE_SHIFT 10
232#define TRB_TYPE_MASK 0x3f
233#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
234
235#define TRB_EV_ED (1<<2)
236
237#define TRB_TR_ENT (1<<1)
238#define TRB_TR_ISP (1<<2)
239#define TRB_TR_NS (1<<3)
240#define TRB_TR_CH (1<<4)
241#define TRB_TR_IOC (1<<5)
242#define TRB_TR_IDT (1<<6)
243#define TRB_TR_TBC_SHIFT 7
244#define TRB_TR_TBC_MASK 0x3
245#define TRB_TR_BEI (1<<9)
246#define TRB_TR_TLBPC_SHIFT 16
247#define TRB_TR_TLBPC_MASK 0xf
248#define TRB_TR_FRAMEID_SHIFT 20
249#define TRB_TR_FRAMEID_MASK 0x7ff
250#define TRB_TR_SIA (1<<31)
251
252#define TRB_TR_DIR (1<<16)
253
254#define TRB_CR_SLOTID_SHIFT 24
255#define TRB_CR_SLOTID_MASK 0xff
256#define TRB_CR_EPID_SHIFT 16
257#define TRB_CR_EPID_MASK 0x1f
258
259#define TRB_CR_BSR (1<<9)
260#define TRB_CR_DC (1<<9)
261
262#define TRB_LK_TC (1<<1)
263
264#define EP_TYPE_MASK 0x7
265#define EP_TYPE_SHIFT 3
266
267#define EP_STATE_MASK 0x7
268#define EP_DISABLED (0<<0)
269#define EP_RUNNING (1<<0)
270#define EP_HALTED (2<<0)
271#define EP_STOPPED (3<<0)
272#define EP_ERROR (4<<0)
273
274#define SLOT_STATE_MASK 0x1f
275#define SLOT_STATE_SHIFT 27
276#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
277#define SLOT_ENABLED 0
278#define SLOT_DEFAULT 1
279#define SLOT_ADDRESSED 2
280#define SLOT_CONFIGURED 3
281
282#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
283#define SLOT_CONTEXT_ENTRIES_SHIFT 27
284
285typedef enum EPType {
286 ET_INVALID = 0,
287 ET_ISO_OUT,
288 ET_BULK_OUT,
289 ET_INTR_OUT,
290 ET_CONTROL,
291 ET_ISO_IN,
292 ET_BULK_IN,
293 ET_INTR_IN,
294} EPType;
295
296typedef struct XHCIRing {
59a70ccd
DG		 297 dma_addr_t base;
298 dma_addr_t dequeue;
62c6ae04
HM		 299 bool ccs;
300} XHCIRing;
301
302typedef struct XHCIPort {
62c6ae04 303 uint32_t portsc;
0846e635
GH		 304 uint32_t portnr;
305 USBPort *uport;
306 uint32_t speedmask;
62c6ae04
HM		 307} XHCIPort;
308
309struct XHCIState;
310typedef struct XHCIState XHCIState;
311
312typedef struct XHCITransfer {
313 XHCIState *xhci;
314 USBPacket packet;
d5a15814 315 QEMUSGList sgl;
7c605a23
GH		 316 bool running_async;
317 bool running_retry;
62c6ae04
HM		 318 bool cancelled;
319 bool complete;
62c6ae04
HM		 320 unsigned int iso_pkts;
321 unsigned int slotid;
322 unsigned int epid;
323 bool in_xfer;
324 bool iso_xfer;
62c6ae04
HM		 325
326 unsigned int trb_count;
327 unsigned int trb_alloced;
328 XHCITRB *trbs;
329
62c6ae04
HM		 330 TRBCCode status;
331
332 unsigned int pkts;
333 unsigned int pktsize;
334 unsigned int cur_pkt;
3d139684
GH		 335
336 uint64_t mfindex_kick;
62c6ae04
HM		 337} XHCITransfer;
338
339typedef struct XHCIEPContext {
3d139684
GH		 340 XHCIState *xhci;
341 unsigned int slotid;
342 unsigned int epid;
343
62c6ae04
HM		 344 XHCIRing ring;
345 unsigned int next_xfer;
346 unsigned int comp_xfer;
347 XHCITransfer transfers[TD_QUEUE];
7c605a23 348 XHCITransfer *retry;
62c6ae04 349 EPType type;
59a70ccd 350 dma_addr_t pctx;
62c6ae04 351 unsigned int max_psize;
62c6ae04 352 uint32_t state;
3d139684
GH		 353
354 /* iso xfer scheduling */
355 unsigned int interval;
356 int64_t mfindex_last;
357 QEMUTimer *kick_timer;
62c6ae04
HM		 358} XHCIEPContext;
359
360typedef struct XHCISlot {
361 bool enabled;
59a70ccd 362 dma_addr_t ctx;
62c6ae04
HM		 363 unsigned int port;
364 unsigned int devaddr;
365 XHCIEPContext * eps[31];
366} XHCISlot;
367
368typedef struct XHCIEvent {
369 TRBType type;
370 TRBCCode ccode;
371 uint64_t ptr;
372 uint32_t length;
373 uint32_t flags;
374 uint8_t slotid;
375 uint8_t epid;
376} XHCIEvent;
377
378struct XHCIState {
379 PCIDevice pci_dev;
380 USBBus bus;
381 qemu_irq irq;
382 MemoryRegion mem;
383 const char *name;
62c6ae04
HM		 384 unsigned int devaddr;
385
0846e635
GH		 386 /* properties */
387 uint32_t numports_2;
388 uint32_t numports_3;
c5e9b02d 389 uint32_t flags;
0846e635 390
62c6ae04
HM		 391 /* Operational Registers */
392 uint32_t usbcmd;
393 uint32_t usbsts;
394 uint32_t dnctrl;
395 uint32_t crcr_low;
396 uint32_t crcr_high;
397 uint32_t dcbaap_low;
398 uint32_t dcbaap_high;
399 uint32_t config;
400
0846e635 401 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
62c6ae04
HM		 402 XHCIPort ports[MAXPORTS];
403 XHCISlot slots[MAXSLOTS];
0846e635 404 uint32_t numports;
62c6ae04
HM		 405
406 /* Runtime Registers */
62c6ae04
HM		 407 uint32_t iman;
408 uint32_t imod;
409 uint32_t erstsz;
410 uint32_t erstba_low;
411 uint32_t erstba_high;
412 uint32_t erdp_low;
413 uint32_t erdp_high;
414
01546fa6
GH		 415 int64_t mfindex_start;
416 QEMUTimer *mfwrap_timer;
417
59a70ccd 418 dma_addr_t er_start;
62c6ae04
HM		 419 uint32_t er_size;
420 bool er_pcs;
421 unsigned int er_ep_idx;
422 bool er_full;
423
424 XHCIEvent ev_buffer[EV_QUEUE];
425 unsigned int ev_buffer_put;
426 unsigned int ev_buffer_get;
427
428 XHCIRing cmd_ring;
429};
430
431typedef struct XHCIEvRingSeg {
432 uint32_t addr_low;
433 uint32_t addr_high;
434 uint32_t size;
435 uint32_t rsvd;
436} XHCIEvRingSeg;
437
c5e9b02d
GH		 438enum xhci_flags {
439 XHCI_FLAG_USE_MSI = 1,
440};
441
01546fa6
GH		 442static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
443 unsigned int epid);
444static void xhci_event(XHCIState *xhci, XHCIEvent *event);
445static void xhci_write_event(XHCIState *xhci, XHCIEvent *event);
446
f10de44e
GH		 447static const char *TRBType_names[] = {
448 [TRB_RESERVED] = "TRB_RESERVED",
449 [TR_NORMAL] = "TR_NORMAL",
450 [TR_SETUP] = "TR_SETUP",
451 [TR_DATA] = "TR_DATA",
452 [TR_STATUS] = "TR_STATUS",
453 [TR_ISOCH] = "TR_ISOCH",
454 [TR_LINK] = "TR_LINK",
455 [TR_EVDATA] = "TR_EVDATA",
456 [TR_NOOP] = "TR_NOOP",
457 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
458 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
459 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
460 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
461 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
462 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
463 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
464 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
465 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
466 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
467 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
468 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
469 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
470 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
471 [CR_NOOP] = "CR_NOOP",
472 [ER_TRANSFER] = "ER_TRANSFER",
473 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
474 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
475 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
476 [ER_DOORBELL] = "ER_DOORBELL",
477 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
478 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
479 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
480 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
481 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
482 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
483};
484
873123fe
GH		 485static const char *TRBCCode_names[] = {
486 [CC_INVALID] = "CC_INVALID",
487 [CC_SUCCESS] = "CC_SUCCESS",
488 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
489 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
490 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
491 [CC_TRB_ERROR] = "CC_TRB_ERROR",
492 [CC_STALL_ERROR] = "CC_STALL_ERROR",
493 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
494 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
495 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
496 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
497 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
498 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
499 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
500 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
501 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
502 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
503 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
504 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
505 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
506 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
507 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
508 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
509 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
510 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
511 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
512 [CC_STOPPED] = "CC_STOPPED",
513 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
514 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
515 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
516 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
517 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
518 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
519 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
520 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
521 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
522};
523
f10de44e
GH		 524static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
525{
526 if (index >= llen || list[index] == NULL) {
527 return "???";
528 }
529 return list[index];
530}
531
532static const char *trb_name(XHCITRB *trb)
533{
534 return lookup_name(TRB_TYPE(*trb), TRBType_names,
535 ARRAY_SIZE(TRBType_names));
536}
f10de44e 537
873123fe
GH		 538static const char *event_name(XHCIEvent *event)
539{
540 return lookup_name(event->ccode, TRBCCode_names,
541 ARRAY_SIZE(TRBCCode_names));
542}
543
01546fa6
GH		 544static uint64_t xhci_mfindex_get(XHCIState *xhci)
545{
546 int64_t now = qemu_get_clock_ns(vm_clock);
547 return (now - xhci->mfindex_start) / 125000;
548}
549
550static void xhci_mfwrap_update(XHCIState *xhci)
551{
552 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
553 uint32_t mfindex, left;
554 int64_t now;
555
556 if ((xhci->usbcmd & bits) == bits) {
557 now = qemu_get_clock_ns(vm_clock);
558 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
559 left = 0x4000 - mfindex;
560 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
561 } else {
562 qemu_del_timer(xhci->mfwrap_timer);
563 }
564}
565
566static void xhci_mfwrap_timer(void *opaque)
567{
568 XHCIState *xhci = opaque;
569 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
570
571 xhci_event(xhci, &wrap);
572 xhci_mfwrap_update(xhci);
573}
62c6ae04 574
59a70ccd 575static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
62c6ae04 576{
59a70ccd
DG		 577 if (sizeof(dma_addr_t) == 4) {
578 return low;
579 } else {
580 return low | (((dma_addr_t)high << 16) << 16);
581 }
62c6ae04
HM		 582}
583
59a70ccd 584static inline dma_addr_t xhci_mask64(uint64_t addr)
62c6ae04 585{
59a70ccd
DG		 586 if (sizeof(dma_addr_t) == 4) {
587 return addr & 0xffffffff;
588 } else {
589 return addr;
590 }
62c6ae04
HM		 591}
592
0846e635
GH		 593static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
594{
595 int index;
596
597 if (!uport->dev) {
598 return NULL;
599 }
600 switch (uport->dev->speed) {
601 case USB_SPEED_LOW:
602 case USB_SPEED_FULL:
603 case USB_SPEED_HIGH:
604 index = uport->index;
605 break;
606 case USB_SPEED_SUPER:
607 index = uport->index + xhci->numports_2;
608 break;
609 default:
610 return NULL;
611 }
612 return &xhci->ports[index];
613}
614
62c6ae04
HM		 615static void xhci_irq_update(XHCIState *xhci)
616{
617 int level = 0;
618
619 if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
215bff17 620 xhci->usbcmd & USBCMD_INTE) {
62c6ae04
HM		 621 level = 1;
622 }
623
c5e9b02d 624 if (msi_enabled(&xhci->pci_dev)) {
62c6ae04 625 if (level) {
7acd279f 626 trace_usb_xhci_irq_msi(0);
62c6ae04
HM		 627 msi_notify(&xhci->pci_dev, 0);
628 }
629 } else {
7acd279f 630 trace_usb_xhci_irq_intx(level);
62c6ae04
HM		 631 qemu_set_irq(xhci->irq, level);
632 }
633}
634
635static inline int xhci_running(XHCIState *xhci)
636{
637 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
638}
639
640static void xhci_die(XHCIState *xhci)
641{
642 xhci->usbsts |= USBSTS_HCE;
643 fprintf(stderr, "xhci: asserted controller error\n");
644}
645
646static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
647{
648 XHCITRB ev_trb;
59a70ccd 649 dma_addr_t addr;
62c6ae04
HM		 650
651 ev_trb.parameter = cpu_to_le64(event->ptr);
652 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
653 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
654 event->flags | (event->type << TRB_TYPE_SHIFT);
655 if (xhci->er_pcs) {
656 ev_trb.control |= TRB_C;
657 }
658 ev_trb.control = cpu_to_le32(ev_trb.control);
659
7acd279f 660 trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb),
873123fe
GH		 661 event_name(event), ev_trb.parameter,
662 ev_trb.status, ev_trb.control);
62c6ae04
HM		 663
664 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx;
59a70ccd 665 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
62c6ae04
HM		 666
667 xhci->er_ep_idx++;
668 if (xhci->er_ep_idx >= xhci->er_size) {
669 xhci->er_ep_idx = 0;
670 xhci->er_pcs = !xhci->er_pcs;
671 }
672}
673
674static void xhci_events_update(XHCIState *xhci)
675{
59a70ccd 676 dma_addr_t erdp;
62c6ae04
HM		 677 unsigned int dp_idx;
678 bool do_irq = 0;
679
680 if (xhci->usbsts & USBSTS_HCH) {
681 return;
682 }
683
684 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
685 if (erdp < xhci->er_start ||
686 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
59a70ccd
DG		 687 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
688 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
62c6ae04
HM		 689 xhci->er_start, xhci->er_size);
690 xhci_die(xhci);
691 return;
692 }
693 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
694 assert(dp_idx < xhci->er_size);
695
696 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
697 * deadlocks when the ER is full. Hack it by holding off events until
698 * the driver decides to free at least half of the ring */
699 if (xhci->er_full) {
700 int er_free = dp_idx - xhci->er_ep_idx;
701 if (er_free <= 0) {
702 er_free += xhci->er_size;
703 }
704 if (er_free < (xhci->er_size/2)) {
705 DPRINTF("xhci_events_update(): event ring still "
706 "more than half full (hack)\n");
707 return;
708 }
709 }
710
711 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
712 assert(xhci->er_full);
713 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
714 DPRINTF("xhci_events_update(): event ring full again\n");
715#ifndef ER_FULL_HACK
716 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
717 xhci_write_event(xhci, &full);
718#endif
719 do_irq = 1;
720 break;
721 }
722 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
723 xhci_write_event(xhci, event);
724 xhci->ev_buffer_get++;
725 do_irq = 1;
726 if (xhci->ev_buffer_get == EV_QUEUE) {
727 xhci->ev_buffer_get = 0;
728 }
729 }
730
731 if (do_irq) {
732 xhci->erdp_low |= ERDP_EHB;
733 xhci->iman |= IMAN_IP;
734 xhci->usbsts |= USBSTS_EINT;
735 xhci_irq_update(xhci);
736 }
737
738 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
739 DPRINTF("xhci_events_update(): event ring no longer full\n");
740 xhci->er_full = 0;
741 }
742 return;
743}
744
745static void xhci_event(XHCIState *xhci, XHCIEvent *event)
746{
59a70ccd 747 dma_addr_t erdp;
62c6ae04
HM		 748 unsigned int dp_idx;
749
750 if (xhci->er_full) {
751 DPRINTF("xhci_event(): ER full, queueing\n");
752 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
753 fprintf(stderr, "xhci: event queue full, dropping event!\n");
754 return;
755 }
756 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
757 if (xhci->ev_buffer_put == EV_QUEUE) {
758 xhci->ev_buffer_put = 0;
759 }
760 return;
761 }
762
763 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
764 if (erdp < xhci->er_start ||
765 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
59a70ccd
DG		 766 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
767 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
62c6ae04
HM		 768 xhci->er_start, xhci->er_size);
769 xhci_die(xhci);
770 return;
771 }
772
773 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
774 assert(dp_idx < xhci->er_size);
775
776 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
777 DPRINTF("xhci_event(): ER full, queueing\n");
778#ifndef ER_FULL_HACK
779 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
780 xhci_write_event(xhci, &full);
781#endif
782 xhci->er_full = 1;
783 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
784 fprintf(stderr, "xhci: event queue full, dropping event!\n");
785 return;
786 }
787 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
788 if (xhci->ev_buffer_put == EV_QUEUE) {
789 xhci->ev_buffer_put = 0;
790 }
791 } else {
792 xhci_write_event(xhci, event);
793 }
794
795 xhci->erdp_low |= ERDP_EHB;
796 xhci->iman |= IMAN_IP;
797 xhci->usbsts |= USBSTS_EINT;
798
799 xhci_irq_update(xhci);
800}
801
802static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
59a70ccd 803 dma_addr_t base)
62c6ae04
HM		 804{
805 ring->base = base;
806 ring->dequeue = base;
807 ring->ccs = 1;
808}
809
810static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
59a70ccd 811 dma_addr_t *addr)
62c6ae04
HM		 812{
813 while (1) {
814 TRBType type;
59a70ccd 815 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
62c6ae04
HM		 816 trb->addr = ring->dequeue;
817 trb->ccs = ring->ccs;
818 le64_to_cpus(&trb->parameter);
819 le32_to_cpus(&trb->status);
820 le32_to_cpus(&trb->control);
821
0703a4a7
GH		 822 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
823 trb->parameter, trb->status, trb->control);
62c6ae04
HM		 824
825 if ((trb->control & TRB_C) != ring->ccs) {
826 return 0;
827 }
828
829 type = TRB_TYPE(*trb);
830
831 if (type != TR_LINK) {
832 if (addr) {
833 *addr = ring->dequeue;
834 }
835 ring->dequeue += TRB_SIZE;
836 return type;
837 } else {
838 ring->dequeue = xhci_mask64(trb->parameter);
839 if (trb->control & TRB_LK_TC) {
840 ring->ccs = !ring->ccs;
841 }
842 }
843 }
844}
845
846static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
847{
848 XHCITRB trb;
849 int length = 0;
59a70ccd 850 dma_addr_t dequeue = ring->dequeue;
62c6ae04
HM		 851 bool ccs = ring->ccs;
852 /* hack to bundle together the two/three TDs that make a setup transfer */
853 bool control_td_set = 0;
854
855 while (1) {
856 TRBType type;
59a70ccd 857 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
62c6ae04
HM		 858 le64_to_cpus(&trb.parameter);
859 le32_to_cpus(&trb.status);
860 le32_to_cpus(&trb.control);
861
62c6ae04
HM		 862 if ((trb.control & TRB_C) != ccs) {
863 return -length;
864 }
865
866 type = TRB_TYPE(trb);
867
868 if (type == TR_LINK) {
869 dequeue = xhci_mask64(trb.parameter);
870 if (trb.control & TRB_LK_TC) {
871 ccs = !ccs;
872 }
873 continue;
874 }
875
876 length += 1;
877 dequeue += TRB_SIZE;
878
879 if (type == TR_SETUP) {
880 control_td_set = 1;
881 } else if (type == TR_STATUS) {
882 control_td_set = 0;
883 }
884
885 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
886 return length;
887 }
888 }
889}
890
891static void xhci_er_reset(XHCIState *xhci)
892{
893 XHCIEvRingSeg seg;
894
895 /* cache the (sole) event ring segment location */
896 if (xhci->erstsz != 1) {
897 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
898 xhci_die(xhci);
899 return;
900 }
59a70ccd
DG		 901 dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
902 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
62c6ae04
HM		 903 le32_to_cpus(&seg.addr_low);
904 le32_to_cpus(&seg.addr_high);
905 le32_to_cpus(&seg.size);
906 if (seg.size < 16 || seg.size > 4096) {
907 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
908 xhci_die(xhci);
909 return;
910 }
911 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
912 xhci->er_size = seg.size;
913
914 xhci->er_ep_idx = 0;
915 xhci->er_pcs = 1;
916 xhci->er_full = 0;
917
59a70ccd 918 DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n",
62c6ae04
HM		 919 xhci->er_start, xhci->er_size);
920}
921
922static void xhci_run(XHCIState *xhci)
923{
fc0ddaca 924 trace_usb_xhci_run();
62c6ae04 925 xhci->usbsts &= ~USBSTS_HCH;
01546fa6 926 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
62c6ae04
HM		 927}
928
929static void xhci_stop(XHCIState *xhci)
930{
fc0ddaca 931 trace_usb_xhci_stop();
62c6ae04
HM		 932 xhci->usbsts |= USBSTS_HCH;
933 xhci->crcr_low &= ~CRCR_CRR;
934}
935
936static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
937 uint32_t state)
938{
939 uint32_t ctx[5];
940 if (epctx->state == state) {
941 return;
942 }
943
59a70ccd 944 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
62c6ae04
HM		 945 ctx[0] &= ~EP_STATE_MASK;
946 ctx[0] |= state;
947 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
948 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
59a70ccd 949 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
62c6ae04 950 epctx->pctx, state, ctx[3], ctx[2]);
59a70ccd 951 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
62c6ae04
HM		 952 epctx->state = state;
953}
954
3d139684
GH		 955static void xhci_ep_kick_timer(void *opaque)
956{
957 XHCIEPContext *epctx = opaque;
958 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid);
959}
960
62c6ae04 961static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
59a70ccd 962 unsigned int epid, dma_addr_t pctx,
62c6ae04
HM		 963 uint32_t *ctx)
964{
965 XHCISlot *slot;
966 XHCIEPContext *epctx;
59a70ccd 967 dma_addr_t dequeue;
62c6ae04
HM		 968 int i;
969
c1f6b493 970 trace_usb_xhci_ep_enable(slotid, epid);
62c6ae04
HM		 971 assert(slotid >= 1 && slotid <= MAXSLOTS);
972 assert(epid >= 1 && epid <= 31);
973
62c6ae04
HM		 974 slot = &xhci->slots[slotid-1];
975 if (slot->eps[epid-1]) {
976 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
977 return CC_TRB_ERROR;
978 }
979
980 epctx = g_malloc(sizeof(XHCIEPContext));
981 memset(epctx, 0, sizeof(XHCIEPContext));
3d139684
GH		 982 epctx->xhci = xhci;
983 epctx->slotid = slotid;
984 epctx->epid = epid;
62c6ae04
HM		 985
986 slot->eps[epid-1] = epctx;
987
988 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
989 xhci_ring_init(xhci, &epctx->ring, dequeue);
990 epctx->ring.ccs = ctx[2] & 1;
991
992 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
993 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
994 epctx->pctx = pctx;
995 epctx->max_psize = ctx[1]>>16;
996 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
62c6ae04
HM		 997 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
998 epid/2, epid%2, epctx->max_psize);
999 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1000 usb_packet_init(&epctx->transfers[i].packet);
1001 }
1002
3d139684
GH		 1003 epctx->interval = 1 << (ctx[0] >> 16) & 0xff;
1004 epctx->mfindex_last = 0;
1005 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx);
1006
62c6ae04
HM		 1007 epctx->state = EP_RUNNING;
1008 ctx[0] &= ~EP_STATE_MASK;
1009 ctx[0] |= EP_RUNNING;
1010
1011 return CC_SUCCESS;
1012}
1013
1014static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1015 unsigned int epid)
1016{
1017 XHCISlot *slot;
1018 XHCIEPContext *epctx;
1019 int i, xferi, killed = 0;
1020 assert(slotid >= 1 && slotid <= MAXSLOTS);
1021 assert(epid >= 1 && epid <= 31);
1022
1023 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1024
1025 slot = &xhci->slots[slotid-1];
1026
1027 if (!slot->eps[epid-1]) {
1028 return 0;
1029 }
1030
1031 epctx = slot->eps[epid-1];
1032
1033 xferi = epctx->next_xfer;
1034 for (i = 0; i < TD_QUEUE; i++) {
1035 XHCITransfer *t = &epctx->transfers[xferi];
7c605a23
GH		 1036 if (t->running_async) {
1037 usb_cancel_packet(&t->packet);
1038 t->running_async = 0;
62c6ae04 1039 t->cancelled = 1;
62c6ae04
HM		 1040 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
1041 killed++;
1042 }
7c605a23
GH		 1043 if (t->running_retry) {
1044 t->running_retry = 0;
1045 epctx->retry = NULL;
3d139684 1046 qemu_del_timer(epctx->kick_timer);
7c605a23 1047 }
62c6ae04
HM		 1048 if (t->trbs) {
1049 g_free(t->trbs);
1050 }
62c6ae04
HM		 1051
1052 t->trbs = NULL;
62c6ae04 1053 t->trb_count = t->trb_alloced = 0;
62c6ae04
HM		 1054 xferi = (xferi + 1) % TD_QUEUE;
1055 }
62c6ae04
HM		 1056 return killed;
1057}
1058
1059static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1060 unsigned int epid)
1061{
1062 XHCISlot *slot;
1063 XHCIEPContext *epctx;
1064
c1f6b493 1065 trace_usb_xhci_ep_disable(slotid, epid);
62c6ae04
HM		 1066 assert(slotid >= 1 && slotid <= MAXSLOTS);
1067 assert(epid >= 1 && epid <= 31);
1068
62c6ae04
HM		 1069 slot = &xhci->slots[slotid-1];
1070
1071 if (!slot->eps[epid-1]) {
1072 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1073 return CC_SUCCESS;
1074 }
1075
1076 xhci_ep_nuke_xfers(xhci, slotid, epid);
1077
1078 epctx = slot->eps[epid-1];
1079
1080 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
1081
3d139684 1082 qemu_free_timer(epctx->kick_timer);
62c6ae04
HM		 1083 g_free(epctx);
1084 slot->eps[epid-1] = NULL;
1085
1086 return CC_SUCCESS;
1087}
1088
1089static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1090 unsigned int epid)
1091{
1092 XHCISlot *slot;
1093 XHCIEPContext *epctx;
1094
c1f6b493 1095 trace_usb_xhci_ep_stop(slotid, epid);
62c6ae04
HM		 1096 assert(slotid >= 1 && slotid <= MAXSLOTS);
1097
1098 if (epid < 1 || epid > 31) {
1099 fprintf(stderr, "xhci: bad ep %d\n", epid);
1100 return CC_TRB_ERROR;
1101 }
1102
1103 slot = &xhci->slots[slotid-1];
1104
1105 if (!slot->eps[epid-1]) {
1106 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1107 return CC_EP_NOT_ENABLED_ERROR;
1108 }
1109
1110 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1111 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1112 "data might be lost\n");
1113 }
1114
1115 epctx = slot->eps[epid-1];
1116
1117 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1118
1119 return CC_SUCCESS;
1120}
1121
1122static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1123 unsigned int epid)
1124{
1125 XHCISlot *slot;
1126 XHCIEPContext *epctx;
1127 USBDevice *dev;
1128
c1f6b493 1129 trace_usb_xhci_ep_reset(slotid, epid);
62c6ae04
HM		 1130 assert(slotid >= 1 && slotid <= MAXSLOTS);
1131
62c6ae04
HM		 1132 if (epid < 1 || epid > 31) {
1133 fprintf(stderr, "xhci: bad ep %d\n", epid);
1134 return CC_TRB_ERROR;
1135 }
1136
1137 slot = &xhci->slots[slotid-1];
1138
1139 if (!slot->eps[epid-1]) {
1140 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1141 return CC_EP_NOT_ENABLED_ERROR;
1142 }
1143
1144 epctx = slot->eps[epid-1];
1145
1146 if (epctx->state != EP_HALTED) {
1147 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1148 epid, epctx->state);
1149 return CC_CONTEXT_STATE_ERROR;
1150 }
1151
1152 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1153 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1154 "data might be lost\n");
1155 }
1156
1157 uint8_t ep = epid>>1;
1158
1159 if (epid & 1) {
1160 ep |= 0x80;
1161 }
1162
0846e635 1163 dev = xhci->ports[xhci->slots[slotid-1].port-1].uport->dev;
62c6ae04
HM		 1164 if (!dev) {
1165 return CC_USB_TRANSACTION_ERROR;
1166 }
1167
1168 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1169
1170 return CC_SUCCESS;
1171}
1172
1173static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1174 unsigned int epid, uint64_t pdequeue)
1175{
1176 XHCISlot *slot;
1177 XHCIEPContext *epctx;
59a70ccd 1178 dma_addr_t dequeue;
62c6ae04
HM		 1179
1180 assert(slotid >= 1 && slotid <= MAXSLOTS);
1181
1182 if (epid < 1 || epid > 31) {
1183 fprintf(stderr, "xhci: bad ep %d\n", epid);
1184 return CC_TRB_ERROR;
1185 }
1186
d829fde9 1187 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue);
62c6ae04
HM		 1188 dequeue = xhci_mask64(pdequeue);
1189
1190 slot = &xhci->slots[slotid-1];
1191
1192 if (!slot->eps[epid-1]) {
1193 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1194 return CC_EP_NOT_ENABLED_ERROR;
1195 }
1196
1197 epctx = slot->eps[epid-1];
1198
1199
1200 if (epctx->state != EP_STOPPED) {
1201 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1202 return CC_CONTEXT_STATE_ERROR;
1203 }
1204
1205 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1206 epctx->ring.ccs = dequeue & 1;
1207
1208 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1209
1210 return CC_SUCCESS;
1211}
1212
d5a15814 1213static int xhci_xfer_map(XHCITransfer *xfer)
62c6ae04 1214{
d5a15814 1215 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN);
62c6ae04 1216 XHCIState *xhci = xfer->xhci;
d5a15814 1217 int i;
62c6ae04 1218
d5a15814 1219 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
62c6ae04
HM		 1220 for (i = 0; i < xfer->trb_count; i++) {
1221 XHCITRB *trb = &xfer->trbs[i];
59a70ccd 1222 dma_addr_t addr;
62c6ae04
HM		 1223 unsigned int chunk = 0;
1224
1225 switch (TRB_TYPE(*trb)) {
1226 case TR_DATA:
1227 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1228 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
d5a15814 1229 goto err;
62c6ae04
HM		 1230 }
1231 /* fallthrough */
1232 case TR_NORMAL:
1233 case TR_ISOCH:
1234 addr = xhci_mask64(trb->parameter);
d5a15814
GH		 1235 chunk = trb->status & 0x1ffff;
1236 if (trb->control & TRB_TR_IDT) {
1237 if (chunk > 8 || in_xfer) {
1238 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1239 goto err;
1240 }
1241 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1242 } else {
1243 qemu_sglist_add(&xfer->sgl, addr, chunk);
1244 }
1245 break;
1246 }
1247 }
1248
1249 usb_packet_map(&xfer->packet, &xfer->sgl);
1250 return 0;
1251
1252err:
1253 qemu_sglist_destroy(&xfer->sgl);
1254 xhci_die(xhci);
1255 return -1;
1256}
1257
1258static void xhci_xfer_unmap(XHCITransfer *xfer)
1259{
1260 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1261 qemu_sglist_destroy(&xfer->sgl);
1262}
1263
1264static void xhci_xfer_report(XHCITransfer *xfer)
1265{
1266 uint32_t edtla = 0;
1267 unsigned int left;
1268 bool reported = 0;
1269 bool shortpkt = 0;
1270 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1271 XHCIState *xhci = xfer->xhci;
1272 int i;
1273
1274 left = xfer->packet.result < 0 ? 0 : xfer->packet.result;
1275
1276 for (i = 0; i < xfer->trb_count; i++) {
1277 XHCITRB *trb = &xfer->trbs[i];
1278 unsigned int chunk = 0;
1279
1280 switch (TRB_TYPE(*trb)) {
1281 case TR_DATA:
1282 case TR_NORMAL:
1283 case TR_ISOCH:
62c6ae04
HM		 1284 chunk = trb->status & 0x1ffff;
1285 if (chunk > left) {
1286 chunk = left;
d5a15814
GH		 1287 if (xfer->status == CC_SUCCESS) {
1288 shortpkt = 1;
62c6ae04
HM		 1289 }
1290 }
1291 left -= chunk;
62c6ae04 1292 edtla += chunk;
62c6ae04
HM		 1293 break;
1294 case TR_STATUS:
1295 reported = 0;
1296 shortpkt = 0;
1297 break;
1298 }
1299
d5a15814
GH		 1300 if (!reported && ((trb->control & TRB_TR_IOC) ||
1301 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1302 (xfer->status != CC_SUCCESS))) {
62c6ae04
HM		 1303 event.slotid = xfer->slotid;
1304 event.epid = xfer->epid;
1305 event.length = (trb->status & 0x1ffff) - chunk;
1306 event.flags = 0;
1307 event.ptr = trb->addr;
1308 if (xfer->status == CC_SUCCESS) {
1309 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1310 } else {
1311 event.ccode = xfer->status;
1312 }
1313 if (TRB_TYPE(*trb) == TR_EVDATA) {
1314 event.ptr = trb->parameter;
1315 event.flags |= TRB_EV_ED;
1316 event.length = edtla & 0xffffff;
1317 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1318 edtla = 0;
1319 }
1320 xhci_event(xhci, &event);
1321 reported = 1;
d5a15814
GH		 1322 if (xfer->status != CC_SUCCESS) {
1323 return;
1324 }
62c6ae04
HM		 1325 }
1326 }
62c6ae04
HM		 1327}
1328
1329static void xhci_stall_ep(XHCITransfer *xfer)
1330{
1331 XHCIState *xhci = xfer->xhci;
1332 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1333 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1334
1335 epctx->ring.dequeue = xfer->trbs[0].addr;
1336 epctx->ring.ccs = xfer->trbs[0].ccs;
1337 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1338 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
59a70ccd 1339 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue);
62c6ae04
HM		 1340}
1341
1342static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1343 XHCIEPContext *epctx);
1344
5c08106f 1345static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
62c6ae04 1346{
5c08106f
GH		 1347 if (!(port->portsc & PORTSC_PED)) {
1348 return NULL;
1349 }
0846e635 1350 return usb_find_device(port->uport, addr);
5c08106f
GH		 1351}
1352
1353static int xhci_setup_packet(XHCITransfer *xfer)
1354{
1355 XHCIState *xhci = xfer->xhci;
1356 XHCIPort *port;
1357 USBDevice *dev;
079d0b7f
GH		 1358 USBEndpoint *ep;
1359 int dir;
1360
1361 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
5c08106f
GH		 1362
1363 if (xfer->packet.ep) {
1364 ep = xfer->packet.ep;
1365 dev = ep->dev;
1366 } else {
1367 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1368 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1369 if (!dev) {
1370 fprintf(stderr, "xhci: slot %d port %d has no device\n",
1371 xfer->slotid, xhci->slots[xfer->slotid-1].port);
1372 return -1;
1373 }
1374 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1375 }
1376
e983395d 1377 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr);
d5a15814 1378 xhci_xfer_map(xfer);
62c6ae04 1379 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
079d0b7f 1380 xfer->packet.pid, dev->addr, ep->nr);
62c6ae04
HM		 1381 return 0;
1382}
1383
1384static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1385{
1386 if (ret == USB_RET_ASYNC) {
97df650b 1387 trace_usb_xhci_xfer_async(xfer);
7c605a23
GH		 1388 xfer->running_async = 1;
1389 xfer->running_retry = 0;
1390 xfer->complete = 0;
1391 xfer->cancelled = 0;
1392 return 0;
1393 } else if (ret == USB_RET_NAK) {
97df650b 1394 trace_usb_xhci_xfer_nak(xfer);
7c605a23
GH		 1395 xfer->running_async = 0;
1396 xfer->running_retry = 1;
62c6ae04
HM		 1397 xfer->complete = 0;
1398 xfer->cancelled = 0;
1399 return 0;
1400 } else {
7c605a23
GH		 1401 xfer->running_async = 0;
1402 xfer->running_retry = 0;
62c6ae04 1403 xfer->complete = 1;
d5a15814 1404 xhci_xfer_unmap(xfer);
62c6ae04
HM		 1405 }
1406
1407 if (ret >= 0) {
97df650b 1408 trace_usb_xhci_xfer_success(xfer, ret);
d5a15814
GH		 1409 xfer->status = CC_SUCCESS;
1410 xhci_xfer_report(xfer);
62c6ae04
HM		 1411 return 0;
1412 }
1413
1414 /* error */
97df650b 1415 trace_usb_xhci_xfer_error(xfer, ret);
62c6ae04
HM		 1416 switch (ret) {
1417 case USB_RET_NODEV:
1418 xfer->status = CC_USB_TRANSACTION_ERROR;
d5a15814 1419 xhci_xfer_report(xfer);
62c6ae04
HM		 1420 xhci_stall_ep(xfer);
1421 break;
1422 case USB_RET_STALL:
1423 xfer->status = CC_STALL_ERROR;
d5a15814 1424 xhci_xfer_report(xfer);
62c6ae04
HM		 1425 xhci_stall_ep(xfer);
1426 break;
1427 default:
1428 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1429 FIXME();
1430 }
1431 return 0;
1432}
1433
1434static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1435{
1436 XHCITRB *trb_setup, *trb_status;
2850ca9e 1437 uint8_t bmRequestType;
62c6ae04
HM		 1438 int ret;
1439
62c6ae04
HM		 1440 trb_setup = &xfer->trbs[0];
1441 trb_status = &xfer->trbs[xfer->trb_count-1];
1442
d5a15814 1443 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
97df650b 1444
62c6ae04
HM		 1445 /* at most one Event Data TRB allowed after STATUS */
1446 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1447 trb_status--;
1448 }
1449
1450 /* do some sanity checks */
1451 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1452 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1453 TRB_TYPE(*trb_setup));
1454 return -1;
1455 }
1456 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1457 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1458 TRB_TYPE(*trb_status));
1459 return -1;
1460 }
1461 if (!(trb_setup->control & TRB_TR_IDT)) {
1462 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1463 return -1;
1464 }
1465 if ((trb_setup->status & 0x1ffff) != 8) {
1466 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1467 (trb_setup->status & 0x1ffff));
1468 return -1;
1469 }
1470
1471 bmRequestType = trb_setup->parameter;
62c6ae04 1472
62c6ae04
HM		 1473 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1474 xfer->iso_xfer = false;
1475
5c08106f
GH		 1476 if (xhci_setup_packet(xfer) < 0) {
1477 return -1;
1478 }
2850ca9e 1479 xfer->packet.parameter = trb_setup->parameter;
2850ca9e 1480
5c08106f 1481 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
62c6ae04
HM		 1482
1483 xhci_complete_packet(xfer, ret);
7c605a23 1484 if (!xfer->running_async && !xfer->running_retry) {
62c6ae04
HM		 1485 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1486 }
1487 return 0;
1488}
1489
3d139684
GH		 1490static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1491 XHCIEPContext *epctx, uint64_t mfindex)
1492{
1493 if (xfer->trbs[0].control & TRB_TR_SIA) {
1494 uint64_t asap = ((mfindex + epctx->interval - 1) &
1495 ~(epctx->interval-1));
1496 if (asap >= epctx->mfindex_last &&
1497 asap <= epctx->mfindex_last + epctx->interval * 4) {
1498 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1499 } else {
1500 xfer->mfindex_kick = asap;
1501 }
1502 } else {
1503 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1504 & TRB_TR_FRAMEID_MASK;
1505 xfer->mfindex_kick |= mfindex & ~0x3fff;
1506 if (xfer->mfindex_kick < mfindex) {
1507 xfer->mfindex_kick += 0x4000;
1508 }
1509 }
1510}
1511
1512static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1513 XHCIEPContext *epctx, uint64_t mfindex)
1514{
1515 if (xfer->mfindex_kick > mfindex) {
1516 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) +
1517 (xfer->mfindex_kick - mfindex) * 125000);
1518 xfer->running_retry = 1;
1519 } else {
1520 epctx->mfindex_last = xfer->mfindex_kick;
1521 qemu_del_timer(epctx->kick_timer);
1522 xfer->running_retry = 0;
1523 }
1524}
1525
1526
62c6ae04
HM		 1527static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1528{
3d139684 1529 uint64_t mfindex;
62c6ae04
HM		 1530 int ret;
1531
1532 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
62c6ae04
HM		 1533
1534 xfer->in_xfer = epctx->type>>2;
62c6ae04 1535
62c6ae04
HM		 1536 switch(epctx->type) {
1537 case ET_INTR_OUT:
1538 case ET_INTR_IN:
1539 case ET_BULK_OUT:
1540 case ET_BULK_IN:
3d139684
GH		 1541 xfer->pkts = 0;
1542 xfer->iso_xfer = false;
62c6ae04
HM		 1543 break;
1544 case ET_ISO_OUT:
1545 case ET_ISO_IN:
3d139684
GH		 1546 xfer->pkts = 1;
1547 xfer->iso_xfer = true;
1548 mfindex = xhci_mfindex_get(xhci);
1549 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1550 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1551 if (xfer->running_retry) {
1552 return -1;
1553 }
62c6ae04
HM		 1554 break;
1555 default:
079d0b7f
GH		 1556 fprintf(stderr, "xhci: unknown or unhandled EP "
1557 "(type %d, in %d, ep %02x)\n",
1558 epctx->type, xfer->in_xfer, xfer->epid);
62c6ae04
HM		 1559 return -1;
1560 }
1561
5c08106f
GH		 1562 if (xhci_setup_packet(xfer) < 0) {
1563 return -1;
1564 }
1565 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
62c6ae04
HM		 1566
1567 xhci_complete_packet(xfer, ret);
7c605a23 1568 if (!xfer->running_async && !xfer->running_retry) {
62c6ae04
HM		 1569 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1570 }
1571 return 0;
1572}
1573
1574static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1575{
d5a15814 1576 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
331e9406 1577 return xhci_submit(xhci, xfer, epctx);
62c6ae04
HM		 1578}
1579
1580static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1581{
1582 XHCIEPContext *epctx;
3d139684 1583 uint64_t mfindex;
62c6ae04
HM		 1584 int length;
1585 int i;
1586
c1f6b493 1587 trace_usb_xhci_ep_kick(slotid, epid);
62c6ae04
HM		 1588 assert(slotid >= 1 && slotid <= MAXSLOTS);
1589 assert(epid >= 1 && epid <= 31);
62c6ae04
HM		 1590
1591 if (!xhci->slots[slotid-1].enabled) {
1592 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1593 return;
1594 }
1595 epctx = xhci->slots[slotid-1].eps[epid-1];
1596 if (!epctx) {
1597 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1598 epid, slotid);
1599 return;
1600 }
1601
7c605a23 1602 if (epctx->retry) {
7c605a23
GH		 1603 XHCITransfer *xfer = epctx->retry;
1604 int result;
1605
97df650b 1606 trace_usb_xhci_xfer_retry(xfer);
7c605a23 1607 assert(xfer->running_retry);
3d139684
GH		 1608 if (xfer->iso_xfer) {
1609 /* retry delayed iso transfer */
1610 mfindex = xhci_mfindex_get(xhci);
1611 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1612 if (xfer->running_retry) {
1613 return;
1614 }
1615 if (xhci_setup_packet(xfer) < 0) {
1616 return;
1617 }
1618 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1619 assert(result != USB_RET_NAK);
1620 xhci_complete_packet(xfer, result);
1621 } else {
1622 /* retry nak'ed transfer */
1623 if (xhci_setup_packet(xfer) < 0) {
1624 return;
1625 }
1626 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1627 if (result == USB_RET_NAK) {
1628 return;
1629 }
1630 xhci_complete_packet(xfer, result);
7c605a23 1631 }
7c605a23
GH		 1632 assert(!xfer->running_retry);
1633 epctx->retry = NULL;
1634 }
1635
62c6ae04
HM		 1636 if (epctx->state == EP_HALTED) {
1637 DPRINTF("xhci: ep halted, not running schedule\n");
1638 return;
1639 }
1640
1641 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1642
1643 while (1) {
1644 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
331e9406 1645 if (xfer->running_async || xfer->running_retry) {
62c6ae04
HM		 1646 break;
1647 }
1648 length = xhci_ring_chain_length(xhci, &epctx->ring);
1649 if (length < 0) {
62c6ae04
HM		 1650 break;
1651 } else if (length == 0) {
1652 break;
1653 }
62c6ae04
HM		 1654 if (xfer->trbs && xfer->trb_alloced < length) {
1655 xfer->trb_count = 0;
1656 xfer->trb_alloced = 0;
1657 g_free(xfer->trbs);
1658 xfer->trbs = NULL;
1659 }
1660 if (!xfer->trbs) {
1661 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1662 xfer->trb_alloced = length;
1663 }
1664 xfer->trb_count = length;
1665
1666 for (i = 0; i < length; i++) {
1667 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1668 }
1669 xfer->xhci = xhci;
1670 xfer->epid = epid;
1671 xfer->slotid = slotid;
1672
1673 if (epid == 1) {
1674 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1675 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1676 } else {
1677 fprintf(stderr, "xhci: error firing CTL transfer\n");
1678 }
1679 } else {
1680 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1681 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1682 } else {
3d139684
GH		 1683 if (!xfer->iso_xfer) {
1684 fprintf(stderr, "xhci: error firing data transfer\n");
1685 }
62c6ae04
HM		 1686 }
1687 }
1688
3c4866e0 1689 if (epctx->state == EP_HALTED) {
3c4866e0
GH		 1690 break;
1691 }
7c605a23
GH		 1692 if (xfer->running_retry) {
1693 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1694 epctx->retry = xfer;
1695 break;
1696 }
62c6ae04
HM		 1697 }
1698}
1699
1700static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1701{
348f1037 1702 trace_usb_xhci_slot_enable(slotid);
62c6ae04 1703 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1704 xhci->slots[slotid-1].enabled = 1;
1705 xhci->slots[slotid-1].port = 0;
1706 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1707
1708 return CC_SUCCESS;
1709}
1710
1711static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1712{
1713 int i;
1714
348f1037 1715 trace_usb_xhci_slot_disable(slotid);
62c6ae04 1716 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1717
1718 for (i = 1; i <= 31; i++) {
1719 if (xhci->slots[slotid-1].eps[i-1]) {
1720 xhci_disable_ep(xhci, slotid, i);
1721 }
1722 }
1723
1724 xhci->slots[slotid-1].enabled = 0;
1725 return CC_SUCCESS;
1726}
1727
1728static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1729 uint64_t pictx, bool bsr)
1730{
1731 XHCISlot *slot;
1732 USBDevice *dev;
59a70ccd 1733 dma_addr_t ictx, octx, dcbaap;
62c6ae04
HM		 1734 uint64_t poctx;
1735 uint32_t ictl_ctx[2];
1736 uint32_t slot_ctx[4];
1737 uint32_t ep0_ctx[5];
1738 unsigned int port;
1739 int i;
1740 TRBCCode res;
1741
348f1037 1742 trace_usb_xhci_slot_address(slotid);
62c6ae04 1743 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1744
1745 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
59a70ccd 1746 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx));
62c6ae04
HM		 1747 ictx = xhci_mask64(pictx);
1748 octx = xhci_mask64(le64_to_cpu(poctx));
1749
59a70ccd
DG		 1750 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1751 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 1752
59a70ccd 1753 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 1754
1755 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1756 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1757 ictl_ctx[0], ictl_ctx[1]);
1758 return CC_TRB_ERROR;
1759 }
1760
59a70ccd
DG		 1761 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx));
1762 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 1763
1764 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1765 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1766
1767 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1768 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1769
1770 port = (slot_ctx[1]>>16) & 0xFF;
0846e635 1771 dev = xhci->ports[port-1].uport->dev;
62c6ae04 1772
0846e635 1773 if (port < 1 || port > xhci->numports) {
62c6ae04
HM		 1774 fprintf(stderr, "xhci: bad port %d\n", port);
1775 return CC_TRB_ERROR;
1776 } else if (!dev) {
1777 fprintf(stderr, "xhci: port %d not connected\n", port);
1778 return CC_USB_TRANSACTION_ERROR;
1779 }
1780
1781 for (i = 0; i < MAXSLOTS; i++) {
1782 if (xhci->slots[i].port == port) {
1783 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1784 port, i+1);
1785 return CC_TRB_ERROR;
1786 }
1787 }
1788
1789 slot = &xhci->slots[slotid-1];
1790 slot->port = port;
1791 slot->ctx = octx;
1792
1793 if (bsr) {
1794 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1795 } else {
1796 slot->devaddr = xhci->devaddr++;
1797 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1798 DPRINTF("xhci: device address is %d\n", slot->devaddr);
62aed765 1799 usb_device_handle_control(dev, NULL,
62c6ae04
HM		 1800 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1801 slot->devaddr, 0, 0, NULL);
1802 }
1803
1804 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1805
1806 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1807 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1808 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1809 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1810
59a70ccd
DG		 1811 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1812 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 1813
1814 return res;
1815}
1816
1817
1818static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1819 uint64_t pictx, bool dc)
1820{
59a70ccd 1821 dma_addr_t ictx, octx;
62c6ae04
HM		 1822 uint32_t ictl_ctx[2];
1823 uint32_t slot_ctx[4];
1824 uint32_t islot_ctx[4];
1825 uint32_t ep_ctx[5];
1826 int i;
1827 TRBCCode res;
1828
348f1037 1829 trace_usb_xhci_slot_configure(slotid);
62c6ae04 1830 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1831
1832 ictx = xhci_mask64(pictx);
1833 octx = xhci->slots[slotid-1].ctx;
1834
59a70ccd
DG		 1835 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1836 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 1837
1838 if (dc) {
1839 for (i = 2; i <= 31; i++) {
1840 if (xhci->slots[slotid-1].eps[i-1]) {
1841 xhci_disable_ep(xhci, slotid, i);
1842 }
1843 }
1844
59a70ccd 1845 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1846 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1847 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1848 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1849 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
59a70ccd 1850 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1851
1852 return CC_SUCCESS;
1853 }
1854
59a70ccd 1855 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 1856
1857 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1858 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1859 ictl_ctx[0], ictl_ctx[1]);
1860 return CC_TRB_ERROR;
1861 }
1862
59a70ccd
DG		 1863 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1864 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1865
1866 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1867 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1868 return CC_CONTEXT_STATE_ERROR;
1869 }
1870
1871 for (i = 2; i <= 31; i++) {
1872 if (ictl_ctx[0] & (1<<i)) {
1873 xhci_disable_ep(xhci, slotid, i);
1874 }
1875 if (ictl_ctx[1] & (1<<i)) {
59a70ccd
DG		 1876 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx,
1877 sizeof(ep_ctx));
62c6ae04
HM		 1878 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1879 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1880 ep_ctx[3], ep_ctx[4]);
1881 xhci_disable_ep(xhci, slotid, i);
1882 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1883 if (res != CC_SUCCESS) {
1884 return res;
1885 }
1886 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1887 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1888 ep_ctx[3], ep_ctx[4]);
59a70ccd 1889 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx));
62c6ae04
HM		 1890 }
1891 }
1892
1893 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1894 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1895 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1896 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1897 SLOT_CONTEXT_ENTRIES_SHIFT);
1898 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1899 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1900
59a70ccd 1901 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1902
1903 return CC_SUCCESS;
1904}
1905
1906
1907static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1908 uint64_t pictx)
1909{
59a70ccd 1910 dma_addr_t ictx, octx;
62c6ae04
HM		 1911 uint32_t ictl_ctx[2];
1912 uint32_t iep0_ctx[5];
1913 uint32_t ep0_ctx[5];
1914 uint32_t islot_ctx[4];
1915 uint32_t slot_ctx[4];
1916
348f1037 1917 trace_usb_xhci_slot_evaluate(slotid);
62c6ae04 1918 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1919
1920 ictx = xhci_mask64(pictx);
1921 octx = xhci->slots[slotid-1].ctx;
1922
59a70ccd
DG		 1923 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1924 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04 1925
59a70ccd 1926 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
62c6ae04
HM		 1927
1928 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1929 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1930 ictl_ctx[0], ictl_ctx[1]);
1931 return CC_TRB_ERROR;
1932 }
1933
1934 if (ictl_ctx[1] & 0x1) {
59a70ccd 1935 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
62c6ae04
HM		 1936
1937 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1938 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1939
59a70ccd 1940 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1941
1942 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1943 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1944 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1945 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1946
1947 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1948 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1949
59a70ccd 1950 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1951 }
1952
1953 if (ictl_ctx[1] & 0x2) {
59a70ccd 1954 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx));
62c6ae04
HM		 1955
1956 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1957 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
1958 iep0_ctx[3], iep0_ctx[4]);
1959
59a70ccd 1960 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 1961
1962 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
1963 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
1964
1965 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1966 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1967
59a70ccd 1968 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
62c6ae04
HM		 1969 }
1970
1971 return CC_SUCCESS;
1972}
1973
1974static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
1975{
1976 uint32_t slot_ctx[4];
59a70ccd 1977 dma_addr_t octx;
62c6ae04
HM		 1978 int i;
1979
348f1037 1980 trace_usb_xhci_slot_reset(slotid);
62c6ae04 1981 assert(slotid >= 1 && slotid <= MAXSLOTS);
62c6ae04
HM		 1982
1983 octx = xhci->slots[slotid-1].ctx;
1984
59a70ccd 1985 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
62c6ae04
HM		 1986
1987 for (i = 2; i <= 31; i++) {
1988 if (xhci->slots[slotid-1].eps[i-1]) {
1989 xhci_disable_ep(xhci, slotid, i);
1990 }
1991 }
1992
59a70ccd 1993 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1994 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1995 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
1996 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1997 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
59a70ccd 1998 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
62c6ae04
HM		 1999
2000 return CC_SUCCESS;
2001}
2002
2003static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2004{
2005 unsigned int slotid;
2006 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2007 if (slotid < 1 || slotid > MAXSLOTS) {
2008 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2009 event->ccode = CC_TRB_ERROR;
2010 return 0;
2011 } else if (!xhci->slots[slotid-1].enabled) {
2012 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2013 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2014 return 0;
2015 }
2016 return slotid;
2017}
2018
2019static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2020{
59a70ccd 2021 dma_addr_t ctx;
0846e635 2022 uint8_t bw_ctx[xhci->numports+1];
62c6ae04
HM		 2023
2024 DPRINTF("xhci_get_port_bandwidth()\n");
2025
2026 ctx = xhci_mask64(pctx);
2027
59a70ccd 2028 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
62c6ae04
HM		 2029
2030 /* TODO: actually implement real values here */
2031 bw_ctx[0] = 0;
0846e635 2032 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
59a70ccd 2033 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
62c6ae04
HM		 2034
2035 return CC_SUCCESS;
2036}
2037
2038static uint32_t rotl(uint32_t v, unsigned count)
2039{
2040 count &= 31;
2041 return (v << count) | (v >> (32 - count));
2042}
2043
2044
2045static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2046{
2047 uint32_t val;
2048 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2049 val += rotl(lo + 0x49434878, hi & 0x1F);
2050 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2051 return ~val;
2052}
2053
59a70ccd 2054static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
62c6ae04
HM		 2055{
2056 uint32_t buf[8];
2057 uint32_t obuf[8];
59a70ccd 2058 dma_addr_t paddr = xhci_mask64(addr);
62c6ae04 2059
59a70ccd 2060 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
62c6ae04
HM		 2061
2062 memcpy(obuf, buf, sizeof(obuf));
2063
2064 if ((buf[0] & 0xff) == 2) {
2065 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2066 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2067 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2068 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2069 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2070 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2071 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2072 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2073 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2074 }
2075
59a70ccd 2076 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
62c6ae04
HM		 2077}
2078
2079static void xhci_process_commands(XHCIState *xhci)
2080{
2081 XHCITRB trb;
2082 TRBType type;
2083 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
59a70ccd 2084 dma_addr_t addr;
62c6ae04
HM		 2085 unsigned int i, slotid = 0;
2086
2087 DPRINTF("xhci_process_commands()\n");
2088 if (!xhci_running(xhci)) {
2089 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2090 return;
2091 }
2092
2093 xhci->crcr_low |= CRCR_CRR;
2094
2095 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2096 event.ptr = addr;
2097 switch (type) {
2098 case CR_ENABLE_SLOT:
2099 for (i = 0; i < MAXSLOTS; i++) {
2100 if (!xhci->slots[i].enabled) {
2101 break;
2102 }
2103 }
2104 if (i >= MAXSLOTS) {
2105 fprintf(stderr, "xhci: no device slots available\n");
2106 event.ccode = CC_NO_SLOTS_ERROR;
2107 } else {
2108 slotid = i+1;
2109 event.ccode = xhci_enable_slot(xhci, slotid);
2110 }
2111 break;
2112 case CR_DISABLE_SLOT:
2113 slotid = xhci_get_slot(xhci, &event, &trb);
2114 if (slotid) {
2115 event.ccode = xhci_disable_slot(xhci, slotid);
2116 }
2117 break;
2118 case CR_ADDRESS_DEVICE:
2119 slotid = xhci_get_slot(xhci, &event, &trb);
2120 if (slotid) {
2121 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2122 trb.control & TRB_CR_BSR);
2123 }
2124 break;
2125 case CR_CONFIGURE_ENDPOINT:
2126 slotid = xhci_get_slot(xhci, &event, &trb);
2127 if (slotid) {
2128 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2129 trb.control & TRB_CR_DC);
2130 }
2131 break;
2132 case CR_EVALUATE_CONTEXT:
2133 slotid = xhci_get_slot(xhci, &event, &trb);
2134 if (slotid) {
2135 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2136 }
2137 break;
2138 case CR_STOP_ENDPOINT:
2139 slotid = xhci_get_slot(xhci, &event, &trb);
2140 if (slotid) {
2141 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2142 & TRB_CR_EPID_MASK;
2143 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2144 }
2145 break;
2146 case CR_RESET_ENDPOINT:
2147 slotid = xhci_get_slot(xhci, &event, &trb);
2148 if (slotid) {
2149 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2150 & TRB_CR_EPID_MASK;
2151 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2152 }
2153 break;
2154 case CR_SET_TR_DEQUEUE:
2155 slotid = xhci_get_slot(xhci, &event, &trb);
2156 if (slotid) {
2157 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2158 & TRB_CR_EPID_MASK;
2159 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2160 trb.parameter);
2161 }
2162 break;
2163 case CR_RESET_DEVICE:
2164 slotid = xhci_get_slot(xhci, &event, &trb);
2165 if (slotid) {
2166 event.ccode = xhci_reset_slot(xhci, slotid);
2167 }
2168 break;
2169 case CR_GET_PORT_BANDWIDTH:
2170 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2171 break;
2172 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
59a70ccd 2173 xhci_via_challenge(xhci, trb.parameter);
62c6ae04
HM		 2174 break;
2175 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2176 event.type = 48; /* NEC reply */
2177 event.length = 0x3025;
2178 break;
2179 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2180 {
2181 uint32_t chi = trb.parameter >> 32;
2182 uint32_t clo = trb.parameter;
2183 uint32_t val = xhci_nec_challenge(chi, clo);
2184 event.length = val & 0xFFFF;
2185 event.epid = val >> 16;
2186 slotid = val >> 24;
2187 event.type = 48; /* NEC reply */
2188 }
2189 break;
2190 default:
2191 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2192 event.ccode = CC_TRB_ERROR;
2193 break;
2194 }
2195 event.slotid = slotid;
2196 xhci_event(xhci, &event);
2197 }
2198}
2199
2200static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2201{
62c6ae04 2202 port->portsc = PORTSC_PP;
0846e635
GH		 2203 if (port->uport->dev && port->uport->dev->attached && !is_detach &&
2204 (1 << port->uport->dev->speed) & port->speedmask) {
62c6ae04 2205 port->portsc |= PORTSC_CCS;
0846e635 2206 switch (port->uport->dev->speed) {
62c6ae04
HM		 2207 case USB_SPEED_LOW:
2208 port->portsc |= PORTSC_SPEED_LOW;
2209 break;
2210 case USB_SPEED_FULL:
2211 port->portsc |= PORTSC_SPEED_FULL;
2212 break;
2213 case USB_SPEED_HIGH:
2214 port->portsc |= PORTSC_SPEED_HIGH;
2215 break;
0846e635
GH		 2216 case USB_SPEED_SUPER:
2217 port->portsc |= PORTSC_SPEED_SUPER;
2218 break;
62c6ae04
HM		 2219 }
2220 }
2221
2222 if (xhci_running(xhci)) {
2223 port->portsc |= PORTSC_CSC;
0846e635
GH		 2224 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2225 port->portnr << 24};
62c6ae04 2226 xhci_event(xhci, &ev);
0846e635 2227 DPRINTF("xhci: port change event for port %d\n", port->portnr);
62c6ae04
HM		 2228 }
2229}
2230
64619739 2231static void xhci_reset(DeviceState *dev)
62c6ae04 2232{
64619739 2233 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
62c6ae04
HM		 2234 int i;
2235
2d754a10 2236 trace_usb_xhci_reset();
62c6ae04
HM		 2237 if (!(xhci->usbsts & USBSTS_HCH)) {
2238 fprintf(stderr, "xhci: reset while running!\n");
2239 }
2240
2241 xhci->usbcmd = 0;
2242 xhci->usbsts = USBSTS_HCH;
2243 xhci->dnctrl = 0;
2244 xhci->crcr_low = 0;
2245 xhci->crcr_high = 0;
2246 xhci->dcbaap_low = 0;
2247 xhci->dcbaap_high = 0;
2248 xhci->config = 0;
2249 xhci->devaddr = 2;
2250
2251 for (i = 0; i < MAXSLOTS; i++) {
2252 xhci_disable_slot(xhci, i+1);
2253 }
2254
0846e635 2255 for (i = 0; i < xhci->numports; i++) {
62c6ae04
HM		 2256 xhci_update_port(xhci, xhci->ports + i, 0);
2257 }
2258
62c6ae04
HM		 2259 xhci->iman = 0;
2260 xhci->imod = 0;
2261 xhci->erstsz = 0;
2262 xhci->erstba_low = 0;
2263 xhci->erstba_high = 0;
2264 xhci->erdp_low = 0;
2265 xhci->erdp_high = 0;
2266
2267 xhci->er_ep_idx = 0;
2268 xhci->er_pcs = 1;
2269 xhci->er_full = 0;
2270 xhci->ev_buffer_put = 0;
2271 xhci->ev_buffer_get = 0;
01546fa6
GH		 2272
2273 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
2274 xhci_mfwrap_update(xhci);
62c6ae04
HM		 2275}
2276
2277static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2278{
2d754a10 2279 uint32_t ret;
62c6ae04
HM		 2280
2281 switch (reg) {
2282 case 0x00: /* HCIVERSION, CAPLENGTH */
2d754a10
GH		 2283 ret = 0x01000000 | LEN_CAP;
2284 break;
62c6ae04 2285 case 0x04: /* HCSPARAMS 1 */
0846e635
GH		 2286 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2287 | (MAXINTRS<<8) | MAXSLOTS;
2d754a10 2288 break;
62c6ae04 2289 case 0x08: /* HCSPARAMS 2 */
2d754a10
GH		 2290 ret = 0x0000000f;
2291 break;
62c6ae04 2292 case 0x0c: /* HCSPARAMS 3 */
2d754a10
GH		 2293 ret = 0x00000000;
2294 break;
62c6ae04 2295 case 0x10: /* HCCPARAMS */
2d754a10
GH		 2296 if (sizeof(dma_addr_t) == 4) {
2297 ret = 0x00081000;
2298 } else {
2299 ret = 0x00081001;
2300 }
2301 break;
62c6ae04 2302 case 0x14: /* DBOFF */
2d754a10
GH		 2303 ret = OFF_DOORBELL;
2304 break;
62c6ae04 2305 case 0x18: /* RTSOFF */
2d754a10
GH		 2306 ret = OFF_RUNTIME;
2307 break;
62c6ae04
HM		 2308
2309 /* extended capabilities */
2310 case 0x20: /* Supported Protocol:00 */
2d754a10
GH		 2311 ret = 0x02000402; /* USB 2.0 */
2312 break;
62c6ae04 2313 case 0x24: /* Supported Protocol:04 */
2d754a10
GH		 2314 ret = 0x20425455; /* "USB " */
2315 break;
62c6ae04 2316 case 0x28: /* Supported Protocol:08 */
0846e635 2317 ret = 0x00000001 | (xhci->numports_2<<8);
2d754a10 2318 break;
62c6ae04 2319 case 0x2c: /* Supported Protocol:0c */
2d754a10
GH		 2320 ret = 0x00000000; /* reserved */
2321 break;
62c6ae04 2322 case 0x30: /* Supported Protocol:00 */
2d754a10
GH		 2323 ret = 0x03000002; /* USB 3.0 */
2324 break;
62c6ae04 2325 case 0x34: /* Supported Protocol:04 */
2d754a10
GH		 2326 ret = 0x20425455; /* "USB " */
2327 break;
62c6ae04 2328 case 0x38: /* Supported Protocol:08 */
0846e635 2329 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2d754a10 2330 break;
62c6ae04 2331 case 0x3c: /* Supported Protocol:0c */
2d754a10
GH		 2332 ret = 0x00000000; /* reserved */
2333 break;
62c6ae04
HM		 2334 default:
2335 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2d754a10 2336 ret = 0;
62c6ae04 2337 }
2d754a10
GH		 2338
2339 trace_usb_xhci_cap_read(reg, ret);
2340 return ret;
62c6ae04
HM		 2341}
2342
2343static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2344{
2345 uint32_t port = reg >> 4;
2d754a10
GH		 2346 uint32_t ret;
2347
0846e635 2348 if (port >= xhci->numports) {
62c6ae04 2349 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2d754a10
GH		 2350 ret = 0;
2351 goto out;
62c6ae04
HM		 2352 }
2353
2354 switch (reg & 0xf) {
2355 case 0x00: /* PORTSC */
2d754a10
GH		 2356 ret = xhci->ports[port].portsc;
2357 break;
62c6ae04
HM		 2358 case 0x04: /* PORTPMSC */
2359 case 0x08: /* PORTLI */
2d754a10
GH		 2360 ret = 0;
2361 break;
62c6ae04
HM		 2362 case 0x0c: /* reserved */
2363 default:
2364 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2365 port, reg);
2d754a10 2366 ret = 0;
62c6ae04 2367 }
2d754a10
GH		 2368
2369out:
2370 trace_usb_xhci_port_read(port, reg & 0x0f, ret);
2371 return ret;
62c6ae04
HM		 2372}
2373
2374static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2375{
2376 uint32_t port = reg >> 4;
2377 uint32_t portsc;
2378
2d754a10
GH		 2379 trace_usb_xhci_port_write(port, reg & 0x0f, val);
2380
0846e635 2381 if (port >= xhci->numports) {
62c6ae04
HM		 2382 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2383 return;
2384 }
2385
2386 switch (reg & 0xf) {
2387 case 0x00: /* PORTSC */
2388 portsc = xhci->ports[port].portsc;
2389 /* write-1-to-clear bits*/
2390 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2391 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2392 if (val & PORTSC_LWS) {
2393 /* overwrite PLS only when LWS=1 */
2394 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2395 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2396 }
2397 /* read/write bits */
2398 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2399 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2400 /* write-1-to-start bits */
2401 if (val & PORTSC_PR) {
2402 DPRINTF("xhci: port %d reset\n", port);
0846e635 2403 usb_device_reset(xhci->ports[port].uport->dev);
62c6ae04
HM		 2404 portsc |= PORTSC_PRC | PORTSC_PED;
2405 }
2406 xhci->ports[port].portsc = portsc;
2407 break;
2408 case 0x04: /* PORTPMSC */
2409 case 0x08: /* PORTLI */
2410 default:
2411 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2412 port, reg);
2413 }
2414}
2415
2416static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2417{
2d754a10 2418 uint32_t ret;
62c6ae04
HM		 2419
2420 if (reg >= 0x400) {
2421 return xhci_port_read(xhci, reg - 0x400);
2422 }
2423
2424 switch (reg) {
2425 case 0x00: /* USBCMD */
2d754a10
GH		 2426 ret = xhci->usbcmd;
2427 break;
62c6ae04 2428 case 0x04: /* USBSTS */
2d754a10
GH		 2429 ret = xhci->usbsts;
2430 break;
62c6ae04 2431 case 0x08: /* PAGESIZE */
2d754a10
GH		 2432 ret = 1; /* 4KiB */
2433 break;
62c6ae04 2434 case 0x14: /* DNCTRL */
2d754a10
GH		 2435 ret = xhci->dnctrl;
2436 break;
62c6ae04 2437 case 0x18: /* CRCR low */
2d754a10
GH		 2438 ret = xhci->crcr_low & ~0xe;
2439 break;
62c6ae04 2440 case 0x1c: /* CRCR high */
2d754a10
GH		 2441 ret = xhci->crcr_high;
2442 break;
62c6ae04 2443 case 0x30: /* DCBAAP low */
2d754a10
GH		 2444 ret = xhci->dcbaap_low;
2445 break;
62c6ae04 2446 case 0x34: /* DCBAAP high */
2d754a10
GH		 2447 ret = xhci->dcbaap_high;
2448 break;
62c6ae04 2449 case 0x38: /* CONFIG */
2d754a10
GH		 2450 ret = xhci->config;
2451 break;
62c6ae04
HM		 2452 default:
2453 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2d754a10 2454 ret = 0;
62c6ae04 2455 }
2d754a10
GH		 2456
2457 trace_usb_xhci_oper_read(reg, ret);
2458 return ret;
62c6ae04
HM		 2459}
2460
2461static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2462{
62c6ae04
HM		 2463 if (reg >= 0x400) {
2464 xhci_port_write(xhci, reg - 0x400, val);
2465 return;
2466 }
2467
2d754a10
GH		 2468 trace_usb_xhci_oper_write(reg, val);
2469
62c6ae04
HM		 2470 switch (reg) {
2471 case 0x00: /* USBCMD */
2472 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2473 xhci_run(xhci);
2474 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2475 xhci_stop(xhci);
2476 }
2477 xhci->usbcmd = val & 0xc0f;
01546fa6 2478 xhci_mfwrap_update(xhci);
62c6ae04 2479 if (val & USBCMD_HCRST) {
64619739 2480 xhci_reset(&xhci->pci_dev.qdev);
62c6ae04
HM		 2481 }
2482 xhci_irq_update(xhci);
2483 break;
2484
2485 case 0x04: /* USBSTS */
2486 /* these bits are write-1-to-clear */
2487 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2488 xhci_irq_update(xhci);
2489 break;
2490
2491 case 0x14: /* DNCTRL */
2492 xhci->dnctrl = val & 0xffff;
2493 break;
2494 case 0x18: /* CRCR low */
2495 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2496 break;
2497 case 0x1c: /* CRCR high */
2498 xhci->crcr_high = val;
2499 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2500 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2501 xhci->crcr_low &= ~CRCR_CRR;
2502 xhci_event(xhci, &event);
2503 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2504 } else {
59a70ccd 2505 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
62c6ae04
HM		 2506 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2507 }
2508 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2509 break;
2510 case 0x30: /* DCBAAP low */
2511 xhci->dcbaap_low = val & 0xffffffc0;
2512 break;
2513 case 0x34: /* DCBAAP high */
2514 xhci->dcbaap_high = val;
2515 break;
2516 case 0x38: /* CONFIG */
2517 xhci->config = val & 0xff;
2518 break;
2519 default:
2520 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2521 }
2522}
2523
2524static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2525{
2d754a10 2526 uint32_t ret;
62c6ae04
HM		 2527
2528 switch (reg) {
2529 case 0x00: /* MFINDEX */
01546fa6 2530 ret = xhci_mfindex_get(xhci) & 0x3fff;
2d754a10 2531 break;
62c6ae04 2532 case 0x20: /* IMAN */
2d754a10
GH		 2533 ret = xhci->iman;
2534 break;
62c6ae04 2535 case 0x24: /* IMOD */
2d754a10
GH		 2536 ret = xhci->imod;
2537 break;
62c6ae04 2538 case 0x28: /* ERSTSZ */
2d754a10
GH		 2539 ret = xhci->erstsz;
2540 break;
62c6ae04 2541 case 0x30: /* ERSTBA low */
2d754a10
GH		 2542 ret = xhci->erstba_low;
2543 break;
62c6ae04 2544 case 0x34: /* ERSTBA high */
2d754a10
GH		 2545 ret = xhci->erstba_high;
2546 break;
62c6ae04 2547 case 0x38: /* ERDP low */
2d754a10
GH		 2548 ret = xhci->erdp_low;
2549 break;
62c6ae04 2550 case 0x3c: /* ERDP high */
2d754a10
GH		 2551 ret = xhci->erdp_high;
2552 break;
62c6ae04
HM		 2553 default:
2554 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2d754a10 2555 ret = 0;
62c6ae04 2556 }
2d754a10
GH		 2557
2558 trace_usb_xhci_runtime_read(reg, ret);
2559 return ret;
62c6ae04
HM		 2560}
2561
2562static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2563{
8e9f18b6 2564 trace_usb_xhci_runtime_write(reg, val);
62c6ae04
HM		 2565
2566 switch (reg) {
2567 case 0x20: /* IMAN */
2568 if (val & IMAN_IP) {
2569 xhci->iman &= ~IMAN_IP;
2570 }
2571 xhci->iman &= ~IMAN_IE;
2572 xhci->iman |= val & IMAN_IE;
2573 xhci_irq_update(xhci);
2574 break;
2575 case 0x24: /* IMOD */
2576 xhci->imod = val;
2577 break;
2578 case 0x28: /* ERSTSZ */
2579 xhci->erstsz = val & 0xffff;
2580 break;
2581 case 0x30: /* ERSTBA low */
2582 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2583 xhci->erstba_low = val & 0xffffffc0; */
2584 xhci->erstba_low = val & 0xfffffff0;
2585 break;
2586 case 0x34: /* ERSTBA high */
2587 xhci->erstba_high = val;
2588 xhci_er_reset(xhci);
2589 break;
2590 case 0x38: /* ERDP low */
2591 if (val & ERDP_EHB) {
2592 xhci->erdp_low &= ~ERDP_EHB;
2593 }
2594 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB);
2595 break;
2596 case 0x3c: /* ERDP high */
2597 xhci->erdp_high = val;
2598 xhci_events_update(xhci);
2599 break;
2600 default:
2601 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2602 }
2603}
2604
2605static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2606{
62c6ae04 2607 /* doorbells always read as 0 */
2d754a10 2608 trace_usb_xhci_doorbell_read(reg, 0);
62c6ae04
HM		 2609 return 0;
2610}
2611
2612static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2613{
2d754a10 2614 trace_usb_xhci_doorbell_write(reg, val);
62c6ae04
HM		 2615
2616 if (!xhci_running(xhci)) {
2617 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2618 return;
2619 }
2620
2621 reg >>= 2;
2622
2623 if (reg == 0) {
2624 if (val == 0) {
2625 xhci_process_commands(xhci);
2626 } else {
2627 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2628 }
2629 } else {
2630 if (reg > MAXSLOTS) {
2631 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2632 } else if (val > 31) {
2633 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2634 } else {
2635 xhci_kick_ep(xhci, reg, val);
2636 }
2637 }
2638}
2639
2640static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2641 unsigned size)
2642{
2643 XHCIState *xhci = ptr;
2644
2645 /* Only aligned reads are allowed on xHCI */
2646 if (addr & 3) {
2647 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2648 return 0;
2649 }
2650
2651 if (addr < LEN_CAP) {
2652 return xhci_cap_read(xhci, addr);
2653 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2654 return xhci_oper_read(xhci, addr - OFF_OPER);
2655 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2656 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2657 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2658 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2659 } else {
2660 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2661 return 0;
2662 }
2663}
2664
2665static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2666 uint64_t val, unsigned size)
2667{
2668 XHCIState *xhci = ptr;
2669
2670 /* Only aligned writes are allowed on xHCI */
2671 if (addr & 3) {
2672 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2673 return;
2674 }
2675
2676 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2677 xhci_oper_write(xhci, addr - OFF_OPER, val);
2678 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2679 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2680 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2681 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2682 } else {
2683 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2684 }
2685}
2686
2687static const MemoryRegionOps xhci_mem_ops = {
2688 .read = xhci_mem_read,
2689 .write = xhci_mem_write,
2690 .valid.min_access_size = 4,
2691 .valid.max_access_size = 4,
2692 .endianness = DEVICE_LITTLE_ENDIAN,
2693};
2694
2695static void xhci_attach(USBPort *usbport)
2696{
2697 XHCIState *xhci = usbport->opaque;
0846e635 2698 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04
HM		 2699
2700 xhci_update_port(xhci, port, 0);
2701}
2702
2703static void xhci_detach(USBPort *usbport)
2704{
2705 XHCIState *xhci = usbport->opaque;
0846e635 2706 XHCIPort *port = xhci_lookup_port(xhci, usbport);
62c6ae04
HM		 2707
2708 xhci_update_port(xhci, port, 1);
2709}
2710
8c735e43
GH		 2711static void xhci_wakeup(USBPort *usbport)
2712{
2713 XHCIState *xhci = usbport->opaque;
0846e635
GH		 2714 XHCIPort *port = xhci_lookup_port(xhci, usbport);
2715 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2716 port->portnr << 24};
8c735e43
GH		 2717 uint32_t pls;
2718
2719 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
2720 if (pls != 3) {
2721 return;
2722 }
2723 port->portsc |= 0xf << PORTSC_PLS_SHIFT;
2724 if (port->portsc & PORTSC_PLC) {
2725 return;
2726 }
2727 port->portsc |= PORTSC_PLC;
2728 xhci_event(xhci, &ev);
2729}
2730
62c6ae04
HM		 2731static void xhci_complete(USBPort *port, USBPacket *packet)
2732{
2733 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2734
2735 xhci_complete_packet(xfer, packet->result);
2736 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2737}
2738
2739static void xhci_child_detach(USBPort *port, USBDevice *child)
2740{
2741 FIXME();
2742}
2743
2744static USBPortOps xhci_port_ops = {
2745 .attach = xhci_attach,
2746 .detach = xhci_detach,
8c735e43 2747 .wakeup = xhci_wakeup,
62c6ae04
HM		 2748 .complete = xhci_complete,
2749 .child_detach = xhci_child_detach,
2750};
2751
7c605a23
GH		 2752static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev)
2753{
2754 XHCISlot *slot;
2755 int slotid;
2756
2757 for (slotid = 1; slotid <= MAXSLOTS; slotid++) {
2758 slot = &xhci->slots[slotid-1];
2759 if (slot->devaddr == dev->addr) {
2760 return slotid;
2761 }
2762 }
2763 return 0;
2764}
2765
2766static int xhci_find_epid(USBEndpoint *ep)
2767{
2768 if (ep->nr == 0) {
2769 return 1;
2770 }
2771 if (ep->pid == USB_TOKEN_IN) {
2772 return ep->nr * 2 + 1;
2773 } else {
2774 return ep->nr * 2;
2775 }
2776}
2777
2778static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
2779{
2780 XHCIState *xhci = container_of(bus, XHCIState, bus);
2781 int slotid;
2782
2783 DPRINTF("%s\n", __func__);
2784 slotid = xhci_find_slotid(xhci, ep->dev);
2785 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
2786 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
2787 return;
2788 }
2789 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep));
2790}
2791
62c6ae04 2792static USBBusOps xhci_bus_ops = {
7c605a23 2793 .wakeup_endpoint = xhci_wakeup_endpoint,
62c6ae04
HM		 2794};
2795
2796static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2797{
0846e635
GH		 2798 XHCIPort *port;
2799 int i, usbports, speedmask;
62c6ae04
HM		 2800
2801 xhci->usbsts = USBSTS_HCH;
2802
0846e635
GH		 2803 if (xhci->numports_2 > MAXPORTS_2) {
2804 xhci->numports_2 = MAXPORTS_2;
2805 }
2806 if (xhci->numports_3 > MAXPORTS_3) {
2807 xhci->numports_3 = MAXPORTS_3;
2808 }
2809 usbports = MAX(xhci->numports_2, xhci->numports_3);
2810 xhci->numports = xhci->numports_2 + xhci->numports_3;
2811
62c6ae04
HM		 2812 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2813
0846e635
GH		 2814 for (i = 0; i < usbports; i++) {
2815 speedmask = 0;
2816 if (i < xhci->numports_2) {
2817 port = &xhci->ports[i];
2818 port->portnr = i + 1;
2819 port->uport = &xhci->uports[i];
2820 port->speedmask =
2821 USB_SPEED_MASK_LOW |
2822 USB_SPEED_MASK_FULL |
2823 USB_SPEED_MASK_HIGH;
2824 speedmask |= port->speedmask;
2825 }
2826 if (i < xhci->numports_3) {
2827 port = &xhci->ports[i + xhci->numports_2];
2828 port->portnr = i + 1 + xhci->numports_2;
2829 port->uport = &xhci->uports[i];
2830 port->speedmask = USB_SPEED_MASK_SUPER;
2831 speedmask |= port->speedmask;
2832 }
2833 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
2834 &xhci_port_ops, speedmask);
62c6ae04 2835 }
62c6ae04
HM		 2836}
2837
2838static int usb_xhci_initfn(struct PCIDevice *dev)
2839{
2840 int ret;
2841
2842 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2843
2844 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2845 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2846 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2847 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2848
2849 usb_xhci_init(xhci, &dev->qdev);
2850
01546fa6
GH		 2851 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
2852
62c6ae04
HM		 2853 xhci->irq = xhci->pci_dev.irq[0];
2854
2855 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2856 "xhci", LEN_REGS);
2857 pci_register_bar(&xhci->pci_dev, 0,
2858 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2859 &xhci->mem);
2860
2861 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2862 assert(ret >= 0);
2863
c5e9b02d
GH		 2864 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
2865 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false);
62c6ae04
HM		 2866 }
2867
2868 return 0;
2869}
2870
62c6ae04
HM		 2871static const VMStateDescription vmstate_xhci = {
2872 .name = "xhci",
2873 .unmigratable = 1,
2874};
2875
39bffca2 2876static Property xhci_properties[] = {
c5e9b02d 2877 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
0846e635
GH		 2878 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
2879 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
39bffca2
AL		 2880 DEFINE_PROP_END_OF_LIST(),
2881};
2882
40021f08
AL		 2883static void xhci_class_init(ObjectClass *klass, void *data)
2884{
2885 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2 2886 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 2887
39bffca2
AL		 2888 dc->vmsd = &vmstate_xhci;
2889 dc->props = xhci_properties;
64619739 2890 dc->reset = xhci_reset;
40021f08
AL		 2891 k->init = usb_xhci_initfn;
2892 k->vendor_id = PCI_VENDOR_ID_NEC;
2893 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2894 k->class_id = PCI_CLASS_SERIAL_USB;
2895 k->revision = 0x03;
2896 k->is_express = 1;
40021f08
AL		 2897}
2898
39bffca2
AL		 2899static TypeInfo xhci_info = {
2900 .name = "nec-usb-xhci",
2901 .parent = TYPE_PCI_DEVICE,
2902 .instance_size = sizeof(XHCIState),
2903 .class_init = xhci_class_init,
62c6ae04
HM		 2904};
2905
83f7d43a 2906static void xhci_register_types(void)
62c6ae04 2907{
39bffca2 2908 type_register_static(&xhci_info);
62c6ae04 2909}
83f7d43a
AF		 2910
2911type_init(xhci_register_types)
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