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Commit | Line | Data |
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62c6ae04 HM |
1 | /* |
2 | * USB xHCI controller emulation | |
3 | * | |
4 | * Copyright (c) 2011 Securiforest | |
5 | * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> | |
6 | * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 | |
7 | * | |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
f1ae32a1 | 21 | #include "hw/hw.h" |
1de7afc9 | 22 | #include "qemu/timer.h" |
f1ae32a1 | 23 | #include "hw/usb.h" |
a2cb15b0 MT |
24 | #include "hw/pci/pci.h" |
25 | #include "hw/pci/msi.h" | |
26 | #include "hw/pci/msix.h" | |
2d754a10 | 27 | #include "trace.h" |
62c6ae04 HM |
28 | |
29 | //#define DEBUG_XHCI | |
30 | //#define DEBUG_DATA | |
31 | ||
32 | #ifdef DEBUG_XHCI | |
33 | #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) | |
34 | #else | |
35 | #define DPRINTF(...) do {} while (0) | |
36 | #endif | |
024426ac GH |
37 | #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ |
38 | __func__, __LINE__, _msg); abort(); } while (0) | |
62c6ae04 | 39 | |
d95e74ea GH |
40 | #define MAXPORTS_2 15 |
41 | #define MAXPORTS_3 15 | |
62c6ae04 | 42 | |
0846e635 | 43 | #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) |
d95e74ea GH |
44 | #define MAXSLOTS 64 |
45 | #define MAXINTRS 16 | |
62c6ae04 HM |
46 | |
47 | #define TD_QUEUE 24 | |
62c6ae04 HM |
48 | |
49 | /* Very pessimistic, let's hope it's enough for all cases */ | |
50 | #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) | |
51 | /* Do not deliver ER Full events. NEC's driver does some things not bound | |
52 | * to the specs when it gets them */ | |
53 | #define ER_FULL_HACK | |
54 | ||
55 | #define LEN_CAP 0x40 | |
62c6ae04 | 56 | #define LEN_OPER (0x400 + 0x10 * MAXPORTS) |
106b214c | 57 | #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) |
62c6ae04 HM |
58 | #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) |
59 | ||
106b214c GH |
60 | #define OFF_OPER LEN_CAP |
61 | #define OFF_RUNTIME 0x1000 | |
62 | #define OFF_DOORBELL 0x2000 | |
4c47f800 GH |
63 | #define OFF_MSIX_TABLE 0x3000 |
64 | #define OFF_MSIX_PBA 0x3800 | |
62c6ae04 | 65 | /* must be power of 2 */ |
106b214c | 66 | #define LEN_REGS 0x4000 |
62c6ae04 | 67 | |
106b214c GH |
68 | #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME |
69 | #error Increase OFF_RUNTIME | |
70 | #endif | |
71 | #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL | |
72 | #error Increase OFF_DOORBELL | |
73 | #endif | |
62c6ae04 HM |
74 | #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS |
75 | # error Increase LEN_REGS | |
76 | #endif | |
77 | ||
62c6ae04 HM |
78 | /* bit definitions */ |
79 | #define USBCMD_RS (1<<0) | |
80 | #define USBCMD_HCRST (1<<1) | |
81 | #define USBCMD_INTE (1<<2) | |
82 | #define USBCMD_HSEE (1<<3) | |
83 | #define USBCMD_LHCRST (1<<7) | |
84 | #define USBCMD_CSS (1<<8) | |
85 | #define USBCMD_CRS (1<<9) | |
86 | #define USBCMD_EWE (1<<10) | |
87 | #define USBCMD_EU3S (1<<11) | |
88 | ||
89 | #define USBSTS_HCH (1<<0) | |
90 | #define USBSTS_HSE (1<<2) | |
91 | #define USBSTS_EINT (1<<3) | |
92 | #define USBSTS_PCD (1<<4) | |
93 | #define USBSTS_SSS (1<<8) | |
94 | #define USBSTS_RSS (1<<9) | |
95 | #define USBSTS_SRE (1<<10) | |
96 | #define USBSTS_CNR (1<<11) | |
97 | #define USBSTS_HCE (1<<12) | |
98 | ||
99 | ||
100 | #define PORTSC_CCS (1<<0) | |
101 | #define PORTSC_PED (1<<1) | |
102 | #define PORTSC_OCA (1<<3) | |
103 | #define PORTSC_PR (1<<4) | |
104 | #define PORTSC_PLS_SHIFT 5 | |
105 | #define PORTSC_PLS_MASK 0xf | |
106 | #define PORTSC_PP (1<<9) | |
107 | #define PORTSC_SPEED_SHIFT 10 | |
108 | #define PORTSC_SPEED_MASK 0xf | |
109 | #define PORTSC_SPEED_FULL (1<<10) | |
110 | #define PORTSC_SPEED_LOW (2<<10) | |
111 | #define PORTSC_SPEED_HIGH (3<<10) | |
112 | #define PORTSC_SPEED_SUPER (4<<10) | |
113 | #define PORTSC_PIC_SHIFT 14 | |
114 | #define PORTSC_PIC_MASK 0x3 | |
115 | #define PORTSC_LWS (1<<16) | |
116 | #define PORTSC_CSC (1<<17) | |
117 | #define PORTSC_PEC (1<<18) | |
118 | #define PORTSC_WRC (1<<19) | |
119 | #define PORTSC_OCC (1<<20) | |
120 | #define PORTSC_PRC (1<<21) | |
121 | #define PORTSC_PLC (1<<22) | |
122 | #define PORTSC_CEC (1<<23) | |
123 | #define PORTSC_CAS (1<<24) | |
124 | #define PORTSC_WCE (1<<25) | |
125 | #define PORTSC_WDE (1<<26) | |
126 | #define PORTSC_WOE (1<<27) | |
127 | #define PORTSC_DR (1<<30) | |
128 | #define PORTSC_WPR (1<<31) | |
129 | ||
130 | #define CRCR_RCS (1<<0) | |
131 | #define CRCR_CS (1<<1) | |
132 | #define CRCR_CA (1<<2) | |
133 | #define CRCR_CRR (1<<3) | |
134 | ||
135 | #define IMAN_IP (1<<0) | |
136 | #define IMAN_IE (1<<1) | |
137 | ||
138 | #define ERDP_EHB (1<<3) | |
139 | ||
140 | #define TRB_SIZE 16 | |
141 | typedef struct XHCITRB { | |
142 | uint64_t parameter; | |
143 | uint32_t status; | |
144 | uint32_t control; | |
59a70ccd | 145 | dma_addr_t addr; |
62c6ae04 HM |
146 | bool ccs; |
147 | } XHCITRB; | |
148 | ||
85e05d82 GH |
149 | enum { |
150 | PLS_U0 = 0, | |
151 | PLS_U1 = 1, | |
152 | PLS_U2 = 2, | |
153 | PLS_U3 = 3, | |
154 | PLS_DISABLED = 4, | |
155 | PLS_RX_DETECT = 5, | |
156 | PLS_INACTIVE = 6, | |
157 | PLS_POLLING = 7, | |
158 | PLS_RECOVERY = 8, | |
159 | PLS_HOT_RESET = 9, | |
160 | PLS_COMPILANCE_MODE = 10, | |
161 | PLS_TEST_MODE = 11, | |
162 | PLS_RESUME = 15, | |
163 | }; | |
62c6ae04 HM |
164 | |
165 | typedef enum TRBType { | |
166 | TRB_RESERVED = 0, | |
167 | TR_NORMAL, | |
168 | TR_SETUP, | |
169 | TR_DATA, | |
170 | TR_STATUS, | |
171 | TR_ISOCH, | |
172 | TR_LINK, | |
173 | TR_EVDATA, | |
174 | TR_NOOP, | |
175 | CR_ENABLE_SLOT, | |
176 | CR_DISABLE_SLOT, | |
177 | CR_ADDRESS_DEVICE, | |
178 | CR_CONFIGURE_ENDPOINT, | |
179 | CR_EVALUATE_CONTEXT, | |
180 | CR_RESET_ENDPOINT, | |
181 | CR_STOP_ENDPOINT, | |
182 | CR_SET_TR_DEQUEUE, | |
183 | CR_RESET_DEVICE, | |
184 | CR_FORCE_EVENT, | |
185 | CR_NEGOTIATE_BW, | |
186 | CR_SET_LATENCY_TOLERANCE, | |
187 | CR_GET_PORT_BANDWIDTH, | |
188 | CR_FORCE_HEADER, | |
189 | CR_NOOP, | |
190 | ER_TRANSFER = 32, | |
191 | ER_COMMAND_COMPLETE, | |
192 | ER_PORT_STATUS_CHANGE, | |
193 | ER_BANDWIDTH_REQUEST, | |
194 | ER_DOORBELL, | |
195 | ER_HOST_CONTROLLER, | |
196 | ER_DEVICE_NOTIFICATION, | |
197 | ER_MFINDEX_WRAP, | |
198 | /* vendor specific bits */ | |
199 | CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, | |
200 | CR_VENDOR_NEC_FIRMWARE_REVISION = 49, | |
201 | CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, | |
202 | } TRBType; | |
203 | ||
204 | #define CR_LINK TR_LINK | |
205 | ||
206 | typedef enum TRBCCode { | |
207 | CC_INVALID = 0, | |
208 | CC_SUCCESS, | |
209 | CC_DATA_BUFFER_ERROR, | |
210 | CC_BABBLE_DETECTED, | |
211 | CC_USB_TRANSACTION_ERROR, | |
212 | CC_TRB_ERROR, | |
213 | CC_STALL_ERROR, | |
214 | CC_RESOURCE_ERROR, | |
215 | CC_BANDWIDTH_ERROR, | |
216 | CC_NO_SLOTS_ERROR, | |
217 | CC_INVALID_STREAM_TYPE_ERROR, | |
218 | CC_SLOT_NOT_ENABLED_ERROR, | |
219 | CC_EP_NOT_ENABLED_ERROR, | |
220 | CC_SHORT_PACKET, | |
221 | CC_RING_UNDERRUN, | |
222 | CC_RING_OVERRUN, | |
223 | CC_VF_ER_FULL, | |
224 | CC_PARAMETER_ERROR, | |
225 | CC_BANDWIDTH_OVERRUN, | |
226 | CC_CONTEXT_STATE_ERROR, | |
227 | CC_NO_PING_RESPONSE_ERROR, | |
228 | CC_EVENT_RING_FULL_ERROR, | |
229 | CC_INCOMPATIBLE_DEVICE_ERROR, | |
230 | CC_MISSED_SERVICE_ERROR, | |
231 | CC_COMMAND_RING_STOPPED, | |
232 | CC_COMMAND_ABORTED, | |
233 | CC_STOPPED, | |
234 | CC_STOPPED_LENGTH_INVALID, | |
235 | CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, | |
236 | CC_ISOCH_BUFFER_OVERRUN = 31, | |
237 | CC_EVENT_LOST_ERROR, | |
238 | CC_UNDEFINED_ERROR, | |
239 | CC_INVALID_STREAM_ID_ERROR, | |
240 | CC_SECONDARY_BANDWIDTH_ERROR, | |
241 | CC_SPLIT_TRANSACTION_ERROR | |
242 | } TRBCCode; | |
243 | ||
244 | #define TRB_C (1<<0) | |
245 | #define TRB_TYPE_SHIFT 10 | |
246 | #define TRB_TYPE_MASK 0x3f | |
247 | #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) | |
248 | ||
249 | #define TRB_EV_ED (1<<2) | |
250 | ||
251 | #define TRB_TR_ENT (1<<1) | |
252 | #define TRB_TR_ISP (1<<2) | |
253 | #define TRB_TR_NS (1<<3) | |
254 | #define TRB_TR_CH (1<<4) | |
255 | #define TRB_TR_IOC (1<<5) | |
256 | #define TRB_TR_IDT (1<<6) | |
257 | #define TRB_TR_TBC_SHIFT 7 | |
258 | #define TRB_TR_TBC_MASK 0x3 | |
259 | #define TRB_TR_BEI (1<<9) | |
260 | #define TRB_TR_TLBPC_SHIFT 16 | |
261 | #define TRB_TR_TLBPC_MASK 0xf | |
262 | #define TRB_TR_FRAMEID_SHIFT 20 | |
263 | #define TRB_TR_FRAMEID_MASK 0x7ff | |
264 | #define TRB_TR_SIA (1<<31) | |
265 | ||
266 | #define TRB_TR_DIR (1<<16) | |
267 | ||
268 | #define TRB_CR_SLOTID_SHIFT 24 | |
269 | #define TRB_CR_SLOTID_MASK 0xff | |
270 | #define TRB_CR_EPID_SHIFT 16 | |
271 | #define TRB_CR_EPID_MASK 0x1f | |
272 | ||
273 | #define TRB_CR_BSR (1<<9) | |
274 | #define TRB_CR_DC (1<<9) | |
275 | ||
276 | #define TRB_LK_TC (1<<1) | |
277 | ||
2d1de850 GH |
278 | #define TRB_INTR_SHIFT 22 |
279 | #define TRB_INTR_MASK 0x3ff | |
280 | #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) | |
281 | ||
62c6ae04 HM |
282 | #define EP_TYPE_MASK 0x7 |
283 | #define EP_TYPE_SHIFT 3 | |
284 | ||
285 | #define EP_STATE_MASK 0x7 | |
286 | #define EP_DISABLED (0<<0) | |
287 | #define EP_RUNNING (1<<0) | |
288 | #define EP_HALTED (2<<0) | |
289 | #define EP_STOPPED (3<<0) | |
290 | #define EP_ERROR (4<<0) | |
291 | ||
292 | #define SLOT_STATE_MASK 0x1f | |
293 | #define SLOT_STATE_SHIFT 27 | |
294 | #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) | |
295 | #define SLOT_ENABLED 0 | |
296 | #define SLOT_DEFAULT 1 | |
297 | #define SLOT_ADDRESSED 2 | |
298 | #define SLOT_CONFIGURED 3 | |
299 | ||
300 | #define SLOT_CONTEXT_ENTRIES_MASK 0x1f | |
301 | #define SLOT_CONTEXT_ENTRIES_SHIFT 27 | |
302 | ||
1d8a4e69 | 303 | typedef struct XHCIState XHCIState; |
024426ac GH |
304 | typedef struct XHCIStreamContext XHCIStreamContext; |
305 | typedef struct XHCIEPContext XHCIEPContext; | |
1d8a4e69 | 306 | |
85e05d82 GH |
307 | #define get_field(data, field) \ |
308 | (((data) >> field##_SHIFT) & field##_MASK) | |
309 | ||
310 | #define set_field(data, newval, field) do { \ | |
311 | uint32_t val = *data; \ | |
312 | val &= ~(field##_MASK << field##_SHIFT); \ | |
313 | val |= ((newval) & field##_MASK) << field##_SHIFT; \ | |
314 | *data = val; \ | |
315 | } while (0) | |
316 | ||
62c6ae04 HM |
317 | typedef enum EPType { |
318 | ET_INVALID = 0, | |
319 | ET_ISO_OUT, | |
320 | ET_BULK_OUT, | |
321 | ET_INTR_OUT, | |
322 | ET_CONTROL, | |
323 | ET_ISO_IN, | |
324 | ET_BULK_IN, | |
325 | ET_INTR_IN, | |
326 | } EPType; | |
327 | ||
328 | typedef struct XHCIRing { | |
59a70ccd | 329 | dma_addr_t dequeue; |
62c6ae04 HM |
330 | bool ccs; |
331 | } XHCIRing; | |
332 | ||
333 | typedef struct XHCIPort { | |
1d8a4e69 | 334 | XHCIState *xhci; |
62c6ae04 | 335 | uint32_t portsc; |
0846e635 GH |
336 | uint32_t portnr; |
337 | USBPort *uport; | |
338 | uint32_t speedmask; | |
1d8a4e69 GH |
339 | char name[16]; |
340 | MemoryRegion mem; | |
62c6ae04 HM |
341 | } XHCIPort; |
342 | ||
62c6ae04 HM |
343 | typedef struct XHCITransfer { |
344 | XHCIState *xhci; | |
345 | USBPacket packet; | |
d5a15814 | 346 | QEMUSGList sgl; |
7c605a23 GH |
347 | bool running_async; |
348 | bool running_retry; | |
62c6ae04 | 349 | bool complete; |
a6fb2ddb | 350 | bool int_req; |
62c6ae04 HM |
351 | unsigned int iso_pkts; |
352 | unsigned int slotid; | |
353 | unsigned int epid; | |
024426ac | 354 | unsigned int streamid; |
62c6ae04 HM |
355 | bool in_xfer; |
356 | bool iso_xfer; | |
4d7a81c0 | 357 | bool timed_xfer; |
62c6ae04 HM |
358 | |
359 | unsigned int trb_count; | |
360 | unsigned int trb_alloced; | |
361 | XHCITRB *trbs; | |
362 | ||
62c6ae04 HM |
363 | TRBCCode status; |
364 | ||
365 | unsigned int pkts; | |
366 | unsigned int pktsize; | |
367 | unsigned int cur_pkt; | |
3d139684 GH |
368 | |
369 | uint64_t mfindex_kick; | |
62c6ae04 HM |
370 | } XHCITransfer; |
371 | ||
024426ac GH |
372 | struct XHCIStreamContext { |
373 | dma_addr_t pctx; | |
374 | unsigned int sct; | |
375 | XHCIRing ring; | |
024426ac GH |
376 | }; |
377 | ||
378 | struct XHCIEPContext { | |
3d139684 GH |
379 | XHCIState *xhci; |
380 | unsigned int slotid; | |
381 | unsigned int epid; | |
382 | ||
62c6ae04 HM |
383 | XHCIRing ring; |
384 | unsigned int next_xfer; | |
385 | unsigned int comp_xfer; | |
386 | XHCITransfer transfers[TD_QUEUE]; | |
7c605a23 | 387 | XHCITransfer *retry; |
62c6ae04 | 388 | EPType type; |
59a70ccd | 389 | dma_addr_t pctx; |
62c6ae04 | 390 | unsigned int max_psize; |
62c6ae04 | 391 | uint32_t state; |
3d139684 | 392 | |
024426ac GH |
393 | /* streams */ |
394 | unsigned int max_pstreams; | |
395 | bool lsa; | |
396 | unsigned int nr_pstreams; | |
397 | XHCIStreamContext *pstreams; | |
398 | ||
3d139684 GH |
399 | /* iso xfer scheduling */ |
400 | unsigned int interval; | |
401 | int64_t mfindex_last; | |
402 | QEMUTimer *kick_timer; | |
024426ac | 403 | }; |
62c6ae04 HM |
404 | |
405 | typedef struct XHCISlot { | |
406 | bool enabled; | |
4034e693 | 407 | bool addressed; |
59a70ccd | 408 | dma_addr_t ctx; |
ccaf87a0 | 409 | USBPort *uport; |
62c6ae04 HM |
410 | XHCIEPContext * eps[31]; |
411 | } XHCISlot; | |
412 | ||
413 | typedef struct XHCIEvent { | |
414 | TRBType type; | |
415 | TRBCCode ccode; | |
416 | uint64_t ptr; | |
417 | uint32_t length; | |
418 | uint32_t flags; | |
419 | uint8_t slotid; | |
420 | uint8_t epid; | |
421 | } XHCIEvent; | |
422 | ||
962d11e1 GH |
423 | typedef struct XHCIInterrupter { |
424 | uint32_t iman; | |
425 | uint32_t imod; | |
426 | uint32_t erstsz; | |
427 | uint32_t erstba_low; | |
428 | uint32_t erstba_high; | |
429 | uint32_t erdp_low; | |
430 | uint32_t erdp_high; | |
431 | ||
432 | bool msix_used, er_pcs, er_full; | |
433 | ||
434 | dma_addr_t er_start; | |
435 | uint32_t er_size; | |
436 | unsigned int er_ep_idx; | |
437 | ||
438 | XHCIEvent ev_buffer[EV_QUEUE]; | |
439 | unsigned int ev_buffer_put; | |
440 | unsigned int ev_buffer_get; | |
441 | ||
442 | } XHCIInterrupter; | |
443 | ||
62c6ae04 | 444 | struct XHCIState { |
9b7d3334 AF |
445 | /*< private >*/ |
446 | PCIDevice parent_obj; | |
447 | /*< public >*/ | |
448 | ||
62c6ae04 | 449 | USBBus bus; |
62c6ae04 | 450 | MemoryRegion mem; |
1b067564 GH |
451 | MemoryRegion mem_cap; |
452 | MemoryRegion mem_oper; | |
453 | MemoryRegion mem_runtime; | |
454 | MemoryRegion mem_doorbell; | |
62c6ae04 | 455 | |
0846e635 GH |
456 | /* properties */ |
457 | uint32_t numports_2; | |
458 | uint32_t numports_3; | |
91062ae0 GH |
459 | uint32_t numintrs; |
460 | uint32_t numslots; | |
c5e9b02d | 461 | uint32_t flags; |
0846e635 | 462 | |
62c6ae04 HM |
463 | /* Operational Registers */ |
464 | uint32_t usbcmd; | |
465 | uint32_t usbsts; | |
466 | uint32_t dnctrl; | |
467 | uint32_t crcr_low; | |
468 | uint32_t crcr_high; | |
469 | uint32_t dcbaap_low; | |
470 | uint32_t dcbaap_high; | |
471 | uint32_t config; | |
472 | ||
0846e635 | 473 | USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; |
62c6ae04 HM |
474 | XHCIPort ports[MAXPORTS]; |
475 | XHCISlot slots[MAXSLOTS]; | |
0846e635 | 476 | uint32_t numports; |
62c6ae04 HM |
477 | |
478 | /* Runtime Registers */ | |
01546fa6 GH |
479 | int64_t mfindex_start; |
480 | QEMUTimer *mfwrap_timer; | |
962d11e1 | 481 | XHCIInterrupter intr[MAXINTRS]; |
62c6ae04 HM |
482 | |
483 | XHCIRing cmd_ring; | |
484 | }; | |
485 | ||
37034575 PC |
486 | #define TYPE_XHCI "nec-usb-xhci" |
487 | ||
488 | #define XHCI(obj) \ | |
489 | OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) | |
490 | ||
62c6ae04 HM |
491 | typedef struct XHCIEvRingSeg { |
492 | uint32_t addr_low; | |
493 | uint32_t addr_high; | |
494 | uint32_t size; | |
495 | uint32_t rsvd; | |
496 | } XHCIEvRingSeg; | |
497 | ||
c5e9b02d GH |
498 | enum xhci_flags { |
499 | XHCI_FLAG_USE_MSI = 1, | |
4c47f800 | 500 | XHCI_FLAG_USE_MSI_X, |
7bafd888 | 501 | XHCI_FLAG_SS_FIRST, |
e6043e92 | 502 | XHCI_FLAG_FORCE_PCIE_ENDCAP, |
c5e9b02d GH |
503 | }; |
504 | ||
01546fa6 | 505 | static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
024426ac | 506 | unsigned int epid, unsigned int streamid); |
0bc85da6 GH |
507 | static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, |
508 | unsigned int epid); | |
582d6f4a | 509 | static void xhci_xfer_report(XHCITransfer *xfer); |
962d11e1 GH |
510 | static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); |
511 | static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); | |
518ad5f2 HG |
512 | static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, |
513 | unsigned int slotid, unsigned int epid); | |
01546fa6 | 514 | |
f10de44e GH |
515 | static const char *TRBType_names[] = { |
516 | [TRB_RESERVED] = "TRB_RESERVED", | |
517 | [TR_NORMAL] = "TR_NORMAL", | |
518 | [TR_SETUP] = "TR_SETUP", | |
519 | [TR_DATA] = "TR_DATA", | |
520 | [TR_STATUS] = "TR_STATUS", | |
521 | [TR_ISOCH] = "TR_ISOCH", | |
522 | [TR_LINK] = "TR_LINK", | |
523 | [TR_EVDATA] = "TR_EVDATA", | |
524 | [TR_NOOP] = "TR_NOOP", | |
525 | [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", | |
526 | [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", | |
527 | [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", | |
528 | [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", | |
529 | [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", | |
530 | [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", | |
531 | [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", | |
532 | [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", | |
533 | [CR_RESET_DEVICE] = "CR_RESET_DEVICE", | |
534 | [CR_FORCE_EVENT] = "CR_FORCE_EVENT", | |
535 | [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", | |
536 | [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", | |
537 | [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", | |
538 | [CR_FORCE_HEADER] = "CR_FORCE_HEADER", | |
539 | [CR_NOOP] = "CR_NOOP", | |
540 | [ER_TRANSFER] = "ER_TRANSFER", | |
541 | [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", | |
542 | [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", | |
543 | [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", | |
544 | [ER_DOORBELL] = "ER_DOORBELL", | |
545 | [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", | |
546 | [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", | |
547 | [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", | |
548 | [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", | |
549 | [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", | |
550 | [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", | |
551 | }; | |
552 | ||
873123fe GH |
553 | static const char *TRBCCode_names[] = { |
554 | [CC_INVALID] = "CC_INVALID", | |
555 | [CC_SUCCESS] = "CC_SUCCESS", | |
556 | [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", | |
557 | [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", | |
558 | [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", | |
559 | [CC_TRB_ERROR] = "CC_TRB_ERROR", | |
560 | [CC_STALL_ERROR] = "CC_STALL_ERROR", | |
561 | [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", | |
562 | [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", | |
563 | [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", | |
564 | [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", | |
565 | [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", | |
566 | [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", | |
567 | [CC_SHORT_PACKET] = "CC_SHORT_PACKET", | |
568 | [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", | |
569 | [CC_RING_OVERRUN] = "CC_RING_OVERRUN", | |
570 | [CC_VF_ER_FULL] = "CC_VF_ER_FULL", | |
571 | [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", | |
572 | [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", | |
573 | [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", | |
574 | [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", | |
575 | [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", | |
576 | [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", | |
577 | [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", | |
578 | [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", | |
579 | [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", | |
580 | [CC_STOPPED] = "CC_STOPPED", | |
581 | [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", | |
582 | [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] | |
583 | = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", | |
584 | [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", | |
585 | [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", | |
586 | [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", | |
587 | [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", | |
588 | [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", | |
589 | [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", | |
590 | }; | |
591 | ||
1c82392a GH |
592 | static const char *ep_state_names[] = { |
593 | [EP_DISABLED] = "disabled", | |
594 | [EP_RUNNING] = "running", | |
595 | [EP_HALTED] = "halted", | |
596 | [EP_STOPPED] = "stopped", | |
597 | [EP_ERROR] = "error", | |
598 | }; | |
599 | ||
f10de44e GH |
600 | static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) |
601 | { | |
602 | if (index >= llen || list[index] == NULL) { | |
603 | return "???"; | |
604 | } | |
605 | return list[index]; | |
606 | } | |
607 | ||
608 | static const char *trb_name(XHCITRB *trb) | |
609 | { | |
610 | return lookup_name(TRB_TYPE(*trb), TRBType_names, | |
611 | ARRAY_SIZE(TRBType_names)); | |
612 | } | |
f10de44e | 613 | |
873123fe GH |
614 | static const char *event_name(XHCIEvent *event) |
615 | { | |
616 | return lookup_name(event->ccode, TRBCCode_names, | |
617 | ARRAY_SIZE(TRBCCode_names)); | |
618 | } | |
619 | ||
1c82392a GH |
620 | static const char *ep_state_name(uint32_t state) |
621 | { | |
622 | return lookup_name(state, ep_state_names, | |
623 | ARRAY_SIZE(ep_state_names)); | |
624 | } | |
625 | ||
f9955235 GH |
626 | static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) |
627 | { | |
628 | return xhci->flags & (1 << bit); | |
629 | } | |
630 | ||
01546fa6 GH |
631 | static uint64_t xhci_mfindex_get(XHCIState *xhci) |
632 | { | |
bc72ad67 | 633 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
01546fa6 GH |
634 | return (now - xhci->mfindex_start) / 125000; |
635 | } | |
636 | ||
637 | static void xhci_mfwrap_update(XHCIState *xhci) | |
638 | { | |
639 | const uint32_t bits = USBCMD_RS | USBCMD_EWE; | |
640 | uint32_t mfindex, left; | |
641 | int64_t now; | |
642 | ||
643 | if ((xhci->usbcmd & bits) == bits) { | |
bc72ad67 | 644 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
01546fa6 GH |
645 | mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; |
646 | left = 0x4000 - mfindex; | |
bc72ad67 | 647 | timer_mod(xhci->mfwrap_timer, now + left * 125000); |
01546fa6 | 648 | } else { |
bc72ad67 | 649 | timer_del(xhci->mfwrap_timer); |
01546fa6 GH |
650 | } |
651 | } | |
652 | ||
653 | static void xhci_mfwrap_timer(void *opaque) | |
654 | { | |
655 | XHCIState *xhci = opaque; | |
656 | XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; | |
657 | ||
962d11e1 | 658 | xhci_event(xhci, &wrap, 0); |
01546fa6 GH |
659 | xhci_mfwrap_update(xhci); |
660 | } | |
62c6ae04 | 661 | |
59a70ccd | 662 | static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) |
62c6ae04 | 663 | { |
59a70ccd DG |
664 | if (sizeof(dma_addr_t) == 4) { |
665 | return low; | |
666 | } else { | |
667 | return low | (((dma_addr_t)high << 16) << 16); | |
668 | } | |
62c6ae04 HM |
669 | } |
670 | ||
59a70ccd | 671 | static inline dma_addr_t xhci_mask64(uint64_t addr) |
62c6ae04 | 672 | { |
59a70ccd DG |
673 | if (sizeof(dma_addr_t) == 4) { |
674 | return addr & 0xffffffff; | |
675 | } else { | |
676 | return addr; | |
677 | } | |
62c6ae04 HM |
678 | } |
679 | ||
616b5d53 DG |
680 | static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, |
681 | uint32_t *buf, size_t len) | |
682 | { | |
683 | int i; | |
684 | ||
685 | assert((len % sizeof(uint32_t)) == 0); | |
686 | ||
9b7d3334 | 687 | pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); |
616b5d53 DG |
688 | |
689 | for (i = 0; i < (len / sizeof(uint32_t)); i++) { | |
690 | buf[i] = le32_to_cpu(buf[i]); | |
691 | } | |
692 | } | |
693 | ||
694 | static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, | |
695 | uint32_t *buf, size_t len) | |
696 | { | |
697 | int i; | |
698 | uint32_t tmp[len / sizeof(uint32_t)]; | |
699 | ||
700 | assert((len % sizeof(uint32_t)) == 0); | |
701 | ||
702 | for (i = 0; i < (len / sizeof(uint32_t)); i++) { | |
703 | tmp[i] = cpu_to_le32(buf[i]); | |
704 | } | |
9b7d3334 | 705 | pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); |
616b5d53 DG |
706 | } |
707 | ||
0846e635 GH |
708 | static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) |
709 | { | |
710 | int index; | |
711 | ||
712 | if (!uport->dev) { | |
713 | return NULL; | |
714 | } | |
715 | switch (uport->dev->speed) { | |
716 | case USB_SPEED_LOW: | |
717 | case USB_SPEED_FULL: | |
718 | case USB_SPEED_HIGH: | |
7bafd888 GH |
719 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
720 | index = uport->index + xhci->numports_3; | |
721 | } else { | |
722 | index = uport->index; | |
723 | } | |
0846e635 GH |
724 | break; |
725 | case USB_SPEED_SUPER: | |
7bafd888 GH |
726 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
727 | index = uport->index; | |
728 | } else { | |
729 | index = uport->index + xhci->numports_2; | |
730 | } | |
0846e635 GH |
731 | break; |
732 | default: | |
733 | return NULL; | |
734 | } | |
735 | return &xhci->ports[index]; | |
736 | } | |
737 | ||
4c4abe7c | 738 | static void xhci_intx_update(XHCIState *xhci) |
62c6ae04 | 739 | { |
9b7d3334 | 740 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
62c6ae04 HM |
741 | int level = 0; |
742 | ||
9b7d3334 AF |
743 | if (msix_enabled(pci_dev) || |
744 | msi_enabled(pci_dev)) { | |
4c4abe7c GH |
745 | return; |
746 | } | |
747 | ||
962d11e1 GH |
748 | if (xhci->intr[0].iman & IMAN_IP && |
749 | xhci->intr[0].iman & IMAN_IE && | |
215bff17 | 750 | xhci->usbcmd & USBCMD_INTE) { |
62c6ae04 HM |
751 | level = 1; |
752 | } | |
753 | ||
4c4abe7c | 754 | trace_usb_xhci_irq_intx(level); |
9e64f8a3 | 755 | pci_set_irq(pci_dev, level); |
4c4abe7c GH |
756 | } |
757 | ||
962d11e1 | 758 | static void xhci_msix_update(XHCIState *xhci, int v) |
4c47f800 | 759 | { |
9b7d3334 | 760 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
4c47f800 GH |
761 | bool enabled; |
762 | ||
9b7d3334 | 763 | if (!msix_enabled(pci_dev)) { |
4c47f800 GH |
764 | return; |
765 | } | |
766 | ||
962d11e1 GH |
767 | enabled = xhci->intr[v].iman & IMAN_IE; |
768 | if (enabled == xhci->intr[v].msix_used) { | |
4c47f800 GH |
769 | return; |
770 | } | |
771 | ||
772 | if (enabled) { | |
962d11e1 | 773 | trace_usb_xhci_irq_msix_use(v); |
9b7d3334 | 774 | msix_vector_use(pci_dev, v); |
962d11e1 | 775 | xhci->intr[v].msix_used = true; |
4c47f800 | 776 | } else { |
962d11e1 | 777 | trace_usb_xhci_irq_msix_unuse(v); |
9b7d3334 | 778 | msix_vector_unuse(pci_dev, v); |
962d11e1 | 779 | xhci->intr[v].msix_used = false; |
4c47f800 GH |
780 | } |
781 | } | |
782 | ||
962d11e1 | 783 | static void xhci_intr_raise(XHCIState *xhci, int v) |
4c4abe7c | 784 | { |
9b7d3334 AF |
785 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
786 | ||
962d11e1 GH |
787 | xhci->intr[v].erdp_low |= ERDP_EHB; |
788 | xhci->intr[v].iman |= IMAN_IP; | |
2cae4119 GH |
789 | xhci->usbsts |= USBSTS_EINT; |
790 | ||
962d11e1 | 791 | if (!(xhci->intr[v].iman & IMAN_IE)) { |
4c4abe7c GH |
792 | return; |
793 | } | |
794 | ||
795 | if (!(xhci->usbcmd & USBCMD_INTE)) { | |
796 | return; | |
797 | } | |
798 | ||
9b7d3334 | 799 | if (msix_enabled(pci_dev)) { |
962d11e1 | 800 | trace_usb_xhci_irq_msix(v); |
9b7d3334 | 801 | msix_notify(pci_dev, v); |
4c47f800 GH |
802 | return; |
803 | } | |
804 | ||
9b7d3334 | 805 | if (msi_enabled(pci_dev)) { |
962d11e1 | 806 | trace_usb_xhci_irq_msi(v); |
9b7d3334 | 807 | msi_notify(pci_dev, v); |
4c4abe7c | 808 | return; |
62c6ae04 | 809 | } |
4c4abe7c | 810 | |
962d11e1 GH |
811 | if (v == 0) { |
812 | trace_usb_xhci_irq_intx(1); | |
9e64f8a3 | 813 | pci_irq_assert(pci_dev); |
962d11e1 | 814 | } |
62c6ae04 HM |
815 | } |
816 | ||
817 | static inline int xhci_running(XHCIState *xhci) | |
818 | { | |
962d11e1 | 819 | return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; |
62c6ae04 HM |
820 | } |
821 | ||
822 | static void xhci_die(XHCIState *xhci) | |
823 | { | |
824 | xhci->usbsts |= USBSTS_HCE; | |
d6bb65fc | 825 | DPRINTF("xhci: asserted controller error\n"); |
62c6ae04 HM |
826 | } |
827 | ||
962d11e1 | 828 | static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) |
62c6ae04 | 829 | { |
9b7d3334 | 830 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
962d11e1 | 831 | XHCIInterrupter *intr = &xhci->intr[v]; |
62c6ae04 | 832 | XHCITRB ev_trb; |
59a70ccd | 833 | dma_addr_t addr; |
62c6ae04 HM |
834 | |
835 | ev_trb.parameter = cpu_to_le64(event->ptr); | |
836 | ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); | |
837 | ev_trb.control = (event->slotid << 24) | (event->epid << 16) | | |
838 | event->flags | (event->type << TRB_TYPE_SHIFT); | |
962d11e1 | 839 | if (intr->er_pcs) { |
62c6ae04 HM |
840 | ev_trb.control |= TRB_C; |
841 | } | |
842 | ev_trb.control = cpu_to_le32(ev_trb.control); | |
843 | ||
962d11e1 | 844 | trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), |
873123fe GH |
845 | event_name(event), ev_trb.parameter, |
846 | ev_trb.status, ev_trb.control); | |
62c6ae04 | 847 | |
962d11e1 | 848 | addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; |
9b7d3334 | 849 | pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); |
62c6ae04 | 850 | |
962d11e1 GH |
851 | intr->er_ep_idx++; |
852 | if (intr->er_ep_idx >= intr->er_size) { | |
853 | intr->er_ep_idx = 0; | |
854 | intr->er_pcs = !intr->er_pcs; | |
62c6ae04 HM |
855 | } |
856 | } | |
857 | ||
962d11e1 | 858 | static void xhci_events_update(XHCIState *xhci, int v) |
62c6ae04 | 859 | { |
962d11e1 | 860 | XHCIInterrupter *intr = &xhci->intr[v]; |
59a70ccd | 861 | dma_addr_t erdp; |
62c6ae04 HM |
862 | unsigned int dp_idx; |
863 | bool do_irq = 0; | |
864 | ||
865 | if (xhci->usbsts & USBSTS_HCH) { | |
866 | return; | |
867 | } | |
868 | ||
962d11e1 GH |
869 | erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
870 | if (erdp < intr->er_start || | |
871 | erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { | |
d6bb65fc GH |
872 | DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
873 | DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", | |
962d11e1 | 874 | v, intr->er_start, intr->er_size); |
62c6ae04 HM |
875 | xhci_die(xhci); |
876 | return; | |
877 | } | |
962d11e1 GH |
878 | dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
879 | assert(dp_idx < intr->er_size); | |
62c6ae04 HM |
880 | |
881 | /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus | |
882 | * deadlocks when the ER is full. Hack it by holding off events until | |
883 | * the driver decides to free at least half of the ring */ | |
962d11e1 GH |
884 | if (intr->er_full) { |
885 | int er_free = dp_idx - intr->er_ep_idx; | |
62c6ae04 | 886 | if (er_free <= 0) { |
962d11e1 | 887 | er_free += intr->er_size; |
62c6ae04 | 888 | } |
962d11e1 | 889 | if (er_free < (intr->er_size/2)) { |
62c6ae04 HM |
890 | DPRINTF("xhci_events_update(): event ring still " |
891 | "more than half full (hack)\n"); | |
892 | return; | |
893 | } | |
894 | } | |
895 | ||
962d11e1 GH |
896 | while (intr->ev_buffer_put != intr->ev_buffer_get) { |
897 | assert(intr->er_full); | |
898 | if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { | |
62c6ae04 HM |
899 | DPRINTF("xhci_events_update(): event ring full again\n"); |
900 | #ifndef ER_FULL_HACK | |
901 | XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; | |
962d11e1 | 902 | xhci_write_event(xhci, &full, v); |
62c6ae04 HM |
903 | #endif |
904 | do_irq = 1; | |
905 | break; | |
906 | } | |
962d11e1 GH |
907 | XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; |
908 | xhci_write_event(xhci, event, v); | |
909 | intr->ev_buffer_get++; | |
62c6ae04 | 910 | do_irq = 1; |
962d11e1 GH |
911 | if (intr->ev_buffer_get == EV_QUEUE) { |
912 | intr->ev_buffer_get = 0; | |
62c6ae04 HM |
913 | } |
914 | } | |
915 | ||
916 | if (do_irq) { | |
962d11e1 | 917 | xhci_intr_raise(xhci, v); |
62c6ae04 HM |
918 | } |
919 | ||
962d11e1 | 920 | if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { |
62c6ae04 | 921 | DPRINTF("xhci_events_update(): event ring no longer full\n"); |
962d11e1 | 922 | intr->er_full = 0; |
62c6ae04 | 923 | } |
62c6ae04 HM |
924 | } |
925 | ||
962d11e1 | 926 | static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) |
62c6ae04 | 927 | { |
2d1de850 | 928 | XHCIInterrupter *intr; |
59a70ccd | 929 | dma_addr_t erdp; |
62c6ae04 HM |
930 | unsigned int dp_idx; |
931 | ||
91062ae0 GH |
932 | if (v >= xhci->numintrs) { |
933 | DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); | |
2d1de850 GH |
934 | return; |
935 | } | |
936 | intr = &xhci->intr[v]; | |
937 | ||
962d11e1 | 938 | if (intr->er_full) { |
62c6ae04 | 939 | DPRINTF("xhci_event(): ER full, queueing\n"); |
962d11e1 | 940 | if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { |
d6bb65fc | 941 | DPRINTF("xhci: event queue full, dropping event!\n"); |
62c6ae04 HM |
942 | return; |
943 | } | |
962d11e1 GH |
944 | intr->ev_buffer[intr->ev_buffer_put++] = *event; |
945 | if (intr->ev_buffer_put == EV_QUEUE) { | |
946 | intr->ev_buffer_put = 0; | |
62c6ae04 HM |
947 | } |
948 | return; | |
949 | } | |
950 | ||
962d11e1 GH |
951 | erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
952 | if (erdp < intr->er_start || | |
953 | erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { | |
d6bb65fc GH |
954 | DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
955 | DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", | |
962d11e1 | 956 | v, intr->er_start, intr->er_size); |
62c6ae04 HM |
957 | xhci_die(xhci); |
958 | return; | |
959 | } | |
960 | ||
962d11e1 GH |
961 | dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
962 | assert(dp_idx < intr->er_size); | |
62c6ae04 | 963 | |
962d11e1 | 964 | if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { |
62c6ae04 HM |
965 | DPRINTF("xhci_event(): ER full, queueing\n"); |
966 | #ifndef ER_FULL_HACK | |
967 | XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; | |
968 | xhci_write_event(xhci, &full); | |
969 | #endif | |
962d11e1 GH |
970 | intr->er_full = 1; |
971 | if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { | |
d6bb65fc | 972 | DPRINTF("xhci: event queue full, dropping event!\n"); |
62c6ae04 HM |
973 | return; |
974 | } | |
962d11e1 GH |
975 | intr->ev_buffer[intr->ev_buffer_put++] = *event; |
976 | if (intr->ev_buffer_put == EV_QUEUE) { | |
977 | intr->ev_buffer_put = 0; | |
62c6ae04 HM |
978 | } |
979 | } else { | |
962d11e1 | 980 | xhci_write_event(xhci, event, v); |
62c6ae04 HM |
981 | } |
982 | ||
962d11e1 | 983 | xhci_intr_raise(xhci, v); |
62c6ae04 HM |
984 | } |
985 | ||
986 | static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, | |
59a70ccd | 987 | dma_addr_t base) |
62c6ae04 | 988 | { |
62c6ae04 HM |
989 | ring->dequeue = base; |
990 | ring->ccs = 1; | |
991 | } | |
992 | ||
993 | static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, | |
59a70ccd | 994 | dma_addr_t *addr) |
62c6ae04 | 995 | { |
9b7d3334 AF |
996 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
997 | ||
62c6ae04 HM |
998 | while (1) { |
999 | TRBType type; | |
9b7d3334 | 1000 | pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); |
62c6ae04 HM |
1001 | trb->addr = ring->dequeue; |
1002 | trb->ccs = ring->ccs; | |
1003 | le64_to_cpus(&trb->parameter); | |
1004 | le32_to_cpus(&trb->status); | |
1005 | le32_to_cpus(&trb->control); | |
1006 | ||
0703a4a7 GH |
1007 | trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), |
1008 | trb->parameter, trb->status, trb->control); | |
62c6ae04 HM |
1009 | |
1010 | if ((trb->control & TRB_C) != ring->ccs) { | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | type = TRB_TYPE(*trb); | |
1015 | ||
1016 | if (type != TR_LINK) { | |
1017 | if (addr) { | |
1018 | *addr = ring->dequeue; | |
1019 | } | |
1020 | ring->dequeue += TRB_SIZE; | |
1021 | return type; | |
1022 | } else { | |
1023 | ring->dequeue = xhci_mask64(trb->parameter); | |
1024 | if (trb->control & TRB_LK_TC) { | |
1025 | ring->ccs = !ring->ccs; | |
1026 | } | |
1027 | } | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) | |
1032 | { | |
9b7d3334 | 1033 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
62c6ae04 HM |
1034 | XHCITRB trb; |
1035 | int length = 0; | |
59a70ccd | 1036 | dma_addr_t dequeue = ring->dequeue; |
62c6ae04 HM |
1037 | bool ccs = ring->ccs; |
1038 | /* hack to bundle together the two/three TDs that make a setup transfer */ | |
1039 | bool control_td_set = 0; | |
1040 | ||
1041 | while (1) { | |
1042 | TRBType type; | |
9b7d3334 | 1043 | pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); |
62c6ae04 HM |
1044 | le64_to_cpus(&trb.parameter); |
1045 | le32_to_cpus(&trb.status); | |
1046 | le32_to_cpus(&trb.control); | |
1047 | ||
62c6ae04 HM |
1048 | if ((trb.control & TRB_C) != ccs) { |
1049 | return -length; | |
1050 | } | |
1051 | ||
1052 | type = TRB_TYPE(trb); | |
1053 | ||
1054 | if (type == TR_LINK) { | |
1055 | dequeue = xhci_mask64(trb.parameter); | |
1056 | if (trb.control & TRB_LK_TC) { | |
1057 | ccs = !ccs; | |
1058 | } | |
1059 | continue; | |
1060 | } | |
1061 | ||
1062 | length += 1; | |
1063 | dequeue += TRB_SIZE; | |
1064 | ||
1065 | if (type == TR_SETUP) { | |
1066 | control_td_set = 1; | |
1067 | } else if (type == TR_STATUS) { | |
1068 | control_td_set = 0; | |
1069 | } | |
1070 | ||
1071 | if (!control_td_set && !(trb.control & TRB_TR_CH)) { | |
1072 | return length; | |
1073 | } | |
1074 | } | |
1075 | } | |
1076 | ||
962d11e1 | 1077 | static void xhci_er_reset(XHCIState *xhci, int v) |
62c6ae04 | 1078 | { |
962d11e1 | 1079 | XHCIInterrupter *intr = &xhci->intr[v]; |
62c6ae04 HM |
1080 | XHCIEvRingSeg seg; |
1081 | ||
e099ad4b GH |
1082 | if (intr->erstsz == 0) { |
1083 | /* disabled */ | |
1084 | intr->er_start = 0; | |
1085 | intr->er_size = 0; | |
1086 | return; | |
1087 | } | |
62c6ae04 | 1088 | /* cache the (sole) event ring segment location */ |
962d11e1 | 1089 | if (intr->erstsz != 1) { |
d6bb65fc | 1090 | DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); |
62c6ae04 HM |
1091 | xhci_die(xhci); |
1092 | return; | |
1093 | } | |
962d11e1 | 1094 | dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); |
9b7d3334 | 1095 | pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); |
62c6ae04 HM |
1096 | le32_to_cpus(&seg.addr_low); |
1097 | le32_to_cpus(&seg.addr_high); | |
1098 | le32_to_cpus(&seg.size); | |
1099 | if (seg.size < 16 || seg.size > 4096) { | |
d6bb65fc | 1100 | DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); |
62c6ae04 HM |
1101 | xhci_die(xhci); |
1102 | return; | |
1103 | } | |
962d11e1 GH |
1104 | intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); |
1105 | intr->er_size = seg.size; | |
62c6ae04 | 1106 | |
962d11e1 GH |
1107 | intr->er_ep_idx = 0; |
1108 | intr->er_pcs = 1; | |
1109 | intr->er_full = 0; | |
62c6ae04 | 1110 | |
962d11e1 GH |
1111 | DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", |
1112 | v, intr->er_start, intr->er_size); | |
62c6ae04 HM |
1113 | } |
1114 | ||
1115 | static void xhci_run(XHCIState *xhci) | |
1116 | { | |
fc0ddaca | 1117 | trace_usb_xhci_run(); |
62c6ae04 | 1118 | xhci->usbsts &= ~USBSTS_HCH; |
bc72ad67 | 1119 | xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
62c6ae04 HM |
1120 | } |
1121 | ||
1122 | static void xhci_stop(XHCIState *xhci) | |
1123 | { | |
fc0ddaca | 1124 | trace_usb_xhci_stop(); |
62c6ae04 HM |
1125 | xhci->usbsts |= USBSTS_HCH; |
1126 | xhci->crcr_low &= ~CRCR_CRR; | |
1127 | } | |
1128 | ||
024426ac GH |
1129 | static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, |
1130 | dma_addr_t base) | |
1131 | { | |
1132 | XHCIStreamContext *stctx; | |
1133 | unsigned int i; | |
1134 | ||
1135 | stctx = g_new0(XHCIStreamContext, count); | |
1136 | for (i = 0; i < count; i++) { | |
1137 | stctx[i].pctx = base + i * 16; | |
1138 | stctx[i].sct = -1; | |
1139 | } | |
1140 | return stctx; | |
1141 | } | |
1142 | ||
1143 | static void xhci_reset_streams(XHCIEPContext *epctx) | |
1144 | { | |
1145 | unsigned int i; | |
1146 | ||
1147 | for (i = 0; i < epctx->nr_pstreams; i++) { | |
1148 | epctx->pstreams[i].sct = -1; | |
024426ac GH |
1149 | } |
1150 | } | |
1151 | ||
1152 | static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) | |
1153 | { | |
1154 | assert(epctx->pstreams == NULL); | |
f90e160b | 1155 | epctx->nr_pstreams = 2 << epctx->max_pstreams; |
024426ac GH |
1156 | epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); |
1157 | } | |
1158 | ||
1159 | static void xhci_free_streams(XHCIEPContext *epctx) | |
1160 | { | |
024426ac GH |
1161 | assert(epctx->pstreams != NULL); |
1162 | ||
024426ac GH |
1163 | g_free(epctx->pstreams); |
1164 | epctx->pstreams = NULL; | |
1165 | epctx->nr_pstreams = 0; | |
1166 | } | |
1167 | ||
72391da5 HG |
1168 | static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, |
1169 | unsigned int slotid, | |
1170 | uint32_t epmask, | |
1171 | XHCIEPContext **epctxs, | |
1172 | USBEndpoint **eps) | |
1173 | { | |
1174 | XHCISlot *slot; | |
1175 | XHCIEPContext *epctx; | |
1176 | USBEndpoint *ep; | |
1177 | int i, j; | |
1178 | ||
1179 | assert(slotid >= 1 && slotid <= xhci->numslots); | |
1180 | ||
1181 | slot = &xhci->slots[slotid - 1]; | |
1182 | ||
1183 | for (i = 2, j = 0; i <= 31; i++) { | |
3d80365b | 1184 | if (!(epmask & (1u << i))) { |
72391da5 HG |
1185 | continue; |
1186 | } | |
1187 | ||
1188 | epctx = slot->eps[i - 1]; | |
1189 | ep = xhci_epid_to_usbep(xhci, slotid, i); | |
1190 | if (!epctx || !epctx->nr_pstreams || !ep) { | |
1191 | continue; | |
1192 | } | |
1193 | ||
1194 | if (epctxs) { | |
1195 | epctxs[j] = epctx; | |
1196 | } | |
1197 | eps[j++] = ep; | |
1198 | } | |
1199 | return j; | |
1200 | } | |
1201 | ||
1202 | static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, | |
1203 | uint32_t epmask) | |
1204 | { | |
1205 | USBEndpoint *eps[30]; | |
1206 | int nr_eps; | |
1207 | ||
1208 | nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); | |
1209 | if (nr_eps) { | |
1210 | usb_device_free_streams(eps[0]->dev, eps, nr_eps); | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, | |
1215 | uint32_t epmask) | |
1216 | { | |
1217 | XHCIEPContext *epctxs[30]; | |
1218 | USBEndpoint *eps[30]; | |
1219 | int i, r, nr_eps, req_nr_streams, dev_max_streams; | |
1220 | ||
1221 | nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, | |
1222 | eps); | |
1223 | if (nr_eps == 0) { | |
1224 | return CC_SUCCESS; | |
1225 | } | |
1226 | ||
1227 | req_nr_streams = epctxs[0]->nr_pstreams; | |
1228 | dev_max_streams = eps[0]->max_streams; | |
1229 | ||
1230 | for (i = 1; i < nr_eps; i++) { | |
1231 | /* | |
1232 | * HdG: I don't expect these to ever trigger, but if they do we need | |
1233 | * to come up with another solution, ie group identical endpoints | |
1234 | * together and make an usb_device_alloc_streams call per group. | |
1235 | */ | |
1236 | if (epctxs[i]->nr_pstreams != req_nr_streams) { | |
1237 | FIXME("guest streams config not identical for all eps"); | |
1238 | return CC_RESOURCE_ERROR; | |
1239 | } | |
1240 | if (eps[i]->max_streams != dev_max_streams) { | |
1241 | FIXME("device streams config not identical for all eps"); | |
1242 | return CC_RESOURCE_ERROR; | |
1243 | } | |
1244 | } | |
1245 | ||
1246 | /* | |
1247 | * max-streams in both the device descriptor and in the controller is a | |
1248 | * power of 2. But stream id 0 is reserved, so if a device can do up to 4 | |
1249 | * streams the guest will ask for 5 rounded up to the next power of 2 which | |
1250 | * becomes 8. For emulated devices usb_device_alloc_streams is a nop. | |
1251 | * | |
1252 | * For redirected devices however this is an issue, as there we must ask | |
1253 | * the real xhci controller to alloc streams, and the host driver for the | |
1254 | * real xhci controller will likely disallow allocating more streams then | |
1255 | * the device can handle. | |
1256 | * | |
1257 | * So we limit the requested nr_streams to the maximum number the device | |
1258 | * can handle. | |
1259 | */ | |
1260 | if (req_nr_streams > dev_max_streams) { | |
1261 | req_nr_streams = dev_max_streams; | |
1262 | } | |
1263 | ||
1264 | r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); | |
1265 | if (r != 0) { | |
d6bb65fc | 1266 | DPRINTF("xhci: alloc streams failed\n"); |
72391da5 HG |
1267 | return CC_RESOURCE_ERROR; |
1268 | } | |
1269 | ||
1270 | return CC_SUCCESS; | |
1271 | } | |
1272 | ||
024426ac GH |
1273 | static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, |
1274 | unsigned int streamid, | |
1275 | uint32_t *cc_error) | |
1276 | { | |
1277 | XHCIStreamContext *sctx; | |
1278 | dma_addr_t base; | |
1279 | uint32_t ctx[2], sct; | |
1280 | ||
1281 | assert(streamid != 0); | |
1282 | if (epctx->lsa) { | |
1283 | if (streamid >= epctx->nr_pstreams) { | |
1284 | *cc_error = CC_INVALID_STREAM_ID_ERROR; | |
1285 | return NULL; | |
1286 | } | |
1287 | sctx = epctx->pstreams + streamid; | |
1288 | } else { | |
1289 | FIXME("secondary streams not implemented yet"); | |
1290 | } | |
1291 | ||
1292 | if (sctx->sct == -1) { | |
1293 | xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); | |
024426ac GH |
1294 | sct = (ctx[0] >> 1) & 0x07; |
1295 | if (epctx->lsa && sct != 1) { | |
1296 | *cc_error = CC_INVALID_STREAM_TYPE_ERROR; | |
1297 | return NULL; | |
1298 | } | |
1299 | sctx->sct = sct; | |
1300 | base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); | |
1301 | xhci_ring_init(epctx->xhci, &sctx->ring, base); | |
1302 | } | |
1303 | return sctx; | |
1304 | } | |
1305 | ||
62c6ae04 | 1306 | static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
024426ac | 1307 | XHCIStreamContext *sctx, uint32_t state) |
62c6ae04 | 1308 | { |
c90daa1c | 1309 | XHCIRing *ring = NULL; |
62c6ae04 | 1310 | uint32_t ctx[5]; |
024426ac | 1311 | uint32_t ctx2[2]; |
62c6ae04 | 1312 | |
616b5d53 | 1313 | xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); |
62c6ae04 HM |
1314 | ctx[0] &= ~EP_STATE_MASK; |
1315 | ctx[0] |= state; | |
024426ac GH |
1316 | |
1317 | /* update ring dequeue ptr */ | |
1318 | if (epctx->nr_pstreams) { | |
1319 | if (sctx != NULL) { | |
c90daa1c | 1320 | ring = &sctx->ring; |
024426ac GH |
1321 | xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); |
1322 | ctx2[0] &= 0xe; | |
1323 | ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; | |
1324 | ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; | |
1325 | xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); | |
1326 | } | |
1327 | } else { | |
c90daa1c HG |
1328 | ring = &epctx->ring; |
1329 | } | |
1330 | if (ring) { | |
1331 | ctx[2] = ring->dequeue | ring->ccs; | |
1332 | ctx[3] = (ring->dequeue >> 16) >> 16; | |
1333 | ||
024426ac GH |
1334 | DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", |
1335 | epctx->pctx, state, ctx[3], ctx[2]); | |
1336 | } | |
1337 | ||
616b5d53 | 1338 | xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); |
1c82392a GH |
1339 | if (epctx->state != state) { |
1340 | trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, | |
1341 | ep_state_name(epctx->state), | |
1342 | ep_state_name(state)); | |
1343 | } | |
62c6ae04 HM |
1344 | epctx->state = state; |
1345 | } | |
1346 | ||
3d139684 GH |
1347 | static void xhci_ep_kick_timer(void *opaque) |
1348 | { | |
1349 | XHCIEPContext *epctx = opaque; | |
024426ac | 1350 | xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); |
3d139684 GH |
1351 | } |
1352 | ||
492b21f6 GH |
1353 | static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, |
1354 | unsigned int slotid, | |
1355 | unsigned int epid) | |
1356 | { | |
1357 | XHCIEPContext *epctx; | |
1358 | int i; | |
1359 | ||
1360 | epctx = g_new0(XHCIEPContext, 1); | |
1361 | epctx->xhci = xhci; | |
1362 | epctx->slotid = slotid; | |
1363 | epctx->epid = epid; | |
1364 | ||
1365 | for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { | |
4c5d82ec HG |
1366 | epctx->transfers[i].xhci = xhci; |
1367 | epctx->transfers[i].slotid = slotid; | |
1368 | epctx->transfers[i].epid = epid; | |
492b21f6 GH |
1369 | usb_packet_init(&epctx->transfers[i].packet); |
1370 | } | |
bc72ad67 | 1371 | epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); |
492b21f6 GH |
1372 | |
1373 | return epctx; | |
1374 | } | |
1375 | ||
003e15a1 GH |
1376 | static void xhci_init_epctx(XHCIEPContext *epctx, |
1377 | dma_addr_t pctx, uint32_t *ctx) | |
62c6ae04 | 1378 | { |
59a70ccd | 1379 | dma_addr_t dequeue; |
62c6ae04 | 1380 | |
62c6ae04 | 1381 | dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); |
62c6ae04 HM |
1382 | |
1383 | epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; | |
62c6ae04 HM |
1384 | epctx->pctx = pctx; |
1385 | epctx->max_psize = ctx[1]>>16; | |
1386 | epctx->max_psize *= 1+((ctx[1]>>8)&0xff); | |
024426ac GH |
1387 | epctx->max_pstreams = (ctx[0] >> 10) & 0xf; |
1388 | epctx->lsa = (ctx[0] >> 15) & 1; | |
024426ac GH |
1389 | if (epctx->max_pstreams) { |
1390 | xhci_alloc_streams(epctx, dequeue); | |
1391 | } else { | |
003e15a1 | 1392 | xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); |
024426ac GH |
1393 | epctx->ring.ccs = ctx[2] & 1; |
1394 | } | |
62c6ae04 | 1395 | |
ca716278 | 1396 | epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); |
003e15a1 GH |
1397 | } |
1398 | ||
1399 | static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, | |
1400 | unsigned int epid, dma_addr_t pctx, | |
1401 | uint32_t *ctx) | |
1402 | { | |
1403 | XHCISlot *slot; | |
1404 | XHCIEPContext *epctx; | |
1405 | ||
1406 | trace_usb_xhci_ep_enable(slotid, epid); | |
1407 | assert(slotid >= 1 && slotid <= xhci->numslots); | |
1408 | assert(epid >= 1 && epid <= 31); | |
1409 | ||
1410 | slot = &xhci->slots[slotid-1]; | |
1411 | if (slot->eps[epid-1]) { | |
1412 | xhci_disable_ep(xhci, slotid, epid); | |
1413 | } | |
1414 | ||
1415 | epctx = xhci_alloc_epctx(xhci, slotid, epid); | |
1416 | slot->eps[epid-1] = epctx; | |
1417 | xhci_init_epctx(epctx, pctx, ctx); | |
1418 | ||
8c244210 GA |
1419 | DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " |
1420 | "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); | |
1421 | ||
3d139684 | 1422 | epctx->mfindex_last = 0; |
3d139684 | 1423 | |
62c6ae04 HM |
1424 | epctx->state = EP_RUNNING; |
1425 | ctx[0] &= ~EP_STATE_MASK; | |
1426 | ctx[0] |= EP_RUNNING; | |
1427 | ||
1428 | return CC_SUCCESS; | |
1429 | } | |
1430 | ||
582d6f4a | 1431 | static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) |
3151f209 HG |
1432 | { |
1433 | int killed = 0; | |
1434 | ||
582d6f4a HG |
1435 | if (report && (t->running_async || t->running_retry)) { |
1436 | t->status = report; | |
1437 | xhci_xfer_report(t); | |
1438 | } | |
1439 | ||
3151f209 HG |
1440 | if (t->running_async) { |
1441 | usb_cancel_packet(&t->packet); | |
1442 | t->running_async = 0; | |
3151f209 HG |
1443 | killed = 1; |
1444 | } | |
1445 | if (t->running_retry) { | |
1446 | XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; | |
1447 | if (epctx) { | |
1448 | epctx->retry = NULL; | |
bc72ad67 | 1449 | timer_del(epctx->kick_timer); |
3151f209 HG |
1450 | } |
1451 | t->running_retry = 0; | |
582d6f4a | 1452 | killed = 1; |
3151f209 HG |
1453 | } |
1454 | if (t->trbs) { | |
1455 | g_free(t->trbs); | |
1456 | } | |
1457 | ||
1458 | t->trbs = NULL; | |
1459 | t->trb_count = t->trb_alloced = 0; | |
1460 | ||
1461 | return killed; | |
1462 | } | |
1463 | ||
62c6ae04 | 1464 | static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, |
582d6f4a | 1465 | unsigned int epid, TRBCCode report) |
62c6ae04 HM |
1466 | { |
1467 | XHCISlot *slot; | |
1468 | XHCIEPContext *epctx; | |
1469 | int i, xferi, killed = 0; | |
f79738b0 | 1470 | USBEndpoint *ep = NULL; |
91062ae0 | 1471 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1472 | assert(epid >= 1 && epid <= 31); |
1473 | ||
1474 | DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); | |
1475 | ||
1476 | slot = &xhci->slots[slotid-1]; | |
1477 | ||
1478 | if (!slot->eps[epid-1]) { | |
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | epctx = slot->eps[epid-1]; | |
1483 | ||
1484 | xferi = epctx->next_xfer; | |
1485 | for (i = 0; i < TD_QUEUE; i++) { | |
582d6f4a HG |
1486 | killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report); |
1487 | if (killed) { | |
1488 | report = 0; /* Only report once */ | |
1489 | } | |
0cb41e2c | 1490 | epctx->transfers[xferi].packet.ep = NULL; |
62c6ae04 HM |
1491 | xferi = (xferi + 1) % TD_QUEUE; |
1492 | } | |
518ad5f2 HG |
1493 | |
1494 | ep = xhci_epid_to_usbep(xhci, slotid, epid); | |
f79738b0 HG |
1495 | if (ep) { |
1496 | usb_device_ep_stopped(ep->dev, ep); | |
1497 | } | |
62c6ae04 HM |
1498 | return killed; |
1499 | } | |
1500 | ||
1501 | static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, | |
1502 | unsigned int epid) | |
1503 | { | |
1504 | XHCISlot *slot; | |
1505 | XHCIEPContext *epctx; | |
b21da4e5 | 1506 | int i; |
62c6ae04 | 1507 | |
c1f6b493 | 1508 | trace_usb_xhci_ep_disable(slotid, epid); |
91062ae0 | 1509 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1510 | assert(epid >= 1 && epid <= 31); |
1511 | ||
62c6ae04 HM |
1512 | slot = &xhci->slots[slotid-1]; |
1513 | ||
1514 | if (!slot->eps[epid-1]) { | |
1515 | DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); | |
1516 | return CC_SUCCESS; | |
1517 | } | |
1518 | ||
582d6f4a | 1519 | xhci_ep_nuke_xfers(xhci, slotid, epid, 0); |
62c6ae04 HM |
1520 | |
1521 | epctx = slot->eps[epid-1]; | |
1522 | ||
024426ac GH |
1523 | if (epctx->nr_pstreams) { |
1524 | xhci_free_streams(epctx); | |
1525 | } | |
1526 | ||
b21da4e5 HG |
1527 | for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { |
1528 | usb_packet_cleanup(&epctx->transfers[i].packet); | |
1529 | } | |
1530 | ||
024426ac | 1531 | xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); |
62c6ae04 | 1532 | |
bc72ad67 | 1533 | timer_free(epctx->kick_timer); |
62c6ae04 HM |
1534 | g_free(epctx); |
1535 | slot->eps[epid-1] = NULL; | |
1536 | ||
1537 | return CC_SUCCESS; | |
1538 | } | |
1539 | ||
1540 | static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, | |
1541 | unsigned int epid) | |
1542 | { | |
1543 | XHCISlot *slot; | |
1544 | XHCIEPContext *epctx; | |
1545 | ||
c1f6b493 | 1546 | trace_usb_xhci_ep_stop(slotid, epid); |
91062ae0 | 1547 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1548 | |
1549 | if (epid < 1 || epid > 31) { | |
d6bb65fc | 1550 | DPRINTF("xhci: bad ep %d\n", epid); |
62c6ae04 HM |
1551 | return CC_TRB_ERROR; |
1552 | } | |
1553 | ||
1554 | slot = &xhci->slots[slotid-1]; | |
1555 | ||
1556 | if (!slot->eps[epid-1]) { | |
1557 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1558 | return CC_EP_NOT_ENABLED_ERROR; | |
1559 | } | |
1560 | ||
582d6f4a | 1561 | if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { |
d6bb65fc | 1562 | DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " |
62c6ae04 HM |
1563 | "data might be lost\n"); |
1564 | } | |
1565 | ||
1566 | epctx = slot->eps[epid-1]; | |
1567 | ||
024426ac GH |
1568 | xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); |
1569 | ||
1570 | if (epctx->nr_pstreams) { | |
1571 | xhci_reset_streams(epctx); | |
1572 | } | |
62c6ae04 HM |
1573 | |
1574 | return CC_SUCCESS; | |
1575 | } | |
1576 | ||
1577 | static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, | |
1578 | unsigned int epid) | |
1579 | { | |
1580 | XHCISlot *slot; | |
1581 | XHCIEPContext *epctx; | |
62c6ae04 | 1582 | |
c1f6b493 | 1583 | trace_usb_xhci_ep_reset(slotid, epid); |
91062ae0 | 1584 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 1585 | |
62c6ae04 | 1586 | if (epid < 1 || epid > 31) { |
d6bb65fc | 1587 | DPRINTF("xhci: bad ep %d\n", epid); |
62c6ae04 HM |
1588 | return CC_TRB_ERROR; |
1589 | } | |
1590 | ||
1591 | slot = &xhci->slots[slotid-1]; | |
1592 | ||
1593 | if (!slot->eps[epid-1]) { | |
1594 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1595 | return CC_EP_NOT_ENABLED_ERROR; | |
1596 | } | |
1597 | ||
1598 | epctx = slot->eps[epid-1]; | |
1599 | ||
1600 | if (epctx->state != EP_HALTED) { | |
d6bb65fc | 1601 | DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", |
62c6ae04 HM |
1602 | epid, epctx->state); |
1603 | return CC_CONTEXT_STATE_ERROR; | |
1604 | } | |
1605 | ||
582d6f4a | 1606 | if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { |
d6bb65fc | 1607 | DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " |
62c6ae04 HM |
1608 | "data might be lost\n"); |
1609 | } | |
1610 | ||
1611 | uint8_t ep = epid>>1; | |
1612 | ||
1613 | if (epid & 1) { | |
1614 | ep |= 0x80; | |
1615 | } | |
1616 | ||
75cc1c1f | 1617 | if (!xhci->slots[slotid-1].uport || |
de9de157 HG |
1618 | !xhci->slots[slotid-1].uport->dev || |
1619 | !xhci->slots[slotid-1].uport->dev->attached) { | |
62c6ae04 HM |
1620 | return CC_USB_TRANSACTION_ERROR; |
1621 | } | |
1622 | ||
024426ac GH |
1623 | xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); |
1624 | ||
1625 | if (epctx->nr_pstreams) { | |
1626 | xhci_reset_streams(epctx); | |
1627 | } | |
62c6ae04 HM |
1628 | |
1629 | return CC_SUCCESS; | |
1630 | } | |
1631 | ||
1632 | static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, | |
024426ac GH |
1633 | unsigned int epid, unsigned int streamid, |
1634 | uint64_t pdequeue) | |
62c6ae04 HM |
1635 | { |
1636 | XHCISlot *slot; | |
1637 | XHCIEPContext *epctx; | |
024426ac | 1638 | XHCIStreamContext *sctx; |
59a70ccd | 1639 | dma_addr_t dequeue; |
62c6ae04 | 1640 | |
91062ae0 | 1641 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1642 | |
1643 | if (epid < 1 || epid > 31) { | |
d6bb65fc | 1644 | DPRINTF("xhci: bad ep %d\n", epid); |
62c6ae04 HM |
1645 | return CC_TRB_ERROR; |
1646 | } | |
1647 | ||
024426ac | 1648 | trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); |
62c6ae04 HM |
1649 | dequeue = xhci_mask64(pdequeue); |
1650 | ||
1651 | slot = &xhci->slots[slotid-1]; | |
1652 | ||
1653 | if (!slot->eps[epid-1]) { | |
1654 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1655 | return CC_EP_NOT_ENABLED_ERROR; | |
1656 | } | |
1657 | ||
1658 | epctx = slot->eps[epid-1]; | |
1659 | ||
62c6ae04 | 1660 | if (epctx->state != EP_STOPPED) { |
d6bb65fc | 1661 | DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); |
62c6ae04 HM |
1662 | return CC_CONTEXT_STATE_ERROR; |
1663 | } | |
1664 | ||
024426ac GH |
1665 | if (epctx->nr_pstreams) { |
1666 | uint32_t err; | |
1667 | sctx = xhci_find_stream(epctx, streamid, &err); | |
1668 | if (sctx == NULL) { | |
1669 | return err; | |
1670 | } | |
1671 | xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); | |
1672 | sctx->ring.ccs = dequeue & 1; | |
1673 | } else { | |
1674 | sctx = NULL; | |
1675 | xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); | |
1676 | epctx->ring.ccs = dequeue & 1; | |
1677 | } | |
62c6ae04 | 1678 | |
024426ac | 1679 | xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); |
62c6ae04 HM |
1680 | |
1681 | return CC_SUCCESS; | |
1682 | } | |
1683 | ||
a6fb2ddb | 1684 | static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) |
62c6ae04 | 1685 | { |
62c6ae04 | 1686 | XHCIState *xhci = xfer->xhci; |
d5a15814 | 1687 | int i; |
62c6ae04 | 1688 | |
a6fb2ddb | 1689 | xfer->int_req = false; |
9b7d3334 | 1690 | pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); |
62c6ae04 HM |
1691 | for (i = 0; i < xfer->trb_count; i++) { |
1692 | XHCITRB *trb = &xfer->trbs[i]; | |
59a70ccd | 1693 | dma_addr_t addr; |
62c6ae04 HM |
1694 | unsigned int chunk = 0; |
1695 | ||
a6fb2ddb HG |
1696 | if (trb->control & TRB_TR_IOC) { |
1697 | xfer->int_req = true; | |
1698 | } | |
1699 | ||
62c6ae04 HM |
1700 | switch (TRB_TYPE(*trb)) { |
1701 | case TR_DATA: | |
1702 | if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { | |
d6bb65fc | 1703 | DPRINTF("xhci: data direction mismatch for TR_DATA\n"); |
d5a15814 | 1704 | goto err; |
62c6ae04 HM |
1705 | } |
1706 | /* fallthrough */ | |
1707 | case TR_NORMAL: | |
1708 | case TR_ISOCH: | |
1709 | addr = xhci_mask64(trb->parameter); | |
d5a15814 GH |
1710 | chunk = trb->status & 0x1ffff; |
1711 | if (trb->control & TRB_TR_IDT) { | |
1712 | if (chunk > 8 || in_xfer) { | |
d6bb65fc | 1713 | DPRINTF("xhci: invalid immediate data TRB\n"); |
d5a15814 GH |
1714 | goto err; |
1715 | } | |
1716 | qemu_sglist_add(&xfer->sgl, trb->addr, chunk); | |
1717 | } else { | |
1718 | qemu_sglist_add(&xfer->sgl, addr, chunk); | |
1719 | } | |
1720 | break; | |
1721 | } | |
1722 | } | |
1723 | ||
d5a15814 GH |
1724 | return 0; |
1725 | ||
1726 | err: | |
1727 | qemu_sglist_destroy(&xfer->sgl); | |
1728 | xhci_die(xhci); | |
1729 | return -1; | |
1730 | } | |
1731 | ||
1732 | static void xhci_xfer_unmap(XHCITransfer *xfer) | |
1733 | { | |
1734 | usb_packet_unmap(&xfer->packet, &xfer->sgl); | |
1735 | qemu_sglist_destroy(&xfer->sgl); | |
1736 | } | |
1737 | ||
1738 | static void xhci_xfer_report(XHCITransfer *xfer) | |
1739 | { | |
1740 | uint32_t edtla = 0; | |
1741 | unsigned int left; | |
1742 | bool reported = 0; | |
1743 | bool shortpkt = 0; | |
1744 | XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; | |
1745 | XHCIState *xhci = xfer->xhci; | |
1746 | int i; | |
1747 | ||
9b8251c5 | 1748 | left = xfer->packet.actual_length; |
d5a15814 GH |
1749 | |
1750 | for (i = 0; i < xfer->trb_count; i++) { | |
1751 | XHCITRB *trb = &xfer->trbs[i]; | |
1752 | unsigned int chunk = 0; | |
1753 | ||
1754 | switch (TRB_TYPE(*trb)) { | |
1755 | case TR_DATA: | |
1756 | case TR_NORMAL: | |
1757 | case TR_ISOCH: | |
62c6ae04 HM |
1758 | chunk = trb->status & 0x1ffff; |
1759 | if (chunk > left) { | |
1760 | chunk = left; | |
d5a15814 GH |
1761 | if (xfer->status == CC_SUCCESS) { |
1762 | shortpkt = 1; | |
62c6ae04 HM |
1763 | } |
1764 | } | |
1765 | left -= chunk; | |
62c6ae04 | 1766 | edtla += chunk; |
62c6ae04 HM |
1767 | break; |
1768 | case TR_STATUS: | |
1769 | reported = 0; | |
1770 | shortpkt = 0; | |
1771 | break; | |
1772 | } | |
1773 | ||
d5a15814 GH |
1774 | if (!reported && ((trb->control & TRB_TR_IOC) || |
1775 | (shortpkt && (trb->control & TRB_TR_ISP)) || | |
9b8251c5 | 1776 | (xfer->status != CC_SUCCESS && left == 0))) { |
62c6ae04 HM |
1777 | event.slotid = xfer->slotid; |
1778 | event.epid = xfer->epid; | |
1779 | event.length = (trb->status & 0x1ffff) - chunk; | |
1780 | event.flags = 0; | |
1781 | event.ptr = trb->addr; | |
1782 | if (xfer->status == CC_SUCCESS) { | |
1783 | event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; | |
1784 | } else { | |
1785 | event.ccode = xfer->status; | |
1786 | } | |
1787 | if (TRB_TYPE(*trb) == TR_EVDATA) { | |
1788 | event.ptr = trb->parameter; | |
1789 | event.flags |= TRB_EV_ED; | |
1790 | event.length = edtla & 0xffffff; | |
1791 | DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); | |
1792 | edtla = 0; | |
1793 | } | |
2d1de850 | 1794 | xhci_event(xhci, &event, TRB_INTR(*trb)); |
62c6ae04 | 1795 | reported = 1; |
d5a15814 GH |
1796 | if (xfer->status != CC_SUCCESS) { |
1797 | return; | |
1798 | } | |
62c6ae04 HM |
1799 | } |
1800 | } | |
62c6ae04 HM |
1801 | } |
1802 | ||
1803 | static void xhci_stall_ep(XHCITransfer *xfer) | |
1804 | { | |
1805 | XHCIState *xhci = xfer->xhci; | |
1806 | XHCISlot *slot = &xhci->slots[xfer->slotid-1]; | |
1807 | XHCIEPContext *epctx = slot->eps[xfer->epid-1]; | |
024426ac GH |
1808 | uint32_t err; |
1809 | XHCIStreamContext *sctx; | |
62c6ae04 | 1810 | |
024426ac GH |
1811 | if (epctx->nr_pstreams) { |
1812 | sctx = xhci_find_stream(epctx, xfer->streamid, &err); | |
1813 | if (sctx == NULL) { | |
1814 | return; | |
1815 | } | |
1816 | sctx->ring.dequeue = xfer->trbs[0].addr; | |
1817 | sctx->ring.ccs = xfer->trbs[0].ccs; | |
1818 | xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); | |
1819 | } else { | |
1820 | epctx->ring.dequeue = xfer->trbs[0].addr; | |
1821 | epctx->ring.ccs = xfer->trbs[0].ccs; | |
1822 | xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); | |
1823 | } | |
62c6ae04 HM |
1824 | } |
1825 | ||
1826 | static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, | |
1827 | XHCIEPContext *epctx); | |
1828 | ||
5c08106f GH |
1829 | static int xhci_setup_packet(XHCITransfer *xfer) |
1830 | { | |
1831 | XHCIState *xhci = xfer->xhci; | |
079d0b7f GH |
1832 | USBEndpoint *ep; |
1833 | int dir; | |
1834 | ||
1835 | dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; | |
5c08106f GH |
1836 | |
1837 | if (xfer->packet.ep) { | |
1838 | ep = xfer->packet.ep; | |
5c08106f | 1839 | } else { |
518ad5f2 HG |
1840 | ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid); |
1841 | if (!ep) { | |
d6bb65fc | 1842 | DPRINTF("xhci: slot %d has no device\n", |
ccaf87a0 | 1843 | xfer->slotid); |
5c08106f GH |
1844 | return -1; |
1845 | } | |
5c08106f GH |
1846 | } |
1847 | ||
a6fb2ddb | 1848 | xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ |
024426ac | 1849 | usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, |
8550a02d | 1850 | xfer->trbs[0].addr, false, xfer->int_req); |
a6fb2ddb | 1851 | usb_packet_map(&xfer->packet, &xfer->sgl); |
62c6ae04 | 1852 | DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", |
518ad5f2 | 1853 | xfer->packet.pid, ep->dev->addr, ep->nr); |
62c6ae04 HM |
1854 | return 0; |
1855 | } | |
1856 | ||
9a77a0f5 | 1857 | static int xhci_complete_packet(XHCITransfer *xfer) |
62c6ae04 | 1858 | { |
9a77a0f5 | 1859 | if (xfer->packet.status == USB_RET_ASYNC) { |
97df650b | 1860 | trace_usb_xhci_xfer_async(xfer); |
7c605a23 GH |
1861 | xfer->running_async = 1; |
1862 | xfer->running_retry = 0; | |
1863 | xfer->complete = 0; | |
7c605a23 | 1864 | return 0; |
9a77a0f5 | 1865 | } else if (xfer->packet.status == USB_RET_NAK) { |
97df650b | 1866 | trace_usb_xhci_xfer_nak(xfer); |
7c605a23 GH |
1867 | xfer->running_async = 0; |
1868 | xfer->running_retry = 1; | |
62c6ae04 | 1869 | xfer->complete = 0; |
62c6ae04 HM |
1870 | return 0; |
1871 | } else { | |
7c605a23 GH |
1872 | xfer->running_async = 0; |
1873 | xfer->running_retry = 0; | |
62c6ae04 | 1874 | xfer->complete = 1; |
d5a15814 | 1875 | xhci_xfer_unmap(xfer); |
62c6ae04 HM |
1876 | } |
1877 | ||
9a77a0f5 HG |
1878 | if (xfer->packet.status == USB_RET_SUCCESS) { |
1879 | trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); | |
d5a15814 GH |
1880 | xfer->status = CC_SUCCESS; |
1881 | xhci_xfer_report(xfer); | |
62c6ae04 HM |
1882 | return 0; |
1883 | } | |
1884 | ||
1885 | /* error */ | |
9a77a0f5 HG |
1886 | trace_usb_xhci_xfer_error(xfer, xfer->packet.status); |
1887 | switch (xfer->packet.status) { | |
62c6ae04 | 1888 | case USB_RET_NODEV: |
ed60ff02 | 1889 | case USB_RET_IOERROR: |
62c6ae04 | 1890 | xfer->status = CC_USB_TRANSACTION_ERROR; |
d5a15814 | 1891 | xhci_xfer_report(xfer); |
62c6ae04 HM |
1892 | xhci_stall_ep(xfer); |
1893 | break; | |
1894 | case USB_RET_STALL: | |
1895 | xfer->status = CC_STALL_ERROR; | |
d5a15814 | 1896 | xhci_xfer_report(xfer); |
62c6ae04 HM |
1897 | xhci_stall_ep(xfer); |
1898 | break; | |
4e906d56 GH |
1899 | case USB_RET_BABBLE: |
1900 | xfer->status = CC_BABBLE_DETECTED; | |
1901 | xhci_xfer_report(xfer); | |
1902 | xhci_stall_ep(xfer); | |
1903 | break; | |
62c6ae04 | 1904 | default: |
d6bb65fc | 1905 | DPRINTF("%s: FIXME: status = %d\n", __func__, |
9a77a0f5 | 1906 | xfer->packet.status); |
024426ac | 1907 | FIXME("unhandled USB_RET_*"); |
62c6ae04 HM |
1908 | } |
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) | |
1913 | { | |
1914 | XHCITRB *trb_setup, *trb_status; | |
2850ca9e | 1915 | uint8_t bmRequestType; |
62c6ae04 | 1916 | |
62c6ae04 HM |
1917 | trb_setup = &xfer->trbs[0]; |
1918 | trb_status = &xfer->trbs[xfer->trb_count-1]; | |
1919 | ||
024426ac | 1920 | trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); |
97df650b | 1921 | |
62c6ae04 HM |
1922 | /* at most one Event Data TRB allowed after STATUS */ |
1923 | if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { | |
1924 | trb_status--; | |
1925 | } | |
1926 | ||
1927 | /* do some sanity checks */ | |
1928 | if (TRB_TYPE(*trb_setup) != TR_SETUP) { | |
d6bb65fc | 1929 | DPRINTF("xhci: ep0 first TD not SETUP: %d\n", |
62c6ae04 HM |
1930 | TRB_TYPE(*trb_setup)); |
1931 | return -1; | |
1932 | } | |
1933 | if (TRB_TYPE(*trb_status) != TR_STATUS) { | |
d6bb65fc | 1934 | DPRINTF("xhci: ep0 last TD not STATUS: %d\n", |
62c6ae04 HM |
1935 | TRB_TYPE(*trb_status)); |
1936 | return -1; | |
1937 | } | |
1938 | if (!(trb_setup->control & TRB_TR_IDT)) { | |
d6bb65fc | 1939 | DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); |
62c6ae04 HM |
1940 | return -1; |
1941 | } | |
1942 | if ((trb_setup->status & 0x1ffff) != 8) { | |
d6bb65fc | 1943 | DPRINTF("xhci: Setup TRB has bad length (%d)\n", |
62c6ae04 HM |
1944 | (trb_setup->status & 0x1ffff)); |
1945 | return -1; | |
1946 | } | |
1947 | ||
1948 | bmRequestType = trb_setup->parameter; | |
62c6ae04 | 1949 | |
62c6ae04 HM |
1950 | xfer->in_xfer = bmRequestType & USB_DIR_IN; |
1951 | xfer->iso_xfer = false; | |
4d7a81c0 | 1952 | xfer->timed_xfer = false; |
62c6ae04 | 1953 | |
5c08106f GH |
1954 | if (xhci_setup_packet(xfer) < 0) { |
1955 | return -1; | |
1956 | } | |
2850ca9e | 1957 | xfer->packet.parameter = trb_setup->parameter; |
2850ca9e | 1958 | |
9a77a0f5 | 1959 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
62c6ae04 | 1960 | |
9a77a0f5 | 1961 | xhci_complete_packet(xfer); |
7c605a23 | 1962 | if (!xfer->running_async && !xfer->running_retry) { |
024426ac | 1963 | xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); |
62c6ae04 HM |
1964 | } |
1965 | return 0; | |
1966 | } | |
1967 | ||
4d7a81c0 GH |
1968 | static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, |
1969 | XHCIEPContext *epctx, uint64_t mfindex) | |
1970 | { | |
1971 | uint64_t asap = ((mfindex + epctx->interval - 1) & | |
1972 | ~(epctx->interval-1)); | |
1973 | uint64_t kick = epctx->mfindex_last + epctx->interval; | |
1974 | ||
1975 | assert(epctx->interval != 0); | |
1976 | xfer->mfindex_kick = MAX(asap, kick); | |
1977 | } | |
1978 | ||
3d139684 GH |
1979 | static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
1980 | XHCIEPContext *epctx, uint64_t mfindex) | |
1981 | { | |
1982 | if (xfer->trbs[0].control & TRB_TR_SIA) { | |
1983 | uint64_t asap = ((mfindex + epctx->interval - 1) & | |
1984 | ~(epctx->interval-1)); | |
1985 | if (asap >= epctx->mfindex_last && | |
1986 | asap <= epctx->mfindex_last + epctx->interval * 4) { | |
1987 | xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; | |
1988 | } else { | |
1989 | xfer->mfindex_kick = asap; | |
1990 | } | |
1991 | } else { | |
786ad214 GH |
1992 | xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) |
1993 | & TRB_TR_FRAMEID_MASK) << 3; | |
3d139684 | 1994 | xfer->mfindex_kick |= mfindex & ~0x3fff; |
cc03ff9d | 1995 | if (xfer->mfindex_kick + 0x100 < mfindex) { |
3d139684 GH |
1996 | xfer->mfindex_kick += 0x4000; |
1997 | } | |
1998 | } | |
1999 | } | |
2000 | ||
4d7a81c0 GH |
2001 | static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
2002 | XHCIEPContext *epctx, uint64_t mfindex) | |
3d139684 GH |
2003 | { |
2004 | if (xfer->mfindex_kick > mfindex) { | |
bc72ad67 | 2005 | timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
3d139684 GH |
2006 | (xfer->mfindex_kick - mfindex) * 125000); |
2007 | xfer->running_retry = 1; | |
2008 | } else { | |
2009 | epctx->mfindex_last = xfer->mfindex_kick; | |
bc72ad67 | 2010 | timer_del(epctx->kick_timer); |
3d139684 GH |
2011 | xfer->running_retry = 0; |
2012 | } | |
2013 | } | |
2014 | ||
2015 | ||
62c6ae04 HM |
2016 | static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
2017 | { | |
3d139684 | 2018 | uint64_t mfindex; |
62c6ae04 HM |
2019 | |
2020 | DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); | |
62c6ae04 HM |
2021 | |
2022 | xfer->in_xfer = epctx->type>>2; | |
62c6ae04 | 2023 | |
62c6ae04 HM |
2024 | switch(epctx->type) { |
2025 | case ET_INTR_OUT: | |
2026 | case ET_INTR_IN: | |
4d7a81c0 GH |
2027 | xfer->pkts = 0; |
2028 | xfer->iso_xfer = false; | |
2029 | xfer->timed_xfer = true; | |
2030 | mfindex = xhci_mfindex_get(xhci); | |
2031 | xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); | |
2032 | xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); | |
2033 | if (xfer->running_retry) { | |
2034 | return -1; | |
2035 | } | |
2036 | break; | |
62c6ae04 HM |
2037 | case ET_BULK_OUT: |
2038 | case ET_BULK_IN: | |
3d139684 GH |
2039 | xfer->pkts = 0; |
2040 | xfer->iso_xfer = false; | |
4d7a81c0 | 2041 | xfer->timed_xfer = false; |
62c6ae04 HM |
2042 | break; |
2043 | case ET_ISO_OUT: | |
2044 | case ET_ISO_IN: | |
3d139684 GH |
2045 | xfer->pkts = 1; |
2046 | xfer->iso_xfer = true; | |
4d7a81c0 | 2047 | xfer->timed_xfer = true; |
3d139684 GH |
2048 | mfindex = xhci_mfindex_get(xhci); |
2049 | xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); | |
4d7a81c0 | 2050 | xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); |
3d139684 GH |
2051 | if (xfer->running_retry) { |
2052 | return -1; | |
2053 | } | |
62c6ae04 HM |
2054 | break; |
2055 | default: | |
4f9cc734 | 2056 | trace_usb_xhci_unimplemented("endpoint type", epctx->type); |
62c6ae04 HM |
2057 | return -1; |
2058 | } | |
2059 | ||
5c08106f GH |
2060 | if (xhci_setup_packet(xfer) < 0) { |
2061 | return -1; | |
2062 | } | |
9a77a0f5 | 2063 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
62c6ae04 | 2064 | |
9a77a0f5 | 2065 | xhci_complete_packet(xfer); |
7c605a23 | 2066 | if (!xfer->running_async && !xfer->running_retry) { |
024426ac | 2067 | xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); |
62c6ae04 HM |
2068 | } |
2069 | return 0; | |
2070 | } | |
2071 | ||
2072 | static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) | |
2073 | { | |
024426ac | 2074 | trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); |
331e9406 | 2075 | return xhci_submit(xhci, xfer, epctx); |
62c6ae04 HM |
2076 | } |
2077 | ||
024426ac GH |
2078 | static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
2079 | unsigned int epid, unsigned int streamid) | |
62c6ae04 | 2080 | { |
024426ac | 2081 | XHCIStreamContext *stctx; |
62c6ae04 | 2082 | XHCIEPContext *epctx; |
024426ac | 2083 | XHCIRing *ring; |
36dfe324 | 2084 | USBEndpoint *ep = NULL; |
3d139684 | 2085 | uint64_t mfindex; |
62c6ae04 HM |
2086 | int length; |
2087 | int i; | |
2088 | ||
024426ac | 2089 | trace_usb_xhci_ep_kick(slotid, epid, streamid); |
91062ae0 | 2090 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 2091 | assert(epid >= 1 && epid <= 31); |
62c6ae04 HM |
2092 | |
2093 | if (!xhci->slots[slotid-1].enabled) { | |
d6bb65fc | 2094 | DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); |
62c6ae04 HM |
2095 | return; |
2096 | } | |
2097 | epctx = xhci->slots[slotid-1].eps[epid-1]; | |
2098 | if (!epctx) { | |
d6bb65fc | 2099 | DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", |
62c6ae04 HM |
2100 | epid, slotid); |
2101 | return; | |
2102 | } | |
2103 | ||
de9de157 HG |
2104 | /* If the device has been detached, but the guest has not noticed this |
2105 | yet the 2 above checks will succeed, but we must NOT continue */ | |
2106 | if (!xhci->slots[slotid - 1].uport || | |
2107 | !xhci->slots[slotid - 1].uport->dev || | |
2108 | !xhci->slots[slotid - 1].uport->dev->attached) { | |
2109 | return; | |
2110 | } | |
2111 | ||
7c605a23 | 2112 | if (epctx->retry) { |
7c605a23 | 2113 | XHCITransfer *xfer = epctx->retry; |
7c605a23 | 2114 | |
97df650b | 2115 | trace_usb_xhci_xfer_retry(xfer); |
7c605a23 | 2116 | assert(xfer->running_retry); |
4d7a81c0 GH |
2117 | if (xfer->timed_xfer) { |
2118 | /* time to kick the transfer? */ | |
3d139684 | 2119 | mfindex = xhci_mfindex_get(xhci); |
4d7a81c0 | 2120 | xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); |
3d139684 GH |
2121 | if (xfer->running_retry) { |
2122 | return; | |
2123 | } | |
4d7a81c0 GH |
2124 | xfer->timed_xfer = 0; |
2125 | xfer->running_retry = 1; | |
2126 | } | |
2127 | if (xfer->iso_xfer) { | |
2128 | /* retry iso transfer */ | |
3d139684 GH |
2129 | if (xhci_setup_packet(xfer) < 0) { |
2130 | return; | |
2131 | } | |
9a77a0f5 HG |
2132 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
2133 | assert(xfer->packet.status != USB_RET_NAK); | |
2134 | xhci_complete_packet(xfer); | |
3d139684 GH |
2135 | } else { |
2136 | /* retry nak'ed transfer */ | |
2137 | if (xhci_setup_packet(xfer) < 0) { | |
2138 | return; | |
2139 | } | |
9a77a0f5 HG |
2140 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
2141 | if (xfer->packet.status == USB_RET_NAK) { | |
3d139684 GH |
2142 | return; |
2143 | } | |
9a77a0f5 | 2144 | xhci_complete_packet(xfer); |
7c605a23 | 2145 | } |
7c605a23 GH |
2146 | assert(!xfer->running_retry); |
2147 | epctx->retry = NULL; | |
2148 | } | |
2149 | ||
62c6ae04 HM |
2150 | if (epctx->state == EP_HALTED) { |
2151 | DPRINTF("xhci: ep halted, not running schedule\n"); | |
2152 | return; | |
2153 | } | |
2154 | ||
024426ac GH |
2155 | |
2156 | if (epctx->nr_pstreams) { | |
2157 | uint32_t err; | |
2158 | stctx = xhci_find_stream(epctx, streamid, &err); | |
2159 | if (stctx == NULL) { | |
2160 | return; | |
2161 | } | |
2162 | ring = &stctx->ring; | |
2163 | xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); | |
2164 | } else { | |
2165 | ring = &epctx->ring; | |
2166 | streamid = 0; | |
2167 | xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); | |
2168 | } | |
7d04c2b7 | 2169 | assert(ring->dequeue != 0); |
62c6ae04 HM |
2170 | |
2171 | while (1) { | |
2172 | XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; | |
331e9406 | 2173 | if (xfer->running_async || xfer->running_retry) { |
62c6ae04 HM |
2174 | break; |
2175 | } | |
024426ac | 2176 | length = xhci_ring_chain_length(xhci, ring); |
62c6ae04 | 2177 | if (length < 0) { |
62c6ae04 HM |
2178 | break; |
2179 | } else if (length == 0) { | |
2180 | break; | |
2181 | } | |
62c6ae04 HM |
2182 | if (xfer->trbs && xfer->trb_alloced < length) { |
2183 | xfer->trb_count = 0; | |
2184 | xfer->trb_alloced = 0; | |
2185 | g_free(xfer->trbs); | |
2186 | xfer->trbs = NULL; | |
2187 | } | |
2188 | if (!xfer->trbs) { | |
2189 | xfer->trbs = g_malloc(sizeof(XHCITRB) * length); | |
2190 | xfer->trb_alloced = length; | |
2191 | } | |
2192 | xfer->trb_count = length; | |
2193 | ||
2194 | for (i = 0; i < length; i++) { | |
024426ac | 2195 | assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); |
62c6ae04 | 2196 | } |
024426ac | 2197 | xfer->streamid = streamid; |
62c6ae04 HM |
2198 | |
2199 | if (epid == 1) { | |
2200 | if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { | |
2201 | epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; | |
36dfe324 | 2202 | ep = xfer->packet.ep; |
62c6ae04 | 2203 | } else { |
d6bb65fc | 2204 | DPRINTF("xhci: error firing CTL transfer\n"); |
62c6ae04 HM |
2205 | } |
2206 | } else { | |
2207 | if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { | |
2208 | epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; | |
2209 | } else { | |
4d7a81c0 | 2210 | if (!xfer->timed_xfer) { |
d6bb65fc | 2211 | DPRINTF("xhci: error firing data transfer\n"); |
3d139684 | 2212 | } |
62c6ae04 HM |
2213 | } |
2214 | } | |
2215 | ||
3c4866e0 | 2216 | if (epctx->state == EP_HALTED) { |
3c4866e0 GH |
2217 | break; |
2218 | } | |
7c605a23 GH |
2219 | if (xfer->running_retry) { |
2220 | DPRINTF("xhci: xfer nacked, stopping schedule\n"); | |
2221 | epctx->retry = xfer; | |
2222 | break; | |
2223 | } | |
62c6ae04 | 2224 | } |
518ad5f2 HG |
2225 | |
2226 | ep = xhci_epid_to_usbep(xhci, slotid, epid); | |
36dfe324 HG |
2227 | if (ep) { |
2228 | usb_device_flush_ep_queue(ep->dev, ep); | |
2229 | } | |
62c6ae04 HM |
2230 | } |
2231 | ||
2232 | static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) | |
2233 | { | |
348f1037 | 2234 | trace_usb_xhci_slot_enable(slotid); |
91062ae0 | 2235 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 2236 | xhci->slots[slotid-1].enabled = 1; |
ccaf87a0 | 2237 | xhci->slots[slotid-1].uport = NULL; |
62c6ae04 HM |
2238 | memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); |
2239 | ||
2240 | return CC_SUCCESS; | |
2241 | } | |
2242 | ||
2243 | static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) | |
2244 | { | |
2245 | int i; | |
2246 | ||
348f1037 | 2247 | trace_usb_xhci_slot_disable(slotid); |
91062ae0 | 2248 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2249 | |
2250 | for (i = 1; i <= 31; i++) { | |
2251 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2252 | xhci_disable_ep(xhci, slotid, i); | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | xhci->slots[slotid-1].enabled = 0; | |
4034e693 | 2257 | xhci->slots[slotid-1].addressed = 0; |
5c67dd7b | 2258 | xhci->slots[slotid-1].uport = NULL; |
62c6ae04 HM |
2259 | return CC_SUCCESS; |
2260 | } | |
2261 | ||
ccaf87a0 GH |
2262 | static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) |
2263 | { | |
2264 | USBPort *uport; | |
2265 | char path[32]; | |
2266 | int i, pos, port; | |
2267 | ||
2268 | port = (slot_ctx[1]>>16) & 0xFF; | |
2269 | port = xhci->ports[port-1].uport->index+1; | |
2270 | pos = snprintf(path, sizeof(path), "%d", port); | |
2271 | for (i = 0; i < 5; i++) { | |
2272 | port = (slot_ctx[0] >> 4*i) & 0x0f; | |
2273 | if (!port) { | |
2274 | break; | |
2275 | } | |
2276 | pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); | |
2277 | } | |
2278 | ||
2279 | QTAILQ_FOREACH(uport, &xhci->bus.used, next) { | |
2280 | if (strcmp(uport->path, path) == 0) { | |
2281 | return uport; | |
2282 | } | |
2283 | } | |
2284 | return NULL; | |
2285 | } | |
2286 | ||
62c6ae04 HM |
2287 | static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, |
2288 | uint64_t pictx, bool bsr) | |
2289 | { | |
2290 | XHCISlot *slot; | |
ccaf87a0 | 2291 | USBPort *uport; |
62c6ae04 | 2292 | USBDevice *dev; |
59a70ccd | 2293 | dma_addr_t ictx, octx, dcbaap; |
62c6ae04 HM |
2294 | uint64_t poctx; |
2295 | uint32_t ictl_ctx[2]; | |
2296 | uint32_t slot_ctx[4]; | |
2297 | uint32_t ep0_ctx[5]; | |
62c6ae04 HM |
2298 | int i; |
2299 | TRBCCode res; | |
2300 | ||
91062ae0 | 2301 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2302 | |
2303 | dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); | |
9b7d3334 | 2304 | poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); |
62c6ae04 | 2305 | ictx = xhci_mask64(pictx); |
616b5d53 | 2306 | octx = xhci_mask64(poctx); |
62c6ae04 | 2307 | |
59a70ccd DG |
2308 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2309 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 | 2310 | |
616b5d53 | 2311 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2312 | |
2313 | if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { | |
d6bb65fc | 2314 | DPRINTF("xhci: invalid input context control %08x %08x\n", |
62c6ae04 HM |
2315 | ictl_ctx[0], ictl_ctx[1]); |
2316 | return CC_TRB_ERROR; | |
2317 | } | |
2318 | ||
616b5d53 DG |
2319 | xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); |
2320 | xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); | |
62c6ae04 HM |
2321 | |
2322 | DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", | |
2323 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2324 | ||
2325 | DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", | |
2326 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2327 | ||
ccaf87a0 GH |
2328 | uport = xhci_lookup_uport(xhci, slot_ctx); |
2329 | if (uport == NULL) { | |
d6bb65fc | 2330 | DPRINTF("xhci: port not found\n"); |
62c6ae04 | 2331 | return CC_TRB_ERROR; |
ccaf87a0 | 2332 | } |
65d81ed4 | 2333 | trace_usb_xhci_slot_address(slotid, uport->path); |
ccaf87a0 GH |
2334 | |
2335 | dev = uport->dev; | |
de9de157 | 2336 | if (!dev || !dev->attached) { |
d6bb65fc | 2337 | DPRINTF("xhci: port %s not connected\n", uport->path); |
62c6ae04 HM |
2338 | return CC_USB_TRANSACTION_ERROR; |
2339 | } | |
2340 | ||
91062ae0 | 2341 | for (i = 0; i < xhci->numslots; i++) { |
0bc85da6 GH |
2342 | if (i == slotid-1) { |
2343 | continue; | |
2344 | } | |
ccaf87a0 | 2345 | if (xhci->slots[i].uport == uport) { |
d6bb65fc | 2346 | DPRINTF("xhci: port %s already assigned to slot %d\n", |
ccaf87a0 | 2347 | uport->path, i+1); |
62c6ae04 HM |
2348 | return CC_TRB_ERROR; |
2349 | } | |
2350 | } | |
2351 | ||
2352 | slot = &xhci->slots[slotid-1]; | |
ccaf87a0 | 2353 | slot->uport = uport; |
62c6ae04 HM |
2354 | slot->ctx = octx; |
2355 | ||
2356 | if (bsr) { | |
2357 | slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; | |
2358 | } else { | |
a820b575 | 2359 | USBPacket p; |
a6718874 GH |
2360 | uint8_t buf[1]; |
2361 | ||
af203be3 | 2362 | slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; |
0bc85da6 | 2363 | usb_device_reset(dev); |
a6718874 GH |
2364 | memset(&p, 0, sizeof(p)); |
2365 | usb_packet_addbuf(&p, buf, sizeof(buf)); | |
a820b575 | 2366 | usb_packet_setup(&p, USB_TOKEN_OUT, |
8550a02d | 2367 | usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, |
a820b575 GH |
2368 | 0, false, false); |
2369 | usb_device_handle_control(dev, &p, | |
62c6ae04 | 2370 | DeviceOutRequest | USB_REQ_SET_ADDRESS, |
af203be3 | 2371 | slotid, 0, 0, NULL); |
a820b575 | 2372 | assert(p.status != USB_RET_ASYNC); |
62c6ae04 HM |
2373 | } |
2374 | ||
2375 | res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); | |
2376 | ||
2377 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2378 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2379 | DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", | |
2380 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2381 | ||
616b5d53 DG |
2382 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
2383 | xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); | |
62c6ae04 | 2384 | |
4034e693 | 2385 | xhci->slots[slotid-1].addressed = 1; |
62c6ae04 HM |
2386 | return res; |
2387 | } | |
2388 | ||
2389 | ||
2390 | static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, | |
2391 | uint64_t pictx, bool dc) | |
2392 | { | |
59a70ccd | 2393 | dma_addr_t ictx, octx; |
62c6ae04 HM |
2394 | uint32_t ictl_ctx[2]; |
2395 | uint32_t slot_ctx[4]; | |
2396 | uint32_t islot_ctx[4]; | |
2397 | uint32_t ep_ctx[5]; | |
2398 | int i; | |
2399 | TRBCCode res; | |
2400 | ||
348f1037 | 2401 | trace_usb_xhci_slot_configure(slotid); |
91062ae0 | 2402 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2403 | |
2404 | ictx = xhci_mask64(pictx); | |
2405 | octx = xhci->slots[slotid-1].ctx; | |
2406 | ||
59a70ccd DG |
2407 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2408 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 HM |
2409 | |
2410 | if (dc) { | |
2411 | for (i = 2; i <= 31; i++) { | |
2412 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2413 | xhci_disable_ep(xhci, slotid, i); | |
2414 | } | |
2415 | } | |
2416 | ||
616b5d53 | 2417 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2418 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2419 | slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; | |
2420 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2421 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
616b5d53 | 2422 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2423 | |
2424 | return CC_SUCCESS; | |
2425 | } | |
2426 | ||
616b5d53 | 2427 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2428 | |
2429 | if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { | |
d6bb65fc | 2430 | DPRINTF("xhci: invalid input context control %08x %08x\n", |
62c6ae04 HM |
2431 | ictl_ctx[0], ictl_ctx[1]); |
2432 | return CC_TRB_ERROR; | |
2433 | } | |
2434 | ||
616b5d53 DG |
2435 | xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); |
2436 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); | |
62c6ae04 HM |
2437 | |
2438 | if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { | |
d6bb65fc | 2439 | DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); |
62c6ae04 HM |
2440 | return CC_CONTEXT_STATE_ERROR; |
2441 | } | |
2442 | ||
72391da5 HG |
2443 | xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); |
2444 | ||
62c6ae04 HM |
2445 | for (i = 2; i <= 31; i++) { |
2446 | if (ictl_ctx[0] & (1<<i)) { | |
2447 | xhci_disable_ep(xhci, slotid, i); | |
2448 | } | |
2449 | if (ictl_ctx[1] & (1<<i)) { | |
616b5d53 | 2450 | xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); |
62c6ae04 HM |
2451 | DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", |
2452 | i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], | |
2453 | ep_ctx[3], ep_ctx[4]); | |
2454 | xhci_disable_ep(xhci, slotid, i); | |
2455 | res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); | |
2456 | if (res != CC_SUCCESS) { | |
2457 | return res; | |
2458 | } | |
2459 | DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", | |
2460 | i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], | |
2461 | ep_ctx[3], ep_ctx[4]); | |
616b5d53 | 2462 | xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); |
62c6ae04 HM |
2463 | } |
2464 | } | |
2465 | ||
72391da5 HG |
2466 | res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); |
2467 | if (res != CC_SUCCESS) { | |
2468 | for (i = 2; i <= 31; i++) { | |
3d80365b | 2469 | if (ictl_ctx[1] & (1u << i)) { |
72391da5 HG |
2470 | xhci_disable_ep(xhci, slotid, i); |
2471 | } | |
2472 | } | |
2473 | return res; | |
2474 | } | |
2475 | ||
62c6ae04 HM |
2476 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2477 | slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; | |
2478 | slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); | |
2479 | slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << | |
2480 | SLOT_CONTEXT_ENTRIES_SHIFT); | |
2481 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2482 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2483 | ||
616b5d53 | 2484 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2485 | |
2486 | return CC_SUCCESS; | |
2487 | } | |
2488 | ||
2489 | ||
2490 | static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, | |
2491 | uint64_t pictx) | |
2492 | { | |
59a70ccd | 2493 | dma_addr_t ictx, octx; |
62c6ae04 HM |
2494 | uint32_t ictl_ctx[2]; |
2495 | uint32_t iep0_ctx[5]; | |
2496 | uint32_t ep0_ctx[5]; | |
2497 | uint32_t islot_ctx[4]; | |
2498 | uint32_t slot_ctx[4]; | |
2499 | ||
348f1037 | 2500 | trace_usb_xhci_slot_evaluate(slotid); |
91062ae0 | 2501 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2502 | |
2503 | ictx = xhci_mask64(pictx); | |
2504 | octx = xhci->slots[slotid-1].ctx; | |
2505 | ||
59a70ccd DG |
2506 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2507 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 | 2508 | |
616b5d53 | 2509 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2510 | |
2511 | if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { | |
d6bb65fc | 2512 | DPRINTF("xhci: invalid input context control %08x %08x\n", |
62c6ae04 HM |
2513 | ictl_ctx[0], ictl_ctx[1]); |
2514 | return CC_TRB_ERROR; | |
2515 | } | |
2516 | ||
2517 | if (ictl_ctx[1] & 0x1) { | |
616b5d53 | 2518 | xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); |
62c6ae04 HM |
2519 | |
2520 | DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", | |
2521 | islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); | |
2522 | ||
616b5d53 | 2523 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2524 | |
2525 | slot_ctx[1] &= ~0xFFFF; /* max exit latency */ | |
2526 | slot_ctx[1] |= islot_ctx[1] & 0xFFFF; | |
2527 | slot_ctx[2] &= ~0xFF00000; /* interrupter target */ | |
2528 | slot_ctx[2] |= islot_ctx[2] & 0xFF000000; | |
2529 | ||
2530 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2531 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2532 | ||
616b5d53 | 2533 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2534 | } |
2535 | ||
2536 | if (ictl_ctx[1] & 0x2) { | |
616b5d53 | 2537 | xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); |
62c6ae04 HM |
2538 | |
2539 | DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", | |
2540 | iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], | |
2541 | iep0_ctx[3], iep0_ctx[4]); | |
2542 | ||
616b5d53 | 2543 | xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
62c6ae04 HM |
2544 | |
2545 | ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ | |
2546 | ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; | |
2547 | ||
2548 | DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", | |
2549 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2550 | ||
616b5d53 | 2551 | xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
62c6ae04 HM |
2552 | } |
2553 | ||
2554 | return CC_SUCCESS; | |
2555 | } | |
2556 | ||
2557 | static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) | |
2558 | { | |
2559 | uint32_t slot_ctx[4]; | |
59a70ccd | 2560 | dma_addr_t octx; |
62c6ae04 HM |
2561 | int i; |
2562 | ||
348f1037 | 2563 | trace_usb_xhci_slot_reset(slotid); |
91062ae0 | 2564 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2565 | |
2566 | octx = xhci->slots[slotid-1].ctx; | |
2567 | ||
59a70ccd | 2568 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
62c6ae04 HM |
2569 | |
2570 | for (i = 2; i <= 31; i++) { | |
2571 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2572 | xhci_disable_ep(xhci, slotid, i); | |
2573 | } | |
2574 | } | |
2575 | ||
616b5d53 | 2576 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2577 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2578 | slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; | |
2579 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2580 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
616b5d53 | 2581 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2582 | |
2583 | return CC_SUCCESS; | |
2584 | } | |
2585 | ||
2586 | static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) | |
2587 | { | |
2588 | unsigned int slotid; | |
2589 | slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; | |
91062ae0 | 2590 | if (slotid < 1 || slotid > xhci->numslots) { |
d6bb65fc | 2591 | DPRINTF("xhci: bad slot id %d\n", slotid); |
62c6ae04 HM |
2592 | event->ccode = CC_TRB_ERROR; |
2593 | return 0; | |
2594 | } else if (!xhci->slots[slotid-1].enabled) { | |
d6bb65fc | 2595 | DPRINTF("xhci: slot id %d not enabled\n", slotid); |
62c6ae04 HM |
2596 | event->ccode = CC_SLOT_NOT_ENABLED_ERROR; |
2597 | return 0; | |
2598 | } | |
2599 | return slotid; | |
2600 | } | |
2601 | ||
81251841 GH |
2602 | /* cleanup slot state on usb device detach */ |
2603 | static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) | |
2604 | { | |
0cb41e2c | 2605 | int slot, ep; |
81251841 GH |
2606 | |
2607 | for (slot = 0; slot < xhci->numslots; slot++) { | |
2608 | if (xhci->slots[slot].uport == uport) { | |
2609 | break; | |
2610 | } | |
2611 | } | |
2612 | if (slot == xhci->numslots) { | |
2613 | return; | |
2614 | } | |
2615 | ||
0cb41e2c GH |
2616 | for (ep = 0; ep < 31; ep++) { |
2617 | if (xhci->slots[slot].eps[ep]) { | |
582d6f4a | 2618 | xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); |
0cb41e2c GH |
2619 | } |
2620 | } | |
81251841 GH |
2621 | xhci->slots[slot].uport = NULL; |
2622 | } | |
2623 | ||
62c6ae04 HM |
2624 | static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) |
2625 | { | |
59a70ccd | 2626 | dma_addr_t ctx; |
0846e635 | 2627 | uint8_t bw_ctx[xhci->numports+1]; |
62c6ae04 HM |
2628 | |
2629 | DPRINTF("xhci_get_port_bandwidth()\n"); | |
2630 | ||
2631 | ctx = xhci_mask64(pctx); | |
2632 | ||
59a70ccd | 2633 | DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); |
62c6ae04 HM |
2634 | |
2635 | /* TODO: actually implement real values here */ | |
2636 | bw_ctx[0] = 0; | |
0846e635 | 2637 | memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ |
9b7d3334 | 2638 | pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); |
62c6ae04 HM |
2639 | |
2640 | return CC_SUCCESS; | |
2641 | } | |
2642 | ||
2643 | static uint32_t rotl(uint32_t v, unsigned count) | |
2644 | { | |
2645 | count &= 31; | |
2646 | return (v << count) | (v >> (32 - count)); | |
2647 | } | |
2648 | ||
2649 | ||
2650 | static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) | |
2651 | { | |
2652 | uint32_t val; | |
2653 | val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); | |
2654 | val += rotl(lo + 0x49434878, hi & 0x1F); | |
2655 | val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); | |
2656 | return ~val; | |
2657 | } | |
2658 | ||
59a70ccd | 2659 | static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) |
62c6ae04 | 2660 | { |
9b7d3334 | 2661 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
62c6ae04 HM |
2662 | uint32_t buf[8]; |
2663 | uint32_t obuf[8]; | |
59a70ccd | 2664 | dma_addr_t paddr = xhci_mask64(addr); |
62c6ae04 | 2665 | |
9b7d3334 | 2666 | pci_dma_read(pci_dev, paddr, &buf, 32); |
62c6ae04 HM |
2667 | |
2668 | memcpy(obuf, buf, sizeof(obuf)); | |
2669 | ||
2670 | if ((buf[0] & 0xff) == 2) { | |
2671 | obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; | |
2672 | obuf[0] |= (buf[2] * buf[3]) & 0xff; | |
2673 | obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; | |
2674 | obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; | |
2675 | obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; | |
2676 | obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; | |
2677 | obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; | |
2678 | obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; | |
2679 | obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; | |
2680 | } | |
2681 | ||
9b7d3334 | 2682 | pci_dma_write(pci_dev, paddr, &obuf, 32); |
62c6ae04 HM |
2683 | } |
2684 | ||
2685 | static void xhci_process_commands(XHCIState *xhci) | |
2686 | { | |
2687 | XHCITRB trb; | |
2688 | TRBType type; | |
2689 | XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; | |
59a70ccd | 2690 | dma_addr_t addr; |
62c6ae04 HM |
2691 | unsigned int i, slotid = 0; |
2692 | ||
2693 | DPRINTF("xhci_process_commands()\n"); | |
2694 | if (!xhci_running(xhci)) { | |
2695 | DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); | |
2696 | return; | |
2697 | } | |
2698 | ||
2699 | xhci->crcr_low |= CRCR_CRR; | |
2700 | ||
2701 | while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { | |
2702 | event.ptr = addr; | |
2703 | switch (type) { | |
2704 | case CR_ENABLE_SLOT: | |
91062ae0 | 2705 | for (i = 0; i < xhci->numslots; i++) { |
62c6ae04 HM |
2706 | if (!xhci->slots[i].enabled) { |
2707 | break; | |
2708 | } | |
2709 | } | |
91062ae0 | 2710 | if (i >= xhci->numslots) { |
d6bb65fc | 2711 | DPRINTF("xhci: no device slots available\n"); |
62c6ae04 HM |
2712 | event.ccode = CC_NO_SLOTS_ERROR; |
2713 | } else { | |
2714 | slotid = i+1; | |
2715 | event.ccode = xhci_enable_slot(xhci, slotid); | |
2716 | } | |
2717 | break; | |
2718 | case CR_DISABLE_SLOT: | |
2719 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2720 | if (slotid) { | |
2721 | event.ccode = xhci_disable_slot(xhci, slotid); | |
2722 | } | |
2723 | break; | |
2724 | case CR_ADDRESS_DEVICE: | |
2725 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2726 | if (slotid) { | |
2727 | event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, | |
2728 | trb.control & TRB_CR_BSR); | |
2729 | } | |
2730 | break; | |
2731 | case CR_CONFIGURE_ENDPOINT: | |
2732 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2733 | if (slotid) { | |
2734 | event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, | |
2735 | trb.control & TRB_CR_DC); | |
2736 | } | |
2737 | break; | |
2738 | case CR_EVALUATE_CONTEXT: | |
2739 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2740 | if (slotid) { | |
2741 | event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); | |
2742 | } | |
2743 | break; | |
2744 | case CR_STOP_ENDPOINT: | |
2745 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2746 | if (slotid) { | |
2747 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2748 | & TRB_CR_EPID_MASK; | |
2749 | event.ccode = xhci_stop_ep(xhci, slotid, epid); | |
2750 | } | |
2751 | break; | |
2752 | case CR_RESET_ENDPOINT: | |
2753 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2754 | if (slotid) { | |
2755 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2756 | & TRB_CR_EPID_MASK; | |
2757 | event.ccode = xhci_reset_ep(xhci, slotid, epid); | |
2758 | } | |
2759 | break; | |
2760 | case CR_SET_TR_DEQUEUE: | |
2761 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2762 | if (slotid) { | |
2763 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2764 | & TRB_CR_EPID_MASK; | |
024426ac GH |
2765 | unsigned int streamid = (trb.status >> 16) & 0xffff; |
2766 | event.ccode = xhci_set_ep_dequeue(xhci, slotid, | |
2767 | epid, streamid, | |
62c6ae04 HM |
2768 | trb.parameter); |
2769 | } | |
2770 | break; | |
2771 | case CR_RESET_DEVICE: | |
2772 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2773 | if (slotid) { | |
2774 | event.ccode = xhci_reset_slot(xhci, slotid); | |
2775 | } | |
2776 | break; | |
2777 | case CR_GET_PORT_BANDWIDTH: | |
2778 | event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); | |
2779 | break; | |
2780 | case CR_VENDOR_VIA_CHALLENGE_RESPONSE: | |
59a70ccd | 2781 | xhci_via_challenge(xhci, trb.parameter); |
62c6ae04 HM |
2782 | break; |
2783 | case CR_VENDOR_NEC_FIRMWARE_REVISION: | |
2784 | event.type = 48; /* NEC reply */ | |
2785 | event.length = 0x3025; | |
2786 | break; | |
2787 | case CR_VENDOR_NEC_CHALLENGE_RESPONSE: | |
2788 | { | |
2789 | uint32_t chi = trb.parameter >> 32; | |
2790 | uint32_t clo = trb.parameter; | |
2791 | uint32_t val = xhci_nec_challenge(chi, clo); | |
2792 | event.length = val & 0xFFFF; | |
2793 | event.epid = val >> 16; | |
2794 | slotid = val >> 24; | |
2795 | event.type = 48; /* NEC reply */ | |
2796 | } | |
2797 | break; | |
2798 | default: | |
0ab966cf | 2799 | trace_usb_xhci_unimplemented("command", type); |
62c6ae04 HM |
2800 | event.ccode = CC_TRB_ERROR; |
2801 | break; | |
2802 | } | |
2803 | event.slotid = slotid; | |
2d1de850 | 2804 | xhci_event(xhci, &event, 0); |
62c6ae04 HM |
2805 | } |
2806 | } | |
2807 | ||
6a32f80f GH |
2808 | static bool xhci_port_have_device(XHCIPort *port) |
2809 | { | |
2810 | if (!port->uport->dev || !port->uport->dev->attached) { | |
2811 | return false; /* no device present */ | |
2812 | } | |
2813 | if (!((1 << port->uport->dev->speed) & port->speedmask)) { | |
2814 | return false; /* speed mismatch */ | |
2815 | } | |
2816 | return true; | |
2817 | } | |
2818 | ||
f705a362 GH |
2819 | static void xhci_port_notify(XHCIPort *port, uint32_t bits) |
2820 | { | |
2821 | XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, | |
2822 | port->portnr << 24 }; | |
2823 | ||
2824 | if ((port->portsc & bits) == bits) { | |
2825 | return; | |
2826 | } | |
bdfce20d | 2827 | trace_usb_xhci_port_notify(port->portnr, bits); |
f705a362 GH |
2828 | port->portsc |= bits; |
2829 | if (!xhci_running(port->xhci)) { | |
2830 | return; | |
2831 | } | |
2832 | xhci_event(port->xhci, &ev, 0); | |
2833 | } | |
2834 | ||
f3214027 | 2835 | static void xhci_port_update(XHCIPort *port, int is_detach) |
62c6ae04 | 2836 | { |
b62b0828 GH |
2837 | uint32_t pls = PLS_RX_DETECT; |
2838 | ||
62c6ae04 | 2839 | port->portsc = PORTSC_PP; |
6a32f80f | 2840 | if (!is_detach && xhci_port_have_device(port)) { |
62c6ae04 | 2841 | port->portsc |= PORTSC_CCS; |
0846e635 | 2842 | switch (port->uport->dev->speed) { |
62c6ae04 HM |
2843 | case USB_SPEED_LOW: |
2844 | port->portsc |= PORTSC_SPEED_LOW; | |
b62b0828 | 2845 | pls = PLS_POLLING; |
62c6ae04 HM |
2846 | break; |
2847 | case USB_SPEED_FULL: | |
2848 | port->portsc |= PORTSC_SPEED_FULL; | |
b62b0828 | 2849 | pls = PLS_POLLING; |
62c6ae04 HM |
2850 | break; |
2851 | case USB_SPEED_HIGH: | |
2852 | port->portsc |= PORTSC_SPEED_HIGH; | |
b62b0828 | 2853 | pls = PLS_POLLING; |
62c6ae04 | 2854 | break; |
0846e635 GH |
2855 | case USB_SPEED_SUPER: |
2856 | port->portsc |= PORTSC_SPEED_SUPER; | |
b62b0828 GH |
2857 | port->portsc |= PORTSC_PED; |
2858 | pls = PLS_U0; | |
0846e635 | 2859 | break; |
62c6ae04 HM |
2860 | } |
2861 | } | |
b62b0828 | 2862 | set_field(&port->portsc, pls, PORTSC_PLS); |
4f47f0f8 | 2863 | trace_usb_xhci_port_link(port->portnr, pls); |
f705a362 | 2864 | xhci_port_notify(port, PORTSC_CSC); |
62c6ae04 HM |
2865 | } |
2866 | ||
dad5b9ea | 2867 | static void xhci_port_reset(XHCIPort *port, bool warm_reset) |
40030130 | 2868 | { |
7bd3055f | 2869 | trace_usb_xhci_port_reset(port->portnr, warm_reset); |
4f47f0f8 | 2870 | |
b62b0828 GH |
2871 | if (!xhci_port_have_device(port)) { |
2872 | return; | |
2873 | } | |
2874 | ||
40030130 | 2875 | usb_device_reset(port->uport->dev); |
b62b0828 GH |
2876 | |
2877 | switch (port->uport->dev->speed) { | |
dad5b9ea GH |
2878 | case USB_SPEED_SUPER: |
2879 | if (warm_reset) { | |
2880 | port->portsc |= PORTSC_WRC; | |
2881 | } | |
2882 | /* fall through */ | |
b62b0828 GH |
2883 | case USB_SPEED_LOW: |
2884 | case USB_SPEED_FULL: | |
2885 | case USB_SPEED_HIGH: | |
2886 | set_field(&port->portsc, PLS_U0, PORTSC_PLS); | |
4f47f0f8 | 2887 | trace_usb_xhci_port_link(port->portnr, PLS_U0); |
b62b0828 GH |
2888 | port->portsc |= PORTSC_PED; |
2889 | break; | |
2890 | } | |
2891 | ||
2892 | port->portsc &= ~PORTSC_PR; | |
2893 | xhci_port_notify(port, PORTSC_PRC); | |
40030130 GH |
2894 | } |
2895 | ||
64619739 | 2896 | static void xhci_reset(DeviceState *dev) |
62c6ae04 | 2897 | { |
37034575 | 2898 | XHCIState *xhci = XHCI(dev); |
62c6ae04 HM |
2899 | int i; |
2900 | ||
2d754a10 | 2901 | trace_usb_xhci_reset(); |
62c6ae04 | 2902 | if (!(xhci->usbsts & USBSTS_HCH)) { |
d6bb65fc | 2903 | DPRINTF("xhci: reset while running!\n"); |
62c6ae04 HM |
2904 | } |
2905 | ||
2906 | xhci->usbcmd = 0; | |
2907 | xhci->usbsts = USBSTS_HCH; | |
2908 | xhci->dnctrl = 0; | |
2909 | xhci->crcr_low = 0; | |
2910 | xhci->crcr_high = 0; | |
2911 | xhci->dcbaap_low = 0; | |
2912 | xhci->dcbaap_high = 0; | |
2913 | xhci->config = 0; | |
62c6ae04 | 2914 | |
91062ae0 | 2915 | for (i = 0; i < xhci->numslots; i++) { |
62c6ae04 HM |
2916 | xhci_disable_slot(xhci, i+1); |
2917 | } | |
2918 | ||
0846e635 | 2919 | for (i = 0; i < xhci->numports; i++) { |
f3214027 | 2920 | xhci_port_update(xhci->ports + i, 0); |
62c6ae04 HM |
2921 | } |
2922 | ||
91062ae0 | 2923 | for (i = 0; i < xhci->numintrs; i++) { |
962d11e1 GH |
2924 | xhci->intr[i].iman = 0; |
2925 | xhci->intr[i].imod = 0; | |
2926 | xhci->intr[i].erstsz = 0; | |
2927 | xhci->intr[i].erstba_low = 0; | |
2928 | xhci->intr[i].erstba_high = 0; | |
2929 | xhci->intr[i].erdp_low = 0; | |
2930 | xhci->intr[i].erdp_high = 0; | |
2931 | xhci->intr[i].msix_used = 0; | |
62c6ae04 | 2932 | |
962d11e1 GH |
2933 | xhci->intr[i].er_ep_idx = 0; |
2934 | xhci->intr[i].er_pcs = 1; | |
2935 | xhci->intr[i].er_full = 0; | |
2936 | xhci->intr[i].ev_buffer_put = 0; | |
2937 | xhci->intr[i].ev_buffer_get = 0; | |
2938 | } | |
01546fa6 | 2939 | |
bc72ad67 | 2940 | xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
01546fa6 | 2941 | xhci_mfwrap_update(xhci); |
62c6ae04 HM |
2942 | } |
2943 | ||
a8170e5e | 2944 | static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2945 | { |
1b067564 | 2946 | XHCIState *xhci = ptr; |
2d754a10 | 2947 | uint32_t ret; |
62c6ae04 HM |
2948 | |
2949 | switch (reg) { | |
2950 | case 0x00: /* HCIVERSION, CAPLENGTH */ | |
2d754a10 GH |
2951 | ret = 0x01000000 | LEN_CAP; |
2952 | break; | |
62c6ae04 | 2953 | case 0x04: /* HCSPARAMS 1 */ |
0846e635 | 2954 | ret = ((xhci->numports_2+xhci->numports_3)<<24) |
91062ae0 | 2955 | | (xhci->numintrs<<8) | xhci->numslots; |
2d754a10 | 2956 | break; |
62c6ae04 | 2957 | case 0x08: /* HCSPARAMS 2 */ |
2d754a10 GH |
2958 | ret = 0x0000000f; |
2959 | break; | |
62c6ae04 | 2960 | case 0x0c: /* HCSPARAMS 3 */ |
2d754a10 GH |
2961 | ret = 0x00000000; |
2962 | break; | |
62c6ae04 | 2963 | case 0x10: /* HCCPARAMS */ |
2d754a10 | 2964 | if (sizeof(dma_addr_t) == 4) { |
024426ac | 2965 | ret = 0x00087000; |
2d754a10 | 2966 | } else { |
024426ac | 2967 | ret = 0x00087001; |
2d754a10 GH |
2968 | } |
2969 | break; | |
62c6ae04 | 2970 | case 0x14: /* DBOFF */ |
2d754a10 GH |
2971 | ret = OFF_DOORBELL; |
2972 | break; | |
62c6ae04 | 2973 | case 0x18: /* RTSOFF */ |
2d754a10 GH |
2974 | ret = OFF_RUNTIME; |
2975 | break; | |
62c6ae04 HM |
2976 | |
2977 | /* extended capabilities */ | |
2978 | case 0x20: /* Supported Protocol:00 */ | |
2d754a10 GH |
2979 | ret = 0x02000402; /* USB 2.0 */ |
2980 | break; | |
62c6ae04 | 2981 | case 0x24: /* Supported Protocol:04 */ |
0ebfb144 | 2982 | ret = 0x20425355; /* "USB " */ |
2d754a10 | 2983 | break; |
62c6ae04 | 2984 | case 0x28: /* Supported Protocol:08 */ |
7bafd888 GH |
2985 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
2986 | ret = (xhci->numports_2<<8) | (xhci->numports_3+1); | |
2987 | } else { | |
2988 | ret = (xhci->numports_2<<8) | 1; | |
2989 | } | |
2d754a10 | 2990 | break; |
62c6ae04 | 2991 | case 0x2c: /* Supported Protocol:0c */ |
2d754a10 GH |
2992 | ret = 0x00000000; /* reserved */ |
2993 | break; | |
62c6ae04 | 2994 | case 0x30: /* Supported Protocol:00 */ |
2d754a10 GH |
2995 | ret = 0x03000002; /* USB 3.0 */ |
2996 | break; | |
62c6ae04 | 2997 | case 0x34: /* Supported Protocol:04 */ |
0ebfb144 | 2998 | ret = 0x20425355; /* "USB " */ |
2d754a10 | 2999 | break; |
62c6ae04 | 3000 | case 0x38: /* Supported Protocol:08 */ |
7bafd888 GH |
3001 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
3002 | ret = (xhci->numports_3<<8) | 1; | |
3003 | } else { | |
3004 | ret = (xhci->numports_3<<8) | (xhci->numports_2+1); | |
3005 | } | |
2d754a10 | 3006 | break; |
62c6ae04 | 3007 | case 0x3c: /* Supported Protocol:0c */ |
2d754a10 GH |
3008 | ret = 0x00000000; /* reserved */ |
3009 | break; | |
62c6ae04 | 3010 | default: |
0ab966cf | 3011 | trace_usb_xhci_unimplemented("cap read", reg); |
2d754a10 | 3012 | ret = 0; |
62c6ae04 | 3013 | } |
2d754a10 GH |
3014 | |
3015 | trace_usb_xhci_cap_read(reg, ret); | |
3016 | return ret; | |
62c6ae04 HM |
3017 | } |
3018 | ||
a8170e5e | 3019 | static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 3020 | { |
1d8a4e69 | 3021 | XHCIPort *port = ptr; |
2d754a10 GH |
3022 | uint32_t ret; |
3023 | ||
1d8a4e69 | 3024 | switch (reg) { |
62c6ae04 | 3025 | case 0x00: /* PORTSC */ |
1d8a4e69 | 3026 | ret = port->portsc; |
2d754a10 | 3027 | break; |
62c6ae04 HM |
3028 | case 0x04: /* PORTPMSC */ |
3029 | case 0x08: /* PORTLI */ | |
2d754a10 GH |
3030 | ret = 0; |
3031 | break; | |
62c6ae04 HM |
3032 | case 0x0c: /* reserved */ |
3033 | default: | |
0ab966cf | 3034 | trace_usb_xhci_unimplemented("port read", reg); |
2d754a10 | 3035 | ret = 0; |
62c6ae04 | 3036 | } |
2d754a10 | 3037 | |
1d8a4e69 | 3038 | trace_usb_xhci_port_read(port->portnr, reg, ret); |
2d754a10 | 3039 | return ret; |
62c6ae04 HM |
3040 | } |
3041 | ||
a8170e5e | 3042 | static void xhci_port_write(void *ptr, hwaddr reg, |
1d8a4e69 | 3043 | uint64_t val, unsigned size) |
62c6ae04 | 3044 | { |
1d8a4e69 | 3045 | XHCIPort *port = ptr; |
bdfce20d | 3046 | uint32_t portsc, notify; |
62c6ae04 | 3047 | |
1d8a4e69 | 3048 | trace_usb_xhci_port_write(port->portnr, reg, val); |
2d754a10 | 3049 | |
1d8a4e69 | 3050 | switch (reg) { |
62c6ae04 | 3051 | case 0x00: /* PORTSC */ |
bdfce20d | 3052 | /* write-1-to-start bits */ |
dad5b9ea GH |
3053 | if (val & PORTSC_WPR) { |
3054 | xhci_port_reset(port, true); | |
3055 | break; | |
3056 | } | |
bdfce20d | 3057 | if (val & PORTSC_PR) { |
dad5b9ea | 3058 | xhci_port_reset(port, false); |
bdfce20d GH |
3059 | break; |
3060 | } | |
3061 | ||
1d8a4e69 | 3062 | portsc = port->portsc; |
bdfce20d | 3063 | notify = 0; |
62c6ae04 HM |
3064 | /* write-1-to-clear bits*/ |
3065 | portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| | |
3066 | PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); | |
3067 | if (val & PORTSC_LWS) { | |
3068 | /* overwrite PLS only when LWS=1 */ | |
bdfce20d GH |
3069 | uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); |
3070 | uint32_t new_pls = get_field(val, PORTSC_PLS); | |
3071 | switch (new_pls) { | |
3072 | case PLS_U0: | |
3073 | if (old_pls != PLS_U0) { | |
3074 | set_field(&portsc, new_pls, PORTSC_PLS); | |
3075 | trace_usb_xhci_port_link(port->portnr, new_pls); | |
3076 | notify = PORTSC_PLC; | |
3077 | } | |
3078 | break; | |
3079 | case PLS_U3: | |
3080 | if (old_pls < PLS_U3) { | |
3081 | set_field(&portsc, new_pls, PORTSC_PLS); | |
3082 | trace_usb_xhci_port_link(port->portnr, new_pls); | |
3083 | } | |
3084 | break; | |
3085 | case PLS_RESUME: | |
3086 | /* windows does this for some reason, don't spam stderr */ | |
3087 | break; | |
3088 | default: | |
d6bb65fc | 3089 | DPRINTF("%s: ignore pls write (old %d, new %d)\n", |
bdfce20d GH |
3090 | __func__, old_pls, new_pls); |
3091 | break; | |
3092 | } | |
62c6ae04 HM |
3093 | } |
3094 | /* read/write bits */ | |
3095 | portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); | |
3096 | portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); | |
40030130 | 3097 | port->portsc = portsc; |
bdfce20d GH |
3098 | if (notify) { |
3099 | xhci_port_notify(port, notify); | |
62c6ae04 | 3100 | } |
62c6ae04 HM |
3101 | break; |
3102 | case 0x04: /* PORTPMSC */ | |
3103 | case 0x08: /* PORTLI */ | |
3104 | default: | |
0ab966cf | 3105 | trace_usb_xhci_unimplemented("port write", reg); |
62c6ae04 HM |
3106 | } |
3107 | } | |
3108 | ||
a8170e5e | 3109 | static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 3110 | { |
1b067564 | 3111 | XHCIState *xhci = ptr; |
2d754a10 | 3112 | uint32_t ret; |
62c6ae04 | 3113 | |
62c6ae04 HM |
3114 | switch (reg) { |
3115 | case 0x00: /* USBCMD */ | |
2d754a10 GH |
3116 | ret = xhci->usbcmd; |
3117 | break; | |
62c6ae04 | 3118 | case 0x04: /* USBSTS */ |
2d754a10 GH |
3119 | ret = xhci->usbsts; |
3120 | break; | |
62c6ae04 | 3121 | case 0x08: /* PAGESIZE */ |
2d754a10 GH |
3122 | ret = 1; /* 4KiB */ |
3123 | break; | |
62c6ae04 | 3124 | case 0x14: /* DNCTRL */ |
2d754a10 GH |
3125 | ret = xhci->dnctrl; |
3126 | break; | |
62c6ae04 | 3127 | case 0x18: /* CRCR low */ |
2d754a10 GH |
3128 | ret = xhci->crcr_low & ~0xe; |
3129 | break; | |
62c6ae04 | 3130 | case 0x1c: /* CRCR high */ |
2d754a10 GH |
3131 | ret = xhci->crcr_high; |
3132 | break; | |
62c6ae04 | 3133 | case 0x30: /* DCBAAP low */ |
2d754a10 GH |
3134 | ret = xhci->dcbaap_low; |
3135 | break; | |
62c6ae04 | 3136 | case 0x34: /* DCBAAP high */ |
2d754a10 GH |
3137 | ret = xhci->dcbaap_high; |
3138 | break; | |
62c6ae04 | 3139 | case 0x38: /* CONFIG */ |
2d754a10 GH |
3140 | ret = xhci->config; |
3141 | break; | |
62c6ae04 | 3142 | default: |
0ab966cf | 3143 | trace_usb_xhci_unimplemented("oper read", reg); |
2d754a10 | 3144 | ret = 0; |
62c6ae04 | 3145 | } |
2d754a10 GH |
3146 | |
3147 | trace_usb_xhci_oper_read(reg, ret); | |
3148 | return ret; | |
62c6ae04 HM |
3149 | } |
3150 | ||
a8170e5e | 3151 | static void xhci_oper_write(void *ptr, hwaddr reg, |
1b067564 | 3152 | uint64_t val, unsigned size) |
62c6ae04 | 3153 | { |
1b067564 | 3154 | XHCIState *xhci = ptr; |
37034575 | 3155 | DeviceState *d = DEVICE(ptr); |
1b067564 | 3156 | |
2d754a10 GH |
3157 | trace_usb_xhci_oper_write(reg, val); |
3158 | ||
62c6ae04 HM |
3159 | switch (reg) { |
3160 | case 0x00: /* USBCMD */ | |
3161 | if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { | |
3162 | xhci_run(xhci); | |
3163 | } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { | |
3164 | xhci_stop(xhci); | |
3165 | } | |
f1f8bc21 GH |
3166 | if (val & USBCMD_CSS) { |
3167 | /* save state */ | |
3168 | xhci->usbsts &= ~USBSTS_SRE; | |
3169 | } | |
3170 | if (val & USBCMD_CRS) { | |
3171 | /* restore state */ | |
3172 | xhci->usbsts |= USBSTS_SRE; | |
3173 | } | |
62c6ae04 | 3174 | xhci->usbcmd = val & 0xc0f; |
01546fa6 | 3175 | xhci_mfwrap_update(xhci); |
62c6ae04 | 3176 | if (val & USBCMD_HCRST) { |
37034575 | 3177 | xhci_reset(d); |
62c6ae04 | 3178 | } |
4c4abe7c | 3179 | xhci_intx_update(xhci); |
62c6ae04 HM |
3180 | break; |
3181 | ||
3182 | case 0x04: /* USBSTS */ | |
3183 | /* these bits are write-1-to-clear */ | |
3184 | xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); | |
4c4abe7c | 3185 | xhci_intx_update(xhci); |
62c6ae04 HM |
3186 | break; |
3187 | ||
3188 | case 0x14: /* DNCTRL */ | |
3189 | xhci->dnctrl = val & 0xffff; | |
3190 | break; | |
3191 | case 0x18: /* CRCR low */ | |
3192 | xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); | |
3193 | break; | |
3194 | case 0x1c: /* CRCR high */ | |
3195 | xhci->crcr_high = val; | |
3196 | if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { | |
3197 | XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; | |
3198 | xhci->crcr_low &= ~CRCR_CRR; | |
2d1de850 | 3199 | xhci_event(xhci, &event, 0); |
62c6ae04 HM |
3200 | DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); |
3201 | } else { | |
59a70ccd | 3202 | dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); |
62c6ae04 HM |
3203 | xhci_ring_init(xhci, &xhci->cmd_ring, base); |
3204 | } | |
3205 | xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); | |
3206 | break; | |
3207 | case 0x30: /* DCBAAP low */ | |
3208 | xhci->dcbaap_low = val & 0xffffffc0; | |
3209 | break; | |
3210 | case 0x34: /* DCBAAP high */ | |
3211 | xhci->dcbaap_high = val; | |
3212 | break; | |
3213 | case 0x38: /* CONFIG */ | |
3214 | xhci->config = val & 0xff; | |
3215 | break; | |
3216 | default: | |
0ab966cf | 3217 | trace_usb_xhci_unimplemented("oper write", reg); |
62c6ae04 HM |
3218 | } |
3219 | } | |
3220 | ||
a8170e5e | 3221 | static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, |
1b067564 | 3222 | unsigned size) |
62c6ae04 | 3223 | { |
1b067564 | 3224 | XHCIState *xhci = ptr; |
43d9d604 | 3225 | uint32_t ret = 0; |
62c6ae04 | 3226 | |
43d9d604 GH |
3227 | if (reg < 0x20) { |
3228 | switch (reg) { | |
3229 | case 0x00: /* MFINDEX */ | |
3230 | ret = xhci_mfindex_get(xhci) & 0x3fff; | |
3231 | break; | |
3232 | default: | |
0ab966cf | 3233 | trace_usb_xhci_unimplemented("runtime read", reg); |
43d9d604 GH |
3234 | break; |
3235 | } | |
3236 | } else { | |
3237 | int v = (reg - 0x20) / 0x20; | |
3238 | XHCIInterrupter *intr = &xhci->intr[v]; | |
3239 | switch (reg & 0x1f) { | |
3240 | case 0x00: /* IMAN */ | |
3241 | ret = intr->iman; | |
3242 | break; | |
3243 | case 0x04: /* IMOD */ | |
3244 | ret = intr->imod; | |
3245 | break; | |
3246 | case 0x08: /* ERSTSZ */ | |
3247 | ret = intr->erstsz; | |
3248 | break; | |
3249 | case 0x10: /* ERSTBA low */ | |
3250 | ret = intr->erstba_low; | |
3251 | break; | |
3252 | case 0x14: /* ERSTBA high */ | |
3253 | ret = intr->erstba_high; | |
3254 | break; | |
3255 | case 0x18: /* ERDP low */ | |
3256 | ret = intr->erdp_low; | |
3257 | break; | |
3258 | case 0x1c: /* ERDP high */ | |
3259 | ret = intr->erdp_high; | |
3260 | break; | |
3261 | } | |
62c6ae04 | 3262 | } |
2d754a10 GH |
3263 | |
3264 | trace_usb_xhci_runtime_read(reg, ret); | |
3265 | return ret; | |
62c6ae04 HM |
3266 | } |
3267 | ||
a8170e5e | 3268 | static void xhci_runtime_write(void *ptr, hwaddr reg, |
1b067564 | 3269 | uint64_t val, unsigned size) |
62c6ae04 | 3270 | { |
1b067564 | 3271 | XHCIState *xhci = ptr; |
43d9d604 GH |
3272 | int v = (reg - 0x20) / 0x20; |
3273 | XHCIInterrupter *intr = &xhci->intr[v]; | |
8e9f18b6 | 3274 | trace_usb_xhci_runtime_write(reg, val); |
62c6ae04 | 3275 | |
43d9d604 | 3276 | if (reg < 0x20) { |
0ab966cf | 3277 | trace_usb_xhci_unimplemented("runtime write", reg); |
43d9d604 GH |
3278 | return; |
3279 | } | |
3280 | ||
3281 | switch (reg & 0x1f) { | |
3282 | case 0x00: /* IMAN */ | |
62c6ae04 | 3283 | if (val & IMAN_IP) { |
962d11e1 | 3284 | intr->iman &= ~IMAN_IP; |
62c6ae04 | 3285 | } |
962d11e1 GH |
3286 | intr->iman &= ~IMAN_IE; |
3287 | intr->iman |= val & IMAN_IE; | |
43d9d604 GH |
3288 | if (v == 0) { |
3289 | xhci_intx_update(xhci); | |
3290 | } | |
3291 | xhci_msix_update(xhci, v); | |
62c6ae04 | 3292 | break; |
43d9d604 | 3293 | case 0x04: /* IMOD */ |
962d11e1 | 3294 | intr->imod = val; |
62c6ae04 | 3295 | break; |
43d9d604 | 3296 | case 0x08: /* ERSTSZ */ |
962d11e1 | 3297 | intr->erstsz = val & 0xffff; |
62c6ae04 | 3298 | break; |
43d9d604 | 3299 | case 0x10: /* ERSTBA low */ |
62c6ae04 | 3300 | /* XXX NEC driver bug: it doesn't align this to 64 bytes |
962d11e1 GH |
3301 | intr->erstba_low = val & 0xffffffc0; */ |
3302 | intr->erstba_low = val & 0xfffffff0; | |
62c6ae04 | 3303 | break; |
43d9d604 | 3304 | case 0x14: /* ERSTBA high */ |
962d11e1 | 3305 | intr->erstba_high = val; |
43d9d604 | 3306 | xhci_er_reset(xhci, v); |
62c6ae04 | 3307 | break; |
43d9d604 | 3308 | case 0x18: /* ERDP low */ |
62c6ae04 | 3309 | if (val & ERDP_EHB) { |
962d11e1 | 3310 | intr->erdp_low &= ~ERDP_EHB; |
62c6ae04 | 3311 | } |
962d11e1 | 3312 | intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); |
62c6ae04 | 3313 | break; |
43d9d604 | 3314 | case 0x1c: /* ERDP high */ |
962d11e1 | 3315 | intr->erdp_high = val; |
43d9d604 | 3316 | xhci_events_update(xhci, v); |
62c6ae04 HM |
3317 | break; |
3318 | default: | |
0ab966cf | 3319 | trace_usb_xhci_unimplemented("oper write", reg); |
62c6ae04 HM |
3320 | } |
3321 | } | |
3322 | ||
a8170e5e | 3323 | static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, |
1b067564 | 3324 | unsigned size) |
62c6ae04 | 3325 | { |
62c6ae04 | 3326 | /* doorbells always read as 0 */ |
2d754a10 | 3327 | trace_usb_xhci_doorbell_read(reg, 0); |
62c6ae04 HM |
3328 | return 0; |
3329 | } | |
3330 | ||
a8170e5e | 3331 | static void xhci_doorbell_write(void *ptr, hwaddr reg, |
1b067564 | 3332 | uint64_t val, unsigned size) |
62c6ae04 | 3333 | { |
1b067564 | 3334 | XHCIState *xhci = ptr; |
024426ac | 3335 | unsigned int epid, streamid; |
1b067564 | 3336 | |
2d754a10 | 3337 | trace_usb_xhci_doorbell_write(reg, val); |
62c6ae04 HM |
3338 | |
3339 | if (!xhci_running(xhci)) { | |
d6bb65fc | 3340 | DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); |
62c6ae04 HM |
3341 | return; |
3342 | } | |
3343 | ||
3344 | reg >>= 2; | |
3345 | ||
3346 | if (reg == 0) { | |
3347 | if (val == 0) { | |
3348 | xhci_process_commands(xhci); | |
3349 | } else { | |
d6bb65fc | 3350 | DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", |
1b067564 | 3351 | (uint32_t)val); |
62c6ae04 HM |
3352 | } |
3353 | } else { | |
024426ac GH |
3354 | epid = val & 0xff; |
3355 | streamid = (val >> 16) & 0xffff; | |
91062ae0 | 3356 | if (reg > xhci->numslots) { |
d6bb65fc | 3357 | DPRINTF("xhci: bad doorbell %d\n", (int)reg); |
024426ac | 3358 | } else if (epid > 31) { |
d6bb65fc | 3359 | DPRINTF("xhci: bad doorbell %d write: 0x%x\n", |
1b067564 | 3360 | (int)reg, (uint32_t)val); |
62c6ae04 | 3361 | } else { |
024426ac | 3362 | xhci_kick_ep(xhci, reg, epid, streamid); |
62c6ae04 HM |
3363 | } |
3364 | } | |
3365 | } | |
3366 | ||
6d3bc22e GH |
3367 | static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, |
3368 | unsigned width) | |
3369 | { | |
3370 | /* nothing */ | |
3371 | } | |
3372 | ||
1b067564 GH |
3373 | static const MemoryRegionOps xhci_cap_ops = { |
3374 | .read = xhci_cap_read, | |
6d3bc22e | 3375 | .write = xhci_cap_write, |
6ee021d4 | 3376 | .valid.min_access_size = 1, |
1b067564 | 3377 | .valid.max_access_size = 4, |
6ee021d4 GH |
3378 | .impl.min_access_size = 4, |
3379 | .impl.max_access_size = 4, | |
1b067564 GH |
3380 | .endianness = DEVICE_LITTLE_ENDIAN, |
3381 | }; | |
62c6ae04 | 3382 | |
1b067564 GH |
3383 | static const MemoryRegionOps xhci_oper_ops = { |
3384 | .read = xhci_oper_read, | |
3385 | .write = xhci_oper_write, | |
3386 | .valid.min_access_size = 4, | |
3387 | .valid.max_access_size = 4, | |
3388 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3389 | }; | |
62c6ae04 | 3390 | |
1d8a4e69 GH |
3391 | static const MemoryRegionOps xhci_port_ops = { |
3392 | .read = xhci_port_read, | |
3393 | .write = xhci_port_write, | |
3394 | .valid.min_access_size = 4, | |
3395 | .valid.max_access_size = 4, | |
3396 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3397 | }; | |
3398 | ||
1b067564 GH |
3399 | static const MemoryRegionOps xhci_runtime_ops = { |
3400 | .read = xhci_runtime_read, | |
3401 | .write = xhci_runtime_write, | |
3402 | .valid.min_access_size = 4, | |
3403 | .valid.max_access_size = 4, | |
3404 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3405 | }; | |
62c6ae04 | 3406 | |
1b067564 GH |
3407 | static const MemoryRegionOps xhci_doorbell_ops = { |
3408 | .read = xhci_doorbell_read, | |
3409 | .write = xhci_doorbell_write, | |
62c6ae04 HM |
3410 | .valid.min_access_size = 4, |
3411 | .valid.max_access_size = 4, | |
3412 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3413 | }; | |
3414 | ||
3415 | static void xhci_attach(USBPort *usbport) | |
3416 | { | |
3417 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3418 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
62c6ae04 | 3419 | |
f3214027 | 3420 | xhci_port_update(port, 0); |
62c6ae04 HM |
3421 | } |
3422 | ||
3423 | static void xhci_detach(USBPort *usbport) | |
3424 | { | |
3425 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3426 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
62c6ae04 | 3427 | |
f3dcf638 | 3428 | xhci_detach_slot(xhci, usbport); |
f3214027 | 3429 | xhci_port_update(port, 1); |
62c6ae04 HM |
3430 | } |
3431 | ||
8c735e43 GH |
3432 | static void xhci_wakeup(USBPort *usbport) |
3433 | { | |
3434 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3435 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
8c735e43 | 3436 | |
85e05d82 | 3437 | if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { |
8c735e43 GH |
3438 | return; |
3439 | } | |
85e05d82 | 3440 | set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); |
f705a362 | 3441 | xhci_port_notify(port, PORTSC_PLC); |
8c735e43 GH |
3442 | } |
3443 | ||
62c6ae04 HM |
3444 | static void xhci_complete(USBPort *port, USBPacket *packet) |
3445 | { | |
3446 | XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); | |
3447 | ||
9a77a0f5 | 3448 | if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { |
582d6f4a | 3449 | xhci_ep_nuke_one_xfer(xfer, 0); |
0cae7b1a HG |
3450 | return; |
3451 | } | |
9a77a0f5 | 3452 | xhci_complete_packet(xfer); |
024426ac | 3453 | xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); |
62c6ae04 HM |
3454 | } |
3455 | ||
ccaf87a0 | 3456 | static void xhci_child_detach(USBPort *uport, USBDevice *child) |
62c6ae04 | 3457 | { |
ccaf87a0 GH |
3458 | USBBus *bus = usb_bus_from_device(child); |
3459 | XHCIState *xhci = container_of(bus, XHCIState, bus); | |
ccaf87a0 | 3460 | |
463c534d | 3461 | xhci_detach_slot(xhci, child->port); |
62c6ae04 HM |
3462 | } |
3463 | ||
1d8a4e69 | 3464 | static USBPortOps xhci_uport_ops = { |
62c6ae04 HM |
3465 | .attach = xhci_attach, |
3466 | .detach = xhci_detach, | |
8c735e43 | 3467 | .wakeup = xhci_wakeup, |
62c6ae04 HM |
3468 | .complete = xhci_complete, |
3469 | .child_detach = xhci_child_detach, | |
3470 | }; | |
3471 | ||
7c605a23 GH |
3472 | static int xhci_find_epid(USBEndpoint *ep) |
3473 | { | |
3474 | if (ep->nr == 0) { | |
3475 | return 1; | |
3476 | } | |
3477 | if (ep->pid == USB_TOKEN_IN) { | |
3478 | return ep->nr * 2 + 1; | |
3479 | } else { | |
3480 | return ep->nr * 2; | |
3481 | } | |
3482 | } | |
3483 | ||
518ad5f2 HG |
3484 | static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, |
3485 | unsigned int slotid, unsigned int epid) | |
3486 | { | |
3487 | assert(slotid >= 1 && slotid <= xhci->numslots); | |
3488 | ||
3489 | if (!xhci->slots[slotid - 1].uport) { | |
3490 | return NULL; | |
3491 | } | |
3492 | ||
3493 | return usb_ep_get(xhci->slots[slotid - 1].uport->dev, | |
3494 | (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1); | |
3495 | } | |
3496 | ||
8550a02d GH |
3497 | static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, |
3498 | unsigned int stream) | |
7c605a23 GH |
3499 | { |
3500 | XHCIState *xhci = container_of(bus, XHCIState, bus); | |
3501 | int slotid; | |
3502 | ||
3503 | DPRINTF("%s\n", __func__); | |
af203be3 | 3504 | slotid = ep->dev->addr; |
7c605a23 GH |
3505 | if (slotid == 0 || !xhci->slots[slotid-1].enabled) { |
3506 | DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); | |
3507 | return; | |
3508 | } | |
024426ac | 3509 | xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); |
7c605a23 GH |
3510 | } |
3511 | ||
62c6ae04 | 3512 | static USBBusOps xhci_bus_ops = { |
7c605a23 | 3513 | .wakeup_endpoint = xhci_wakeup_endpoint, |
62c6ae04 HM |
3514 | }; |
3515 | ||
37034575 | 3516 | static void usb_xhci_init(XHCIState *xhci) |
62c6ae04 | 3517 | { |
37034575 | 3518 | DeviceState *dev = DEVICE(xhci); |
0846e635 GH |
3519 | XHCIPort *port; |
3520 | int i, usbports, speedmask; | |
62c6ae04 HM |
3521 | |
3522 | xhci->usbsts = USBSTS_HCH; | |
3523 | ||
0846e635 GH |
3524 | if (xhci->numports_2 > MAXPORTS_2) { |
3525 | xhci->numports_2 = MAXPORTS_2; | |
3526 | } | |
3527 | if (xhci->numports_3 > MAXPORTS_3) { | |
3528 | xhci->numports_3 = MAXPORTS_3; | |
3529 | } | |
3530 | usbports = MAX(xhci->numports_2, xhci->numports_3); | |
3531 | xhci->numports = xhci->numports_2 + xhci->numports_3; | |
3532 | ||
c889b3a5 | 3533 | usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); |
62c6ae04 | 3534 | |
0846e635 GH |
3535 | for (i = 0; i < usbports; i++) { |
3536 | speedmask = 0; | |
3537 | if (i < xhci->numports_2) { | |
7bafd888 GH |
3538 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
3539 | port = &xhci->ports[i + xhci->numports_3]; | |
3540 | port->portnr = i + 1 + xhci->numports_3; | |
3541 | } else { | |
3542 | port = &xhci->ports[i]; | |
3543 | port->portnr = i + 1; | |
3544 | } | |
0846e635 GH |
3545 | port->uport = &xhci->uports[i]; |
3546 | port->speedmask = | |
3547 | USB_SPEED_MASK_LOW | | |
3548 | USB_SPEED_MASK_FULL | | |
3549 | USB_SPEED_MASK_HIGH; | |
1d8a4e69 | 3550 | snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); |
0846e635 GH |
3551 | speedmask |= port->speedmask; |
3552 | } | |
3553 | if (i < xhci->numports_3) { | |
7bafd888 GH |
3554 | if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { |
3555 | port = &xhci->ports[i]; | |
3556 | port->portnr = i + 1; | |
3557 | } else { | |
3558 | port = &xhci->ports[i + xhci->numports_2]; | |
3559 | port->portnr = i + 1 + xhci->numports_2; | |
3560 | } | |
0846e635 GH |
3561 | port->uport = &xhci->uports[i]; |
3562 | port->speedmask = USB_SPEED_MASK_SUPER; | |
1d8a4e69 | 3563 | snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); |
0846e635 GH |
3564 | speedmask |= port->speedmask; |
3565 | } | |
3566 | usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, | |
1d8a4e69 | 3567 | &xhci_uport_ops, speedmask); |
62c6ae04 | 3568 | } |
62c6ae04 HM |
3569 | } |
3570 | ||
3571 | static int usb_xhci_initfn(struct PCIDevice *dev) | |
3572 | { | |
1d8a4e69 | 3573 | int i, ret; |
62c6ae04 | 3574 | |
37034575 | 3575 | XHCIState *xhci = XHCI(dev); |
62c6ae04 | 3576 | |
9b7d3334 AF |
3577 | dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ |
3578 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ | |
3579 | dev->config[PCI_CACHE_LINE_SIZE] = 0x10; | |
3580 | dev->config[0x60] = 0x30; /* release number */ | |
62c6ae04 | 3581 | |
37034575 | 3582 | usb_xhci_init(xhci); |
62c6ae04 | 3583 | |
91062ae0 GH |
3584 | if (xhci->numintrs > MAXINTRS) { |
3585 | xhci->numintrs = MAXINTRS; | |
3586 | } | |
c94a7c69 GH |
3587 | while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ |
3588 | xhci->numintrs++; | |
3589 | } | |
91062ae0 GH |
3590 | if (xhci->numintrs < 1) { |
3591 | xhci->numintrs = 1; | |
3592 | } | |
3593 | if (xhci->numslots > MAXSLOTS) { | |
3594 | xhci->numslots = MAXSLOTS; | |
3595 | } | |
3596 | if (xhci->numslots < 1) { | |
3597 | xhci->numslots = 1; | |
3598 | } | |
3599 | ||
bc72ad67 | 3600 | xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); |
01546fa6 | 3601 | |
22fc860b PB |
3602 | memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); |
3603 | memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, | |
1b067564 | 3604 | "capabilities", LEN_CAP); |
22fc860b | 3605 | memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, |
1d8a4e69 | 3606 | "operational", 0x400); |
22fc860b | 3607 | memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, |
1b067564 | 3608 | "runtime", LEN_RUNTIME); |
22fc860b | 3609 | memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, |
1b067564 GH |
3610 | "doorbell", LEN_DOORBELL); |
3611 | ||
3612 | memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); | |
3613 | memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); | |
3614 | memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); | |
3615 | memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); | |
3616 | ||
1d8a4e69 GH |
3617 | for (i = 0; i < xhci->numports; i++) { |
3618 | XHCIPort *port = &xhci->ports[i]; | |
3619 | uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; | |
3620 | port->xhci = xhci; | |
22fc860b | 3621 | memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, |
1d8a4e69 GH |
3622 | port->name, 0x10); |
3623 | memory_region_add_subregion(&xhci->mem, offset, &port->mem); | |
3624 | } | |
3625 | ||
9b7d3334 | 3626 | pci_register_bar(dev, 0, |
62c6ae04 HM |
3627 | PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, |
3628 | &xhci->mem); | |
3629 | ||
e6043e92 DDAG |
3630 | if (pci_bus_is_express(dev->bus) || |
3631 | xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { | |
058fdcf5 GH |
3632 | ret = pcie_endpoint_cap_init(dev, 0xa0); |
3633 | assert(ret >= 0); | |
3634 | } | |
62c6ae04 | 3635 | |
f9955235 | 3636 | if (xhci_get_flag(xhci, XHCI_FLAG_USE_MSI)) { |
9b7d3334 | 3637 | msi_init(dev, 0x70, xhci->numintrs, true, false); |
62c6ae04 | 3638 | } |
f9955235 | 3639 | if (xhci_get_flag(xhci, XHCI_FLAG_USE_MSI_X)) { |
9b7d3334 | 3640 | msix_init(dev, xhci->numintrs, |
4c47f800 GH |
3641 | &xhci->mem, 0, OFF_MSIX_TABLE, |
3642 | &xhci->mem, 0, OFF_MSIX_PBA, | |
3643 | 0x90); | |
3644 | } | |
62c6ae04 HM |
3645 | |
3646 | return 0; | |
3647 | } | |
3648 | ||
53c30545 GA |
3649 | static void usb_xhci_exit(PCIDevice *dev) |
3650 | { | |
3651 | int i; | |
3652 | XHCIState *xhci = XHCI(dev); | |
3653 | ||
d733f74c GA |
3654 | trace_usb_xhci_exit(); |
3655 | ||
53c30545 GA |
3656 | for (i = 0; i < xhci->numslots; i++) { |
3657 | xhci_disable_slot(xhci, i + 1); | |
3658 | } | |
3659 | ||
3660 | if (xhci->mfwrap_timer) { | |
3661 | timer_del(xhci->mfwrap_timer); | |
3662 | timer_free(xhci->mfwrap_timer); | |
3663 | xhci->mfwrap_timer = NULL; | |
3664 | } | |
3665 | ||
3666 | memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); | |
3667 | memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); | |
3668 | memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); | |
3669 | memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); | |
3670 | ||
3671 | for (i = 0; i < xhci->numports; i++) { | |
3672 | XHCIPort *port = &xhci->ports[i]; | |
3673 | memory_region_del_subregion(&xhci->mem, &port->mem); | |
3674 | } | |
3675 | ||
3676 | /* destroy msix memory region */ | |
3677 | if (dev->msix_table && dev->msix_pba | |
3678 | && dev->msix_entry_used) { | |
3679 | memory_region_del_subregion(&xhci->mem, &dev->msix_table_mmio); | |
3680 | memory_region_del_subregion(&xhci->mem, &dev->msix_pba_mmio); | |
3681 | } | |
3682 | ||
3683 | usb_bus_release(&xhci->bus); | |
3684 | } | |
3685 | ||
37352df3 GH |
3686 | static int usb_xhci_post_load(void *opaque, int version_id) |
3687 | { | |
3688 | XHCIState *xhci = opaque; | |
9b7d3334 | 3689 | PCIDevice *pci_dev = PCI_DEVICE(xhci); |
37352df3 GH |
3690 | XHCISlot *slot; |
3691 | XHCIEPContext *epctx; | |
3692 | dma_addr_t dcbaap, pctx; | |
3693 | uint32_t slot_ctx[4]; | |
3694 | uint32_t ep_ctx[5]; | |
3695 | int slotid, epid, state, intr; | |
3696 | ||
3697 | dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); | |
3698 | ||
3699 | for (slotid = 1; slotid <= xhci->numslots; slotid++) { | |
3700 | slot = &xhci->slots[slotid-1]; | |
3701 | if (!slot->addressed) { | |
3702 | continue; | |
3703 | } | |
3704 | slot->ctx = | |
9b7d3334 | 3705 | xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); |
37352df3 GH |
3706 | xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); |
3707 | slot->uport = xhci_lookup_uport(xhci, slot_ctx); | |
3708 | assert(slot->uport && slot->uport->dev); | |
3709 | ||
f6969b9f | 3710 | for (epid = 1; epid <= 31; epid++) { |
37352df3 GH |
3711 | pctx = slot->ctx + 32 * epid; |
3712 | xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); | |
3713 | state = ep_ctx[0] & EP_STATE_MASK; | |
3714 | if (state == EP_DISABLED) { | |
3715 | continue; | |
3716 | } | |
3717 | epctx = xhci_alloc_epctx(xhci, slotid, epid); | |
3718 | slot->eps[epid-1] = epctx; | |
3719 | xhci_init_epctx(epctx, pctx, ep_ctx); | |
3720 | epctx->state = state; | |
3721 | if (state == EP_RUNNING) { | |
3722 | /* kick endpoint after vmload is finished */ | |
bc72ad67 | 3723 | timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
37352df3 GH |
3724 | } |
3725 | } | |
3726 | } | |
3727 | ||
3728 | for (intr = 0; intr < xhci->numintrs; intr++) { | |
3729 | if (xhci->intr[intr].msix_used) { | |
9b7d3334 | 3730 | msix_vector_use(pci_dev, intr); |
37352df3 | 3731 | } else { |
9b7d3334 | 3732 | msix_vector_unuse(pci_dev, intr); |
37352df3 GH |
3733 | } |
3734 | } | |
3735 | ||
3736 | return 0; | |
3737 | } | |
3738 | ||
3739 | static const VMStateDescription vmstate_xhci_ring = { | |
3740 | .name = "xhci-ring", | |
3741 | .version_id = 1, | |
3742 | .fields = (VMStateField[]) { | |
3743 | VMSTATE_UINT64(dequeue, XHCIRing), | |
3744 | VMSTATE_BOOL(ccs, XHCIRing), | |
3745 | VMSTATE_END_OF_LIST() | |
3746 | } | |
3747 | }; | |
3748 | ||
3749 | static const VMStateDescription vmstate_xhci_port = { | |
3750 | .name = "xhci-port", | |
3751 | .version_id = 1, | |
3752 | .fields = (VMStateField[]) { | |
3753 | VMSTATE_UINT32(portsc, XHCIPort), | |
3754 | VMSTATE_END_OF_LIST() | |
3755 | } | |
3756 | }; | |
3757 | ||
3758 | static const VMStateDescription vmstate_xhci_slot = { | |
3759 | .name = "xhci-slot", | |
3760 | .version_id = 1, | |
3761 | .fields = (VMStateField[]) { | |
3762 | VMSTATE_BOOL(enabled, XHCISlot), | |
3763 | VMSTATE_BOOL(addressed, XHCISlot), | |
3764 | VMSTATE_END_OF_LIST() | |
3765 | } | |
3766 | }; | |
3767 | ||
3768 | static const VMStateDescription vmstate_xhci_event = { | |
3769 | .name = "xhci-event", | |
3770 | .version_id = 1, | |
3771 | .fields = (VMStateField[]) { | |
3772 | VMSTATE_UINT32(type, XHCIEvent), | |
3773 | VMSTATE_UINT32(ccode, XHCIEvent), | |
3774 | VMSTATE_UINT64(ptr, XHCIEvent), | |
3775 | VMSTATE_UINT32(length, XHCIEvent), | |
3776 | VMSTATE_UINT32(flags, XHCIEvent), | |
3777 | VMSTATE_UINT8(slotid, XHCIEvent), | |
3778 | VMSTATE_UINT8(epid, XHCIEvent), | |
3afca1d6 | 3779 | VMSTATE_END_OF_LIST() |
37352df3 GH |
3780 | } |
3781 | }; | |
3782 | ||
3783 | static bool xhci_er_full(void *opaque, int version_id) | |
3784 | { | |
3785 | struct XHCIInterrupter *intr = opaque; | |
3786 | return intr->er_full; | |
3787 | } | |
3788 | ||
3789 | static const VMStateDescription vmstate_xhci_intr = { | |
3790 | .name = "xhci-intr", | |
3791 | .version_id = 1, | |
3792 | .fields = (VMStateField[]) { | |
3793 | /* registers */ | |
3794 | VMSTATE_UINT32(iman, XHCIInterrupter), | |
3795 | VMSTATE_UINT32(imod, XHCIInterrupter), | |
3796 | VMSTATE_UINT32(erstsz, XHCIInterrupter), | |
3797 | VMSTATE_UINT32(erstba_low, XHCIInterrupter), | |
3798 | VMSTATE_UINT32(erstba_high, XHCIInterrupter), | |
3799 | VMSTATE_UINT32(erdp_low, XHCIInterrupter), | |
3800 | VMSTATE_UINT32(erdp_high, XHCIInterrupter), | |
3801 | ||
3802 | /* state */ | |
3803 | VMSTATE_BOOL(msix_used, XHCIInterrupter), | |
3804 | VMSTATE_BOOL(er_pcs, XHCIInterrupter), | |
3805 | VMSTATE_UINT64(er_start, XHCIInterrupter), | |
3806 | VMSTATE_UINT32(er_size, XHCIInterrupter), | |
3807 | VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), | |
3808 | ||
3809 | /* event queue (used if ring is full) */ | |
3810 | VMSTATE_BOOL(er_full, XHCIInterrupter), | |
3811 | VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), | |
3812 | VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), | |
3813 | VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, | |
3814 | xhci_er_full, 1, | |
3815 | vmstate_xhci_event, XHCIEvent), | |
3816 | ||
3817 | VMSTATE_END_OF_LIST() | |
3818 | } | |
3819 | }; | |
3820 | ||
62c6ae04 HM |
3821 | static const VMStateDescription vmstate_xhci = { |
3822 | .name = "xhci", | |
37352df3 GH |
3823 | .version_id = 1, |
3824 | .post_load = usb_xhci_post_load, | |
3825 | .fields = (VMStateField[]) { | |
9b7d3334 AF |
3826 | VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), |
3827 | VMSTATE_MSIX(parent_obj, XHCIState), | |
37352df3 GH |
3828 | |
3829 | VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, | |
3830 | vmstate_xhci_port, XHCIPort), | |
3831 | VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, | |
3832 | vmstate_xhci_slot, XHCISlot), | |
3833 | VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, | |
3834 | vmstate_xhci_intr, XHCIInterrupter), | |
3835 | ||
3836 | /* Operational Registers */ | |
3837 | VMSTATE_UINT32(usbcmd, XHCIState), | |
3838 | VMSTATE_UINT32(usbsts, XHCIState), | |
3839 | VMSTATE_UINT32(dnctrl, XHCIState), | |
3840 | VMSTATE_UINT32(crcr_low, XHCIState), | |
3841 | VMSTATE_UINT32(crcr_high, XHCIState), | |
3842 | VMSTATE_UINT32(dcbaap_low, XHCIState), | |
3843 | VMSTATE_UINT32(dcbaap_high, XHCIState), | |
3844 | VMSTATE_UINT32(config, XHCIState), | |
3845 | ||
3846 | /* Runtime Registers & state */ | |
3847 | VMSTATE_INT64(mfindex_start, XHCIState), | |
3848 | VMSTATE_TIMER(mfwrap_timer, XHCIState), | |
3849 | VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), | |
3850 | ||
3851 | VMSTATE_END_OF_LIST() | |
3852 | } | |
62c6ae04 HM |
3853 | }; |
3854 | ||
39bffca2 | 3855 | static Property xhci_properties[] = { |
91062ae0 GH |
3856 | DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), |
3857 | DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), | |
7bafd888 GH |
3858 | DEFINE_PROP_BIT("superspeed-ports-first", |
3859 | XHCIState, flags, XHCI_FLAG_SS_FIRST, true), | |
e6043e92 DDAG |
3860 | DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, |
3861 | XHCI_FLAG_FORCE_PCIE_ENDCAP, false), | |
91062ae0 GH |
3862 | DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), |
3863 | DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), | |
3864 | DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), | |
3865 | DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), | |
39bffca2 AL |
3866 | DEFINE_PROP_END_OF_LIST(), |
3867 | }; | |
3868 | ||
40021f08 AL |
3869 | static void xhci_class_init(ObjectClass *klass, void *data) |
3870 | { | |
3871 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 3872 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 3873 | |
39bffca2 AL |
3874 | dc->vmsd = &vmstate_xhci; |
3875 | dc->props = xhci_properties; | |
64619739 | 3876 | dc->reset = xhci_reset; |
2897ae02 | 3877 | dc->hotpluggable = false; |
125ee0ed | 3878 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
40021f08 | 3879 | k->init = usb_xhci_initfn; |
53c30545 | 3880 | k->exit = usb_xhci_exit; |
40021f08 AL |
3881 | k->vendor_id = PCI_VENDOR_ID_NEC; |
3882 | k->device_id = PCI_DEVICE_ID_NEC_UPD720200; | |
3883 | k->class_id = PCI_CLASS_SERIAL_USB; | |
3884 | k->revision = 0x03; | |
3885 | k->is_express = 1; | |
40021f08 AL |
3886 | } |
3887 | ||
8c43a6f0 | 3888 | static const TypeInfo xhci_info = { |
37034575 | 3889 | .name = TYPE_XHCI, |
39bffca2 AL |
3890 | .parent = TYPE_PCI_DEVICE, |
3891 | .instance_size = sizeof(XHCIState), | |
3892 | .class_init = xhci_class_init, | |
62c6ae04 HM |
3893 | }; |
3894 | ||
83f7d43a | 3895 | static void xhci_register_types(void) |
62c6ae04 | 3896 | { |
39bffca2 | 3897 | type_register_static(&xhci_info); |
62c6ae04 | 3898 | } |
83f7d43a AF |
3899 | |
3900 | type_init(xhci_register_types) |