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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
23 | */ |
24 | ||
25 | #include "hw.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "usb.h" | |
28 | #include "pci.h" | |
29 | #include "monitor.h" | |
439a97cc | 30 | #include "trace.h" |
0ce668bc | 31 | #include "dma.h" |
94527ead GH |
32 | |
33 | #define EHCI_DEBUG 0 | |
94527ead | 34 | |
26d53979 | 35 | #if EHCI_DEBUG |
94527ead GH |
36 | #define DPRINTF printf |
37 | #else | |
38 | #define DPRINTF(...) | |
39 | #endif | |
40 | ||
94527ead GH |
41 | /* internal processing - reset HC to try and recover */ |
42 | #define USB_RET_PROCERR (-99) | |
43 | ||
44 | #define MMIO_SIZE 0x1000 | |
45 | ||
46 | /* Capability Registers Base Address - section 2.2 */ | |
47 | #define CAPREGBASE 0x0000 | |
48 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
49 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
50 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
51 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
52 | #define EECP HCCPARAMS + 1 | |
53 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
54 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
55 | ||
56 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
57 | ||
58 | #define USBCMD OPREGBASE + 0x0000 | |
59 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
60 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
61 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
62 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
63 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
64 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
65 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
66 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
67 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
68 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
69 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
70 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
71 | ||
72 | #define USBSTS OPREGBASE + 0x0004 | |
73 | #define USBSTS_RO_MASK 0x0000003f | |
74 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
75 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
76 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
77 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
78 | #define USBSTS_HSE (1 << 4) // Host System Error | |
79 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
80 | #define USBSTS_HALT (1 << 12) // HC Halted | |
81 | #define USBSTS_REC (1 << 13) // Reclamation | |
82 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
83 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
84 | ||
85 | /* | |
86 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
87 | * so no need to redefine here. | |
88 | */ | |
89 | #define USBINTR OPREGBASE + 0x0008 | |
90 | #define USBINTR_MASK 0x0000003f | |
91 | ||
92 | #define FRINDEX OPREGBASE + 0x000c | |
93 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
94 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
95 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
96 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
97 | ||
98 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
99 | ||
100 | #define PORTSC (OPREGBASE + 0x0044) | |
101 | #define PORTSC_BEGIN PORTSC | |
102 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
103 | /* | |
c44fd61c | 104 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
105 | * written to us by software |
106 | */ | |
a0a3167a | 107 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
108 | #define PORTSC_RWC_MASK 0x0000002a |
109 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
110 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
111 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
112 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
113 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
114 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
115 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
116 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
117 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
118 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
119 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
120 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
121 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
122 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
123 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
124 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
125 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
126 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
127 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
128 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
129 | ||
130 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 131 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
132 | |
133 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
5cc194ca | 134 | #define NB_PORTS 6 // Number of downstream ports |
94527ead GH |
135 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
136 | #define MAX_ITERATIONS 20 // Max number of QH before we break the loop | |
137 | #define MAX_QH 100 // Max allowable queue heads in a chain | |
138 | ||
139 | /* Internal periodic / asynchronous schedule state machine states | |
140 | */ | |
141 | typedef enum { | |
142 | EST_INACTIVE = 1000, | |
143 | EST_ACTIVE, | |
144 | EST_EXECUTING, | |
145 | EST_SLEEPING, | |
146 | /* The following states are internal to the state machine function | |
147 | */ | |
148 | EST_WAITLISTHEAD, | |
149 | EST_FETCHENTRY, | |
150 | EST_FETCHQH, | |
151 | EST_FETCHITD, | |
2fe80192 | 152 | EST_FETCHSITD, |
94527ead GH |
153 | EST_ADVANCEQUEUE, |
154 | EST_FETCHQTD, | |
155 | EST_EXECUTE, | |
156 | EST_WRITEBACK, | |
157 | EST_HORIZONTALQH | |
158 | } EHCI_STATES; | |
159 | ||
160 | /* macros for accessing fields within next link pointer entry */ | |
161 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
162 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
163 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
164 | ||
165 | /* link pointer types */ | |
166 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
167 | #define NLPTR_TYPE_QH 1 // queue head | |
168 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
169 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
170 | ||
171 | ||
172 | /* EHCI spec version 1.0 Section 3.3 | |
173 | */ | |
174 | typedef struct EHCIitd { | |
175 | uint32_t next; | |
176 | ||
177 | uint32_t transact[8]; | |
178 | #define ITD_XACT_ACTIVE (1 << 31) | |
179 | #define ITD_XACT_DBERROR (1 << 30) | |
180 | #define ITD_XACT_BABBLE (1 << 29) | |
181 | #define ITD_XACT_XACTERR (1 << 28) | |
182 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
183 | #define ITD_XACT_LENGTH_SH 16 | |
184 | #define ITD_XACT_IOC (1 << 15) | |
185 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
186 | #define ITD_XACT_PGSEL_SH 12 | |
187 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
188 | ||
189 | uint32_t bufptr[7]; | |
190 | #define ITD_BUFPTR_MASK 0xfffff000 | |
191 | #define ITD_BUFPTR_SH 12 | |
192 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
193 | #define ITD_BUFPTR_EP_SH 8 | |
194 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
195 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
196 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
197 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
198 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
199 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 200 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
201 | } EHCIitd; |
202 | ||
203 | /* EHCI spec version 1.0 Section 3.4 | |
204 | */ | |
205 | typedef struct EHCIsitd { | |
206 | uint32_t next; // Standard next link pointer | |
207 | uint32_t epchar; | |
208 | #define SITD_EPCHAR_IO (1 << 31) | |
209 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
210 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
211 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
212 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
213 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
214 | #define SITD_EPCHAR_EPNUM_SH 8 | |
215 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
216 | ||
217 | uint32_t uframe; | |
218 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
219 | #define SITD_UFRAME_CMASK_SH 8 | |
220 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
221 | ||
222 | uint32_t results; | |
223 | #define SITD_RESULTS_IOC (1 << 31) | |
224 | #define SITD_RESULTS_PGSEL (1 << 30) | |
225 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
226 | #define SITD_RESULTS_TYBYTES_SH 16 | |
227 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
228 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
229 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
230 | #define SITD_RESULTS_ERR (1 << 6) | |
231 | #define SITD_RESULTS_DBERR (1 << 5) | |
232 | #define SITD_RESULTS_BABBLE (1 << 4) | |
233 | #define SITD_RESULTS_XACTERR (1 << 3) | |
234 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
235 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
236 | ||
237 | uint32_t bufptr[2]; | |
238 | #define SITD_BUFPTR_MASK 0xfffff000 | |
239 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
240 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
241 | #define SITD_BUFPTR_TPOS_SH 3 | |
242 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
243 | ||
244 | uint32_t backptr; // Standard next link pointer | |
245 | } EHCIsitd; | |
246 | ||
247 | /* EHCI spec version 1.0 Section 3.5 | |
248 | */ | |
249 | typedef struct EHCIqtd { | |
250 | uint32_t next; // Standard next link pointer | |
251 | uint32_t altnext; // Standard next link pointer | |
252 | uint32_t token; | |
253 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
254 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
255 | #define QTD_TOKEN_TBYTES_SH 16 | |
256 | #define QTD_TOKEN_IOC (1 << 15) | |
257 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
258 | #define QTD_TOKEN_CPAGE_SH 12 | |
259 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
260 | #define QTD_TOKEN_CERR_SH 10 | |
261 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
262 | #define QTD_TOKEN_PID_SH 8 | |
263 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
264 | #define QTD_TOKEN_HALT (1 << 6) | |
265 | #define QTD_TOKEN_DBERR (1 << 5) | |
266 | #define QTD_TOKEN_BABBLE (1 << 4) | |
267 | #define QTD_TOKEN_XACTERR (1 << 3) | |
268 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
269 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
270 | #define QTD_TOKEN_PING (1 << 0) | |
271 | ||
272 | uint32_t bufptr[5]; // Standard buffer pointer | |
273 | #define QTD_BUFPTR_MASK 0xfffff000 | |
0ce668bc | 274 | #define QTD_BUFPTR_SH 12 |
94527ead GH |
275 | } EHCIqtd; |
276 | ||
277 | /* EHCI spec version 1.0 Section 3.6 | |
278 | */ | |
279 | typedef struct EHCIqh { | |
280 | uint32_t next; // Standard next link pointer | |
281 | ||
282 | /* endpoint characteristics */ | |
283 | uint32_t epchar; | |
284 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
285 | #define QH_EPCHAR_RL_SH 28 | |
286 | #define QH_EPCHAR_C (1 << 27) | |
287 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
288 | #define QH_EPCHAR_MPLEN_SH 16 | |
289 | #define QH_EPCHAR_H (1 << 15) | |
290 | #define QH_EPCHAR_DTC (1 << 14) | |
291 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
292 | #define QH_EPCHAR_EPS_SH 12 | |
293 | #define EHCI_QH_EPS_FULL 0 | |
294 | #define EHCI_QH_EPS_LOW 1 | |
295 | #define EHCI_QH_EPS_HIGH 2 | |
296 | #define EHCI_QH_EPS_RESERVED 3 | |
297 | ||
298 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
299 | #define QH_EPCHAR_EP_SH 8 | |
300 | #define QH_EPCHAR_I (1 << 7) | |
301 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
302 | #define QH_EPCHAR_DEVADDR_SH 0 | |
303 | ||
304 | /* endpoint capabilities */ | |
305 | uint32_t epcap; | |
306 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
307 | #define QH_EPCAP_MULT_SH 30 | |
308 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
309 | #define QH_EPCAP_PORTNUM_SH 23 | |
310 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
311 | #define QH_EPCAP_HUBADDR_SH 16 | |
312 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
313 | #define QH_EPCAP_CMASK_SH 8 | |
314 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
315 | #define QH_EPCAP_SMASK_SH 0 | |
316 | ||
317 | uint32_t current_qtd; // Standard next link pointer | |
318 | uint32_t next_qtd; // Standard next link pointer | |
319 | uint32_t altnext_qtd; | |
320 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
321 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
322 | ||
323 | uint32_t token; // Same as QTD token | |
324 | uint32_t bufptr[5]; // Standard buffer pointer | |
325 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
326 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
327 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
328 | #define BUFPTR_SBYTES_SH 5 | |
329 | } EHCIqh; | |
330 | ||
331 | /* EHCI spec version 1.0 Section 3.7 | |
332 | */ | |
333 | typedef struct EHCIfstn { | |
334 | uint32_t next; // Standard next link pointer | |
335 | uint32_t backptr; // Standard next link pointer | |
336 | } EHCIfstn; | |
337 | ||
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
347 | struct EHCIQueue { | |
348 | EHCIState *ehci; | |
8ac6d699 GH |
349 | QTAILQ_ENTRY(EHCIQueue) next; |
350 | bool async_schedule; | |
adddecb1 GH |
351 | uint32_t seen; |
352 | uint64_t ts; | |
0122f472 GH |
353 | |
354 | /* cached data from guest - needs to be flushed | |
355 | * when guest removes an entry (doorbell, handshake sequence) | |
356 | */ | |
357 | EHCIqh qh; // copy of current QH (being worked on) | |
358 | uint32_t qhaddr; // address QH read from | |
359 | EHCIqtd qtd; // copy of current QTD (being worked on) | |
360 | uint32_t qtdaddr; // address QTD read from | |
361 | ||
362 | USBPacket packet; | |
0ce668bc | 363 | QEMUSGList sgl; |
0122f472 GH |
364 | int pid; |
365 | uint32_t tbytes; | |
366 | enum async_state async; | |
367 | int usb_status; | |
368 | }; | |
369 | ||
370 | struct EHCIState { | |
94527ead | 371 | PCIDevice dev; |
0122f472 | 372 | USBBus bus; |
94527ead | 373 | qemu_irq irq; |
e57964f5 | 374 | MemoryRegion mem; |
a0a3167a | 375 | int companion_count; |
16a2dee6 GH |
376 | |
377 | /* properties */ | |
378 | uint32_t freq; | |
379 | uint32_t maxframes; | |
380 | ||
94527ead GH |
381 | /* |
382 | * EHCI spec version 1.0 Section 2.3 | |
383 | * Host Controller Operational Registers | |
384 | */ | |
385 | union { | |
386 | uint8_t mmio[MMIO_SIZE]; | |
387 | struct { | |
388 | uint8_t cap[OPREGBASE]; | |
389 | uint32_t usbcmd; | |
390 | uint32_t usbsts; | |
391 | uint32_t usbintr; | |
392 | uint32_t frindex; | |
393 | uint32_t ctrldssegment; | |
394 | uint32_t periodiclistbase; | |
395 | uint32_t asynclistaddr; | |
396 | uint32_t notused[9]; | |
397 | uint32_t configflag; | |
398 | uint32_t portsc[NB_PORTS]; | |
399 | }; | |
400 | }; | |
0122f472 | 401 | |
94527ead GH |
402 | /* |
403 | * Internal states, shadow registers, etc | |
404 | */ | |
405 | uint32_t sofv; | |
406 | QEMUTimer *frame_timer; | |
407 | int attach_poll_counter; | |
408 | int astate; // Current state in asynchronous schedule | |
409 | int pstate; // Current state in periodic schedule | |
410 | USBPort ports[NB_PORTS]; | |
a0a3167a | 411 | USBPort *companion_ports[NB_PORTS]; |
94527ead | 412 | uint32_t usbsts_pending; |
8ac6d699 | 413 | QTAILQ_HEAD(, EHCIQueue) queues; |
94527ead | 414 | |
0122f472 GH |
415 | uint32_t a_fetch_addr; // which address to look at next |
416 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 417 | |
0122f472 | 418 | USBPacket ipacket; |
0ce668bc | 419 | QEMUSGList isgl; |
94527ead | 420 | int isoch_pause; |
0122f472 | 421 | |
adddecb1 | 422 | uint64_t last_run_ns; |
0122f472 | 423 | }; |
94527ead GH |
424 | |
425 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 426 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
427 | |
428 | /* nifty macros from Arnon's EHCI version */ | |
429 | #define get_field(data, field) \ | |
430 | (((data) & field##_MASK) >> field##_SH) | |
431 | ||
432 | #define set_field(data, newval, field) do { \ | |
433 | uint32_t val = *data; \ | |
434 | val &= ~ field##_MASK; \ | |
435 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
436 | *data = val; \ | |
437 | } while(0) | |
438 | ||
26d53979 | 439 | static const char *ehci_state_names[] = { |
aac882e7 GH |
440 | [EST_INACTIVE] = "INACTIVE", |
441 | [EST_ACTIVE] = "ACTIVE", | |
442 | [EST_EXECUTING] = "EXECUTING", | |
443 | [EST_SLEEPING] = "SLEEPING", | |
444 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
445 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
446 | [EST_FETCHQH] = "FETCH QH", | |
447 | [EST_FETCHITD] = "FETCH ITD", | |
448 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
449 | [EST_FETCHQTD] = "FETCH QTD", | |
450 | [EST_EXECUTE] = "EXECUTE", | |
451 | [EST_WRITEBACK] = "WRITEBACK", | |
452 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
453 | }; |
454 | ||
455 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
456 | [CAPLENGTH] = "CAPLENGTH", |
457 | [HCIVERSION] = "HCIVERSION", | |
458 | [HCSPARAMS] = "HCSPARAMS", | |
459 | [HCCPARAMS] = "HCCPARAMS", | |
460 | [USBCMD] = "USBCMD", | |
461 | [USBSTS] = "USBSTS", | |
462 | [USBINTR] = "USBINTR", | |
463 | [FRINDEX] = "FRINDEX", | |
464 | [PERIODICLISTBASE] = "P-LIST BASE", | |
465 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
466 | [PORTSC_BEGIN] = "PORTSC #0", | |
467 | [PORTSC_BEGIN + 4] = "PORTSC #1", | |
468 | [PORTSC_BEGIN + 8] = "PORTSC #2", | |
469 | [PORTSC_BEGIN + 12] = "PORTSC #3", | |
335b8d20 GH |
470 | [PORTSC_BEGIN + 16] = "PORTSC #4", |
471 | [PORTSC_BEGIN + 20] = "PORTSC #5", | |
aac882e7 | 472 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 473 | }; |
94527ead | 474 | |
26d53979 | 475 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 476 | { |
26d53979 GH |
477 | if (nr < len && n[nr] != NULL) { |
478 | return n[nr]; | |
94527ead | 479 | } else { |
26d53979 | 480 | return "unknown"; |
94527ead GH |
481 | } |
482 | } | |
94527ead | 483 | |
26d53979 GH |
484 | static const char *state2str(uint32_t state) |
485 | { | |
486 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
487 | } | |
488 | ||
489 | static const char *addr2str(target_phys_addr_t addr) | |
490 | { | |
491 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
492 | } | |
493 | ||
439a97cc GH |
494 | static void ehci_trace_usbsts(uint32_t mask, int state) |
495 | { | |
496 | /* interrupts */ | |
497 | if (mask & USBSTS_INT) { | |
498 | trace_usb_ehci_usbsts("INT", state); | |
499 | } | |
500 | if (mask & USBSTS_ERRINT) { | |
501 | trace_usb_ehci_usbsts("ERRINT", state); | |
502 | } | |
503 | if (mask & USBSTS_PCD) { | |
504 | trace_usb_ehci_usbsts("PCD", state); | |
505 | } | |
506 | if (mask & USBSTS_FLR) { | |
507 | trace_usb_ehci_usbsts("FLR", state); | |
508 | } | |
509 | if (mask & USBSTS_HSE) { | |
510 | trace_usb_ehci_usbsts("HSE", state); | |
511 | } | |
512 | if (mask & USBSTS_IAA) { | |
513 | trace_usb_ehci_usbsts("IAA", state); | |
514 | } | |
515 | ||
516 | /* status */ | |
517 | if (mask & USBSTS_HALT) { | |
518 | trace_usb_ehci_usbsts("HALT", state); | |
519 | } | |
520 | if (mask & USBSTS_REC) { | |
521 | trace_usb_ehci_usbsts("REC", state); | |
522 | } | |
523 | if (mask & USBSTS_PSS) { | |
524 | trace_usb_ehci_usbsts("PSS", state); | |
525 | } | |
526 | if (mask & USBSTS_ASS) { | |
527 | trace_usb_ehci_usbsts("ASS", state); | |
528 | } | |
529 | } | |
530 | ||
531 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
532 | { | |
533 | if ((s->usbsts & mask) == mask) { | |
534 | return; | |
535 | } | |
536 | ehci_trace_usbsts(mask, 1); | |
537 | s->usbsts |= mask; | |
538 | } | |
539 | ||
540 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
541 | { | |
542 | if ((s->usbsts & mask) == 0) { | |
543 | return; | |
544 | } | |
545 | ehci_trace_usbsts(mask, 0); | |
546 | s->usbsts &= ~mask; | |
547 | } | |
94527ead GH |
548 | |
549 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
550 | { | |
551 | int level = 0; | |
552 | ||
553 | // TODO honour interrupt threshold requests | |
554 | ||
439a97cc | 555 | ehci_set_usbsts(s, intr); |
94527ead GH |
556 | |
557 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
558 | level = 1; | |
559 | } | |
560 | ||
561 | qemu_set_irq(s->irq, level); | |
562 | } | |
563 | ||
564 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
565 | { | |
566 | s->usbsts_pending |= intr; | |
567 | } | |
568 | ||
569 | static inline void ehci_commit_interrupt(EHCIState *s) | |
570 | { | |
571 | if (!s->usbsts_pending) { | |
572 | return; | |
573 | } | |
574 | ehci_set_interrupt(s, s->usbsts_pending); | |
575 | s->usbsts_pending = 0; | |
576 | } | |
577 | ||
26d53979 GH |
578 | static void ehci_set_state(EHCIState *s, int async, int state) |
579 | { | |
580 | if (async) { | |
581 | trace_usb_ehci_state("async", state2str(state)); | |
582 | s->astate = state; | |
583 | } else { | |
584 | trace_usb_ehci_state("periodic", state2str(state)); | |
585 | s->pstate = state; | |
586 | } | |
587 | } | |
588 | ||
589 | static int ehci_get_state(EHCIState *s, int async) | |
590 | { | |
591 | return async ? s->astate : s->pstate; | |
592 | } | |
593 | ||
0122f472 GH |
594 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
595 | { | |
596 | if (async) { | |
597 | s->a_fetch_addr = addr; | |
598 | } else { | |
599 | s->p_fetch_addr = addr; | |
600 | } | |
601 | } | |
602 | ||
603 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
604 | { | |
605 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
606 | } | |
607 | ||
8ac6d699 | 608 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 609 | { |
025b168c GH |
610 | /* need three here due to argument count limits */ |
611 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
612 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
613 | trace_usb_ehci_qh_fields(addr, | |
614 | get_field(qh->epchar, QH_EPCHAR_RL), | |
615 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
616 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
617 | get_field(qh->epchar, QH_EPCHAR_EP), | |
618 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
619 | trace_usb_ehci_qh_bits(addr, | |
620 | (bool)(qh->epchar & QH_EPCHAR_C), | |
621 | (bool)(qh->epchar & QH_EPCHAR_H), | |
622 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
623 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
624 | } |
625 | ||
8ac6d699 | 626 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 627 | { |
025b168c GH |
628 | /* need three here due to argument count limits */ |
629 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
630 | trace_usb_ehci_qtd_fields(addr, | |
631 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
632 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
633 | get_field(qtd->token, QTD_TOKEN_CERR), | |
634 | get_field(qtd->token, QTD_TOKEN_PID)); | |
635 | trace_usb_ehci_qtd_bits(addr, | |
636 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
637 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
638 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
639 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
640 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
641 | } |
642 | ||
643 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
644 | { | |
e654887f GH |
645 | trace_usb_ehci_itd(addr, itd->next, |
646 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
647 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
648 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
649 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
650 | } |
651 | ||
2fe80192 GH |
652 | static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
653 | EHCIsitd *sitd) | |
654 | { | |
655 | trace_usb_ehci_sitd(addr, sitd->next, | |
656 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
657 | } | |
658 | ||
8ac6d699 GH |
659 | /* queue management */ |
660 | ||
661 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
662 | { | |
663 | EHCIQueue *q; | |
664 | ||
7267c094 | 665 | q = g_malloc0(sizeof(*q)); |
8ac6d699 GH |
666 | q->ehci = ehci; |
667 | q->async_schedule = async; | |
668 | QTAILQ_INSERT_HEAD(&ehci->queues, q, next); | |
669 | trace_usb_ehci_queue_action(q, "alloc"); | |
670 | return q; | |
671 | } | |
672 | ||
673 | static void ehci_free_queue(EHCIQueue *q) | |
674 | { | |
675 | trace_usb_ehci_queue_action(q, "free"); | |
676 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
677 | usb_cancel_packet(&q->packet); | |
678 | } | |
679 | QTAILQ_REMOVE(&q->ehci->queues, q, next); | |
7267c094 | 680 | g_free(q); |
8ac6d699 GH |
681 | } |
682 | ||
683 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr) | |
684 | { | |
685 | EHCIQueue *q; | |
686 | ||
687 | QTAILQ_FOREACH(q, &ehci->queues, next) { | |
688 | if (addr == q->qhaddr) { | |
689 | return q; | |
690 | } | |
691 | } | |
692 | return NULL; | |
693 | } | |
694 | ||
695 | static void ehci_queues_rip_unused(EHCIState *ehci) | |
696 | { | |
697 | EHCIQueue *q, *tmp; | |
698 | ||
699 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
700 | if (q->seen) { | |
701 | q->seen = 0; | |
adddecb1 | 702 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
703 | continue; |
704 | } | |
adddecb1 | 705 | if (ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
706 | /* allow 0.25 sec idle */ |
707 | continue; | |
708 | } | |
709 | ehci_free_queue(q); | |
710 | } | |
711 | } | |
712 | ||
07771f6f GH |
713 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev) |
714 | { | |
715 | EHCIQueue *q, *tmp; | |
716 | ||
717 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
718 | if (q->packet.owner != dev) { | |
719 | continue; | |
720 | } | |
721 | ehci_free_queue(q); | |
722 | } | |
723 | } | |
724 | ||
8ac6d699 GH |
725 | static void ehci_queues_rip_all(EHCIState *ehci) |
726 | { | |
727 | EHCIQueue *q, *tmp; | |
728 | ||
729 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
730 | ehci_free_queue(q); | |
731 | } | |
732 | } | |
733 | ||
94527ead GH |
734 | /* Attach or detach a device on root hub */ |
735 | ||
736 | static void ehci_attach(USBPort *port) | |
737 | { | |
738 | EHCIState *s = port->opaque; | |
739 | uint32_t *portsc = &s->portsc[port->index]; | |
740 | ||
dcbd0b5c | 741 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead | 742 | |
a0a3167a HG |
743 | if (*portsc & PORTSC_POWNER) { |
744 | USBPort *companion = s->companion_ports[port->index]; | |
745 | companion->dev = port->dev; | |
746 | companion->ops->attach(companion); | |
747 | return; | |
748 | } | |
749 | ||
94527ead GH |
750 | *portsc |= PORTSC_CONNECT; |
751 | *portsc |= PORTSC_CSC; | |
752 | ||
a0a3167a | 753 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
754 | } |
755 | ||
756 | static void ehci_detach(USBPort *port) | |
757 | { | |
758 | EHCIState *s = port->opaque; | |
759 | uint32_t *portsc = &s->portsc[port->index]; | |
760 | ||
dcbd0b5c | 761 | trace_usb_ehci_port_detach(port->index); |
94527ead | 762 | |
a0a3167a HG |
763 | if (*portsc & PORTSC_POWNER) { |
764 | USBPort *companion = s->companion_ports[port->index]; | |
765 | companion->ops->detach(companion); | |
766 | companion->dev = NULL; | |
767 | return; | |
768 | } | |
769 | ||
4706ab6c HG |
770 | ehci_queues_rip_device(s, port->dev); |
771 | ||
fbd97532 | 772 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
773 | *portsc |= PORTSC_CSC; |
774 | ||
a0a3167a | 775 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
776 | } |
777 | ||
4706ab6c HG |
778 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
779 | { | |
780 | EHCIState *s = port->opaque; | |
a0a3167a HG |
781 | uint32_t portsc = s->portsc[port->index]; |
782 | ||
783 | if (portsc & PORTSC_POWNER) { | |
784 | USBPort *companion = s->companion_ports[port->index]; | |
785 | companion->ops->child_detach(companion, child); | |
786 | companion->dev = NULL; | |
787 | return; | |
788 | } | |
4706ab6c HG |
789 | |
790 | ehci_queues_rip_device(s, child); | |
791 | } | |
792 | ||
a0a3167a HG |
793 | static void ehci_wakeup(USBPort *port) |
794 | { | |
795 | EHCIState *s = port->opaque; | |
796 | uint32_t portsc = s->portsc[port->index]; | |
797 | ||
798 | if (portsc & PORTSC_POWNER) { | |
799 | USBPort *companion = s->companion_ports[port->index]; | |
800 | if (companion->ops->wakeup) { | |
801 | companion->ops->wakeup(companion); | |
802 | } | |
803 | } | |
804 | } | |
805 | ||
806 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
807 | uint32_t portcount, uint32_t firstport) | |
808 | { | |
809 | EHCIState *s = container_of(bus, EHCIState, bus); | |
810 | uint32_t i; | |
811 | ||
812 | if (firstport + portcount > NB_PORTS) { | |
813 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
814 | "firstport on masterbus"); | |
815 | error_printf_unless_qmp( | |
816 | "firstport value of %u makes companion take ports %u - %u, which " | |
817 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
818 | firstport + portcount - 1, NB_PORTS - 1); | |
819 | return -1; | |
820 | } | |
821 | ||
822 | for (i = 0; i < portcount; i++) { | |
823 | if (s->companion_ports[firstport + i]) { | |
824 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
825 | "an USB masterbus"); | |
826 | error_printf_unless_qmp( | |
827 | "port %u on masterbus %s already has a companion assigned\n", | |
828 | firstport + i, bus->qbus.name); | |
829 | return -1; | |
830 | } | |
831 | } | |
832 | ||
833 | for (i = 0; i < portcount; i++) { | |
834 | s->companion_ports[firstport + i] = ports[i]; | |
835 | s->ports[firstport + i].speedmask |= | |
836 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
837 | /* Ensure devs attached before the initial reset go to the companion */ | |
838 | s->portsc[firstport + i] = PORTSC_POWNER; | |
839 | } | |
840 | ||
841 | s->companion_count++; | |
842 | s->mmio[0x05] = (s->companion_count << 4) | portcount; | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
94527ead GH |
847 | /* 4.1 host controller initialization */ |
848 | static void ehci_reset(void *opaque) | |
849 | { | |
850 | EHCIState *s = opaque; | |
94527ead | 851 | int i; |
a0a3167a | 852 | USBDevice *devs[NB_PORTS]; |
94527ead | 853 | |
439a97cc | 854 | trace_usb_ehci_reset(); |
94527ead | 855 | |
a0a3167a HG |
856 | /* |
857 | * Do the detach before touching portsc, so that it correctly gets send to | |
858 | * us or to our companion based on PORTSC_POWNER before the reset. | |
859 | */ | |
860 | for(i = 0; i < NB_PORTS; i++) { | |
861 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
862 | if (devs[i] && devs[i]->attached) { |
863 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
864 | } |
865 | } | |
866 | ||
94527ead GH |
867 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); |
868 | ||
869 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
870 | s->usbsts = USBSTS_HALT; | |
871 | ||
872 | s->astate = EST_INACTIVE; | |
873 | s->pstate = EST_INACTIVE; | |
94527ead GH |
874 | s->isoch_pause = -1; |
875 | s->attach_poll_counter = 0; | |
876 | ||
877 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
878 | if (s->companion_ports[i]) { |
879 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
880 | } else { | |
881 | s->portsc[i] = PORTSC_PPOWER; | |
882 | } | |
891fb2cd GH |
883 | if (devs[i] && devs[i]->attached) { |
884 | usb_attach(&s->ports[i]); | |
e0b8e72d | 885 | usb_send_msg(devs[i], USB_MSG_RESET); |
94527ead GH |
886 | } |
887 | } | |
8ac6d699 | 888 | ehci_queues_rip_all(s); |
94527ead GH |
889 | } |
890 | ||
891 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
892 | { | |
893 | EHCIState *s = ptr; | |
894 | uint32_t val; | |
895 | ||
896 | val = s->mmio[addr]; | |
897 | ||
898 | return val; | |
899 | } | |
900 | ||
901 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
902 | { | |
903 | EHCIState *s = ptr; | |
904 | uint32_t val; | |
905 | ||
906 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
907 | ||
908 | return val; | |
909 | } | |
910 | ||
911 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
912 | { | |
913 | EHCIState *s = ptr; | |
914 | uint32_t val; | |
915 | ||
916 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
917 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
918 | ||
439a97cc | 919 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
920 | return val; |
921 | } | |
922 | ||
923 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
924 | { | |
925 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
926 | exit(1); | |
927 | } | |
928 | ||
929 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
930 | { | |
931 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
932 | exit(1); | |
933 | } | |
934 | ||
a0a3167a HG |
935 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
936 | { | |
937 | USBDevice *dev = s->ports[port].dev; | |
938 | uint32_t *portsc = &s->portsc[port]; | |
939 | uint32_t orig; | |
940 | ||
941 | if (s->companion_ports[port] == NULL) | |
942 | return; | |
943 | ||
944 | owner = owner & PORTSC_POWNER; | |
945 | orig = *portsc & PORTSC_POWNER; | |
946 | ||
947 | if (!(owner ^ orig)) { | |
948 | return; | |
949 | } | |
950 | ||
891fb2cd GH |
951 | if (dev && dev->attached) { |
952 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
953 | } |
954 | ||
955 | *portsc &= ~PORTSC_POWNER; | |
956 | *portsc |= owner; | |
957 | ||
891fb2cd GH |
958 | if (dev && dev->attached) { |
959 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
960 | } |
961 | } | |
962 | ||
94527ead GH |
963 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) |
964 | { | |
965 | uint32_t *portsc = &s->portsc[port]; | |
94527ead GH |
966 | USBDevice *dev = s->ports[port].dev; |
967 | ||
fbd97532 HG |
968 | /* Clear rwc bits */ |
969 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
970 | /* The guest may clear, but not set the PED bit */ | |
971 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
972 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
973 | handle_port_owner_write(s, port, val); | |
974 | /* And finally apply RO_MASK */ | |
94527ead GH |
975 | val &= PORTSC_RO_MASK; |
976 | ||
94527ead | 977 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 978 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
979 | } |
980 | ||
981 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 982 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 983 | if (dev && dev->attached) { |
e0b8e72d | 984 | usb_reset(&s->ports[port]); |
94527ead GH |
985 | *portsc &= ~PORTSC_CSC; |
986 | } | |
987 | ||
fbd97532 HG |
988 | /* |
989 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 990 | * to SW that this port has a high speed device attached |
94527ead | 991 | */ |
891fb2cd | 992 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
993 | val |= PORTSC_PED; |
994 | } | |
94527ead GH |
995 | } |
996 | ||
997 | *portsc &= ~PORTSC_RO_MASK; | |
998 | *portsc |= val; | |
94527ead GH |
999 | } |
1000 | ||
1001 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1002 | { | |
1003 | EHCIState *s = ptr; | |
c4f8e211 GH |
1004 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
1005 | uint32_t old = *mmio; | |
94527ead | 1006 | int i; |
439a97cc | 1007 | |
c4f8e211 | 1008 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
1009 | |
1010 | /* Only aligned reads are allowed on OHCI */ | |
1011 | if (addr & 3) { | |
1012 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
1013 | TARGET_FMT_plx "\n", addr); | |
1014 | return; | |
1015 | } | |
1016 | ||
1017 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
1018 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 1019 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
1020 | return; |
1021 | } | |
1022 | ||
1023 | if (addr < OPREGBASE) { | |
1024 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
1025 | TARGET_FMT_plx "\n", addr); | |
1026 | return; | |
1027 | } | |
1028 | ||
1029 | ||
1030 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
1031 | switch(addr) { |
1032 | case USBCMD: | |
94527ead | 1033 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { |
94527ead GH |
1034 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
1035 | SET_LAST_RUN_CLOCK(s); | |
439a97cc | 1036 | ehci_clear_usbsts(s, USBSTS_HALT); |
94527ead GH |
1037 | } |
1038 | ||
1039 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
94527ead GH |
1040 | qemu_del_timer(s->frame_timer); |
1041 | // TODO - should finish out some stuff before setting halt | |
439a97cc | 1042 | ehci_set_usbsts(s, USBSTS_HALT); |
94527ead GH |
1043 | } |
1044 | ||
1045 | if (val & USBCMD_HCRESET) { | |
94527ead GH |
1046 | ehci_reset(s); |
1047 | val &= ~USBCMD_HCRESET; | |
1048 | } | |
1049 | ||
1050 | /* not supporting dynamic frame list size at the moment */ | |
1051 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1052 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1053 | val & USBCMD_FLS); | |
1054 | val &= ~USBCMD_FLS; | |
1055 | } | |
94527ead GH |
1056 | break; |
1057 | ||
94527ead GH |
1058 | case USBSTS: |
1059 | val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO | |
439a97cc GH |
1060 | ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC |
1061 | val = s->usbsts; | |
94527ead GH |
1062 | ehci_set_interrupt(s, 0); |
1063 | break; | |
1064 | ||
94527ead GH |
1065 | case USBINTR: |
1066 | val &= USBINTR_MASK; | |
94527ead GH |
1067 | break; |
1068 | ||
1069 | case FRINDEX: | |
1070 | s->sofv = val >> 3; | |
94527ead GH |
1071 | break; |
1072 | ||
1073 | case CONFIGFLAG: | |
94527ead GH |
1074 | val &= 0x1; |
1075 | if (val) { | |
1076 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 1077 | handle_port_owner_write(s, i, 0); |
94527ead GH |
1078 | } |
1079 | break; | |
1080 | ||
1081 | case PERIODICLISTBASE: | |
1082 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1083 | fprintf(stderr, | |
1084 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1085 | " is enabled and HC is enabled\n"); | |
1086 | } | |
94527ead GH |
1087 | break; |
1088 | ||
1089 | case ASYNCLISTADDR: | |
1090 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1091 | fprintf(stderr, | |
1092 | "ehci: ASYNC list address register set while async schedule\n" | |
1093 | " is enabled and HC is enabled\n"); | |
1094 | } | |
94527ead GH |
1095 | break; |
1096 | } | |
1097 | ||
c4f8e211 GH |
1098 | *mmio = val; |
1099 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
1100 | } |
1101 | ||
1102 | ||
1103 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1104 | ||
1105 | /* Get an array of dwords from main memory */ | |
68d55358 DG |
1106 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1107 | uint32_t *buf, int num) | |
94527ead GH |
1108 | { |
1109 | int i; | |
1110 | ||
1111 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
68d55358 | 1112 | pci_dma_read(&ehci->dev, addr, (uint8_t *)buf, sizeof(*buf)); |
94527ead GH |
1113 | *buf = le32_to_cpu(*buf); |
1114 | } | |
1115 | ||
1116 | return 1; | |
1117 | } | |
1118 | ||
1119 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1120 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1121 | uint32_t *buf, int num) | |
94527ead GH |
1122 | { |
1123 | int i; | |
1124 | ||
1125 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1126 | uint32_t tmp = cpu_to_le32(*buf); | |
68d55358 | 1127 | pci_dma_write(&ehci->dev, addr, (uint8_t *)&tmp, sizeof(tmp)); |
94527ead GH |
1128 | } |
1129 | ||
1130 | return 1; | |
1131 | } | |
1132 | ||
1133 | // 4.10.2 | |
1134 | ||
0122f472 | 1135 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead GH |
1136 | { |
1137 | int i; | |
1138 | int dtoggle; | |
1139 | int ping; | |
1140 | int eps; | |
1141 | int reload; | |
1142 | ||
1143 | // remember values in fields to preserve in qh after overlay | |
1144 | ||
0122f472 GH |
1145 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1146 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1147 | |
0122f472 GH |
1148 | q->qh.current_qtd = q->qtdaddr; |
1149 | q->qh.next_qtd = q->qtd.next; | |
1150 | q->qh.altnext_qtd = q->qtd.altnext; | |
1151 | q->qh.token = q->qtd.token; | |
94527ead GH |
1152 | |
1153 | ||
0122f472 | 1154 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1155 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1156 | q->qh.token &= ~QTD_TOKEN_PING; |
1157 | q->qh.token |= ping; | |
94527ead GH |
1158 | } |
1159 | ||
0122f472 GH |
1160 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1161 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1162 | |
1163 | for (i = 0; i < 5; i++) { | |
0122f472 | 1164 | q->qh.bufptr[i] = q->qtd.bufptr[i]; |
94527ead GH |
1165 | } |
1166 | ||
0122f472 | 1167 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1168 | // preserve QH DT bit |
0122f472 GH |
1169 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1170 | q->qh.token |= dtoggle; | |
94527ead GH |
1171 | } |
1172 | ||
0122f472 GH |
1173 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1174 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1175 | |
68d55358 DG |
1176 | put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, |
1177 | sizeof(EHCIqh) >> 2); | |
94527ead GH |
1178 | |
1179 | return 0; | |
1180 | } | |
1181 | ||
0ce668bc | 1182 | static int ehci_init_transfer(EHCIQueue *q) |
94527ead | 1183 | { |
0ce668bc | 1184 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1185 | dma_addr_t page; |
94527ead | 1186 | |
0ce668bc GH |
1187 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
1188 | bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); | |
0122f472 | 1189 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; |
68d55358 | 1190 | pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5); |
94527ead | 1191 | |
0ce668bc GH |
1192 | while (bytes > 0) { |
1193 | if (cpage > 4) { | |
1194 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1195 | return USB_RET_PROCERR; | |
1196 | } | |
94527ead | 1197 | |
0ce668bc GH |
1198 | page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK; |
1199 | page += offset; | |
1200 | plen = bytes; | |
1201 | if (plen > 4096 - offset) { | |
1202 | plen = 4096 - offset; | |
1203 | offset = 0; | |
1204 | cpage++; | |
94527ead GH |
1205 | } |
1206 | ||
0ce668bc GH |
1207 | qemu_sglist_add(&q->sgl, page, plen); |
1208 | bytes -= plen; | |
1209 | } | |
1210 | return 0; | |
1211 | } | |
94527ead | 1212 | |
0ce668bc GH |
1213 | static void ehci_finish_transfer(EHCIQueue *q, int status) |
1214 | { | |
1215 | uint32_t cpage, offset; | |
94527ead | 1216 | |
0ce668bc | 1217 | qemu_sglist_destroy(&q->sgl); |
94527ead | 1218 | |
0ce668bc GH |
1219 | if (status > 0) { |
1220 | /* update cpage & offset */ | |
1221 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1222 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1223 | |
0ce668bc GH |
1224 | offset += status; |
1225 | cpage += offset >> QTD_BUFPTR_SH; | |
1226 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1227 | |
0ce668bc GH |
1228 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1229 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1230 | q->qh.bufptr[0] |= offset; | |
1231 | } | |
94527ead GH |
1232 | } |
1233 | ||
d47e59b8 | 1234 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1235 | { |
a0a3167a HG |
1236 | EHCIQueue *q; |
1237 | EHCIState *s = port->opaque; | |
1238 | uint32_t portsc = s->portsc[port->index]; | |
1239 | ||
1240 | if (portsc & PORTSC_POWNER) { | |
1241 | USBPort *companion = s->companion_ports[port->index]; | |
1242 | companion->ops->complete(companion, packet); | |
1243 | return; | |
1244 | } | |
94527ead | 1245 | |
a0a3167a | 1246 | q = container_of(packet, EHCIQueue, packet); |
8ac6d699 GH |
1247 | trace_usb_ehci_queue_action(q, "wakeup"); |
1248 | assert(q->async == EHCI_ASYNC_INFLIGHT); | |
0122f472 | 1249 | q->async = EHCI_ASYNC_FINISHED; |
4f4321c1 | 1250 | q->usb_status = packet->result; |
94527ead GH |
1251 | } |
1252 | ||
0122f472 | 1253 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead GH |
1254 | { |
1255 | int c_err, reload; | |
1256 | ||
8ac6d699 | 1257 | assert(q->async != EHCI_ASYNC_INFLIGHT); |
0122f472 | 1258 | q->async = EHCI_ASYNC_NONE; |
94527ead GH |
1259 | |
1260 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1261 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1262 | |
0122f472 | 1263 | if (q->usb_status < 0) { |
94527ead GH |
1264 | err: |
1265 | /* TO-DO: put this is in a function that can be invoked below as well */ | |
0122f472 | 1266 | c_err = get_field(q->qh.token, QTD_TOKEN_CERR); |
94527ead | 1267 | c_err--; |
0122f472 | 1268 | set_field(&q->qh.token, c_err, QTD_TOKEN_CERR); |
94527ead | 1269 | |
0122f472 | 1270 | switch(q->usb_status) { |
94527ead | 1271 | case USB_RET_NODEV: |
d2bd525f GH |
1272 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1273 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1274 | break; |
1275 | case USB_RET_STALL: | |
0122f472 GH |
1276 | q->qh.token |= QTD_TOKEN_HALT; |
1277 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1278 | break; |
1279 | case USB_RET_NAK: | |
1280 | /* 4.10.3 */ | |
0122f472 GH |
1281 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1282 | if ((q->pid == USB_TOKEN_IN) && reload) { | |
1283 | int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1284 | nakcnt--; |
0122f472 | 1285 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead | 1286 | } else if (!reload) { |
0122f472 | 1287 | return; |
94527ead GH |
1288 | } |
1289 | break; | |
1290 | case USB_RET_BABBLE: | |
d2bd525f | 1291 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1292 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1293 | break; |
1294 | default: | |
0122f472 GH |
1295 | /* should not be triggerable */ |
1296 | fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status); | |
1297 | assert(0); | |
94527ead GH |
1298 | break; |
1299 | } | |
1300 | } else { | |
1301 | // DPRINTF("Short packet condition\n"); | |
1302 | // TODO check 4.12 for splits | |
1303 | ||
0122f472 GH |
1304 | if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) { |
1305 | q->usb_status = USB_RET_BABBLE; | |
94527ead GH |
1306 | goto err; |
1307 | } | |
1308 | ||
0122f472 | 1309 | if (q->tbytes && q->pid == USB_TOKEN_IN) { |
0122f472 | 1310 | q->tbytes -= q->usb_status; |
94527ead | 1311 | } else { |
0122f472 | 1312 | q->tbytes = 0; |
94527ead GH |
1313 | } |
1314 | ||
0122f472 GH |
1315 | DPRINTF("updating tbytes to %d\n", q->tbytes); |
1316 | set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES); | |
94527ead | 1317 | } |
0ce668bc GH |
1318 | ehci_finish_transfer(q, q->usb_status); |
1319 | usb_packet_unmap(&q->packet); | |
94527ead | 1320 | |
0122f472 GH |
1321 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1322 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1323 | |
0122f472 GH |
1324 | if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) { |
1325 | ehci_record_interrupt(q->ehci, USBSTS_INT); | |
94527ead | 1326 | } |
94527ead GH |
1327 | } |
1328 | ||
1329 | // 4.10.3 | |
1330 | ||
0122f472 | 1331 | static int ehci_execute(EHCIQueue *q) |
94527ead GH |
1332 | { |
1333 | USBPort *port; | |
1334 | USBDevice *dev; | |
1335 | int ret; | |
1336 | int i; | |
1337 | int endp; | |
1338 | int devadr; | |
1339 | ||
0122f472 | 1340 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { |
94527ead GH |
1341 | fprintf(stderr, "Attempting to execute inactive QH\n"); |
1342 | return USB_RET_PROCERR; | |
1343 | } | |
1344 | ||
0122f472 GH |
1345 | q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1346 | if (q->tbytes > BUFF_SIZE) { | |
94527ead GH |
1347 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1348 | return USB_RET_PROCERR; | |
1349 | } | |
1350 | ||
0122f472 GH |
1351 | q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1352 | switch(q->pid) { | |
1353 | case 0: q->pid = USB_TOKEN_OUT; break; | |
1354 | case 1: q->pid = USB_TOKEN_IN; break; | |
1355 | case 2: q->pid = USB_TOKEN_SETUP; break; | |
94527ead GH |
1356 | default: fprintf(stderr, "bad token\n"); break; |
1357 | } | |
1358 | ||
0ce668bc | 1359 | if (ehci_init_transfer(q) != 0) { |
94527ead GH |
1360 | return USB_RET_PROCERR; |
1361 | } | |
1362 | ||
0122f472 GH |
1363 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); |
1364 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
94527ead GH |
1365 | |
1366 | ret = USB_RET_NODEV; | |
1367 | ||
0ce668bc GH |
1368 | usb_packet_setup(&q->packet, q->pid, devadr, endp); |
1369 | usb_packet_map(&q->packet, &q->sgl); | |
1370 | ||
94527ead GH |
1371 | // TO-DO: associating device with ehci port |
1372 | for(i = 0; i < NB_PORTS; i++) { | |
0122f472 | 1373 | port = &q->ehci->ports[i]; |
94527ead GH |
1374 | dev = port->dev; |
1375 | ||
0122f472 | 1376 | if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) { |
94527ead | 1377 | DPRINTF("Port %d, no exec, not connected(%08X)\n", |
0122f472 | 1378 | i, q->ehci->portsc[i]); |
94527ead GH |
1379 | continue; |
1380 | } | |
1381 | ||
0122f472 | 1382 | ret = usb_handle_packet(dev, &q->packet); |
94527ead | 1383 | |
4f4321c1 GH |
1384 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " |
1385 | "(total %d) endp %x ret %d\n", | |
0122f472 | 1386 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, |
4f4321c1 | 1387 | q->packet.iov.size, q->tbytes, endp, ret); |
94527ead GH |
1388 | |
1389 | if (ret != USB_RET_NODEV) { | |
1390 | break; | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | if (ret > BUFF_SIZE) { | |
1395 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1396 | return USB_RET_PROCERR; | |
1397 | } | |
1398 | ||
94527ead GH |
1399 | return ret; |
1400 | } | |
1401 | ||
1402 | /* 4.7.2 | |
1403 | */ | |
1404 | ||
1405 | static int ehci_process_itd(EHCIState *ehci, | |
1406 | EHCIitd *itd) | |
1407 | { | |
1408 | USBPort *port; | |
1409 | USBDevice *dev; | |
1410 | int ret; | |
0ce668bc | 1411 | uint32_t i, j, len, pid, dir, devaddr, endp; |
e654887f | 1412 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead GH |
1413 | |
1414 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1415 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1416 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1417 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1418 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1419 | |
1420 | for(i = 0; i < 8; i++) { | |
1421 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1422 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1423 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1424 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1425 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1426 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1427 | ||
1428 | if (len > max * mult) { | |
1429 | len = max * mult; | |
1430 | } | |
94527ead GH |
1431 | |
1432 | if (len > BUFF_SIZE) { | |
1433 | return USB_RET_PROCERR; | |
1434 | } | |
1435 | ||
68d55358 | 1436 | pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); |
e654887f GH |
1437 | if (off + len > 4096) { |
1438 | /* transfer crosses page border */ | |
0ce668bc GH |
1439 | uint32_t len2 = off + len - 4096; |
1440 | uint32_t len1 = len - len2; | |
1441 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1442 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1443 | } else { |
0ce668bc | 1444 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1445 | } |
94527ead | 1446 | |
0ce668bc | 1447 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1448 | |
0ce668bc GH |
1449 | usb_packet_setup(&ehci->ipacket, pid, devaddr, endp); |
1450 | usb_packet_map(&ehci->ipacket, &ehci->isgl); | |
94527ead | 1451 | |
0ce668bc | 1452 | ret = USB_RET_NODEV; |
94527ead GH |
1453 | for (j = 0; j < NB_PORTS; j++) { |
1454 | port = &ehci->ports[j]; | |
1455 | dev = port->dev; | |
1456 | ||
94527ead | 1457 | if (!(ehci->portsc[j] &(PORTSC_CONNECT))) { |
94527ead GH |
1458 | continue; |
1459 | } | |
1460 | ||
0122f472 | 1461 | ret = usb_handle_packet(dev, &ehci->ipacket); |
94527ead GH |
1462 | |
1463 | if (ret != USB_RET_NODEV) { | |
1464 | break; | |
1465 | } | |
1466 | } | |
1467 | ||
0ce668bc GH |
1468 | usb_packet_unmap(&ehci->ipacket); |
1469 | qemu_sglist_destroy(&ehci->isgl); | |
1470 | ||
e654887f | 1471 | #if 0 |
94527ead GH |
1472 | /* In isoch, there is no facility to indicate a NAK so let's |
1473 | * instead just complete a zero-byte transaction. Setting | |
1474 | * DBERR seems too draconian. | |
1475 | */ | |
1476 | ||
1477 | if (ret == USB_RET_NAK) { | |
1478 | if (ehci->isoch_pause > 0) { | |
1479 | DPRINTF("ISOCH: received a NAK but paused so returning\n"); | |
1480 | ehci->isoch_pause--; | |
1481 | return 0; | |
1482 | } else if (ehci->isoch_pause == -1) { | |
1483 | DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n"); | |
1484 | // Pause frindex for up to 50 msec waiting for data from | |
1485 | // remote | |
1486 | ehci->isoch_pause = 50; | |
1487 | return 0; | |
1488 | } else { | |
1489 | DPRINTF("ISOCH: isoch pause timeout! return 0\n"); | |
1490 | ret = 0; | |
1491 | } | |
1492 | } else { | |
1493 | DPRINTF("ISOCH: received ACK, clearing pause\n"); | |
1494 | ehci->isoch_pause = -1; | |
1495 | } | |
e654887f GH |
1496 | #else |
1497 | if (ret == USB_RET_NAK) { | |
1498 | ret = 0; | |
1499 | } | |
1500 | #endif | |
94527ead GH |
1501 | |
1502 | if (ret >= 0) { | |
e654887f GH |
1503 | if (!dir) { |
1504 | /* OUT */ | |
1505 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1506 | } else { | |
1507 | /* IN */ | |
e654887f GH |
1508 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); |
1509 | } | |
94527ead GH |
1510 | |
1511 | if (itd->transact[i] & ITD_XACT_IOC) { | |
1512 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1513 | } | |
1514 | } | |
e654887f | 1515 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1516 | } |
1517 | } | |
1518 | return 0; | |
1519 | } | |
1520 | ||
1521 | /* This state is the entry point for asynchronous schedule | |
1522 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1523 | */ | |
26d53979 | 1524 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1525 | { |
0122f472 | 1526 | EHCIqh qh; |
94527ead GH |
1527 | int i = 0; |
1528 | int again = 0; | |
1529 | uint32_t entry = ehci->asynclistaddr; | |
1530 | ||
1531 | /* set reclamation flag at start event (4.8.6) */ | |
1532 | if (async) { | |
439a97cc | 1533 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1534 | } |
1535 | ||
8ac6d699 GH |
1536 | ehci_queues_rip_unused(ehci); |
1537 | ||
94527ead GH |
1538 | /* Find the head of the list (4.9.1.1) */ |
1539 | for(i = 0; i < MAX_QH; i++) { | |
68d55358 DG |
1540 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1541 | sizeof(EHCIqh) >> 2); | |
8ac6d699 | 1542 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1543 | |
0122f472 | 1544 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1545 | if (async) { |
1546 | entry |= (NLPTR_TYPE_QH << 1); | |
1547 | } | |
1548 | ||
0122f472 | 1549 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1550 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1551 | again = 1; |
1552 | goto out; | |
1553 | } | |
1554 | ||
0122f472 | 1555 | entry = qh.next; |
94527ead | 1556 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1557 | break; |
1558 | } | |
1559 | } | |
1560 | ||
1561 | /* no head found for list. */ | |
1562 | ||
26d53979 | 1563 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1564 | |
1565 | out: | |
1566 | return again; | |
1567 | } | |
1568 | ||
1569 | ||
1570 | /* This state is the entry point for periodic schedule processing as | |
1571 | * well as being a continuation state for async processing. | |
1572 | */ | |
26d53979 | 1573 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1574 | { |
1575 | int again = 0; | |
0122f472 | 1576 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1577 | |
94527ead GH |
1578 | if (entry < 0x1000) { |
1579 | DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry); | |
26d53979 | 1580 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1581 | goto out; |
1582 | } | |
1583 | ||
1584 | /* section 4.8, only QH in async schedule */ | |
1585 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1586 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1587 | return -1; | |
1588 | } | |
1589 | ||
1590 | switch (NLPTR_TYPE_GET(entry)) { | |
1591 | case NLPTR_TYPE_QH: | |
26d53979 | 1592 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1593 | again = 1; |
1594 | break; | |
1595 | ||
1596 | case NLPTR_TYPE_ITD: | |
26d53979 | 1597 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1598 | again = 1; |
1599 | break; | |
1600 | ||
2fe80192 GH |
1601 | case NLPTR_TYPE_STITD: |
1602 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1603 | again = 1; | |
1604 | break; | |
1605 | ||
94527ead | 1606 | default: |
2fe80192 | 1607 | /* TODO: handle FSTN type */ |
94527ead GH |
1608 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1609 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1610 | return -1; | |
1611 | } | |
1612 | ||
1613 | out: | |
1614 | return again; | |
1615 | } | |
1616 | ||
0122f472 | 1617 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1618 | { |
0122f472 GH |
1619 | uint32_t entry; |
1620 | EHCIQueue *q; | |
94527ead | 1621 | int reload; |
94527ead | 1622 | |
0122f472 | 1623 | entry = ehci_get_fetch_addr(ehci, async); |
8ac6d699 GH |
1624 | q = ehci_find_queue_by_qh(ehci, entry); |
1625 | if (NULL == q) { | |
1626 | q = ehci_alloc_queue(ehci, async); | |
1627 | } | |
0122f472 | 1628 | q->qhaddr = entry; |
8ac6d699 GH |
1629 | q->seen++; |
1630 | ||
1631 | if (q->seen > 1) { | |
1632 | /* we are going in circles -- stop processing */ | |
1633 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1634 | q = NULL; | |
1635 | goto out; | |
1636 | } | |
94527ead | 1637 | |
68d55358 DG |
1638 | get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1639 | (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
8ac6d699 GH |
1640 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1641 | ||
1642 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
1643 | /* I/O still in progress -- skip queue */ | |
1644 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1645 | goto out; | |
1646 | } | |
1647 | if (q->async == EHCI_ASYNC_FINISHED) { | |
1648 | /* I/O finished -- continue processing queue */ | |
1649 | trace_usb_ehci_queue_action(q, "resume"); | |
1650 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1651 | goto out; | |
1652 | } | |
0122f472 GH |
1653 | |
1654 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1655 | |
1656 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1657 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1658 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1659 | } else { |
1660 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1661 | " - done processing\n", q->qhaddr); |
26d53979 | 1662 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1663 | q = NULL; |
94527ead GH |
1664 | goto out; |
1665 | } | |
1666 | } | |
1667 | ||
1668 | #if EHCI_DEBUG | |
0122f472 | 1669 | if (q->qhaddr != q->qh.next) { |
94527ead | 1670 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1671 | q->qhaddr, |
1672 | q->qh.epchar & QH_EPCHAR_H, | |
1673 | q->qh.token & QTD_TOKEN_HALT, | |
1674 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1675 | q->qh.next); | |
94527ead GH |
1676 | } |
1677 | #endif | |
1678 | ||
0122f472 | 1679 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1680 | if (reload) { |
0122f472 | 1681 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1682 | } |
1683 | ||
0122f472 | 1684 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1685 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1686 | |
0122f472 GH |
1687 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) { |
1688 | q->qtdaddr = q->qh.current_qtd; | |
26d53979 | 1689 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1690 | |
1691 | } else { | |
1692 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1693 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1694 | } |
1695 | ||
1696 | out: | |
0122f472 | 1697 | return q; |
94527ead GH |
1698 | } |
1699 | ||
26d53979 | 1700 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1701 | { |
0122f472 | 1702 | uint32_t entry; |
94527ead GH |
1703 | EHCIitd itd; |
1704 | ||
0122f472 GH |
1705 | assert(!async); |
1706 | entry = ehci_get_fetch_addr(ehci, async); | |
1707 | ||
68d55358 | 1708 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1709 | sizeof(EHCIitd) >> 2); |
0122f472 | 1710 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1711 | |
1712 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1713 | return -1; | |
1714 | } | |
1715 | ||
68d55358 DG |
1716 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1717 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1718 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1719 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1720 | |
1721 | return 1; | |
1722 | } | |
1723 | ||
2fe80192 GH |
1724 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1725 | { | |
1726 | uint32_t entry; | |
1727 | EHCIsitd sitd; | |
1728 | ||
1729 | assert(!async); | |
1730 | entry = ehci_get_fetch_addr(ehci, async); | |
1731 | ||
68d55358 | 1732 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
2fe80192 GH |
1733 | sizeof(EHCIsitd) >> 2); |
1734 | ehci_trace_sitd(ehci, entry, &sitd); | |
1735 | ||
1736 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1737 | /* siTD is not active, nothing to do */; | |
1738 | } else { | |
1739 | /* TODO: split transfers are not implemented */ | |
1740 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1741 | } | |
1742 | ||
1743 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1744 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1745 | return 1; | |
1746 | } | |
1747 | ||
94527ead | 1748 | /* Section 4.10.2 - paragraph 3 */ |
0122f472 | 1749 | static int ehci_state_advqueue(EHCIQueue *q, int async) |
94527ead GH |
1750 | { |
1751 | #if 0 | |
1752 | /* TO-DO: 4.10.2 - paragraph 2 | |
1753 | * if I-bit is set to 1 and QH is not active | |
1754 | * go to horizontal QH | |
1755 | */ | |
1756 | if (I-bit set) { | |
26d53979 | 1757 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1758 | goto out; |
1759 | } | |
1760 | #endif | |
1761 | ||
1762 | /* | |
1763 | * want data and alt-next qTD is valid | |
1764 | */ | |
0122f472 GH |
1765 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1766 | (q->qh.altnext_qtd > 0x1000) && | |
1767 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { | |
1768 | q->qtdaddr = q->qh.altnext_qtd; | |
1769 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1770 | |
1771 | /* | |
1772 | * next qTD is valid | |
1773 | */ | |
0122f472 GH |
1774 | } else if ((q->qh.next_qtd > 0x1000) && |
1775 | (NLPTR_TBIT(q->qh.next_qtd) == 0)) { | |
1776 | q->qtdaddr = q->qh.next_qtd; | |
1777 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1778 | |
1779 | /* | |
1780 | * no valid qTD, try next QH | |
1781 | */ | |
1782 | } else { | |
0122f472 | 1783 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1784 | } |
1785 | ||
1786 | return 1; | |
1787 | } | |
1788 | ||
1789 | /* Section 4.10.2 - paragraph 4 */ | |
0122f472 | 1790 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) |
94527ead | 1791 | { |
94527ead GH |
1792 | int again = 0; |
1793 | ||
68d55358 DG |
1794 | get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd, |
1795 | sizeof(EHCIqtd) >> 2); | |
8ac6d699 | 1796 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd); |
94527ead | 1797 | |
0122f472 GH |
1798 | if (q->qtd.token & QTD_TOKEN_ACTIVE) { |
1799 | ehci_set_state(q->ehci, async, EST_EXECUTE); | |
94527ead GH |
1800 | again = 1; |
1801 | } else { | |
0122f472 | 1802 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1803 | again = 1; |
1804 | } | |
1805 | ||
1806 | return again; | |
1807 | } | |
1808 | ||
0122f472 | 1809 | static int ehci_state_horizqh(EHCIQueue *q, int async) |
94527ead GH |
1810 | { |
1811 | int again = 0; | |
1812 | ||
0122f472 GH |
1813 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { |
1814 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1815 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
94527ead GH |
1816 | again = 1; |
1817 | } else { | |
0122f472 | 1818 | ehci_set_state(q->ehci, async, EST_ACTIVE); |
94527ead GH |
1819 | } |
1820 | ||
1821 | return again; | |
1822 | } | |
1823 | ||
8ac6d699 GH |
1824 | /* |
1825 | * Write the qh back to guest physical memory. This step isn't | |
1826 | * in the EHCI spec but we need to do it since we don't share | |
1827 | * physical memory with our guest VM. | |
1828 | * | |
1829 | * The first three dwords are read-only for the EHCI, so skip them | |
1830 | * when writing back the qh. | |
1831 | */ | |
1832 | static void ehci_flush_qh(EHCIQueue *q) | |
1833 | { | |
1834 | uint32_t *qh = (uint32_t *) &q->qh; | |
1835 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1836 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1837 | ||
68d55358 | 1838 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
8ac6d699 GH |
1839 | } |
1840 | ||
0122f472 | 1841 | static int ehci_state_execute(EHCIQueue *q, int async) |
94527ead | 1842 | { |
94527ead GH |
1843 | int again = 0; |
1844 | int reload, nakcnt; | |
1845 | int smask; | |
1846 | ||
0122f472 | 1847 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1848 | return -1; |
1849 | } | |
1850 | ||
0122f472 | 1851 | smask = get_field(q->qh.epcap, QH_EPCAP_SMASK); |
94527ead GH |
1852 | |
1853 | if (!smask) { | |
0122f472 GH |
1854 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1855 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1856 | if (reload && !nakcnt) { |
0122f472 | 1857 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1858 | again = 1; |
1859 | goto out; | |
1860 | } | |
1861 | } | |
1862 | ||
1863 | // TODO verify enough time remains in the uframe as in 4.4.1.1 | |
1864 | // TODO write back ptr to async list when done or out of time | |
1865 | // TODO Windows does not seem to ever set the MULT field | |
1866 | ||
1867 | if (!async) { | |
0122f472 | 1868 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1869 | if (!transactCtr) { |
0122f472 | 1870 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1871 | again = 1; |
1872 | goto out; | |
1873 | } | |
1874 | } | |
1875 | ||
1876 | if (async) { | |
0122f472 | 1877 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1878 | } |
1879 | ||
0122f472 GH |
1880 | q->usb_status = ehci_execute(q); |
1881 | if (q->usb_status == USB_RET_PROCERR) { | |
94527ead GH |
1882 | again = -1; |
1883 | goto out; | |
1884 | } | |
8ac6d699 GH |
1885 | if (q->usb_status == USB_RET_ASYNC) { |
1886 | ehci_flush_qh(q); | |
1887 | trace_usb_ehci_queue_action(q, "suspend"); | |
1888 | q->async = EHCI_ASYNC_INFLIGHT; | |
1889 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1890 | again = 1; |
8ac6d699 | 1891 | goto out; |
94527ead GH |
1892 | } |
1893 | ||
8ac6d699 GH |
1894 | ehci_set_state(q->ehci, async, EST_EXECUTING); |
1895 | again = 1; | |
1896 | ||
94527ead GH |
1897 | out: |
1898 | return again; | |
1899 | } | |
1900 | ||
0122f472 | 1901 | static int ehci_state_executing(EHCIQueue *q, int async) |
94527ead | 1902 | { |
94527ead GH |
1903 | int again = 0; |
1904 | int reload, nakcnt; | |
1905 | ||
0122f472 GH |
1906 | ehci_execute_complete(q); |
1907 | if (q->usb_status == USB_RET_ASYNC) { | |
94527ead GH |
1908 | goto out; |
1909 | } | |
0122f472 | 1910 | if (q->usb_status == USB_RET_PROCERR) { |
94527ead GH |
1911 | again = -1; |
1912 | goto out; | |
1913 | } | |
1914 | ||
1915 | // 4.10.3 | |
1916 | if (!async) { | |
0122f472 | 1917 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1918 | transactCtr--; |
0122f472 | 1919 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
1920 | // 4.10.3, bottom of page 82, should exit this state when transaction |
1921 | // counter decrements to 0 | |
1922 | } | |
1923 | ||
0122f472 | 1924 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1925 | if (reload) { |
0122f472 GH |
1926 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); |
1927 | if (q->usb_status == USB_RET_NAK) { | |
94527ead GH |
1928 | if (nakcnt) { |
1929 | nakcnt--; | |
1930 | } | |
94527ead GH |
1931 | } else { |
1932 | nakcnt = reload; | |
94527ead | 1933 | } |
0122f472 | 1934 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1935 | } |
1936 | ||
94527ead | 1937 | /* 4.10.5 */ |
0122f472 GH |
1938 | if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) { |
1939 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1940 | } else { |
0122f472 | 1941 | ehci_set_state(q->ehci, async, EST_WRITEBACK); |
94527ead GH |
1942 | } |
1943 | ||
1944 | again = 1; | |
1945 | ||
1946 | out: | |
8ac6d699 | 1947 | ehci_flush_qh(q); |
94527ead GH |
1948 | return again; |
1949 | } | |
1950 | ||
1951 | ||
0122f472 | 1952 | static int ehci_state_writeback(EHCIQueue *q, int async) |
94527ead | 1953 | { |
94527ead GH |
1954 | int again = 0; |
1955 | ||
1956 | /* Write back the QTD from the QH area */ | |
8ac6d699 | 1957 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd); |
68d55358 DG |
1958 | put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd, |
1959 | sizeof(EHCIqtd) >> 2); | |
94527ead | 1960 | |
d2bd525f GH |
1961 | /* |
1962 | * EHCI specs say go horizontal here. | |
1963 | * | |
1964 | * We can also advance the queue here for performance reasons. We | |
1965 | * need to take care to only take that shortcut in case we've | |
1966 | * processed the qtd just written back without errors, i.e. halt | |
1967 | * bit is clear. | |
94527ead | 1968 | */ |
d2bd525f GH |
1969 | if (q->qh.token & QTD_TOKEN_HALT) { |
1970 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1971 | again = 1; | |
1972 | } else { | |
0122f472 | 1973 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); |
94527ead | 1974 | again = 1; |
d2bd525f | 1975 | } |
94527ead GH |
1976 | return again; |
1977 | } | |
1978 | ||
1979 | /* | |
1980 | * This is the state machine that is common to both async and periodic | |
1981 | */ | |
1982 | ||
26d53979 GH |
1983 | static void ehci_advance_state(EHCIState *ehci, |
1984 | int async) | |
94527ead | 1985 | { |
0122f472 | 1986 | EHCIQueue *q = NULL; |
94527ead GH |
1987 | int again; |
1988 | int iter = 0; | |
1989 | ||
1990 | do { | |
26d53979 | 1991 | if (ehci_get_state(ehci, async) == EST_FETCHQH) { |
94527ead GH |
1992 | iter++; |
1993 | /* if we are roaming a lot of QH without executing a qTD | |
1994 | * something is wrong with the linked list. TO-DO: why is | |
1995 | * this hack needed? | |
1996 | */ | |
8ac6d699 GH |
1997 | assert(iter < MAX_ITERATIONS); |
1998 | #if 0 | |
94527ead GH |
1999 | if (iter > MAX_ITERATIONS) { |
2000 | DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n"); | |
26d53979 | 2001 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2002 | break; |
2003 | } | |
8ac6d699 | 2004 | #endif |
94527ead | 2005 | } |
26d53979 | 2006 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2007 | case EST_WAITLISTHEAD: |
26d53979 | 2008 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
2009 | break; |
2010 | ||
2011 | case EST_FETCHENTRY: | |
26d53979 | 2012 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
2013 | break; |
2014 | ||
2015 | case EST_FETCHQH: | |
0122f472 GH |
2016 | q = ehci_state_fetchqh(ehci, async); |
2017 | again = q ? 1 : 0; | |
94527ead GH |
2018 | break; |
2019 | ||
2020 | case EST_FETCHITD: | |
26d53979 | 2021 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
2022 | break; |
2023 | ||
2fe80192 GH |
2024 | case EST_FETCHSITD: |
2025 | again = ehci_state_fetchsitd(ehci, async); | |
2026 | break; | |
2027 | ||
94527ead | 2028 | case EST_ADVANCEQUEUE: |
0122f472 | 2029 | again = ehci_state_advqueue(q, async); |
94527ead GH |
2030 | break; |
2031 | ||
2032 | case EST_FETCHQTD: | |
0122f472 | 2033 | again = ehci_state_fetchqtd(q, async); |
94527ead GH |
2034 | break; |
2035 | ||
2036 | case EST_HORIZONTALQH: | |
0122f472 | 2037 | again = ehci_state_horizqh(q, async); |
94527ead GH |
2038 | break; |
2039 | ||
2040 | case EST_EXECUTE: | |
2041 | iter = 0; | |
0122f472 | 2042 | again = ehci_state_execute(q, async); |
94527ead GH |
2043 | break; |
2044 | ||
2045 | case EST_EXECUTING: | |
8ac6d699 | 2046 | assert(q != NULL); |
0122f472 | 2047 | again = ehci_state_executing(q, async); |
94527ead GH |
2048 | break; |
2049 | ||
2050 | case EST_WRITEBACK: | |
b2467216 | 2051 | assert(q != NULL); |
0122f472 | 2052 | again = ehci_state_writeback(q, async); |
94527ead GH |
2053 | break; |
2054 | ||
2055 | default: | |
2056 | fprintf(stderr, "Bad state!\n"); | |
2057 | again = -1; | |
8ac6d699 | 2058 | assert(0); |
94527ead GH |
2059 | break; |
2060 | } | |
2061 | ||
2062 | if (again < 0) { | |
2063 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2064 | ehci_reset(ehci); | |
2065 | again = 0; | |
8ac6d699 | 2066 | assert(0); |
94527ead GH |
2067 | } |
2068 | } | |
2069 | while (again); | |
2070 | ||
2071 | ehci_commit_interrupt(ehci); | |
94527ead GH |
2072 | } |
2073 | ||
2074 | static void ehci_advance_async_state(EHCIState *ehci) | |
2075 | { | |
26d53979 | 2076 | int async = 1; |
94527ead | 2077 | |
26d53979 | 2078 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2079 | case EST_INACTIVE: |
2080 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
2081 | break; | |
2082 | } | |
439a97cc | 2083 | ehci_set_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2084 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2085 | // No break, fall through to ACTIVE |
2086 | ||
2087 | case EST_ACTIVE: | |
2088 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
439a97cc | 2089 | ehci_clear_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2090 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2091 | break; |
2092 | } | |
2093 | ||
2094 | /* If the doorbell is set, the guest wants to make a change to the | |
2095 | * schedule. The host controller needs to release cached data. | |
2096 | * (section 4.8.2) | |
2097 | */ | |
2098 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2099 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
2100 | ehci->usbcmd &= ~USBCMD_IAAD; | |
2101 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
2102 | break; | |
2103 | } | |
2104 | ||
2105 | /* make sure guest has acknowledged */ | |
2106 | /* TO-DO: is this really needed? */ | |
2107 | if (ehci->usbsts & USBSTS_IAA) { | |
2108 | DPRINTF("IAA status bit still set.\n"); | |
2109 | break; | |
2110 | } | |
2111 | ||
94527ead GH |
2112 | /* check that address register has been set */ |
2113 | if (ehci->asynclistaddr == 0) { | |
2114 | break; | |
2115 | } | |
2116 | ||
26d53979 | 2117 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2118 | ehci_advance_state(ehci, async); |
94527ead GH |
2119 | break; |
2120 | ||
2121 | default: | |
2122 | /* this should only be due to a developer mistake */ | |
2123 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2124 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2125 | assert(0); |
94527ead GH |
2126 | } |
2127 | } | |
2128 | ||
2129 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2130 | { | |
2131 | uint32_t entry; | |
2132 | uint32_t list; | |
26d53979 | 2133 | int async = 0; |
94527ead GH |
2134 | |
2135 | // 4.6 | |
2136 | ||
26d53979 | 2137 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2138 | case EST_INACTIVE: |
2139 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2140 | ehci_set_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2141 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2142 | // No break, fall through to ACTIVE |
2143 | } else | |
2144 | break; | |
2145 | ||
2146 | case EST_ACTIVE: | |
2147 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2148 | ehci_clear_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2149 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2150 | break; |
2151 | } | |
2152 | ||
2153 | list = ehci->periodiclistbase & 0xfffff000; | |
2154 | /* check that register has been set */ | |
2155 | if (list == 0) { | |
2156 | break; | |
2157 | } | |
2158 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2159 | ||
68d55358 | 2160 | pci_dma_read(&ehci->dev, list, (uint8_t *) &entry, sizeof entry); |
94527ead GH |
2161 | entry = le32_to_cpu(entry); |
2162 | ||
2163 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2164 | ehci->frindex / 8, list, entry); | |
0122f472 | 2165 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2166 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2167 | ehci_advance_state(ehci, async); | |
94527ead GH |
2168 | break; |
2169 | ||
94527ead GH |
2170 | default: |
2171 | /* this should only be due to a developer mistake */ | |
2172 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2173 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2174 | assert(0); |
94527ead GH |
2175 | } |
2176 | } | |
2177 | ||
2178 | static void ehci_frame_timer(void *opaque) | |
2179 | { | |
2180 | EHCIState *ehci = opaque; | |
2181 | int64_t expire_time, t_now; | |
adddecb1 | 2182 | uint64_t ns_elapsed; |
94527ead | 2183 | int frames; |
94527ead GH |
2184 | int i; |
2185 | int skipped_frames = 0; | |
2186 | ||
94527ead | 2187 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2188 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2189 | |
adddecb1 GH |
2190 | ns_elapsed = t_now - ehci->last_run_ns; |
2191 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2192 | |
2193 | for (i = 0; i < frames; i++) { | |
2194 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
2195 | if (ehci->isoch_pause <= 0) { | |
2196 | ehci->frindex += 8; | |
2197 | } | |
2198 | ||
2199 | if (ehci->frindex > 0x00001fff) { | |
2200 | ehci->frindex = 0; | |
2201 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2202 | } | |
2203 | ||
2204 | ehci->sofv = (ehci->frindex - 1) >> 3; | |
2205 | ehci->sofv &= 0x000003ff; | |
2206 | } | |
2207 | ||
16a2dee6 | 2208 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2209 | skipped_frames++; |
2210 | } else { | |
d0539307 | 2211 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2212 | } |
2213 | ||
adddecb1 | 2214 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2215 | } |
2216 | ||
2217 | #if 0 | |
2218 | if (skipped_frames) { | |
2219 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2220 | } | |
2221 | #endif | |
2222 | ||
2223 | /* Async is not inside loop since it executes everything it can once | |
2224 | * called | |
2225 | */ | |
d0539307 | 2226 | ehci_advance_async_state(ehci); |
94527ead GH |
2227 | |
2228 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2229 | } | |
2230 | ||
94527ead | 2231 | |
e57964f5 AK |
2232 | static const MemoryRegionOps ehci_mem_ops = { |
2233 | .old_mmio = { | |
2234 | .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, | |
2235 | .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, | |
2236 | }, | |
2237 | .endianness = DEVICE_LITTLE_ENDIAN, | |
94527ead GH |
2238 | }; |
2239 | ||
94527ead GH |
2240 | static int usb_ehci_initfn(PCIDevice *dev); |
2241 | ||
2242 | static USBPortOps ehci_port_ops = { | |
2243 | .attach = ehci_attach, | |
2244 | .detach = ehci_detach, | |
4706ab6c | 2245 | .child_detach = ehci_child_detach, |
a0a3167a | 2246 | .wakeup = ehci_wakeup, |
94527ead GH |
2247 | .complete = ehci_async_complete_packet, |
2248 | }; | |
2249 | ||
07771f6f | 2250 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2251 | .register_companion = ehci_register_companion, |
07771f6f GH |
2252 | }; |
2253 | ||
9490fb06 GH |
2254 | static const VMStateDescription vmstate_ehci = { |
2255 | .name = "ehci", | |
2256 | .unmigratable = 1, | |
2257 | }; | |
2258 | ||
3028376e GH |
2259 | static Property ehci_properties[] = { |
2260 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2261 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2262 | DEFINE_PROP_END_OF_LIST(), | |
2263 | }; | |
2264 | ||
2265 | static PCIDeviceInfo ehci_info[] = { | |
2266 | { | |
2267 | .qdev.name = "usb-ehci", | |
2268 | .qdev.size = sizeof(EHCIState), | |
9490fb06 | 2269 | .qdev.vmsd = &vmstate_ehci, |
3028376e GH |
2270 | .init = usb_ehci_initfn, |
2271 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
2272 | .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */ | |
2273 | .revision = 0x10, | |
2274 | .class_id = PCI_CLASS_SERIAL_USB, | |
2275 | .qdev.props = ehci_properties, | |
2276 | },{ | |
2277 | .qdev.name = "ich9-usb-ehci1", | |
2278 | .qdev.size = sizeof(EHCIState), | |
9490fb06 | 2279 | .qdev.vmsd = &vmstate_ehci, |
3028376e GH |
2280 | .init = usb_ehci_initfn, |
2281 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
2282 | .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1, | |
2283 | .revision = 0x03, | |
2284 | .class_id = PCI_CLASS_SERIAL_USB, | |
2285 | .qdev.props = ehci_properties, | |
2286 | },{ | |
2287 | /* end of list */ | |
2288 | } | |
94527ead GH |
2289 | }; |
2290 | ||
2291 | static int usb_ehci_initfn(PCIDevice *dev) | |
2292 | { | |
2293 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2294 | uint8_t *pci_conf = s->dev.config; | |
2295 | int i; | |
2296 | ||
94527ead | 2297 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2298 | |
2299 | /* capabilities pointer */ | |
2300 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2301 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2302 | ||
817e0b6f | 2303 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
94527ead GH |
2304 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); |
2305 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2306 | ||
2307 | // pci_conf[0x50] = 0x01; // power management caps | |
2308 | ||
4001f22f | 2309 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2310 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2311 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2312 | ||
2313 | pci_conf[0x64] = 0x00; | |
2314 | pci_conf[0x65] = 0x00; | |
2315 | pci_conf[0x66] = 0x00; | |
2316 | pci_conf[0x67] = 0x00; | |
2317 | pci_conf[0x68] = 0x01; | |
2318 | pci_conf[0x69] = 0x00; | |
2319 | pci_conf[0x6a] = 0x00; | |
2320 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2321 | pci_conf[0x6c] = 0x00; | |
2322 | pci_conf[0x6d] = 0x00; | |
2323 | pci_conf[0x6e] = 0x00; | |
2324 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2325 | ||
2326 | // 2.2 host controller interface version | |
2327 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2328 | s->mmio[0x01] = 0x00; | |
2329 | s->mmio[0x02] = 0x00; | |
2330 | s->mmio[0x03] = 0x01; // HC version | |
2331 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2332 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2333 | s->mmio[0x06] = 0x00; | |
2334 | s->mmio[0x07] = 0x00; | |
2335 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2336 | s->mmio[0x09] = 0x68; // EECP | |
2337 | s->mmio[0x0a] = 0x00; | |
2338 | s->mmio[0x0b] = 0x00; | |
2339 | ||
2340 | s->irq = s->dev.irq[3]; | |
2341 | ||
07771f6f | 2342 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2343 | for(i = 0; i < NB_PORTS; i++) { |
2344 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2345 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2346 | s->ports[i].dev = 0; |
2347 | } | |
2348 | ||
2349 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
8ac6d699 | 2350 | QTAILQ_INIT(&s->queues); |
94527ead GH |
2351 | |
2352 | qemu_register_reset(ehci_reset, s); | |
2353 | ||
e57964f5 | 2354 | memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); |
e824b2cc | 2355 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); |
94527ead GH |
2356 | |
2357 | fprintf(stderr, "*** EHCI support is under development ***\n"); | |
2358 | ||
2359 | return 0; | |
2360 | } | |
2361 | ||
2362 | static void ehci_register(void) | |
2363 | { | |
3028376e | 2364 | pci_qdev_register_many(ehci_info); |
94527ead GH |
2365 | } |
2366 | device_init(ehci_register); | |
2367 | ||
2368 | /* | |
2369 | * vim: expandtab ts=4 | |
2370 | */ |