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usb-ehci: trace state machine changes
[mirror_qemu.git] / hw / usb-ehci.c
CommitLineData
94527ead
GH		 1/*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28#include "hw.h"
29#include "qemu-timer.h"
30#include "usb.h"
31#include "pci.h"
32#include "monitor.h"
439a97cc 33#include "trace.h"
94527ead
GH		 34
35#define EHCI_DEBUG 0
94527ead 36
26d53979 37#if EHCI_DEBUG
94527ead
GH		 38#define DPRINTF printf
39#else
40#define DPRINTF(...)
41#endif
42
94527ead
GH		 43/* internal processing - reset HC to try and recover */
44#define USB_RET_PROCERR (-99)
45
46#define MMIO_SIZE 0x1000
47
48/* Capability Registers Base Address - section 2.2 */
49#define CAPREGBASE 0x0000
50#define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51#define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52#define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53#define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54#define EECP HCCPARAMS + 1
55#define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56#define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58#define OPREGBASE 0x0020 // Operational Registers Base Address
59
60#define USBCMD OPREGBASE + 0x0000
61#define USBCMD_RUNSTOP (1 << 0) // run / Stop
62#define USBCMD_HCRESET (1 << 1) // HC Reset
63#define USBCMD_FLS (3 << 2) // Frame List Size
64#define USBCMD_FLS_SH 2 // Frame List Size Shift
65#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71#define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72#define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74#define USBSTS OPREGBASE + 0x0004
75#define USBSTS_RO_MASK 0x0000003f
76#define USBSTS_INT (1 << 0) // USB Interrupt
77#define USBSTS_ERRINT (1 << 1) // Error Interrupt
78#define USBSTS_PCD (1 << 2) // Port Change Detect
79#define USBSTS_FLR (1 << 3) // Frame List Rollover
80#define USBSTS_HSE (1 << 4) // Host System Error
81#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82#define USBSTS_HALT (1 << 12) // HC Halted
83#define USBSTS_REC (1 << 13) // Reclamation
84#define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87/*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91#define USBINTR OPREGBASE + 0x0008
92#define USBINTR_MASK 0x0000003f
93
94#define FRINDEX OPREGBASE + 0x000c
95#define CTRLDSSEGMENT OPREGBASE + 0x0010
96#define PERIODICLISTBASE OPREGBASE + 0x0014
97#define ASYNCLISTADDR OPREGBASE + 0x0018
98#define ASYNCLISTADDR_MASK 0xffffffe0
99
100#define CONFIGFLAG OPREGBASE + 0x0040
101
102#define PORTSC (OPREGBASE + 0x0044)
103#define PORTSC_BEGIN PORTSC
104#define PORTSC_END (PORTSC + 4 * NB_PORTS)
105/*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109#define PORTSC_RO_MASK 0x007021c5
110#define PORTSC_RWC_MASK 0x0000002a
111#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114#define PORTSC_PTC (15 << 16) // Port Test Control
115#define PORTSC_PTC_SH 16 // Port Test Control shift
116#define PORTSC_PIC (3 << 14) // Port Indicator Control
117#define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118#define PORTSC_POWNER (1 << 13) // Port Owner
119#define PORTSC_PPOWER (1 << 12) // Port Power
120#define PORTSC_LINESTAT (3 << 10) // Port Line Status
121#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122#define PORTSC_PRESET (1 << 8) // Port Reset
123#define PORTSC_SUSPEND (1 << 7) // Port Suspend
124#define PORTSC_FPRES (1 << 6) // Force Port Resume
125#define PORTSC_OCC (1 << 5) // Over Current Change
126#define PORTSC_OCA (1 << 4) // Over Current Active
127#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128#define PORTSC_PED (1 << 2) // Port Enable/Disable
129#define PORTSC_CSC (1 << 1) // Connect Status Change
130#define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132#define FRAME_TIMER_FREQ 1000
133#define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135#define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136#define NB_PORTS 4 // Number of downstream ports
137#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138#define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139#define MAX_QH 100 // Max allowable queue heads in a chain
140
141/* Internal periodic / asynchronous schedule state machine states
142 */
143typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159} EHCI_STATES;
160
161/* macros for accessing fields within next link pointer entry */
162#define NLPTR_GET(x) ((x) & 0xffffffe0)
163#define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164#define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166/* link pointer types */
167#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168#define NLPTR_TYPE_QH 1 // queue head
169#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170#define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173/* EHCI spec version 1.0 Section 3.3
174 */
175typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179#define ITD_XACT_ACTIVE (1 << 31)
180#define ITD_XACT_DBERROR (1 << 30)
181#define ITD_XACT_BABBLE (1 << 29)
182#define ITD_XACT_XACTERR (1 << 28)
183#define ITD_XACT_LENGTH_MASK 0x0fff0000
184#define ITD_XACT_LENGTH_SH 16
185#define ITD_XACT_IOC (1 << 15)
186#define ITD_XACT_PGSEL_MASK 0x00007000
187#define ITD_XACT_PGSEL_SH 12
188#define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191#define ITD_BUFPTR_MASK 0xfffff000
192#define ITD_BUFPTR_SH 12
193#define ITD_BUFPTR_EP_MASK 0x00000f00
194#define ITD_BUFPTR_EP_SH 8
195#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196#define ITD_BUFPTR_DEVADDR_SH 0
197#define ITD_BUFPTR_DIRECTION (1 << 11)
198#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199#define ITD_BUFPTR_MAXPKT_SH 0
200#define ITD_BUFPTR_MULT_MASK 0x00000003
201} EHCIitd;
202
203/* EHCI spec version 1.0 Section 3.4
204 */
205typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208#define SITD_EPCHAR_IO (1 << 31)
209#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210#define SITD_EPCHAR_PORTNUM_SH 24
211#define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212#define SITD_EPCHAR_HUBADDR_SH 16
213#define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214#define SITD_EPCHAR_EPNUM_SH 8
215#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218#define SITD_UFRAME_CMASK_MASK 0x0000ff00
219#define SITD_UFRAME_CMASK_SH 8
220#define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223#define SITD_RESULTS_IOC (1 << 31)
224#define SITD_RESULTS_PGSEL (1 << 30)
225#define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226#define SITD_RESULTS_TYBYTES_SH 16
227#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228#define SITD_RESULTS_CPROGMASK_SH 8
229#define SITD_RESULTS_ACTIVE (1 << 7)
230#define SITD_RESULTS_ERR (1 << 6)
231#define SITD_RESULTS_DBERR (1 << 5)
232#define SITD_RESULTS_BABBLE (1 << 4)
233#define SITD_RESULTS_XACTERR (1 << 3)
234#define SITD_RESULTS_MISSEDUF (1 << 2)
235#define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238#define SITD_BUFPTR_MASK 0xfffff000
239#define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240#define SITD_BUFPTR_TPOS_MASK 0x00000018
241#define SITD_BUFPTR_TPOS_SH 3
242#define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245} EHCIsitd;
246
247/* EHCI spec version 1.0 Section 3.5
248 */
249typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253#define QTD_TOKEN_DTOGGLE (1 << 31)
254#define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255#define QTD_TOKEN_TBYTES_SH 16
256#define QTD_TOKEN_IOC (1 << 15)
257#define QTD_TOKEN_CPAGE_MASK 0x00007000
258#define QTD_TOKEN_CPAGE_SH 12
259#define QTD_TOKEN_CERR_MASK 0x00000c00
260#define QTD_TOKEN_CERR_SH 10
261#define QTD_TOKEN_PID_MASK 0x00000300
262#define QTD_TOKEN_PID_SH 8
263#define QTD_TOKEN_ACTIVE (1 << 7)
264#define QTD_TOKEN_HALT (1 << 6)
265#define QTD_TOKEN_DBERR (1 << 5)
266#define QTD_TOKEN_BABBLE (1 << 4)
267#define QTD_TOKEN_XACTERR (1 << 3)
268#define QTD_TOKEN_MISSEDUF (1 << 2)
269#define QTD_TOKEN_SPLITXSTATE (1 << 1)
270#define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273#define QTD_BUFPTR_MASK 0xfffff000
274} EHCIqtd;
275
276/* EHCI spec version 1.0 Section 3.6
277 */
278typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283#define QH_EPCHAR_RL_MASK 0xf0000000
284#define QH_EPCHAR_RL_SH 28
285#define QH_EPCHAR_C (1 << 27)
286#define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287#define QH_EPCHAR_MPLEN_SH 16
288#define QH_EPCHAR_H (1 << 15)
289#define QH_EPCHAR_DTC (1 << 14)
290#define QH_EPCHAR_EPS_MASK 0x00003000
291#define QH_EPCHAR_EPS_SH 12
292#define EHCI_QH_EPS_FULL 0
293#define EHCI_QH_EPS_LOW 1
294#define EHCI_QH_EPS_HIGH 2
295#define EHCI_QH_EPS_RESERVED 3
296
297#define QH_EPCHAR_EP_MASK 0x00000f00
298#define QH_EPCHAR_EP_SH 8
299#define QH_EPCHAR_I (1 << 7)
300#define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301#define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305#define QH_EPCAP_MULT_MASK 0xc0000000
306#define QH_EPCAP_MULT_SH 30
307#define QH_EPCAP_PORTNUM_MASK 0x3f800000
308#define QH_EPCAP_PORTNUM_SH 23
309#define QH_EPCAP_HUBADDR_MASK 0x007f0000
310#define QH_EPCAP_HUBADDR_SH 16
311#define QH_EPCAP_CMASK_MASK 0x0000ff00
312#define QH_EPCAP_CMASK_SH 8
313#define QH_EPCAP_SMASK_MASK 0x000000ff
314#define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320#define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324#define BUFPTR_CPROGMASK_MASK 0x000000ff
325#define BUFPTR_FRAMETAG_MASK 0x0000001f
326#define BUFPTR_SBYTES_MASK 0x00000fe0
327#define BUFPTR_SBYTES_SH 5
328} EHCIqh;
329
330/* EHCI spec version 1.0 Section 3.7
331 */
332typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335} EHCIfstn;
336
337typedef struct {
338 PCIDevice dev;
339 qemu_irq irq;
340 target_phys_addr_t mem_base;
341 int mem;
342 int num_ports;
343 /*
344 * EHCI spec version 1.0 Section 2.3
345 * Host Controller Operational Registers
346 */
347 union {
348 uint8_t mmio[MMIO_SIZE];
349 struct {
350 uint8_t cap[OPREGBASE];
351 uint32_t usbcmd;
352 uint32_t usbsts;
353 uint32_t usbintr;
354 uint32_t frindex;
355 uint32_t ctrldssegment;
356 uint32_t periodiclistbase;
357 uint32_t asynclistaddr;
358 uint32_t notused[9];
359 uint32_t configflag;
360 uint32_t portsc[NB_PORTS];
361 };
362 };
363 /*
364 * Internal states, shadow registers, etc
365 */
366 uint32_t sofv;
367 QEMUTimer *frame_timer;
368 int attach_poll_counter;
369 int astate; // Current state in asynchronous schedule
370 int pstate; // Current state in periodic schedule
371 USBPort ports[NB_PORTS];
372 uint8_t buffer[BUFF_SIZE];
373 uint32_t usbsts_pending;
374
375 /* cached data from guest - needs to be flushed
376 * when guest removes an entry (doorbell, handshake sequence)
377 */
378 EHCIqh qh; // copy of current QH (being worked on)
379 uint32_t qhaddr; // address QH read from
380
381 EHCIqtd qtd; // copy of current QTD (being worked on)
382 uint32_t qtdaddr; // address QTD read from
383
384 uint32_t itdaddr; // current ITD
385
386 uint32_t fetch_addr; // which address to look at next
387
388 USBBus bus;
389 USBPacket usb_packet;
390 int async_complete;
391 uint32_t tbytes;
392 int pid;
393 int exec_status;
394 int isoch_pause;
395 uint32_t last_run_usec;
396 uint32_t frame_end_usec;
397} EHCIState;
398
399#define SET_LAST_RUN_CLOCK(s) \
400 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
401
402/* nifty macros from Arnon's EHCI version */
403#define get_field(data, field) \
404 (((data) & field##_MASK) >> field##_SH)
405
406#define set_field(data, newval, field) do { \
407 uint32_t val = *data; \
408 val &= ~ field##_MASK; \
409 val |= ((newval) << field##_SH) & field##_MASK; \
410 *data = val; \
411 } while(0)
412
26d53979
GH		 413static const char *ehci_state_names[] = {
414 [ EST_INACTIVE ] = "INACTIVE",
415 [ EST_ACTIVE ] = "ACTIVE",
416 [ EST_EXECUTING ] = "EXECUTING",
417 [ EST_SLEEPING ] = "SLEEPING",
418 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
419 [ EST_FETCHENTRY ] = "FETCH ENTRY",
420 [ EST_FETCHQH ] = "FETCH QH",
421 [ EST_FETCHITD ] = "FETCH ITD",
422 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
423 [ EST_FETCHQTD ] = "FETCH QTD",
424 [ EST_EXECUTE ] = "EXECUTE",
425 [ EST_WRITEBACK ] = "WRITEBACK",
426 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
427};
428
429static const char *ehci_mmio_names[] = {
430 [ CAPLENGTH ] = "CAPLENGTH",
431 [ HCIVERSION ] = "HCIVERSION",
432 [ HCSPARAMS ] = "HCSPARAMS",
433 [ HCCPARAMS ] = "HCCPARAMS",
434 [ USBCMD ] = "USBCMD",
435 [ USBSTS ] = "USBSTS",
436 [ USBINTR ] = "USBINTR",
437 [ FRINDEX ] = "FRINDEX",
438 [ PERIODICLISTBASE ] = "P-LIST BASE",
439 [ ASYNCLISTADDR ] = "A-LIST ADDR",
440 [ PORTSC_BEGIN ] = "PORTSC #0",
441 [ PORTSC_BEGIN + 4] = "PORTSC #1",
442 [ PORTSC_BEGIN + 8] = "PORTSC #2",
443 [ PORTSC_BEGIN + 12] = "PORTSC #3",
444 [ CONFIGFLAG ] = "CONFIGFLAG",
445};
94527ead 446
26d53979 447static const char *nr2str(const char **n, size_t len, uint32_t nr)
94527ead 448{
26d53979
GH		 449 if (nr < len && n[nr] != NULL) {
450 return n[nr];
94527ead 451 } else {
26d53979 452 return "unknown";
94527ead
GH		 453 }
454}
94527ead 455
26d53979
GH		 456static const char *state2str(uint32_t state)
457{
458 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
459}
460
461static const char *addr2str(target_phys_addr_t addr)
462{
463 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
464}
465
439a97cc
GH		 466static void ehci_trace_usbsts(uint32_t mask, int state)
467{
468 /* interrupts */
469 if (mask & USBSTS_INT) {
470 trace_usb_ehci_usbsts("INT", state);
471 }
472 if (mask & USBSTS_ERRINT) {
473 trace_usb_ehci_usbsts("ERRINT", state);
474 }
475 if (mask & USBSTS_PCD) {
476 trace_usb_ehci_usbsts("PCD", state);
477 }
478 if (mask & USBSTS_FLR) {
479 trace_usb_ehci_usbsts("FLR", state);
480 }
481 if (mask & USBSTS_HSE) {
482 trace_usb_ehci_usbsts("HSE", state);
483 }
484 if (mask & USBSTS_IAA) {
485 trace_usb_ehci_usbsts("IAA", state);
486 }
487
488 /* status */
489 if (mask & USBSTS_HALT) {
490 trace_usb_ehci_usbsts("HALT", state);
491 }
492 if (mask & USBSTS_REC) {
493 trace_usb_ehci_usbsts("REC", state);
494 }
495 if (mask & USBSTS_PSS) {
496 trace_usb_ehci_usbsts("PSS", state);
497 }
498 if (mask & USBSTS_ASS) {
499 trace_usb_ehci_usbsts("ASS", state);
500 }
501}
502
503static inline void ehci_set_usbsts(EHCIState *s, int mask)
504{
505 if ((s->usbsts & mask) == mask) {
506 return;
507 }
508 ehci_trace_usbsts(mask, 1);
509 s->usbsts |= mask;
510}
511
512static inline void ehci_clear_usbsts(EHCIState *s, int mask)
513{
514 if ((s->usbsts & mask) == 0) {
515 return;
516 }
517 ehci_trace_usbsts(mask, 0);
518 s->usbsts &= ~mask;
519}
94527ead
GH		 520
521static inline void ehci_set_interrupt(EHCIState *s, int intr)
522{
523 int level = 0;
524
525 // TODO honour interrupt threshold requests
526
439a97cc 527 ehci_set_usbsts(s, intr);
94527ead
GH		 528
529 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
530 level = 1;
531 }
532
533 qemu_set_irq(s->irq, level);
534}
535
536static inline void ehci_record_interrupt(EHCIState *s, int intr)
537{
538 s->usbsts_pending |= intr;
539}
540
541static inline void ehci_commit_interrupt(EHCIState *s)
542{
543 if (!s->usbsts_pending) {
544 return;
545 }
546 ehci_set_interrupt(s, s->usbsts_pending);
547 s->usbsts_pending = 0;
548}
549
26d53979
GH		 550static void ehci_set_state(EHCIState *s, int async, int state)
551{
552 if (async) {
553 trace_usb_ehci_state("async", state2str(state));
554 s->astate = state;
555 } else {
556 trace_usb_ehci_state("periodic", state2str(state));
557 s->pstate = state;
558 }
559}
560
561static int ehci_get_state(EHCIState *s, int async)
562{
563 return async ? s->astate : s->pstate;
564}
565
566static void ehci_trace_qh(EHCIState *s, target_phys_addr_t addr, EHCIqh *qh)
567{
568 trace_usb_ehci_qh(addr, qh->next,
569 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
570 get_field(qh->epchar, QH_EPCHAR_RL),
571 get_field(qh->epchar, QH_EPCHAR_MPLEN),
572 get_field(qh->epchar, QH_EPCHAR_EPS),
573 get_field(qh->epchar, QH_EPCHAR_EP),
574 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
575 (bool)(qh->epchar & QH_EPCHAR_C),
576 (bool)(qh->epchar & QH_EPCHAR_H),
577 (bool)(qh->epchar & QH_EPCHAR_DTC),
578 (bool)(qh->epchar & QH_EPCHAR_I));
579}
580
581static void ehci_trace_qtd(EHCIState *s, target_phys_addr_t addr, EHCIqtd *qtd)
582{
583 trace_usb_ehci_qtd(addr, qtd->next, qtd->altnext,
584 get_field(qtd->token, QTD_TOKEN_TBYTES),
585 get_field(qtd->token, QTD_TOKEN_CPAGE),
586 get_field(qtd->token, QTD_TOKEN_CERR),
587 get_field(qtd->token, QTD_TOKEN_PID),
588 (bool)(qtd->token & QTD_TOKEN_IOC),
589 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
590 (bool)(qtd->token & QTD_TOKEN_HALT),
591 (bool)(qtd->token & QTD_TOKEN_BABBLE),
592 (bool)(qtd->token & QTD_TOKEN_XACTERR));
593}
594
595static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
596{
597 trace_usb_ehci_itd(addr, itd->next);
598}
599
94527ead
GH		 600/* Attach or detach a device on root hub */
601
602static void ehci_attach(USBPort *port)
603{
604 EHCIState *s = port->opaque;
605 uint32_t *portsc = &s->portsc[port->index];
606
607 DPRINTF("ehci_attach invoked for index %d, portsc 0x%x, desc %s\n",
608 port->index, *portsc, port->dev->product_desc);
609
610 *portsc |= PORTSC_CONNECT;
611 *portsc |= PORTSC_CSC;
612
613 /*
614 * If a high speed device is attached then we own this port(indicated
615 * by zero in the PORTSC_POWNER bit field) so set the status bit
616 * and set an interrupt if enabled.
617 */
618 if ( !(*portsc & PORTSC_POWNER)) {
619 ehci_set_interrupt(s, USBSTS_PCD);
620 }
621}
622
623static void ehci_detach(USBPort *port)
624{
625 EHCIState *s = port->opaque;
626 uint32_t *portsc = &s->portsc[port->index];
627
628 DPRINTF("ehci_attach invoked for index %d, portsc 0x%x\n",
629 port->index, *portsc);
630
631 *portsc &= ~PORTSC_CONNECT;
632 *portsc |= PORTSC_CSC;
633
634 /*
635 * If a high speed device is attached then we own this port(indicated
636 * by zero in the PORTSC_POWNER bit field) so set the status bit
637 * and set an interrupt if enabled.
638 */
639 if ( !(*portsc & PORTSC_POWNER)) {
640 ehci_set_interrupt(s, USBSTS_PCD);
641 }
642}
643
644/* 4.1 host controller initialization */
645static void ehci_reset(void *opaque)
646{
647 EHCIState *s = opaque;
648 uint8_t *pci_conf;
649 int i;
650
439a97cc 651 trace_usb_ehci_reset();
94527ead
GH		 652 pci_conf = s->dev.config;
653
654 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
655
656 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
657 s->usbsts = USBSTS_HALT;
658
659 s->astate = EST_INACTIVE;
660 s->pstate = EST_INACTIVE;
661 s->async_complete = 0;
662 s->isoch_pause = -1;
663 s->attach_poll_counter = 0;
664
665 for(i = 0; i < NB_PORTS; i++) {
666 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
667
668 if (s->ports[i].dev) {
669 usb_attach(&s->ports[i], s->ports[i].dev);
670 }
671 }
672}
673
674static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
675{
676 EHCIState *s = ptr;
677 uint32_t val;
678
679 val = s->mmio[addr];
680
681 return val;
682}
683
684static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
685{
686 EHCIState *s = ptr;
687 uint32_t val;
688
689 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
690
691 return val;
692}
693
694static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
695{
696 EHCIState *s = ptr;
697 uint32_t val;
698
699 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
700 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
701
439a97cc 702 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
94527ead
GH		 703 return val;
704}
705
706static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
707{
708 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
709 exit(1);
710}
711
712static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
713{
714 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
715 exit(1);
716}
717
718static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
719{
720 uint32_t *portsc = &s->portsc[port];
721 int rwc;
722 USBDevice *dev = s->ports[port].dev;
723
724 DPRINTF("port_status_write: "
725 "PORTSC (port %d) curr %08X new %08X rw-clear %08X rw %08X\n",
726 port, *portsc, val, (val & PORTSC_RWC_MASK), val & PORTSC_RO_MASK);
727
728 rwc = val & PORTSC_RWC_MASK;
729 val &= PORTSC_RO_MASK;
730
731 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
732
733 *portsc &= ~rwc;
734
735 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
736 DPRINTF("port_status_write: USBTRAN Port %d reset begin\n", port);
737 }
738
739 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
740 DPRINTF("port_status_write: USBTRAN Port %d reset done\n", port);
741 usb_attach(&s->ports[port], dev);
742
743 // TODO how to handle reset of ports with no device
744 if (dev) {
745 usb_send_msg(dev, USB_MSG_RESET);
746 }
747
748 if (s->ports[port].dev) {
749 DPRINTF("port_status_write: "
750 "Device was connected before reset, clearing CSC bit\n");
751 *portsc &= ~PORTSC_CSC;
752 }
753
754 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
755 * to SW that this port has a high speed device attached
756 *
757 * TODO - when to disable?
758 */
759 val |= PORTSC_PED;
760 val |= PORTSC_PEDC;
761 }
762
763 *portsc &= ~PORTSC_RO_MASK;
764 *portsc |= val;
765 DPRINTF("port_status_write: Port %d status set to 0x%08x\n", port, *portsc);
766}
767
768static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
769{
770 EHCIState *s = ptr;
771 int i;
439a97cc
GH		 772
773 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val,
774 *(uint32_t *)(&s->mmio[addr]));
94527ead
GH		 775
776 /* Only aligned reads are allowed on OHCI */
777 if (addr & 3) {
778 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
779 TARGET_FMT_plx "\n", addr);
780 return;
781 }
782
783 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
784 handle_port_status_write(s, (addr-PORTSC)/4, val);
785 return;
786 }
787
788 if (addr < OPREGBASE) {
789 fprintf(stderr, "usb-ehci: write attempt to read-only register"
790 TARGET_FMT_plx "\n", addr);
791 return;
792 }
793
794
795 /* Do any register specific pre-write processing here. */
94527ead
GH		 796 switch(addr) {
797 case USBCMD:
94527ead 798 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
94527ead
GH		 799 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
800 SET_LAST_RUN_CLOCK(s);
439a97cc 801 ehci_clear_usbsts(s, USBSTS_HALT);
94527ead
GH		 802 }
803
804 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
94527ead
GH		 805 qemu_del_timer(s->frame_timer);
806 // TODO - should finish out some stuff before setting halt
439a97cc 807 ehci_set_usbsts(s, USBSTS_HALT);
94527ead
GH		 808 }
809
810 if (val & USBCMD_HCRESET) {
94527ead
GH		 811 ehci_reset(s);
812 val &= ~USBCMD_HCRESET;
813 }
814
815 /* not supporting dynamic frame list size at the moment */
816 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
817 fprintf(stderr, "attempt to set frame list size -- value %d\n",
818 val & USBCMD_FLS);
819 val &= ~USBCMD_FLS;
820 }
94527ead
GH		 821 break;
822
94527ead
GH		 823 case USBSTS:
824 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
439a97cc
GH		 825 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
826 val = s->usbsts;
94527ead
GH		 827 ehci_set_interrupt(s, 0);
828 break;
829
94527ead
GH		 830 case USBINTR:
831 val &= USBINTR_MASK;
94527ead
GH		 832 break;
833
834 case FRINDEX:
835 s->sofv = val >> 3;
94527ead
GH		 836 break;
837
838 case CONFIGFLAG:
94527ead
GH		 839 val &= 0x1;
840 if (val) {
841 for(i = 0; i < NB_PORTS; i++)
842 s->portsc[i] &= ~PORTSC_POWNER;
843 }
844 break;
845
846 case PERIODICLISTBASE:
847 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
848 fprintf(stderr,
849 "ehci: PERIODIC list base register set while periodic schedule\n"
850 " is enabled and HC is enabled\n");
851 }
94527ead
GH		 852 break;
853
854 case ASYNCLISTADDR:
855 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
856 fprintf(stderr,
857 "ehci: ASYNC list address register set while async schedule\n"
858 " is enabled and HC is enabled\n");
859 }
94527ead
GH		 860 break;
861 }
862
863 *(uint32_t *)(&s->mmio[addr]) = val;
864}
865
866
867// TODO : Put in common header file, duplication from usb-ohci.c
868
869/* Get an array of dwords from main memory */
870static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
871{
872 int i;
873
874 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
875 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
876 *buf = le32_to_cpu(*buf);
877 }
878
879 return 1;
880}
881
882/* Put an array of dwords in to main memory */
883static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
884{
885 int i;
886
887 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
888 uint32_t tmp = cpu_to_le32(*buf);
889 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
890 }
891
892 return 1;
893}
894
895// 4.10.2
896
897static int ehci_qh_do_overlay(EHCIState *ehci, EHCIqh *qh, EHCIqtd *qtd)
898{
899 int i;
900 int dtoggle;
901 int ping;
902 int eps;
903 int reload;
904
905 // remember values in fields to preserve in qh after overlay
906
907 dtoggle = qh->token & QTD_TOKEN_DTOGGLE;
908 ping = qh->token & QTD_TOKEN_PING;
909
910 DPRINTF("setting qh.current from %08X to 0x%08X\n", qh->current_qtd,
911 ehci->qtdaddr);
912 qh->current_qtd = ehci->qtdaddr;
913 qh->next_qtd = qtd->next;
914 qh->altnext_qtd = qtd->altnext;
915 qh->token = qtd->token;
916
917
918 eps = get_field(qh->epchar, QH_EPCHAR_EPS);
919 if (eps == EHCI_QH_EPS_HIGH) {
920 qh->token &= ~QTD_TOKEN_PING;
921 qh->token |= ping;
922 }
923
924 reload = get_field(qh->epchar, QH_EPCHAR_RL);
925 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
926
927 for (i = 0; i < 5; i++) {
928 qh->bufptr[i] = qtd->bufptr[i];
929 }
930
931 if (!(qh->epchar & QH_EPCHAR_DTC)) {
932 // preserve QH DT bit
933 qh->token &= ~QTD_TOKEN_DTOGGLE;
934 qh->token |= dtoggle;
935 }
936
937 qh->bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
938 qh->bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
939
940 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
941
942 return 0;
943}
944
945static int ehci_buffer_rw(uint8_t *buffer, EHCIqh *qh, int bytes, int rw)
946{
947 int bufpos = 0;
948 int cpage, offset;
949 uint32_t head;
950 uint32_t tail;
951
952
953 if (!bytes) {
954 return 0;
955 }
956
957 cpage = get_field(qh->token, QTD_TOKEN_CPAGE);
958 if (cpage > 4) {
959 fprintf(stderr, "cpage out of range (%d)\n", cpage);
960 return USB_RET_PROCERR;
961 }
962
963 offset = qh->bufptr[0] & ~QTD_BUFPTR_MASK;
964 DPRINTF("ehci_buffer_rw: %sing %d bytes %08x cpage %d offset %d\n",
965 rw ? "writ" : "read", bytes, qh->bufptr[0], cpage, offset);
966
967 do {
968 /* start and end of this page */
969 head = qh->bufptr[cpage] & QTD_BUFPTR_MASK;
970 tail = head + ~QTD_BUFPTR_MASK + 1;
971 /* add offset into page */
972 head |= offset;
973
974 if (bytes <= (tail - head)) {
975 tail = head + bytes;
976 }
977
978 DPRINTF("DATA %s cpage:%d head:%08X tail:%08X target:%08X\n",
979 rw ? "WRITE" : "READ ", cpage, head, tail, bufpos);
980
981 cpu_physical_memory_rw(head, &buffer[bufpos], tail - head, rw);
982
983 bufpos += (tail - head);
984 bytes -= (tail - head);
985
986 if (bytes > 0) {
987 cpage++;
988 offset = 0;
989 }
990 } while (bytes > 0);
991
992 /* save cpage */
993 set_field(&qh->token, cpage, QTD_TOKEN_CPAGE);
994
995 /* save offset into cpage */
996 offset = tail - head;
997 qh->bufptr[0] &= ~QTD_BUFPTR_MASK;
998 qh->bufptr[0] |= offset;
999
1000 return 0;
1001}
1002
1003static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1004{
1005 EHCIState *ehci = container_of(packet, EHCIState, usb_packet);
1006
1007 DPRINTF("Async packet complete\n");
1008 ehci->async_complete = 1;
1009 ehci->exec_status = packet->len;
1010}
1011
1012static int ehci_execute_complete(EHCIState *ehci, EHCIqh *qh, int ret)
1013{
1014 int c_err, reload;
1015
1016 if (ret == USB_RET_ASYNC && !ehci->async_complete) {
1017 DPRINTF("not done yet\n");
1018 return ret;
1019 }
1020
1021 ehci->async_complete = 0;
1022
1023 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1024 ehci->qhaddr, qh->next, ehci->qtdaddr, ret);
1025
1026 if (ret < 0) {
1027err:
1028 /* TO-DO: put this is in a function that can be invoked below as well */
1029 c_err = get_field(qh->token, QTD_TOKEN_CERR);
1030 c_err--;
1031 set_field(&qh->token, c_err, QTD_TOKEN_CERR);
1032
1033 switch(ret) {
1034 case USB_RET_NODEV:
1035 fprintf(stderr, "USB no device\n");
1036 break;
1037 case USB_RET_STALL:
1038 fprintf(stderr, "USB stall\n");
1039 qh->token |= QTD_TOKEN_HALT;
1040 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1041 break;
1042 case USB_RET_NAK:
1043 /* 4.10.3 */
1044 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1045 if ((ehci->pid == USB_TOKEN_IN) && reload) {
1046 int nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1047 nakcnt--;
1048 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1049 } else if (!reload) {
1050 return USB_RET_NAK;
1051 }
1052 break;
1053 case USB_RET_BABBLE:
1054 fprintf(stderr, "USB babble TODO\n");
1055 qh->token |= QTD_TOKEN_BABBLE;
1056 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1057 break;
1058 default:
1059 fprintf(stderr, "USB invalid response %d to handle\n", ret);
1060 /* TO-DO: transaction error */
1061 ret = USB_RET_PROCERR;
1062 break;
1063 }
1064 } else {
1065 // DPRINTF("Short packet condition\n");
1066 // TODO check 4.12 for splits
1067
1068 if ((ret > ehci->tbytes) && (ehci->pid == USB_TOKEN_IN)) {
1069 ret = USB_RET_BABBLE;
1070 goto err;
1071 }
1072
1073 if (ehci->tbytes && ehci->pid == USB_TOKEN_IN) {
1074 if (ehci_buffer_rw(ehci->buffer, qh, ret, 1) != 0) {
1075 return USB_RET_PROCERR;
1076 }
1077 ehci->tbytes -= ret;
1078 } else {
1079 ehci->tbytes = 0;
1080 }
1081
1082 DPRINTF("updating tbytes to %d\n", ehci->tbytes);
1083 set_field(&qh->token, ehci->tbytes, QTD_TOKEN_TBYTES);
1084 }
1085
1086 qh->token ^= QTD_TOKEN_DTOGGLE;
1087 qh->token &= ~QTD_TOKEN_ACTIVE;
1088
1089 if ((ret >= 0) && (qh->token & QTD_TOKEN_IOC)) {
1090 ehci_record_interrupt(ehci, USBSTS_INT);
1091 }
1092
1093 return ret;
1094}
1095
1096// 4.10.3
1097
1098static int ehci_execute(EHCIState *ehci, EHCIqh *qh)
1099{
1100 USBPort *port;
1101 USBDevice *dev;
1102 int ret;
1103 int i;
1104 int endp;
1105 int devadr;
1106
1107 if ( !(qh->token & QTD_TOKEN_ACTIVE)) {
1108 fprintf(stderr, "Attempting to execute inactive QH\n");
1109 return USB_RET_PROCERR;
1110 }
1111
1112 ehci->tbytes = (qh->token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1113 if (ehci->tbytes > BUFF_SIZE) {
1114 fprintf(stderr, "Request for more bytes than allowed\n");
1115 return USB_RET_PROCERR;
1116 }
1117
1118 ehci->pid = (qh->token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1119 switch(ehci->pid) {
1120 case 0: ehci->pid = USB_TOKEN_OUT; break;
1121 case 1: ehci->pid = USB_TOKEN_IN; break;
1122 case 2: ehci->pid = USB_TOKEN_SETUP; break;
1123 default: fprintf(stderr, "bad token\n"); break;
1124 }
1125
1126 if ((ehci->tbytes && ehci->pid != USB_TOKEN_IN) &&
1127 (ehci_buffer_rw(ehci->buffer, qh, ehci->tbytes, 0) != 0)) {
1128 return USB_RET_PROCERR;
1129 }
1130
1131 endp = get_field(qh->epchar, QH_EPCHAR_EP);
1132 devadr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
1133
1134 ret = USB_RET_NODEV;
1135
1136 // TO-DO: associating device with ehci port
1137 for(i = 0; i < NB_PORTS; i++) {
1138 port = &ehci->ports[i];
1139 dev = port->dev;
1140
1141 // TODO sometime we will also need to check if we are the port owner
1142
1143 if (!(ehci->portsc[i] &(PORTSC_CONNECT))) {
1144 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1145 i, ehci->portsc[i]);
1146 continue;
1147 }
1148
1149 ehci->usb_packet.pid = ehci->pid;
1150 ehci->usb_packet.devaddr = devadr;
1151 ehci->usb_packet.devep = endp;
1152 ehci->usb_packet.data = ehci->buffer;
1153 ehci->usb_packet.len = ehci->tbytes;
1154
1155 ret = usb_handle_packet(dev, &ehci->usb_packet);
1156
1157 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1158 ehci->qhaddr, qh->next, ehci->qtdaddr, ehci->pid,
1159 ehci->usb_packet.len, ehci->tbytes, endp, ret);
1160
1161 if (ret != USB_RET_NODEV) {
1162 break;
1163 }
1164 }
1165
1166 if (ret > BUFF_SIZE) {
1167 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1168 return USB_RET_PROCERR;
1169 }
1170
1171 if (ret == USB_RET_ASYNC) {
1172 ehci->async_complete = 0;
1173 }
1174
1175 return ret;
1176}
1177
1178/* 4.7.2
1179 */
1180
1181static int ehci_process_itd(EHCIState *ehci,
1182 EHCIitd *itd)
1183{
1184 USBPort *port;
1185 USBDevice *dev;
1186 int ret;
1187 int i, j;
1188 int ptr;
1189 int pid;
1190 int pg;
1191 int len;
1192 int dir;
1193 int devadr;
1194 int endp;
1195 int maxpkt;
1196
1197 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1198 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1199 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1200 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1201
1202 for(i = 0; i < 8; i++) {
1203 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1204 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1205 ehci->frindex >> 3, i);
1206
1207 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1208 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1209 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1210 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1211
1212 if (len > BUFF_SIZE) {
1213 return USB_RET_PROCERR;
1214 }
1215
1216 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1217
1218 if (!dir) {
1219 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 0);
1220 pid = USB_TOKEN_OUT;
1221 } else
1222 pid = USB_TOKEN_IN;
1223
1224 ret = USB_RET_NODEV;
1225
1226 for (j = 0; j < NB_PORTS; j++) {
1227 port = &ehci->ports[j];
1228 dev = port->dev;
1229
1230 // TODO sometime we will also need to check if we are the port owner
1231
1232 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1233 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1234 j, ehci->portsc[j]);
1235 continue;
1236 }
1237
1238 ehci->usb_packet.pid = ehci->pid;
1239 ehci->usb_packet.devaddr = devadr;
1240 ehci->usb_packet.devep = endp;
1241 ehci->usb_packet.data = ehci->buffer;
1242 ehci->usb_packet.len = len;
1243
1244 DPRINTF("calling usb_handle_packet\n");
1245 ret = usb_handle_packet(dev, &ehci->usb_packet);
1246
1247 if (ret != USB_RET_NODEV) {
1248 break;
1249 }
1250 }
1251
1252 /* In isoch, there is no facility to indicate a NAK so let's
1253 * instead just complete a zero-byte transaction. Setting
1254 * DBERR seems too draconian.
1255 */
1256
1257 if (ret == USB_RET_NAK) {
1258 if (ehci->isoch_pause > 0) {
1259 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1260 ehci->isoch_pause--;
1261 return 0;
1262 } else if (ehci->isoch_pause == -1) {
1263 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1264 // Pause frindex for up to 50 msec waiting for data from
1265 // remote
1266 ehci->isoch_pause = 50;
1267 return 0;
1268 } else {
1269 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1270 ret = 0;
1271 }
1272 } else {
1273 DPRINTF("ISOCH: received ACK, clearing pause\n");
1274 ehci->isoch_pause = -1;
1275 }
1276
1277 if (ret >= 0) {
1278 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1279
1280 if (itd->transact[i] & ITD_XACT_IOC) {
1281 ehci_record_interrupt(ehci, USBSTS_INT);
1282 }
1283 }
1284
1285 if (ret >= 0 && dir) {
1286 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 1);
1287
1288 if (ret != len) {
1289 DPRINTF("ISOCH IN expected %d, got %d\n",
1290 len, ret);
1291 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1292 }
1293 }
1294 }
1295 }
1296 return 0;
1297}
1298
1299/* This state is the entry point for asynchronous schedule
1300 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1301 */
26d53979 1302static int ehci_state_waitlisthead(EHCIState *ehci, int async)
94527ead
GH		 1303{
1304 EHCIqh *qh = &ehci->qh;
1305 int i = 0;
1306 int again = 0;
1307 uint32_t entry = ehci->asynclistaddr;
1308
1309 /* set reclamation flag at start event (4.8.6) */
1310 if (async) {
439a97cc 1311 ehci_set_usbsts(ehci, USBSTS_REC);
94527ead
GH		 1312 }
1313
1314 /* Find the head of the list (4.9.1.1) */
1315 for(i = 0; i < MAX_QH; i++) {
1316 get_dwords(NLPTR_GET(entry), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
26d53979 1317 ehci_trace_qh(ehci, NLPTR_GET(entry), qh);
94527ead
GH		 1318
1319 if (qh->epchar & QH_EPCHAR_H) {
94527ead
GH		 1320 if (async) {
1321 entry |= (NLPTR_TYPE_QH << 1);
1322 }
1323
1324 ehci->fetch_addr = entry;
26d53979 1325 ehci_set_state(ehci, async, EST_FETCHENTRY);
94527ead
GH		 1326 again = 1;
1327 goto out;
1328 }
1329
94527ead
GH		 1330 entry = qh->next;
1331 if (entry == ehci->asynclistaddr) {
94527ead
GH		 1332 break;
1333 }
1334 }
1335
1336 /* no head found for list. */
1337
26d53979 1338 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1339
1340out:
1341 return again;
1342}
1343
1344
1345/* This state is the entry point for periodic schedule processing as
1346 * well as being a continuation state for async processing.
1347 */
26d53979 1348static int ehci_state_fetchentry(EHCIState *ehci, int async)
94527ead
GH		 1349{
1350 int again = 0;
1351 uint32_t entry = ehci->fetch_addr;
1352
1353#if EHCI_DEBUG == 0
1354 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1355 if (async) {
1356 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1357 goto out;
1358 } else {
1359 DPRINTF("FETCHENTRY: WARNING "
1360 "- frame timer elapsed during periodic\n");
1361 }
1362 }
1363#endif
1364 if (entry < 0x1000) {
1365 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
26d53979 1366 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1367 goto out;
1368 }
1369
1370 /* section 4.8, only QH in async schedule */
1371 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1372 fprintf(stderr, "non queue head request in async schedule\n");
1373 return -1;
1374 }
1375
1376 switch (NLPTR_TYPE_GET(entry)) {
1377 case NLPTR_TYPE_QH:
26d53979 1378 ehci_set_state(ehci, async, EST_FETCHQH);
94527ead
GH		 1379 ehci->qhaddr = entry;
1380 again = 1;
1381 break;
1382
1383 case NLPTR_TYPE_ITD:
26d53979 1384 ehci_set_state(ehci, async, EST_FETCHITD);
94527ead
GH		 1385 ehci->itdaddr = entry;
1386 again = 1;
1387 break;
1388
1389 default:
1390 // TODO: handle siTD and FSTN types
1391 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1392 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1393 return -1;
1394 }
1395
1396out:
1397 return again;
1398}
1399
26d53979 1400static int ehci_state_fetchqh(EHCIState *ehci, int async)
94527ead
GH		 1401{
1402 EHCIqh *qh = &ehci->qh;
1403 int reload;
1404 int again = 0;
1405
1406 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
26d53979 1407 ehci_trace_qh(ehci, NLPTR_GET(ehci->qhaddr), qh);
94527ead
GH		 1408
1409 if (async && (qh->epchar & QH_EPCHAR_H)) {
1410
1411 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1412 if (ehci->usbsts & USBSTS_REC) {
439a97cc 1413 ehci_clear_usbsts(ehci, USBSTS_REC);
94527ead
GH		 1414 } else {
1415 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1416 " - done processing\n", ehci->qhaddr);
26d53979 1417 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1418 goto out;
1419 }
1420 }
1421
1422#if EHCI_DEBUG
1423 if (ehci->qhaddr != qh->next) {
1424 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1425 ehci->qhaddr,
1426 qh->epchar & QH_EPCHAR_H,
1427 qh->token & QTD_TOKEN_HALT,
1428 qh->token & QTD_TOKEN_ACTIVE,
1429 qh->next);
1430 }
1431#endif
1432
1433 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1434 if (reload) {
94527ead
GH		 1435 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1436 }
1437
1438 if (qh->token & QTD_TOKEN_HALT) {
26d53979 1439 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1440 again = 1;
1441
1442 } else if ((qh->token & QTD_TOKEN_ACTIVE) && (qh->current_qtd > 0x1000)) {
94527ead 1443 ehci->qtdaddr = qh->current_qtd;
26d53979 1444 ehci_set_state(ehci, async, EST_FETCHQTD);
94527ead
GH		 1445 again = 1;
1446
1447 } else {
1448 /* EHCI spec version 1.0 Section 4.10.2 */
26d53979 1449 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
94527ead
GH		 1450 again = 1;
1451 }
1452
1453out:
1454 return again;
1455}
1456
26d53979 1457static int ehci_state_fetchitd(EHCIState *ehci, int async)
94527ead
GH		 1458{
1459 EHCIitd itd;
1460
1461 get_dwords(NLPTR_GET(ehci->itdaddr),(uint32_t *) &itd,
1462 sizeof(EHCIitd) >> 2);
26d53979 1463 ehci_trace_itd(ehci, ehci->itdaddr, &itd);
94527ead
GH		 1464
1465 if (ehci_process_itd(ehci, &itd) != 0) {
1466 return -1;
1467 }
1468
1469 put_dwords(NLPTR_GET(ehci->itdaddr), (uint32_t *) &itd,
1470 sizeof(EHCIitd) >> 2);
1471 ehci->fetch_addr = itd.next;
26d53979 1472 ehci_set_state(ehci, async, EST_FETCHENTRY);
94527ead
GH		 1473
1474 return 1;
1475}
1476
1477/* Section 4.10.2 - paragraph 3 */
26d53979 1478static int ehci_state_advqueue(EHCIState *ehci, int async)
94527ead
GH		 1479{
1480#if 0
1481 /* TO-DO: 4.10.2 - paragraph 2
1482 * if I-bit is set to 1 and QH is not active
1483 * go to horizontal QH
1484 */
1485 if (I-bit set) {
26d53979 1486 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1487 goto out;
1488 }
1489#endif
1490
1491 /*
1492 * want data and alt-next qTD is valid
1493 */
1494 if (((ehci->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1495 (ehci->qh.altnext_qtd > 0x1000) &&
1496 (NLPTR_TBIT(ehci->qh.altnext_qtd) == 0)) {
94527ead 1497 ehci->qtdaddr = ehci->qh.altnext_qtd;
26d53979 1498 ehci_set_state(ehci, async, EST_FETCHQTD);
94527ead
GH		 1499
1500 /*
1501 * next qTD is valid
1502 */
1503 } else if ((ehci->qh.next_qtd > 0x1000) &&
1504 (NLPTR_TBIT(ehci->qh.next_qtd) == 0)) {
94527ead 1505 ehci->qtdaddr = ehci->qh.next_qtd;
26d53979 1506 ehci_set_state(ehci, async, EST_FETCHQTD);
94527ead
GH		 1507
1508 /*
1509 * no valid qTD, try next QH
1510 */
1511 } else {
26d53979 1512 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1513 }
1514
1515 return 1;
1516}
1517
1518/* Section 4.10.2 - paragraph 4 */
26d53979 1519static int ehci_state_fetchqtd(EHCIState *ehci, int async)
94527ead
GH		 1520{
1521 EHCIqtd *qtd = &ehci->qtd;
1522 int again = 0;
1523
1524 get_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) qtd, sizeof(EHCIqtd) >> 2);
26d53979 1525 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), qtd);
94527ead
GH		 1526
1527 if (qtd->token & QTD_TOKEN_ACTIVE) {
26d53979 1528 ehci_set_state(ehci, async, EST_EXECUTE);
94527ead
GH		 1529 again = 1;
1530 } else {
26d53979 1531 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1532 again = 1;
1533 }
1534
1535 return again;
1536}
1537
26d53979 1538static int ehci_state_horizqh(EHCIState *ehci, int async)
94527ead
GH		 1539{
1540 int again = 0;
1541
1542 if (ehci->fetch_addr != ehci->qh.next) {
1543 ehci->fetch_addr = ehci->qh.next;
26d53979 1544 ehci_set_state(ehci, async, EST_FETCHENTRY);
94527ead
GH		 1545 again = 1;
1546 } else {
26d53979 1547 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1548 }
1549
1550 return again;
1551}
1552
26d53979 1553static int ehci_state_execute(EHCIState *ehci, int async)
94527ead
GH		 1554{
1555 EHCIqh *qh = &ehci->qh;
1556 EHCIqtd *qtd = &ehci->qtd;
1557 int again = 0;
1558 int reload, nakcnt;
1559 int smask;
1560
94527ead
GH		 1561 if (ehci_qh_do_overlay(ehci, qh, qtd) != 0) {
1562 return -1;
1563 }
1564
1565 smask = get_field(qh->epcap, QH_EPCAP_SMASK);
1566
1567 if (!smask) {
1568 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1569 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1570 if (reload && !nakcnt) {
26d53979 1571 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1572 again = 1;
1573 goto out;
1574 }
1575 }
1576
1577 // TODO verify enough time remains in the uframe as in 4.4.1.1
1578 // TODO write back ptr to async list when done or out of time
1579 // TODO Windows does not seem to ever set the MULT field
1580
1581 if (!async) {
1582 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1583 if (!transactCtr) {
26d53979 1584 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead
GH		 1585 again = 1;
1586 goto out;
1587 }
1588 }
1589
1590 if (async) {
439a97cc 1591 ehci_set_usbsts(ehci, USBSTS_REC);
94527ead
GH		 1592 }
1593
1594 ehci->exec_status = ehci_execute(ehci, qh);
1595 if (ehci->exec_status == USB_RET_PROCERR) {
1596 again = -1;
1597 goto out;
1598 }
26d53979 1599 ehci_set_state(ehci, async, EST_EXECUTING);
94527ead
GH		 1600
1601 if (ehci->exec_status != USB_RET_ASYNC) {
1602 again = 1;
1603 }
1604
1605out:
1606 return again;
1607}
1608
26d53979 1609static int ehci_state_executing(EHCIState *ehci, int async)
94527ead
GH		 1610{
1611 EHCIqh *qh = &ehci->qh;
1612 int again = 0;
1613 int reload, nakcnt;
1614
1615 ehci->exec_status = ehci_execute_complete(ehci, qh, ehci->exec_status);
1616 if (ehci->exec_status == USB_RET_ASYNC) {
1617 goto out;
1618 }
1619 if (ehci->exec_status == USB_RET_PROCERR) {
1620 again = -1;
1621 goto out;
1622 }
1623
1624 // 4.10.3
1625 if (!async) {
1626 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1627 transactCtr--;
1628 set_field(&qh->epcap, transactCtr, QH_EPCAP_MULT);
1629 // 4.10.3, bottom of page 82, should exit this state when transaction
1630 // counter decrements to 0
1631 }
1632
1633
1634 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1635 if (reload) {
1636 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1637 if (ehci->exec_status == USB_RET_NAK) {
1638 if (nakcnt) {
1639 nakcnt--;
1640 }
94527ead
GH		 1641 } else {
1642 nakcnt = reload;
94527ead
GH		 1643 }
1644 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1645 }
1646
1647 /*
1648 * Write the qh back to guest physical memory. This step isn't
1649 * in the EHCI spec but we need to do it since we don't share
1650 * physical memory with our guest VM.
1651 */
94527ead
GH		 1652 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1653
1654 /* 4.10.5 */
1655 if ((ehci->exec_status == USB_RET_NAK) || (qh->token & QTD_TOKEN_ACTIVE)) {
26d53979 1656 ehci_set_state(ehci, async, EST_HORIZONTALQH);
94527ead 1657 } else {
26d53979 1658 ehci_set_state(ehci, async, EST_WRITEBACK);
94527ead
GH		 1659 }
1660
1661 again = 1;
1662
1663out:
1664 return again;
1665}
1666
1667
26d53979 1668static int ehci_state_writeback(EHCIState *ehci, int async)
94527ead
GH		 1669{
1670 EHCIqh *qh = &ehci->qh;
1671 int again = 0;
1672
1673 /* Write back the QTD from the QH area */
26d53979 1674 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), (EHCIqtd*) &qh->next_qtd);
94527ead
GH		 1675 put_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) &qh->next_qtd,
1676 sizeof(EHCIqtd) >> 2);
1677
1678 /* TODO confirm next state. For now, keep going if async
1679 * but stop after one qtd if periodic
1680 */
1681 //if (async) {
26d53979 1682 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
94527ead
GH		 1683 again = 1;
1684 //} else {
26d53979 1685 // ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1686 //}
1687 return again;
1688}
1689
1690/*
1691 * This is the state machine that is common to both async and periodic
1692 */
1693
26d53979
GH		 1694static void ehci_advance_state(EHCIState *ehci,
1695 int async)
94527ead
GH		 1696{
1697 int again;
1698 int iter = 0;
1699
1700 do {
26d53979 1701 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
94527ead
GH		 1702 iter++;
1703 /* if we are roaming a lot of QH without executing a qTD
1704 * something is wrong with the linked list. TO-DO: why is
1705 * this hack needed?
1706 */
1707 if (iter > MAX_ITERATIONS) {
1708 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
26d53979 1709 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1710 break;
1711 }
1712 }
26d53979 1713 switch(ehci_get_state(ehci, async)) {
94527ead 1714 case EST_WAITLISTHEAD:
26d53979 1715 again = ehci_state_waitlisthead(ehci, async);
94527ead
GH		 1716 break;
1717
1718 case EST_FETCHENTRY:
26d53979 1719 again = ehci_state_fetchentry(ehci, async);
94527ead
GH		 1720 break;
1721
1722 case EST_FETCHQH:
26d53979 1723 again = ehci_state_fetchqh(ehci, async);
94527ead
GH		 1724 break;
1725
1726 case EST_FETCHITD:
26d53979 1727 again = ehci_state_fetchitd(ehci, async);
94527ead
GH		 1728 break;
1729
1730 case EST_ADVANCEQUEUE:
26d53979 1731 again = ehci_state_advqueue(ehci, async);
94527ead
GH		 1732 break;
1733
1734 case EST_FETCHQTD:
26d53979 1735 again = ehci_state_fetchqtd(ehci, async);
94527ead
GH		 1736 break;
1737
1738 case EST_HORIZONTALQH:
26d53979 1739 again = ehci_state_horizqh(ehci, async);
94527ead
GH		 1740 break;
1741
1742 case EST_EXECUTE:
1743 iter = 0;
26d53979 1744 again = ehci_state_execute(ehci, async);
94527ead
GH		 1745 break;
1746
1747 case EST_EXECUTING:
26d53979 1748 again = ehci_state_executing(ehci, async);
94527ead
GH		 1749 break;
1750
1751 case EST_WRITEBACK:
26d53979 1752 again = ehci_state_writeback(ehci, async);
94527ead
GH		 1753 break;
1754
1755 default:
1756 fprintf(stderr, "Bad state!\n");
1757 again = -1;
1758 break;
1759 }
1760
1761 if (again < 0) {
1762 fprintf(stderr, "processing error - resetting ehci HC\n");
1763 ehci_reset(ehci);
1764 again = 0;
1765 }
1766 }
1767 while (again);
1768
1769 ehci_commit_interrupt(ehci);
94527ead
GH		 1770}
1771
1772static void ehci_advance_async_state(EHCIState *ehci)
1773{
1774 EHCIqh qh;
26d53979 1775 int async = 1;
94527ead 1776
26d53979 1777 switch(ehci_get_state(ehci, async)) {
94527ead
GH		 1778 case EST_INACTIVE:
1779 if (!(ehci->usbcmd & USBCMD_ASE)) {
1780 break;
1781 }
439a97cc 1782 ehci_set_usbsts(ehci, USBSTS_ASS);
26d53979 1783 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1784 // No break, fall through to ACTIVE
1785
1786 case EST_ACTIVE:
1787 if ( !(ehci->usbcmd & USBCMD_ASE)) {
439a97cc 1788 ehci_clear_usbsts(ehci, USBSTS_ASS);
26d53979 1789 ehci_set_state(ehci, async, EST_INACTIVE);
94527ead
GH		 1790 break;
1791 }
1792
1793 /* If the doorbell is set, the guest wants to make a change to the
1794 * schedule. The host controller needs to release cached data.
1795 * (section 4.8.2)
1796 */
1797 if (ehci->usbcmd & USBCMD_IAAD) {
1798 DPRINTF("ASYNC: doorbell request acknowledged\n");
1799 ehci->usbcmd &= ~USBCMD_IAAD;
1800 ehci_set_interrupt(ehci, USBSTS_IAA);
1801 break;
1802 }
1803
1804 /* make sure guest has acknowledged */
1805 /* TO-DO: is this really needed? */
1806 if (ehci->usbsts & USBSTS_IAA) {
1807 DPRINTF("IAA status bit still set.\n");
1808 break;
1809 }
1810
94527ead
GH		 1811 /* check that address register has been set */
1812 if (ehci->asynclistaddr == 0) {
1813 break;
1814 }
1815
26d53979 1816 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
94527ead
GH		 1817 /* fall through */
1818
1819 case EST_FETCHENTRY:
1820 /* fall through */
1821
1822 case EST_EXECUTING:
1823 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) &qh,
1824 sizeof(EHCIqh) >> 2);
26d53979 1825 ehci_advance_state(ehci, async);
94527ead
GH		 1826 break;
1827
1828 default:
1829 /* this should only be due to a developer mistake */
1830 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1831 "Resetting to active\n", ehci->astate);
26d53979 1832 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1833 }
1834}
1835
1836static void ehci_advance_periodic_state(EHCIState *ehci)
1837{
1838 uint32_t entry;
1839 uint32_t list;
26d53979 1840 int async = 0;
94527ead
GH		 1841
1842 // 4.6
1843
26d53979 1844 switch(ehci_get_state(ehci, async)) {
94527ead
GH		 1845 case EST_INACTIVE:
1846 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
439a97cc 1847 ehci_set_usbsts(ehci, USBSTS_PSS);
26d53979 1848 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1849 // No break, fall through to ACTIVE
1850 } else
1851 break;
1852
1853 case EST_ACTIVE:
1854 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
439a97cc 1855 ehci_clear_usbsts(ehci, USBSTS_PSS);
26d53979 1856 ehci_set_state(ehci, async, EST_INACTIVE);
94527ead
GH		 1857 break;
1858 }
1859
1860 list = ehci->periodiclistbase & 0xfffff000;
1861 /* check that register has been set */
1862 if (list == 0) {
1863 break;
1864 }
1865 list |= ((ehci->frindex & 0x1ff8) >> 1);
1866
1867 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1868 entry = le32_to_cpu(entry);
1869
1870 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1871 ehci->frindex / 8, list, entry);
1872 ehci->fetch_addr = entry;
26d53979
GH		 1873 ehci_set_state(ehci, async, EST_FETCHENTRY);
1874 ehci_advance_state(ehci, async);
94527ead
GH		 1875 break;
1876
1877 case EST_EXECUTING:
1878 DPRINTF("PERIODIC state adv for executing\n");
26d53979 1879 ehci_advance_state(ehci, async);
94527ead
GH		 1880 break;
1881
1882 default:
1883 /* this should only be due to a developer mistake */
1884 fprintf(stderr, "ehci: Bad periodic state %d. "
1885 "Resetting to active\n", ehci->pstate);
26d53979 1886 ehci_set_state(ehci, async, EST_ACTIVE);
94527ead
GH		 1887 }
1888}
1889
1890static void ehci_frame_timer(void *opaque)
1891{
1892 EHCIState *ehci = opaque;
1893 int64_t expire_time, t_now;
1894 int usec_elapsed;
1895 int frames;
1896 int usec_now;
1897 int i;
1898 int skipped_frames = 0;
1899
1900
1901 t_now = qemu_get_clock_ns(vm_clock);
1902 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1903 if (expire_time == t_now) {
1904 expire_time++;
1905 }
1906
1907 usec_now = t_now / 1000;
1908 usec_elapsed = usec_now - ehci->last_run_usec;
1909 frames = usec_elapsed / FRAME_TIMER_USEC;
1910 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
1911
1912 for (i = 0; i < frames; i++) {
1913 if ( !(ehci->usbsts & USBSTS_HALT)) {
1914 if (ehci->isoch_pause <= 0) {
1915 ehci->frindex += 8;
1916 }
1917
1918 if (ehci->frindex > 0x00001fff) {
1919 ehci->frindex = 0;
1920 ehci_set_interrupt(ehci, USBSTS_FLR);
1921 }
1922
1923 ehci->sofv = (ehci->frindex - 1) >> 3;
1924 ehci->sofv &= 0x000003ff;
1925 }
1926
1927 if (frames - i > 10) {
1928 skipped_frames++;
1929 } else {
1930 // TODO could this cause periodic frames to get skipped if async
1931 // active?
26d53979 1932 if (ehci_get_state(ehci, 1) != EST_EXECUTING) {
94527ead
GH		 1933 ehci_advance_periodic_state(ehci);
1934 }
1935 }
1936
1937 ehci->last_run_usec += FRAME_TIMER_USEC;
1938 }
1939
1940#if 0
1941 if (skipped_frames) {
1942 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
1943 }
1944#endif
1945
1946 /* Async is not inside loop since it executes everything it can once
1947 * called
1948 */
26d53979 1949 if (ehci_get_state(ehci, 0) != EST_EXECUTING) {
94527ead
GH		 1950 ehci_advance_async_state(ehci);
1951 }
1952
1953 qemu_mod_timer(ehci->frame_timer, expire_time);
1954}
1955
1956static CPUReadMemoryFunc *ehci_readfn[3]={
1957 ehci_mem_readb,
1958 ehci_mem_readw,
1959 ehci_mem_readl
1960};
1961
1962static CPUWriteMemoryFunc *ehci_writefn[3]={
1963 ehci_mem_writeb,
1964 ehci_mem_writew,
1965 ehci_mem_writel
1966};
1967
1968static void ehci_map(PCIDevice *pci_dev, int region_num,
1969 pcibus_t addr, pcibus_t size, int type)
1970{
1971 EHCIState *s =(EHCIState *)pci_dev;
1972
1973 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
1974 region_num, addr, size, s->mem);
1975 s->mem_base = addr;
1976 cpu_register_physical_memory(addr, size, s->mem);
1977}
1978
1979static int usb_ehci_initfn(PCIDevice *dev);
1980
1981static USBPortOps ehci_port_ops = {
1982 .attach = ehci_attach,
1983 .detach = ehci_detach,
1984 .complete = ehci_async_complete_packet,
1985};
1986
1987static PCIDeviceInfo ehci_info = {
1988 .qdev.name = "usb-ehci",
1989 .qdev.size = sizeof(EHCIState),
1990 .init = usb_ehci_initfn,
1991};
1992
1993static int usb_ehci_initfn(PCIDevice *dev)
1994{
1995 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
1996 uint8_t *pci_conf = s->dev.config;
1997 int i;
1998
1999 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
2000 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
2001 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
2002 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2003 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
2004 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
2005
2006 /* capabilities pointer */
2007 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2008 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2009
2010 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2011 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2012 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2013
2014 // pci_conf[0x50] = 0x01; // power management caps
2015
2016 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2017 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2018 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2019
2020 pci_conf[0x64] = 0x00;
2021 pci_conf[0x65] = 0x00;
2022 pci_conf[0x66] = 0x00;
2023 pci_conf[0x67] = 0x00;
2024 pci_conf[0x68] = 0x01;
2025 pci_conf[0x69] = 0x00;
2026 pci_conf[0x6a] = 0x00;
2027 pci_conf[0x6b] = 0x00; // USBLEGSUP
2028 pci_conf[0x6c] = 0x00;
2029 pci_conf[0x6d] = 0x00;
2030 pci_conf[0x6e] = 0x00;
2031 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2032
2033 // 2.2 host controller interface version
2034 s->mmio[0x00] = (uint8_t) OPREGBASE;
2035 s->mmio[0x01] = 0x00;
2036 s->mmio[0x02] = 0x00;
2037 s->mmio[0x03] = 0x01; // HC version
2038 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2039 s->mmio[0x05] = 0x00; // No companion ports at present
2040 s->mmio[0x06] = 0x00;
2041 s->mmio[0x07] = 0x00;
2042 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2043 s->mmio[0x09] = 0x68; // EECP
2044 s->mmio[0x0a] = 0x00;
2045 s->mmio[0x0b] = 0x00;
2046
2047 s->irq = s->dev.irq[3];
2048
2049 usb_bus_new(&s->bus, &s->dev.qdev);
2050 for(i = 0; i < NB_PORTS; i++) {
2051 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2052 USB_SPEED_MASK_HIGH);
2053 usb_port_location(&s->ports[i], NULL, i+1);
2054 s->ports[i].dev = 0;
2055 }
2056
2057 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2058
2059 qemu_register_reset(ehci_reset, s);
2060
2061 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2062 DEVICE_LITTLE_ENDIAN);
2063
2064 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2065 ehci_map);
2066
2067 fprintf(stderr, "*** EHCI support is under development ***\n");
2068
2069 return 0;
2070}
2071
2072static void ehci_register(void)
2073{
2074 pci_qdev_register(&ehci_info);
2075}
2076device_init(ehci_register);
2077
2078/*
2079 * vim: expandtab ts=4
2080 */
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