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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * TODO: | |
25 | * o Downstream port handoff | |
26 | */ | |
27 | ||
28 | #include "hw.h" | |
29 | #include "qemu-timer.h" | |
30 | #include "usb.h" | |
31 | #include "pci.h" | |
32 | #include "monitor.h" | |
439a97cc | 33 | #include "trace.h" |
94527ead GH |
34 | |
35 | #define EHCI_DEBUG 0 | |
94527ead | 36 | |
26d53979 | 37 | #if EHCI_DEBUG |
94527ead GH |
38 | #define DPRINTF printf |
39 | #else | |
40 | #define DPRINTF(...) | |
41 | #endif | |
42 | ||
94527ead GH |
43 | /* internal processing - reset HC to try and recover */ |
44 | #define USB_RET_PROCERR (-99) | |
45 | ||
46 | #define MMIO_SIZE 0x1000 | |
47 | ||
48 | /* Capability Registers Base Address - section 2.2 */ | |
49 | #define CAPREGBASE 0x0000 | |
50 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
51 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
52 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
53 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
54 | #define EECP HCCPARAMS + 1 | |
55 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
56 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
57 | ||
58 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
59 | ||
60 | #define USBCMD OPREGBASE + 0x0000 | |
61 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
62 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
63 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
64 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
65 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
66 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
67 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
68 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
69 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
70 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
71 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
72 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
73 | ||
74 | #define USBSTS OPREGBASE + 0x0004 | |
75 | #define USBSTS_RO_MASK 0x0000003f | |
76 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
77 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
78 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
79 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
80 | #define USBSTS_HSE (1 << 4) // Host System Error | |
81 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
82 | #define USBSTS_HALT (1 << 12) // HC Halted | |
83 | #define USBSTS_REC (1 << 13) // Reclamation | |
84 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
85 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
86 | ||
87 | /* | |
88 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
89 | * so no need to redefine here. | |
90 | */ | |
91 | #define USBINTR OPREGBASE + 0x0008 | |
92 | #define USBINTR_MASK 0x0000003f | |
93 | ||
94 | #define FRINDEX OPREGBASE + 0x000c | |
95 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
96 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
97 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
98 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
99 | ||
100 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
101 | ||
102 | #define PORTSC (OPREGBASE + 0x0044) | |
103 | #define PORTSC_BEGIN PORTSC | |
104 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
105 | /* | |
c44fd61c | 106 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
107 | * written to us by software |
108 | */ | |
fbd97532 | 109 | #define PORTSC_RO_MASK 0x007021c0 |
94527ead GH |
110 | #define PORTSC_RWC_MASK 0x0000002a |
111 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
112 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
113 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
114 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
115 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
116 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
117 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
118 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
119 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
120 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
121 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
122 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
123 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
124 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
125 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
126 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
127 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
128 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
129 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
130 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
131 | ||
132 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 133 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
134 | |
135 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
136 | #define NB_PORTS 4 // Number of downstream ports | |
137 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction | |
138 | #define MAX_ITERATIONS 20 // Max number of QH before we break the loop | |
139 | #define MAX_QH 100 // Max allowable queue heads in a chain | |
140 | ||
141 | /* Internal periodic / asynchronous schedule state machine states | |
142 | */ | |
143 | typedef enum { | |
144 | EST_INACTIVE = 1000, | |
145 | EST_ACTIVE, | |
146 | EST_EXECUTING, | |
147 | EST_SLEEPING, | |
148 | /* The following states are internal to the state machine function | |
149 | */ | |
150 | EST_WAITLISTHEAD, | |
151 | EST_FETCHENTRY, | |
152 | EST_FETCHQH, | |
153 | EST_FETCHITD, | |
154 | EST_ADVANCEQUEUE, | |
155 | EST_FETCHQTD, | |
156 | EST_EXECUTE, | |
157 | EST_WRITEBACK, | |
158 | EST_HORIZONTALQH | |
159 | } EHCI_STATES; | |
160 | ||
161 | /* macros for accessing fields within next link pointer entry */ | |
162 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
163 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
164 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
165 | ||
166 | /* link pointer types */ | |
167 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
168 | #define NLPTR_TYPE_QH 1 // queue head | |
169 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
170 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
171 | ||
172 | ||
173 | /* EHCI spec version 1.0 Section 3.3 | |
174 | */ | |
175 | typedef struct EHCIitd { | |
176 | uint32_t next; | |
177 | ||
178 | uint32_t transact[8]; | |
179 | #define ITD_XACT_ACTIVE (1 << 31) | |
180 | #define ITD_XACT_DBERROR (1 << 30) | |
181 | #define ITD_XACT_BABBLE (1 << 29) | |
182 | #define ITD_XACT_XACTERR (1 << 28) | |
183 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
184 | #define ITD_XACT_LENGTH_SH 16 | |
185 | #define ITD_XACT_IOC (1 << 15) | |
186 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
187 | #define ITD_XACT_PGSEL_SH 12 | |
188 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
189 | ||
190 | uint32_t bufptr[7]; | |
191 | #define ITD_BUFPTR_MASK 0xfffff000 | |
192 | #define ITD_BUFPTR_SH 12 | |
193 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
194 | #define ITD_BUFPTR_EP_SH 8 | |
195 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
196 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
197 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
198 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
199 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
200 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 201 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
202 | } EHCIitd; |
203 | ||
204 | /* EHCI spec version 1.0 Section 3.4 | |
205 | */ | |
206 | typedef struct EHCIsitd { | |
207 | uint32_t next; // Standard next link pointer | |
208 | uint32_t epchar; | |
209 | #define SITD_EPCHAR_IO (1 << 31) | |
210 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
211 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
212 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
213 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
214 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
215 | #define SITD_EPCHAR_EPNUM_SH 8 | |
216 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
217 | ||
218 | uint32_t uframe; | |
219 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
220 | #define SITD_UFRAME_CMASK_SH 8 | |
221 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
222 | ||
223 | uint32_t results; | |
224 | #define SITD_RESULTS_IOC (1 << 31) | |
225 | #define SITD_RESULTS_PGSEL (1 << 30) | |
226 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
227 | #define SITD_RESULTS_TYBYTES_SH 16 | |
228 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
229 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
230 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
231 | #define SITD_RESULTS_ERR (1 << 6) | |
232 | #define SITD_RESULTS_DBERR (1 << 5) | |
233 | #define SITD_RESULTS_BABBLE (1 << 4) | |
234 | #define SITD_RESULTS_XACTERR (1 << 3) | |
235 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
236 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
237 | ||
238 | uint32_t bufptr[2]; | |
239 | #define SITD_BUFPTR_MASK 0xfffff000 | |
240 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
241 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
242 | #define SITD_BUFPTR_TPOS_SH 3 | |
243 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
244 | ||
245 | uint32_t backptr; // Standard next link pointer | |
246 | } EHCIsitd; | |
247 | ||
248 | /* EHCI spec version 1.0 Section 3.5 | |
249 | */ | |
250 | typedef struct EHCIqtd { | |
251 | uint32_t next; // Standard next link pointer | |
252 | uint32_t altnext; // Standard next link pointer | |
253 | uint32_t token; | |
254 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
255 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
256 | #define QTD_TOKEN_TBYTES_SH 16 | |
257 | #define QTD_TOKEN_IOC (1 << 15) | |
258 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
259 | #define QTD_TOKEN_CPAGE_SH 12 | |
260 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
261 | #define QTD_TOKEN_CERR_SH 10 | |
262 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
263 | #define QTD_TOKEN_PID_SH 8 | |
264 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
265 | #define QTD_TOKEN_HALT (1 << 6) | |
266 | #define QTD_TOKEN_DBERR (1 << 5) | |
267 | #define QTD_TOKEN_BABBLE (1 << 4) | |
268 | #define QTD_TOKEN_XACTERR (1 << 3) | |
269 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
270 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
271 | #define QTD_TOKEN_PING (1 << 0) | |
272 | ||
273 | uint32_t bufptr[5]; // Standard buffer pointer | |
274 | #define QTD_BUFPTR_MASK 0xfffff000 | |
275 | } EHCIqtd; | |
276 | ||
277 | /* EHCI spec version 1.0 Section 3.6 | |
278 | */ | |
279 | typedef struct EHCIqh { | |
280 | uint32_t next; // Standard next link pointer | |
281 | ||
282 | /* endpoint characteristics */ | |
283 | uint32_t epchar; | |
284 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
285 | #define QH_EPCHAR_RL_SH 28 | |
286 | #define QH_EPCHAR_C (1 << 27) | |
287 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
288 | #define QH_EPCHAR_MPLEN_SH 16 | |
289 | #define QH_EPCHAR_H (1 << 15) | |
290 | #define QH_EPCHAR_DTC (1 << 14) | |
291 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
292 | #define QH_EPCHAR_EPS_SH 12 | |
293 | #define EHCI_QH_EPS_FULL 0 | |
294 | #define EHCI_QH_EPS_LOW 1 | |
295 | #define EHCI_QH_EPS_HIGH 2 | |
296 | #define EHCI_QH_EPS_RESERVED 3 | |
297 | ||
298 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
299 | #define QH_EPCHAR_EP_SH 8 | |
300 | #define QH_EPCHAR_I (1 << 7) | |
301 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
302 | #define QH_EPCHAR_DEVADDR_SH 0 | |
303 | ||
304 | /* endpoint capabilities */ | |
305 | uint32_t epcap; | |
306 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
307 | #define QH_EPCAP_MULT_SH 30 | |
308 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
309 | #define QH_EPCAP_PORTNUM_SH 23 | |
310 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
311 | #define QH_EPCAP_HUBADDR_SH 16 | |
312 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
313 | #define QH_EPCAP_CMASK_SH 8 | |
314 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
315 | #define QH_EPCAP_SMASK_SH 0 | |
316 | ||
317 | uint32_t current_qtd; // Standard next link pointer | |
318 | uint32_t next_qtd; // Standard next link pointer | |
319 | uint32_t altnext_qtd; | |
320 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
321 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
322 | ||
323 | uint32_t token; // Same as QTD token | |
324 | uint32_t bufptr[5]; // Standard buffer pointer | |
325 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
326 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
327 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
328 | #define BUFPTR_SBYTES_SH 5 | |
329 | } EHCIqh; | |
330 | ||
331 | /* EHCI spec version 1.0 Section 3.7 | |
332 | */ | |
333 | typedef struct EHCIfstn { | |
334 | uint32_t next; // Standard next link pointer | |
335 | uint32_t backptr; // Standard next link pointer | |
336 | } EHCIfstn; | |
337 | ||
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
347 | struct EHCIQueue { | |
348 | EHCIState *ehci; | |
8ac6d699 GH |
349 | QTAILQ_ENTRY(EHCIQueue) next; |
350 | bool async_schedule; | |
adddecb1 GH |
351 | uint32_t seen; |
352 | uint64_t ts; | |
0122f472 GH |
353 | |
354 | /* cached data from guest - needs to be flushed | |
355 | * when guest removes an entry (doorbell, handshake sequence) | |
356 | */ | |
357 | EHCIqh qh; // copy of current QH (being worked on) | |
358 | uint32_t qhaddr; // address QH read from | |
359 | EHCIqtd qtd; // copy of current QTD (being worked on) | |
360 | uint32_t qtdaddr; // address QTD read from | |
361 | ||
362 | USBPacket packet; | |
363 | uint8_t buffer[BUFF_SIZE]; | |
364 | int pid; | |
365 | uint32_t tbytes; | |
366 | enum async_state async; | |
367 | int usb_status; | |
368 | }; | |
369 | ||
370 | struct EHCIState { | |
94527ead | 371 | PCIDevice dev; |
0122f472 | 372 | USBBus bus; |
94527ead GH |
373 | qemu_irq irq; |
374 | target_phys_addr_t mem_base; | |
375 | int mem; | |
16a2dee6 GH |
376 | |
377 | /* properties */ | |
378 | uint32_t freq; | |
379 | uint32_t maxframes; | |
380 | ||
94527ead GH |
381 | /* |
382 | * EHCI spec version 1.0 Section 2.3 | |
383 | * Host Controller Operational Registers | |
384 | */ | |
385 | union { | |
386 | uint8_t mmio[MMIO_SIZE]; | |
387 | struct { | |
388 | uint8_t cap[OPREGBASE]; | |
389 | uint32_t usbcmd; | |
390 | uint32_t usbsts; | |
391 | uint32_t usbintr; | |
392 | uint32_t frindex; | |
393 | uint32_t ctrldssegment; | |
394 | uint32_t periodiclistbase; | |
395 | uint32_t asynclistaddr; | |
396 | uint32_t notused[9]; | |
397 | uint32_t configflag; | |
398 | uint32_t portsc[NB_PORTS]; | |
399 | }; | |
400 | }; | |
0122f472 | 401 | |
94527ead GH |
402 | /* |
403 | * Internal states, shadow registers, etc | |
404 | */ | |
405 | uint32_t sofv; | |
406 | QEMUTimer *frame_timer; | |
407 | int attach_poll_counter; | |
408 | int astate; // Current state in asynchronous schedule | |
409 | int pstate; // Current state in periodic schedule | |
410 | USBPort ports[NB_PORTS]; | |
94527ead | 411 | uint32_t usbsts_pending; |
8ac6d699 | 412 | QTAILQ_HEAD(, EHCIQueue) queues; |
94527ead | 413 | |
0122f472 GH |
414 | uint32_t a_fetch_addr; // which address to look at next |
415 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 416 | |
0122f472 GH |
417 | USBPacket ipacket; |
418 | uint8_t ibuffer[BUFF_SIZE]; | |
94527ead | 419 | int isoch_pause; |
0122f472 | 420 | |
adddecb1 | 421 | uint64_t last_run_ns; |
0122f472 | 422 | }; |
94527ead GH |
423 | |
424 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 425 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
426 | |
427 | /* nifty macros from Arnon's EHCI version */ | |
428 | #define get_field(data, field) \ | |
429 | (((data) & field##_MASK) >> field##_SH) | |
430 | ||
431 | #define set_field(data, newval, field) do { \ | |
432 | uint32_t val = *data; \ | |
433 | val &= ~ field##_MASK; \ | |
434 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
435 | *data = val; \ | |
436 | } while(0) | |
437 | ||
26d53979 GH |
438 | static const char *ehci_state_names[] = { |
439 | [ EST_INACTIVE ] = "INACTIVE", | |
440 | [ EST_ACTIVE ] = "ACTIVE", | |
441 | [ EST_EXECUTING ] = "EXECUTING", | |
442 | [ EST_SLEEPING ] = "SLEEPING", | |
443 | [ EST_WAITLISTHEAD ] = "WAITLISTHEAD", | |
444 | [ EST_FETCHENTRY ] = "FETCH ENTRY", | |
445 | [ EST_FETCHQH ] = "FETCH QH", | |
446 | [ EST_FETCHITD ] = "FETCH ITD", | |
447 | [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE", | |
448 | [ EST_FETCHQTD ] = "FETCH QTD", | |
449 | [ EST_EXECUTE ] = "EXECUTE", | |
450 | [ EST_WRITEBACK ] = "WRITEBACK", | |
451 | [ EST_HORIZONTALQH ] = "HORIZONTALQH", | |
452 | }; | |
453 | ||
454 | static const char *ehci_mmio_names[] = { | |
455 | [ CAPLENGTH ] = "CAPLENGTH", | |
456 | [ HCIVERSION ] = "HCIVERSION", | |
457 | [ HCSPARAMS ] = "HCSPARAMS", | |
458 | [ HCCPARAMS ] = "HCCPARAMS", | |
459 | [ USBCMD ] = "USBCMD", | |
460 | [ USBSTS ] = "USBSTS", | |
461 | [ USBINTR ] = "USBINTR", | |
462 | [ FRINDEX ] = "FRINDEX", | |
463 | [ PERIODICLISTBASE ] = "P-LIST BASE", | |
464 | [ ASYNCLISTADDR ] = "A-LIST ADDR", | |
465 | [ PORTSC_BEGIN ] = "PORTSC #0", | |
466 | [ PORTSC_BEGIN + 4] = "PORTSC #1", | |
467 | [ PORTSC_BEGIN + 8] = "PORTSC #2", | |
468 | [ PORTSC_BEGIN + 12] = "PORTSC #3", | |
469 | [ CONFIGFLAG ] = "CONFIGFLAG", | |
470 | }; | |
94527ead | 471 | |
26d53979 | 472 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 473 | { |
26d53979 GH |
474 | if (nr < len && n[nr] != NULL) { |
475 | return n[nr]; | |
94527ead | 476 | } else { |
26d53979 | 477 | return "unknown"; |
94527ead GH |
478 | } |
479 | } | |
94527ead | 480 | |
26d53979 GH |
481 | static const char *state2str(uint32_t state) |
482 | { | |
483 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
484 | } | |
485 | ||
486 | static const char *addr2str(target_phys_addr_t addr) | |
487 | { | |
488 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
489 | } | |
490 | ||
439a97cc GH |
491 | static void ehci_trace_usbsts(uint32_t mask, int state) |
492 | { | |
493 | /* interrupts */ | |
494 | if (mask & USBSTS_INT) { | |
495 | trace_usb_ehci_usbsts("INT", state); | |
496 | } | |
497 | if (mask & USBSTS_ERRINT) { | |
498 | trace_usb_ehci_usbsts("ERRINT", state); | |
499 | } | |
500 | if (mask & USBSTS_PCD) { | |
501 | trace_usb_ehci_usbsts("PCD", state); | |
502 | } | |
503 | if (mask & USBSTS_FLR) { | |
504 | trace_usb_ehci_usbsts("FLR", state); | |
505 | } | |
506 | if (mask & USBSTS_HSE) { | |
507 | trace_usb_ehci_usbsts("HSE", state); | |
508 | } | |
509 | if (mask & USBSTS_IAA) { | |
510 | trace_usb_ehci_usbsts("IAA", state); | |
511 | } | |
512 | ||
513 | /* status */ | |
514 | if (mask & USBSTS_HALT) { | |
515 | trace_usb_ehci_usbsts("HALT", state); | |
516 | } | |
517 | if (mask & USBSTS_REC) { | |
518 | trace_usb_ehci_usbsts("REC", state); | |
519 | } | |
520 | if (mask & USBSTS_PSS) { | |
521 | trace_usb_ehci_usbsts("PSS", state); | |
522 | } | |
523 | if (mask & USBSTS_ASS) { | |
524 | trace_usb_ehci_usbsts("ASS", state); | |
525 | } | |
526 | } | |
527 | ||
528 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
529 | { | |
530 | if ((s->usbsts & mask) == mask) { | |
531 | return; | |
532 | } | |
533 | ehci_trace_usbsts(mask, 1); | |
534 | s->usbsts |= mask; | |
535 | } | |
536 | ||
537 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
538 | { | |
539 | if ((s->usbsts & mask) == 0) { | |
540 | return; | |
541 | } | |
542 | ehci_trace_usbsts(mask, 0); | |
543 | s->usbsts &= ~mask; | |
544 | } | |
94527ead GH |
545 | |
546 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
547 | { | |
548 | int level = 0; | |
549 | ||
550 | // TODO honour interrupt threshold requests | |
551 | ||
439a97cc | 552 | ehci_set_usbsts(s, intr); |
94527ead GH |
553 | |
554 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
555 | level = 1; | |
556 | } | |
557 | ||
558 | qemu_set_irq(s->irq, level); | |
559 | } | |
560 | ||
561 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
562 | { | |
563 | s->usbsts_pending |= intr; | |
564 | } | |
565 | ||
566 | static inline void ehci_commit_interrupt(EHCIState *s) | |
567 | { | |
568 | if (!s->usbsts_pending) { | |
569 | return; | |
570 | } | |
571 | ehci_set_interrupt(s, s->usbsts_pending); | |
572 | s->usbsts_pending = 0; | |
573 | } | |
574 | ||
26d53979 GH |
575 | static void ehci_set_state(EHCIState *s, int async, int state) |
576 | { | |
577 | if (async) { | |
578 | trace_usb_ehci_state("async", state2str(state)); | |
579 | s->astate = state; | |
580 | } else { | |
581 | trace_usb_ehci_state("periodic", state2str(state)); | |
582 | s->pstate = state; | |
583 | } | |
584 | } | |
585 | ||
586 | static int ehci_get_state(EHCIState *s, int async) | |
587 | { | |
588 | return async ? s->astate : s->pstate; | |
589 | } | |
590 | ||
0122f472 GH |
591 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
592 | { | |
593 | if (async) { | |
594 | s->a_fetch_addr = addr; | |
595 | } else { | |
596 | s->p_fetch_addr = addr; | |
597 | } | |
598 | } | |
599 | ||
600 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
601 | { | |
602 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
603 | } | |
604 | ||
8ac6d699 | 605 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 606 | { |
025b168c GH |
607 | /* need three here due to argument count limits */ |
608 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
609 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
610 | trace_usb_ehci_qh_fields(addr, | |
611 | get_field(qh->epchar, QH_EPCHAR_RL), | |
612 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
613 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
614 | get_field(qh->epchar, QH_EPCHAR_EP), | |
615 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
616 | trace_usb_ehci_qh_bits(addr, | |
617 | (bool)(qh->epchar & QH_EPCHAR_C), | |
618 | (bool)(qh->epchar & QH_EPCHAR_H), | |
619 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
620 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
621 | } |
622 | ||
8ac6d699 | 623 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 624 | { |
025b168c GH |
625 | /* need three here due to argument count limits */ |
626 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
627 | trace_usb_ehci_qtd_fields(addr, | |
628 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
629 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
630 | get_field(qtd->token, QTD_TOKEN_CERR), | |
631 | get_field(qtd->token, QTD_TOKEN_PID)); | |
632 | trace_usb_ehci_qtd_bits(addr, | |
633 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
634 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
635 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
636 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
637 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
638 | } |
639 | ||
640 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
641 | { | |
e654887f GH |
642 | trace_usb_ehci_itd(addr, itd->next, |
643 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
644 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
645 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
646 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
647 | } |
648 | ||
8ac6d699 GH |
649 | /* queue management */ |
650 | ||
651 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
652 | { | |
653 | EHCIQueue *q; | |
654 | ||
655 | q = qemu_mallocz(sizeof(*q)); | |
656 | q->ehci = ehci; | |
657 | q->async_schedule = async; | |
658 | QTAILQ_INSERT_HEAD(&ehci->queues, q, next); | |
659 | trace_usb_ehci_queue_action(q, "alloc"); | |
660 | return q; | |
661 | } | |
662 | ||
663 | static void ehci_free_queue(EHCIQueue *q) | |
664 | { | |
665 | trace_usb_ehci_queue_action(q, "free"); | |
666 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
667 | usb_cancel_packet(&q->packet); | |
668 | } | |
669 | QTAILQ_REMOVE(&q->ehci->queues, q, next); | |
670 | qemu_free(q); | |
671 | } | |
672 | ||
673 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr) | |
674 | { | |
675 | EHCIQueue *q; | |
676 | ||
677 | QTAILQ_FOREACH(q, &ehci->queues, next) { | |
678 | if (addr == q->qhaddr) { | |
679 | return q; | |
680 | } | |
681 | } | |
682 | return NULL; | |
683 | } | |
684 | ||
685 | static void ehci_queues_rip_unused(EHCIState *ehci) | |
686 | { | |
687 | EHCIQueue *q, *tmp; | |
688 | ||
689 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
690 | if (q->seen) { | |
691 | q->seen = 0; | |
adddecb1 | 692 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
693 | continue; |
694 | } | |
adddecb1 | 695 | if (ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
696 | /* allow 0.25 sec idle */ |
697 | continue; | |
698 | } | |
699 | ehci_free_queue(q); | |
700 | } | |
701 | } | |
702 | ||
07771f6f GH |
703 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev) |
704 | { | |
705 | EHCIQueue *q, *tmp; | |
706 | ||
707 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
708 | if (q->packet.owner != dev) { | |
709 | continue; | |
710 | } | |
711 | ehci_free_queue(q); | |
712 | } | |
713 | } | |
714 | ||
8ac6d699 GH |
715 | static void ehci_queues_rip_all(EHCIState *ehci) |
716 | { | |
717 | EHCIQueue *q, *tmp; | |
718 | ||
719 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
720 | ehci_free_queue(q); | |
721 | } | |
722 | } | |
723 | ||
94527ead GH |
724 | /* Attach or detach a device on root hub */ |
725 | ||
726 | static void ehci_attach(USBPort *port) | |
727 | { | |
728 | EHCIState *s = port->opaque; | |
729 | uint32_t *portsc = &s->portsc[port->index]; | |
730 | ||
dcbd0b5c | 731 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead GH |
732 | |
733 | *portsc |= PORTSC_CONNECT; | |
734 | *portsc |= PORTSC_CSC; | |
735 | ||
736 | /* | |
737 | * If a high speed device is attached then we own this port(indicated | |
738 | * by zero in the PORTSC_POWNER bit field) so set the status bit | |
739 | * and set an interrupt if enabled. | |
740 | */ | |
741 | if ( !(*portsc & PORTSC_POWNER)) { | |
742 | ehci_set_interrupt(s, USBSTS_PCD); | |
743 | } | |
744 | } | |
745 | ||
746 | static void ehci_detach(USBPort *port) | |
747 | { | |
748 | EHCIState *s = port->opaque; | |
749 | uint32_t *portsc = &s->portsc[port->index]; | |
750 | ||
dcbd0b5c | 751 | trace_usb_ehci_port_detach(port->index); |
94527ead | 752 | |
4706ab6c HG |
753 | ehci_queues_rip_device(s, port->dev); |
754 | ||
fbd97532 | 755 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
756 | *portsc |= PORTSC_CSC; |
757 | ||
758 | /* | |
759 | * If a high speed device is attached then we own this port(indicated | |
760 | * by zero in the PORTSC_POWNER bit field) so set the status bit | |
761 | * and set an interrupt if enabled. | |
762 | */ | |
763 | if ( !(*portsc & PORTSC_POWNER)) { | |
764 | ehci_set_interrupt(s, USBSTS_PCD); | |
765 | } | |
766 | } | |
767 | ||
4706ab6c HG |
768 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
769 | { | |
770 | EHCIState *s = port->opaque; | |
771 | ||
772 | ehci_queues_rip_device(s, child); | |
773 | } | |
774 | ||
94527ead GH |
775 | /* 4.1 host controller initialization */ |
776 | static void ehci_reset(void *opaque) | |
777 | { | |
778 | EHCIState *s = opaque; | |
94527ead GH |
779 | int i; |
780 | ||
439a97cc | 781 | trace_usb_ehci_reset(); |
94527ead GH |
782 | |
783 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); | |
784 | ||
785 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
786 | s->usbsts = USBSTS_HALT; | |
787 | ||
788 | s->astate = EST_INACTIVE; | |
789 | s->pstate = EST_INACTIVE; | |
94527ead GH |
790 | s->isoch_pause = -1; |
791 | s->attach_poll_counter = 0; | |
792 | ||
793 | for(i = 0; i < NB_PORTS; i++) { | |
794 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
795 | ||
796 | if (s->ports[i].dev) { | |
797 | usb_attach(&s->ports[i], s->ports[i].dev); | |
798 | } | |
799 | } | |
8ac6d699 | 800 | ehci_queues_rip_all(s); |
94527ead GH |
801 | } |
802 | ||
803 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
804 | { | |
805 | EHCIState *s = ptr; | |
806 | uint32_t val; | |
807 | ||
808 | val = s->mmio[addr]; | |
809 | ||
810 | return val; | |
811 | } | |
812 | ||
813 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
814 | { | |
815 | EHCIState *s = ptr; | |
816 | uint32_t val; | |
817 | ||
818 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
819 | ||
820 | return val; | |
821 | } | |
822 | ||
823 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
824 | { | |
825 | EHCIState *s = ptr; | |
826 | uint32_t val; | |
827 | ||
828 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
829 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
830 | ||
439a97cc | 831 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
832 | return val; |
833 | } | |
834 | ||
835 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
836 | { | |
837 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
838 | exit(1); | |
839 | } | |
840 | ||
841 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
842 | { | |
843 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
844 | exit(1); | |
845 | } | |
846 | ||
847 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) | |
848 | { | |
849 | uint32_t *portsc = &s->portsc[port]; | |
94527ead GH |
850 | USBDevice *dev = s->ports[port].dev; |
851 | ||
fbd97532 HG |
852 | /* Clear rwc bits */ |
853 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
854 | /* The guest may clear, but not set the PED bit */ | |
855 | *portsc &= val | ~PORTSC_PED; | |
94527ead GH |
856 | val &= PORTSC_RO_MASK; |
857 | ||
94527ead | 858 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 859 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
860 | } |
861 | ||
862 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 863 | trace_usb_ehci_port_reset(port, 0); |
94527ead | 864 | if (dev) { |
fbf9db64 | 865 | usb_attach(&s->ports[port], dev); |
94527ead | 866 | usb_send_msg(dev, USB_MSG_RESET); |
94527ead GH |
867 | *portsc &= ~PORTSC_CSC; |
868 | } | |
869 | ||
fbd97532 HG |
870 | /* |
871 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 872 | * to SW that this port has a high speed device attached |
94527ead | 873 | */ |
fbd97532 HG |
874 | if (dev && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
875 | val |= PORTSC_PED; | |
876 | } | |
94527ead GH |
877 | } |
878 | ||
879 | *portsc &= ~PORTSC_RO_MASK; | |
880 | *portsc |= val; | |
94527ead GH |
881 | } |
882 | ||
883 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
884 | { | |
885 | EHCIState *s = ptr; | |
c4f8e211 GH |
886 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
887 | uint32_t old = *mmio; | |
94527ead | 888 | int i; |
439a97cc | 889 | |
c4f8e211 | 890 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
891 | |
892 | /* Only aligned reads are allowed on OHCI */ | |
893 | if (addr & 3) { | |
894 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
895 | TARGET_FMT_plx "\n", addr); | |
896 | return; | |
897 | } | |
898 | ||
899 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
900 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 901 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
902 | return; |
903 | } | |
904 | ||
905 | if (addr < OPREGBASE) { | |
906 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
907 | TARGET_FMT_plx "\n", addr); | |
908 | return; | |
909 | } | |
910 | ||
911 | ||
912 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
913 | switch(addr) { |
914 | case USBCMD: | |
94527ead | 915 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { |
94527ead GH |
916 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
917 | SET_LAST_RUN_CLOCK(s); | |
439a97cc | 918 | ehci_clear_usbsts(s, USBSTS_HALT); |
94527ead GH |
919 | } |
920 | ||
921 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
94527ead GH |
922 | qemu_del_timer(s->frame_timer); |
923 | // TODO - should finish out some stuff before setting halt | |
439a97cc | 924 | ehci_set_usbsts(s, USBSTS_HALT); |
94527ead GH |
925 | } |
926 | ||
927 | if (val & USBCMD_HCRESET) { | |
94527ead GH |
928 | ehci_reset(s); |
929 | val &= ~USBCMD_HCRESET; | |
930 | } | |
931 | ||
932 | /* not supporting dynamic frame list size at the moment */ | |
933 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
934 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
935 | val & USBCMD_FLS); | |
936 | val &= ~USBCMD_FLS; | |
937 | } | |
94527ead GH |
938 | break; |
939 | ||
94527ead GH |
940 | case USBSTS: |
941 | val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO | |
439a97cc GH |
942 | ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC |
943 | val = s->usbsts; | |
94527ead GH |
944 | ehci_set_interrupt(s, 0); |
945 | break; | |
946 | ||
94527ead GH |
947 | case USBINTR: |
948 | val &= USBINTR_MASK; | |
94527ead GH |
949 | break; |
950 | ||
951 | case FRINDEX: | |
952 | s->sofv = val >> 3; | |
94527ead GH |
953 | break; |
954 | ||
955 | case CONFIGFLAG: | |
94527ead GH |
956 | val &= 0x1; |
957 | if (val) { | |
958 | for(i = 0; i < NB_PORTS; i++) | |
959 | s->portsc[i] &= ~PORTSC_POWNER; | |
960 | } | |
961 | break; | |
962 | ||
963 | case PERIODICLISTBASE: | |
964 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
965 | fprintf(stderr, | |
966 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
967 | " is enabled and HC is enabled\n"); | |
968 | } | |
94527ead GH |
969 | break; |
970 | ||
971 | case ASYNCLISTADDR: | |
972 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
973 | fprintf(stderr, | |
974 | "ehci: ASYNC list address register set while async schedule\n" | |
975 | " is enabled and HC is enabled\n"); | |
976 | } | |
94527ead GH |
977 | break; |
978 | } | |
979 | ||
c4f8e211 GH |
980 | *mmio = val; |
981 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
982 | } |
983 | ||
984 | ||
985 | // TODO : Put in common header file, duplication from usb-ohci.c | |
986 | ||
987 | /* Get an array of dwords from main memory */ | |
988 | static inline int get_dwords(uint32_t addr, uint32_t *buf, int num) | |
989 | { | |
990 | int i; | |
991 | ||
992 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
993 | cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0); | |
994 | *buf = le32_to_cpu(*buf); | |
995 | } | |
996 | ||
997 | return 1; | |
998 | } | |
999 | ||
1000 | /* Put an array of dwords in to main memory */ | |
1001 | static inline int put_dwords(uint32_t addr, uint32_t *buf, int num) | |
1002 | { | |
1003 | int i; | |
1004 | ||
1005 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1006 | uint32_t tmp = cpu_to_le32(*buf); | |
1007 | cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1); | |
1008 | } | |
1009 | ||
1010 | return 1; | |
1011 | } | |
1012 | ||
1013 | // 4.10.2 | |
1014 | ||
0122f472 | 1015 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead GH |
1016 | { |
1017 | int i; | |
1018 | int dtoggle; | |
1019 | int ping; | |
1020 | int eps; | |
1021 | int reload; | |
1022 | ||
1023 | // remember values in fields to preserve in qh after overlay | |
1024 | ||
0122f472 GH |
1025 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1026 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1027 | |
0122f472 GH |
1028 | q->qh.current_qtd = q->qtdaddr; |
1029 | q->qh.next_qtd = q->qtd.next; | |
1030 | q->qh.altnext_qtd = q->qtd.altnext; | |
1031 | q->qh.token = q->qtd.token; | |
94527ead GH |
1032 | |
1033 | ||
0122f472 | 1034 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1035 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1036 | q->qh.token &= ~QTD_TOKEN_PING; |
1037 | q->qh.token |= ping; | |
94527ead GH |
1038 | } |
1039 | ||
0122f472 GH |
1040 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1041 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1042 | |
1043 | for (i = 0; i < 5; i++) { | |
0122f472 | 1044 | q->qh.bufptr[i] = q->qtd.bufptr[i]; |
94527ead GH |
1045 | } |
1046 | ||
0122f472 | 1047 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1048 | // preserve QH DT bit |
0122f472 GH |
1049 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1050 | q->qh.token |= dtoggle; | |
94527ead GH |
1051 | } |
1052 | ||
0122f472 GH |
1053 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1054 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1055 | |
0122f472 | 1056 | put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); |
94527ead GH |
1057 | |
1058 | return 0; | |
1059 | } | |
1060 | ||
0122f472 | 1061 | static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw) |
94527ead GH |
1062 | { |
1063 | int bufpos = 0; | |
1064 | int cpage, offset; | |
1065 | uint32_t head; | |
1066 | uint32_t tail; | |
1067 | ||
1068 | ||
1069 | if (!bytes) { | |
1070 | return 0; | |
1071 | } | |
1072 | ||
0122f472 | 1073 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
94527ead GH |
1074 | if (cpage > 4) { |
1075 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1076 | return USB_RET_PROCERR; | |
1077 | } | |
1078 | ||
0122f472 | 1079 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; |
94527ead GH |
1080 | |
1081 | do { | |
1082 | /* start and end of this page */ | |
0122f472 | 1083 | head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK; |
94527ead GH |
1084 | tail = head + ~QTD_BUFPTR_MASK + 1; |
1085 | /* add offset into page */ | |
1086 | head |= offset; | |
1087 | ||
1088 | if (bytes <= (tail - head)) { | |
1089 | tail = head + bytes; | |
1090 | } | |
1091 | ||
f2c88dc1 | 1092 | trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos); |
0122f472 | 1093 | cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw); |
94527ead GH |
1094 | |
1095 | bufpos += (tail - head); | |
ba7cb5a8 | 1096 | offset += (tail - head); |
94527ead GH |
1097 | bytes -= (tail - head); |
1098 | ||
1099 | if (bytes > 0) { | |
1100 | cpage++; | |
1101 | offset = 0; | |
1102 | } | |
1103 | } while (bytes > 0); | |
1104 | ||
1105 | /* save cpage */ | |
0122f472 | 1106 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
94527ead GH |
1107 | |
1108 | /* save offset into cpage */ | |
ba7cb5a8 | 1109 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; |
0122f472 | 1110 | q->qh.bufptr[0] |= offset; |
94527ead GH |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
d47e59b8 | 1115 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1116 | { |
0122f472 | 1117 | EHCIQueue *q = container_of(packet, EHCIQueue, packet); |
94527ead | 1118 | |
8ac6d699 GH |
1119 | trace_usb_ehci_queue_action(q, "wakeup"); |
1120 | assert(q->async == EHCI_ASYNC_INFLIGHT); | |
0122f472 GH |
1121 | q->async = EHCI_ASYNC_FINISHED; |
1122 | q->usb_status = packet->len; | |
94527ead GH |
1123 | } |
1124 | ||
0122f472 | 1125 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead GH |
1126 | { |
1127 | int c_err, reload; | |
1128 | ||
8ac6d699 | 1129 | assert(q->async != EHCI_ASYNC_INFLIGHT); |
0122f472 | 1130 | q->async = EHCI_ASYNC_NONE; |
94527ead GH |
1131 | |
1132 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1133 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1134 | |
0122f472 | 1135 | if (q->usb_status < 0) { |
94527ead GH |
1136 | err: |
1137 | /* TO-DO: put this is in a function that can be invoked below as well */ | |
0122f472 | 1138 | c_err = get_field(q->qh.token, QTD_TOKEN_CERR); |
94527ead | 1139 | c_err--; |
0122f472 | 1140 | set_field(&q->qh.token, c_err, QTD_TOKEN_CERR); |
94527ead | 1141 | |
0122f472 | 1142 | switch(q->usb_status) { |
94527ead | 1143 | case USB_RET_NODEV: |
d2bd525f GH |
1144 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1145 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1146 | break; |
1147 | case USB_RET_STALL: | |
0122f472 GH |
1148 | q->qh.token |= QTD_TOKEN_HALT; |
1149 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1150 | break; |
1151 | case USB_RET_NAK: | |
1152 | /* 4.10.3 */ | |
0122f472 GH |
1153 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1154 | if ((q->pid == USB_TOKEN_IN) && reload) { | |
1155 | int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1156 | nakcnt--; |
0122f472 | 1157 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead | 1158 | } else if (!reload) { |
0122f472 | 1159 | return; |
94527ead GH |
1160 | } |
1161 | break; | |
1162 | case USB_RET_BABBLE: | |
d2bd525f | 1163 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1164 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1165 | break; |
1166 | default: | |
0122f472 GH |
1167 | /* should not be triggerable */ |
1168 | fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status); | |
1169 | assert(0); | |
94527ead GH |
1170 | break; |
1171 | } | |
1172 | } else { | |
1173 | // DPRINTF("Short packet condition\n"); | |
1174 | // TODO check 4.12 for splits | |
1175 | ||
0122f472 GH |
1176 | if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) { |
1177 | q->usb_status = USB_RET_BABBLE; | |
94527ead GH |
1178 | goto err; |
1179 | } | |
1180 | ||
0122f472 GH |
1181 | if (q->tbytes && q->pid == USB_TOKEN_IN) { |
1182 | if (ehci_buffer_rw(q, q->usb_status, 1) != 0) { | |
1183 | q->usb_status = USB_RET_PROCERR; | |
1184 | return; | |
94527ead | 1185 | } |
0122f472 | 1186 | q->tbytes -= q->usb_status; |
94527ead | 1187 | } else { |
0122f472 | 1188 | q->tbytes = 0; |
94527ead GH |
1189 | } |
1190 | ||
0122f472 GH |
1191 | DPRINTF("updating tbytes to %d\n", q->tbytes); |
1192 | set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES); | |
94527ead GH |
1193 | } |
1194 | ||
0122f472 GH |
1195 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1196 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1197 | |
0122f472 GH |
1198 | if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) { |
1199 | ehci_record_interrupt(q->ehci, USBSTS_INT); | |
94527ead | 1200 | } |
94527ead GH |
1201 | } |
1202 | ||
1203 | // 4.10.3 | |
1204 | ||
0122f472 | 1205 | static int ehci_execute(EHCIQueue *q) |
94527ead GH |
1206 | { |
1207 | USBPort *port; | |
1208 | USBDevice *dev; | |
1209 | int ret; | |
1210 | int i; | |
1211 | int endp; | |
1212 | int devadr; | |
1213 | ||
0122f472 | 1214 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { |
94527ead GH |
1215 | fprintf(stderr, "Attempting to execute inactive QH\n"); |
1216 | return USB_RET_PROCERR; | |
1217 | } | |
1218 | ||
0122f472 GH |
1219 | q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1220 | if (q->tbytes > BUFF_SIZE) { | |
94527ead GH |
1221 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1222 | return USB_RET_PROCERR; | |
1223 | } | |
1224 | ||
0122f472 GH |
1225 | q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1226 | switch(q->pid) { | |
1227 | case 0: q->pid = USB_TOKEN_OUT; break; | |
1228 | case 1: q->pid = USB_TOKEN_IN; break; | |
1229 | case 2: q->pid = USB_TOKEN_SETUP; break; | |
94527ead GH |
1230 | default: fprintf(stderr, "bad token\n"); break; |
1231 | } | |
1232 | ||
0122f472 GH |
1233 | if ((q->tbytes && q->pid != USB_TOKEN_IN) && |
1234 | (ehci_buffer_rw(q, q->tbytes, 0) != 0)) { | |
94527ead GH |
1235 | return USB_RET_PROCERR; |
1236 | } | |
1237 | ||
0122f472 GH |
1238 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); |
1239 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
94527ead GH |
1240 | |
1241 | ret = USB_RET_NODEV; | |
1242 | ||
1243 | // TO-DO: associating device with ehci port | |
1244 | for(i = 0; i < NB_PORTS; i++) { | |
0122f472 | 1245 | port = &q->ehci->ports[i]; |
94527ead GH |
1246 | dev = port->dev; |
1247 | ||
1248 | // TODO sometime we will also need to check if we are the port owner | |
1249 | ||
0122f472 | 1250 | if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) { |
94527ead | 1251 | DPRINTF("Port %d, no exec, not connected(%08X)\n", |
0122f472 | 1252 | i, q->ehci->portsc[i]); |
94527ead GH |
1253 | continue; |
1254 | } | |
1255 | ||
0122f472 GH |
1256 | q->packet.pid = q->pid; |
1257 | q->packet.devaddr = devadr; | |
1258 | q->packet.devep = endp; | |
1259 | q->packet.data = q->buffer; | |
1260 | q->packet.len = q->tbytes; | |
94527ead | 1261 | |
0122f472 | 1262 | ret = usb_handle_packet(dev, &q->packet); |
94527ead GH |
1263 | |
1264 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n", | |
0122f472 GH |
1265 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, |
1266 | q->packet.len, q->tbytes, endp, ret); | |
94527ead GH |
1267 | |
1268 | if (ret != USB_RET_NODEV) { | |
1269 | break; | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | if (ret > BUFF_SIZE) { | |
1274 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1275 | return USB_RET_PROCERR; | |
1276 | } | |
1277 | ||
94527ead GH |
1278 | return ret; |
1279 | } | |
1280 | ||
1281 | /* 4.7.2 | |
1282 | */ | |
1283 | ||
1284 | static int ehci_process_itd(EHCIState *ehci, | |
1285 | EHCIitd *itd) | |
1286 | { | |
1287 | USBPort *port; | |
1288 | USBDevice *dev; | |
1289 | int ret; | |
e654887f GH |
1290 | uint32_t i, j, len, len1, len2, pid, dir, devaddr, endp; |
1291 | uint32_t pg, off, ptr1, ptr2, max, mult; | |
94527ead GH |
1292 | |
1293 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1294 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1295 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1296 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1297 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1298 | |
1299 | for(i = 0; i < 8; i++) { | |
1300 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1301 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1302 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1303 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1304 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1305 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1306 | ||
1307 | if (len > max * mult) { | |
1308 | len = max * mult; | |
1309 | } | |
94527ead GH |
1310 | |
1311 | if (len > BUFF_SIZE) { | |
1312 | return USB_RET_PROCERR; | |
1313 | } | |
1314 | ||
e654887f GH |
1315 | if (off + len > 4096) { |
1316 | /* transfer crosses page border */ | |
1317 | len2 = off + len - 4096; | |
1318 | len1 = len - len2; | |
1319 | } else { | |
1320 | len1 = len; | |
1321 | len2 = 0; | |
1322 | } | |
94527ead GH |
1323 | |
1324 | if (!dir) { | |
94527ead | 1325 | pid = USB_TOKEN_OUT; |
e654887f GH |
1326 | trace_usb_ehci_data(0, pg, off, ptr1 + off, len1, 0); |
1327 | cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 0); | |
1328 | if (len2) { | |
1329 | trace_usb_ehci_data(0, pg+1, 0, ptr2, len2, len1); | |
1330 | cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 0); | |
1331 | } | |
1332 | } else { | |
94527ead | 1333 | pid = USB_TOKEN_IN; |
e654887f | 1334 | } |
94527ead GH |
1335 | |
1336 | ret = USB_RET_NODEV; | |
1337 | ||
1338 | for (j = 0; j < NB_PORTS; j++) { | |
1339 | port = &ehci->ports[j]; | |
1340 | dev = port->dev; | |
1341 | ||
1342 | // TODO sometime we will also need to check if we are the port owner | |
1343 | ||
1344 | if (!(ehci->portsc[j] &(PORTSC_CONNECT))) { | |
94527ead GH |
1345 | continue; |
1346 | } | |
1347 | ||
0122f472 | 1348 | ehci->ipacket.pid = pid; |
e654887f | 1349 | ehci->ipacket.devaddr = devaddr; |
0122f472 GH |
1350 | ehci->ipacket.devep = endp; |
1351 | ehci->ipacket.data = ehci->ibuffer; | |
1352 | ehci->ipacket.len = len; | |
94527ead | 1353 | |
0122f472 | 1354 | ret = usb_handle_packet(dev, &ehci->ipacket); |
94527ead GH |
1355 | |
1356 | if (ret != USB_RET_NODEV) { | |
1357 | break; | |
1358 | } | |
1359 | } | |
1360 | ||
e654887f | 1361 | #if 0 |
94527ead GH |
1362 | /* In isoch, there is no facility to indicate a NAK so let's |
1363 | * instead just complete a zero-byte transaction. Setting | |
1364 | * DBERR seems too draconian. | |
1365 | */ | |
1366 | ||
1367 | if (ret == USB_RET_NAK) { | |
1368 | if (ehci->isoch_pause > 0) { | |
1369 | DPRINTF("ISOCH: received a NAK but paused so returning\n"); | |
1370 | ehci->isoch_pause--; | |
1371 | return 0; | |
1372 | } else if (ehci->isoch_pause == -1) { | |
1373 | DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n"); | |
1374 | // Pause frindex for up to 50 msec waiting for data from | |
1375 | // remote | |
1376 | ehci->isoch_pause = 50; | |
1377 | return 0; | |
1378 | } else { | |
1379 | DPRINTF("ISOCH: isoch pause timeout! return 0\n"); | |
1380 | ret = 0; | |
1381 | } | |
1382 | } else { | |
1383 | DPRINTF("ISOCH: received ACK, clearing pause\n"); | |
1384 | ehci->isoch_pause = -1; | |
1385 | } | |
e654887f GH |
1386 | #else |
1387 | if (ret == USB_RET_NAK) { | |
1388 | ret = 0; | |
1389 | } | |
1390 | #endif | |
94527ead GH |
1391 | |
1392 | if (ret >= 0) { | |
e654887f GH |
1393 | if (!dir) { |
1394 | /* OUT */ | |
1395 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1396 | } else { | |
1397 | /* IN */ | |
1398 | if (len1 > ret) { | |
1399 | len1 = ret; | |
1400 | } | |
1401 | if (len2 > ret - len1) { | |
1402 | len2 = ret - len1; | |
1403 | } | |
1404 | if (len1) { | |
1405 | trace_usb_ehci_data(1, pg, off, ptr1 + off, len1, 0); | |
1406 | cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 1); | |
1407 | } | |
1408 | if (len2) { | |
1409 | trace_usb_ehci_data(1, pg+1, 0, ptr2, len2, len1); | |
1410 | cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 1); | |
1411 | } | |
1412 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
1413 | } | |
94527ead GH |
1414 | |
1415 | if (itd->transact[i] & ITD_XACT_IOC) { | |
1416 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1417 | } | |
1418 | } | |
e654887f | 1419 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1420 | } |
1421 | } | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | /* This state is the entry point for asynchronous schedule | |
1426 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1427 | */ | |
26d53979 | 1428 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1429 | { |
0122f472 | 1430 | EHCIqh qh; |
94527ead GH |
1431 | int i = 0; |
1432 | int again = 0; | |
1433 | uint32_t entry = ehci->asynclistaddr; | |
1434 | ||
1435 | /* set reclamation flag at start event (4.8.6) */ | |
1436 | if (async) { | |
439a97cc | 1437 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1438 | } |
1439 | ||
8ac6d699 GH |
1440 | ehci_queues_rip_unused(ehci); |
1441 | ||
94527ead GH |
1442 | /* Find the head of the list (4.9.1.1) */ |
1443 | for(i = 0; i < MAX_QH; i++) { | |
0122f472 | 1444 | get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2); |
8ac6d699 | 1445 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1446 | |
0122f472 | 1447 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1448 | if (async) { |
1449 | entry |= (NLPTR_TYPE_QH << 1); | |
1450 | } | |
1451 | ||
0122f472 | 1452 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1453 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1454 | again = 1; |
1455 | goto out; | |
1456 | } | |
1457 | ||
0122f472 | 1458 | entry = qh.next; |
94527ead | 1459 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1460 | break; |
1461 | } | |
1462 | } | |
1463 | ||
1464 | /* no head found for list. */ | |
1465 | ||
26d53979 | 1466 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1467 | |
1468 | out: | |
1469 | return again; | |
1470 | } | |
1471 | ||
1472 | ||
1473 | /* This state is the entry point for periodic schedule processing as | |
1474 | * well as being a continuation state for async processing. | |
1475 | */ | |
26d53979 | 1476 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1477 | { |
1478 | int again = 0; | |
0122f472 | 1479 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1480 | |
94527ead GH |
1481 | if (entry < 0x1000) { |
1482 | DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry); | |
26d53979 | 1483 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1484 | goto out; |
1485 | } | |
1486 | ||
1487 | /* section 4.8, only QH in async schedule */ | |
1488 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1489 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1490 | return -1; | |
1491 | } | |
1492 | ||
1493 | switch (NLPTR_TYPE_GET(entry)) { | |
1494 | case NLPTR_TYPE_QH: | |
26d53979 | 1495 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1496 | again = 1; |
1497 | break; | |
1498 | ||
1499 | case NLPTR_TYPE_ITD: | |
26d53979 | 1500 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1501 | again = 1; |
1502 | break; | |
1503 | ||
1504 | default: | |
1505 | // TODO: handle siTD and FSTN types | |
1506 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " | |
1507 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1508 | return -1; | |
1509 | } | |
1510 | ||
1511 | out: | |
1512 | return again; | |
1513 | } | |
1514 | ||
0122f472 | 1515 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1516 | { |
0122f472 GH |
1517 | uint32_t entry; |
1518 | EHCIQueue *q; | |
94527ead | 1519 | int reload; |
94527ead | 1520 | |
0122f472 | 1521 | entry = ehci_get_fetch_addr(ehci, async); |
8ac6d699 GH |
1522 | q = ehci_find_queue_by_qh(ehci, entry); |
1523 | if (NULL == q) { | |
1524 | q = ehci_alloc_queue(ehci, async); | |
1525 | } | |
0122f472 | 1526 | q->qhaddr = entry; |
8ac6d699 GH |
1527 | q->seen++; |
1528 | ||
1529 | if (q->seen > 1) { | |
1530 | /* we are going in circles -- stop processing */ | |
1531 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1532 | q = NULL; | |
1533 | goto out; | |
1534 | } | |
94527ead | 1535 | |
0122f472 | 1536 | get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); |
8ac6d699 GH |
1537 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1538 | ||
1539 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
1540 | /* I/O still in progress -- skip queue */ | |
1541 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1542 | goto out; | |
1543 | } | |
1544 | if (q->async == EHCI_ASYNC_FINISHED) { | |
1545 | /* I/O finished -- continue processing queue */ | |
1546 | trace_usb_ehci_queue_action(q, "resume"); | |
1547 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1548 | goto out; | |
1549 | } | |
0122f472 GH |
1550 | |
1551 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1552 | |
1553 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1554 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1555 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1556 | } else { |
1557 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1558 | " - done processing\n", q->qhaddr); |
26d53979 | 1559 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1560 | q = NULL; |
94527ead GH |
1561 | goto out; |
1562 | } | |
1563 | } | |
1564 | ||
1565 | #if EHCI_DEBUG | |
0122f472 | 1566 | if (q->qhaddr != q->qh.next) { |
94527ead | 1567 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1568 | q->qhaddr, |
1569 | q->qh.epchar & QH_EPCHAR_H, | |
1570 | q->qh.token & QTD_TOKEN_HALT, | |
1571 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1572 | q->qh.next); | |
94527ead GH |
1573 | } |
1574 | #endif | |
1575 | ||
0122f472 | 1576 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1577 | if (reload) { |
0122f472 | 1578 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1579 | } |
1580 | ||
0122f472 | 1581 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1582 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1583 | |
0122f472 GH |
1584 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) { |
1585 | q->qtdaddr = q->qh.current_qtd; | |
26d53979 | 1586 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1587 | |
1588 | } else { | |
1589 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1590 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1591 | } |
1592 | ||
1593 | out: | |
0122f472 | 1594 | return q; |
94527ead GH |
1595 | } |
1596 | ||
26d53979 | 1597 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1598 | { |
0122f472 | 1599 | uint32_t entry; |
94527ead GH |
1600 | EHCIitd itd; |
1601 | ||
0122f472 GH |
1602 | assert(!async); |
1603 | entry = ehci_get_fetch_addr(ehci, async); | |
1604 | ||
1605 | get_dwords(NLPTR_GET(entry),(uint32_t *) &itd, | |
94527ead | 1606 | sizeof(EHCIitd) >> 2); |
0122f472 | 1607 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1608 | |
1609 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1610 | return -1; | |
1611 | } | |
1612 | ||
0122f472 | 1613 | put_dwords(NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1614 | sizeof(EHCIitd) >> 2); |
0122f472 | 1615 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1616 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1617 | |
1618 | return 1; | |
1619 | } | |
1620 | ||
1621 | /* Section 4.10.2 - paragraph 3 */ | |
0122f472 | 1622 | static int ehci_state_advqueue(EHCIQueue *q, int async) |
94527ead GH |
1623 | { |
1624 | #if 0 | |
1625 | /* TO-DO: 4.10.2 - paragraph 2 | |
1626 | * if I-bit is set to 1 and QH is not active | |
1627 | * go to horizontal QH | |
1628 | */ | |
1629 | if (I-bit set) { | |
26d53979 | 1630 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1631 | goto out; |
1632 | } | |
1633 | #endif | |
1634 | ||
1635 | /* | |
1636 | * want data and alt-next qTD is valid | |
1637 | */ | |
0122f472 GH |
1638 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1639 | (q->qh.altnext_qtd > 0x1000) && | |
1640 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { | |
1641 | q->qtdaddr = q->qh.altnext_qtd; | |
1642 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1643 | |
1644 | /* | |
1645 | * next qTD is valid | |
1646 | */ | |
0122f472 GH |
1647 | } else if ((q->qh.next_qtd > 0x1000) && |
1648 | (NLPTR_TBIT(q->qh.next_qtd) == 0)) { | |
1649 | q->qtdaddr = q->qh.next_qtd; | |
1650 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1651 | |
1652 | /* | |
1653 | * no valid qTD, try next QH | |
1654 | */ | |
1655 | } else { | |
0122f472 | 1656 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1657 | } |
1658 | ||
1659 | return 1; | |
1660 | } | |
1661 | ||
1662 | /* Section 4.10.2 - paragraph 4 */ | |
0122f472 | 1663 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) |
94527ead | 1664 | { |
94527ead GH |
1665 | int again = 0; |
1666 | ||
0122f472 | 1667 | get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2); |
8ac6d699 | 1668 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd); |
94527ead | 1669 | |
0122f472 GH |
1670 | if (q->qtd.token & QTD_TOKEN_ACTIVE) { |
1671 | ehci_set_state(q->ehci, async, EST_EXECUTE); | |
94527ead GH |
1672 | again = 1; |
1673 | } else { | |
0122f472 | 1674 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1675 | again = 1; |
1676 | } | |
1677 | ||
1678 | return again; | |
1679 | } | |
1680 | ||
0122f472 | 1681 | static int ehci_state_horizqh(EHCIQueue *q, int async) |
94527ead GH |
1682 | { |
1683 | int again = 0; | |
1684 | ||
0122f472 GH |
1685 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { |
1686 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1687 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
94527ead GH |
1688 | again = 1; |
1689 | } else { | |
0122f472 | 1690 | ehci_set_state(q->ehci, async, EST_ACTIVE); |
94527ead GH |
1691 | } |
1692 | ||
1693 | return again; | |
1694 | } | |
1695 | ||
8ac6d699 GH |
1696 | /* |
1697 | * Write the qh back to guest physical memory. This step isn't | |
1698 | * in the EHCI spec but we need to do it since we don't share | |
1699 | * physical memory with our guest VM. | |
1700 | * | |
1701 | * The first three dwords are read-only for the EHCI, so skip them | |
1702 | * when writing back the qh. | |
1703 | */ | |
1704 | static void ehci_flush_qh(EHCIQueue *q) | |
1705 | { | |
1706 | uint32_t *qh = (uint32_t *) &q->qh; | |
1707 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1708 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1709 | ||
1710 | put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); | |
1711 | } | |
1712 | ||
0122f472 | 1713 | static int ehci_state_execute(EHCIQueue *q, int async) |
94527ead | 1714 | { |
94527ead GH |
1715 | int again = 0; |
1716 | int reload, nakcnt; | |
1717 | int smask; | |
1718 | ||
0122f472 | 1719 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1720 | return -1; |
1721 | } | |
1722 | ||
0122f472 | 1723 | smask = get_field(q->qh.epcap, QH_EPCAP_SMASK); |
94527ead GH |
1724 | |
1725 | if (!smask) { | |
0122f472 GH |
1726 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1727 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1728 | if (reload && !nakcnt) { |
0122f472 | 1729 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1730 | again = 1; |
1731 | goto out; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | // TODO verify enough time remains in the uframe as in 4.4.1.1 | |
1736 | // TODO write back ptr to async list when done or out of time | |
1737 | // TODO Windows does not seem to ever set the MULT field | |
1738 | ||
1739 | if (!async) { | |
0122f472 | 1740 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1741 | if (!transactCtr) { |
0122f472 | 1742 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1743 | again = 1; |
1744 | goto out; | |
1745 | } | |
1746 | } | |
1747 | ||
1748 | if (async) { | |
0122f472 | 1749 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1750 | } |
1751 | ||
0122f472 GH |
1752 | q->usb_status = ehci_execute(q); |
1753 | if (q->usb_status == USB_RET_PROCERR) { | |
94527ead GH |
1754 | again = -1; |
1755 | goto out; | |
1756 | } | |
8ac6d699 GH |
1757 | if (q->usb_status == USB_RET_ASYNC) { |
1758 | ehci_flush_qh(q); | |
1759 | trace_usb_ehci_queue_action(q, "suspend"); | |
1760 | q->async = EHCI_ASYNC_INFLIGHT; | |
1761 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1762 | again = 1; |
8ac6d699 | 1763 | goto out; |
94527ead GH |
1764 | } |
1765 | ||
8ac6d699 GH |
1766 | ehci_set_state(q->ehci, async, EST_EXECUTING); |
1767 | again = 1; | |
1768 | ||
94527ead GH |
1769 | out: |
1770 | return again; | |
1771 | } | |
1772 | ||
0122f472 | 1773 | static int ehci_state_executing(EHCIQueue *q, int async) |
94527ead | 1774 | { |
94527ead GH |
1775 | int again = 0; |
1776 | int reload, nakcnt; | |
1777 | ||
0122f472 GH |
1778 | ehci_execute_complete(q); |
1779 | if (q->usb_status == USB_RET_ASYNC) { | |
94527ead GH |
1780 | goto out; |
1781 | } | |
0122f472 | 1782 | if (q->usb_status == USB_RET_PROCERR) { |
94527ead GH |
1783 | again = -1; |
1784 | goto out; | |
1785 | } | |
1786 | ||
1787 | // 4.10.3 | |
1788 | if (!async) { | |
0122f472 | 1789 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1790 | transactCtr--; |
0122f472 | 1791 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
1792 | // 4.10.3, bottom of page 82, should exit this state when transaction |
1793 | // counter decrements to 0 | |
1794 | } | |
1795 | ||
0122f472 | 1796 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1797 | if (reload) { |
0122f472 GH |
1798 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); |
1799 | if (q->usb_status == USB_RET_NAK) { | |
94527ead GH |
1800 | if (nakcnt) { |
1801 | nakcnt--; | |
1802 | } | |
94527ead GH |
1803 | } else { |
1804 | nakcnt = reload; | |
94527ead | 1805 | } |
0122f472 | 1806 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1807 | } |
1808 | ||
94527ead | 1809 | /* 4.10.5 */ |
0122f472 GH |
1810 | if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) { |
1811 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1812 | } else { |
0122f472 | 1813 | ehci_set_state(q->ehci, async, EST_WRITEBACK); |
94527ead GH |
1814 | } |
1815 | ||
1816 | again = 1; | |
1817 | ||
1818 | out: | |
8ac6d699 | 1819 | ehci_flush_qh(q); |
94527ead GH |
1820 | return again; |
1821 | } | |
1822 | ||
1823 | ||
0122f472 | 1824 | static int ehci_state_writeback(EHCIQueue *q, int async) |
94527ead | 1825 | { |
94527ead GH |
1826 | int again = 0; |
1827 | ||
1828 | /* Write back the QTD from the QH area */ | |
8ac6d699 | 1829 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd); |
0122f472 | 1830 | put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd, |
94527ead GH |
1831 | sizeof(EHCIqtd) >> 2); |
1832 | ||
d2bd525f GH |
1833 | /* |
1834 | * EHCI specs say go horizontal here. | |
1835 | * | |
1836 | * We can also advance the queue here for performance reasons. We | |
1837 | * need to take care to only take that shortcut in case we've | |
1838 | * processed the qtd just written back without errors, i.e. halt | |
1839 | * bit is clear. | |
94527ead | 1840 | */ |
d2bd525f GH |
1841 | if (q->qh.token & QTD_TOKEN_HALT) { |
1842 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1843 | again = 1; | |
1844 | } else { | |
0122f472 | 1845 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); |
94527ead | 1846 | again = 1; |
d2bd525f | 1847 | } |
94527ead GH |
1848 | return again; |
1849 | } | |
1850 | ||
1851 | /* | |
1852 | * This is the state machine that is common to both async and periodic | |
1853 | */ | |
1854 | ||
26d53979 GH |
1855 | static void ehci_advance_state(EHCIState *ehci, |
1856 | int async) | |
94527ead | 1857 | { |
0122f472 | 1858 | EHCIQueue *q = NULL; |
94527ead GH |
1859 | int again; |
1860 | int iter = 0; | |
1861 | ||
1862 | do { | |
26d53979 | 1863 | if (ehci_get_state(ehci, async) == EST_FETCHQH) { |
94527ead GH |
1864 | iter++; |
1865 | /* if we are roaming a lot of QH without executing a qTD | |
1866 | * something is wrong with the linked list. TO-DO: why is | |
1867 | * this hack needed? | |
1868 | */ | |
8ac6d699 GH |
1869 | assert(iter < MAX_ITERATIONS); |
1870 | #if 0 | |
94527ead GH |
1871 | if (iter > MAX_ITERATIONS) { |
1872 | DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n"); | |
26d53979 | 1873 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1874 | break; |
1875 | } | |
8ac6d699 | 1876 | #endif |
94527ead | 1877 | } |
26d53979 | 1878 | switch(ehci_get_state(ehci, async)) { |
94527ead | 1879 | case EST_WAITLISTHEAD: |
26d53979 | 1880 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
1881 | break; |
1882 | ||
1883 | case EST_FETCHENTRY: | |
26d53979 | 1884 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
1885 | break; |
1886 | ||
1887 | case EST_FETCHQH: | |
0122f472 GH |
1888 | q = ehci_state_fetchqh(ehci, async); |
1889 | again = q ? 1 : 0; | |
94527ead GH |
1890 | break; |
1891 | ||
1892 | case EST_FETCHITD: | |
26d53979 | 1893 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
1894 | break; |
1895 | ||
1896 | case EST_ADVANCEQUEUE: | |
0122f472 | 1897 | again = ehci_state_advqueue(q, async); |
94527ead GH |
1898 | break; |
1899 | ||
1900 | case EST_FETCHQTD: | |
0122f472 | 1901 | again = ehci_state_fetchqtd(q, async); |
94527ead GH |
1902 | break; |
1903 | ||
1904 | case EST_HORIZONTALQH: | |
0122f472 | 1905 | again = ehci_state_horizqh(q, async); |
94527ead GH |
1906 | break; |
1907 | ||
1908 | case EST_EXECUTE: | |
1909 | iter = 0; | |
0122f472 | 1910 | again = ehci_state_execute(q, async); |
94527ead GH |
1911 | break; |
1912 | ||
1913 | case EST_EXECUTING: | |
8ac6d699 | 1914 | assert(q != NULL); |
0122f472 | 1915 | again = ehci_state_executing(q, async); |
94527ead GH |
1916 | break; |
1917 | ||
1918 | case EST_WRITEBACK: | |
0122f472 | 1919 | again = ehci_state_writeback(q, async); |
94527ead GH |
1920 | break; |
1921 | ||
1922 | default: | |
1923 | fprintf(stderr, "Bad state!\n"); | |
1924 | again = -1; | |
8ac6d699 | 1925 | assert(0); |
94527ead GH |
1926 | break; |
1927 | } | |
1928 | ||
1929 | if (again < 0) { | |
1930 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
1931 | ehci_reset(ehci); | |
1932 | again = 0; | |
8ac6d699 | 1933 | assert(0); |
94527ead GH |
1934 | } |
1935 | } | |
1936 | while (again); | |
1937 | ||
1938 | ehci_commit_interrupt(ehci); | |
94527ead GH |
1939 | } |
1940 | ||
1941 | static void ehci_advance_async_state(EHCIState *ehci) | |
1942 | { | |
26d53979 | 1943 | int async = 1; |
94527ead | 1944 | |
26d53979 | 1945 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
1946 | case EST_INACTIVE: |
1947 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
1948 | break; | |
1949 | } | |
439a97cc | 1950 | ehci_set_usbsts(ehci, USBSTS_ASS); |
26d53979 | 1951 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1952 | // No break, fall through to ACTIVE |
1953 | ||
1954 | case EST_ACTIVE: | |
1955 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
439a97cc | 1956 | ehci_clear_usbsts(ehci, USBSTS_ASS); |
26d53979 | 1957 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
1958 | break; |
1959 | } | |
1960 | ||
1961 | /* If the doorbell is set, the guest wants to make a change to the | |
1962 | * schedule. The host controller needs to release cached data. | |
1963 | * (section 4.8.2) | |
1964 | */ | |
1965 | if (ehci->usbcmd & USBCMD_IAAD) { | |
1966 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
1967 | ehci->usbcmd &= ~USBCMD_IAAD; | |
1968 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
1969 | break; | |
1970 | } | |
1971 | ||
1972 | /* make sure guest has acknowledged */ | |
1973 | /* TO-DO: is this really needed? */ | |
1974 | if (ehci->usbsts & USBSTS_IAA) { | |
1975 | DPRINTF("IAA status bit still set.\n"); | |
1976 | break; | |
1977 | } | |
1978 | ||
94527ead GH |
1979 | /* check that address register has been set */ |
1980 | if (ehci->asynclistaddr == 0) { | |
1981 | break; | |
1982 | } | |
1983 | ||
26d53979 | 1984 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 1985 | ehci_advance_state(ehci, async); |
94527ead GH |
1986 | break; |
1987 | ||
1988 | default: | |
1989 | /* this should only be due to a developer mistake */ | |
1990 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
1991 | "Resetting to active\n", ehci->astate); | |
0122f472 | 1992 | assert(0); |
94527ead GH |
1993 | } |
1994 | } | |
1995 | ||
1996 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
1997 | { | |
1998 | uint32_t entry; | |
1999 | uint32_t list; | |
26d53979 | 2000 | int async = 0; |
94527ead GH |
2001 | |
2002 | // 4.6 | |
2003 | ||
26d53979 | 2004 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2005 | case EST_INACTIVE: |
2006 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2007 | ehci_set_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2008 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2009 | // No break, fall through to ACTIVE |
2010 | } else | |
2011 | break; | |
2012 | ||
2013 | case EST_ACTIVE: | |
2014 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2015 | ehci_clear_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2016 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2017 | break; |
2018 | } | |
2019 | ||
2020 | list = ehci->periodiclistbase & 0xfffff000; | |
2021 | /* check that register has been set */ | |
2022 | if (list == 0) { | |
2023 | break; | |
2024 | } | |
2025 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2026 | ||
2027 | cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0); | |
2028 | entry = le32_to_cpu(entry); | |
2029 | ||
2030 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2031 | ehci->frindex / 8, list, entry); | |
0122f472 | 2032 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2033 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2034 | ehci_advance_state(ehci, async); | |
94527ead GH |
2035 | break; |
2036 | ||
94527ead GH |
2037 | default: |
2038 | /* this should only be due to a developer mistake */ | |
2039 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2040 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2041 | assert(0); |
94527ead GH |
2042 | } |
2043 | } | |
2044 | ||
2045 | static void ehci_frame_timer(void *opaque) | |
2046 | { | |
2047 | EHCIState *ehci = opaque; | |
2048 | int64_t expire_time, t_now; | |
adddecb1 | 2049 | uint64_t ns_elapsed; |
94527ead | 2050 | int frames; |
94527ead GH |
2051 | int i; |
2052 | int skipped_frames = 0; | |
2053 | ||
94527ead | 2054 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2055 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2056 | |
adddecb1 GH |
2057 | ns_elapsed = t_now - ehci->last_run_ns; |
2058 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2059 | |
2060 | for (i = 0; i < frames; i++) { | |
2061 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
2062 | if (ehci->isoch_pause <= 0) { | |
2063 | ehci->frindex += 8; | |
2064 | } | |
2065 | ||
2066 | if (ehci->frindex > 0x00001fff) { | |
2067 | ehci->frindex = 0; | |
2068 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2069 | } | |
2070 | ||
2071 | ehci->sofv = (ehci->frindex - 1) >> 3; | |
2072 | ehci->sofv &= 0x000003ff; | |
2073 | } | |
2074 | ||
16a2dee6 | 2075 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2076 | skipped_frames++; |
2077 | } else { | |
d0539307 | 2078 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2079 | } |
2080 | ||
adddecb1 | 2081 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2082 | } |
2083 | ||
2084 | #if 0 | |
2085 | if (skipped_frames) { | |
2086 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2087 | } | |
2088 | #endif | |
2089 | ||
2090 | /* Async is not inside loop since it executes everything it can once | |
2091 | * called | |
2092 | */ | |
d0539307 | 2093 | ehci_advance_async_state(ehci); |
94527ead GH |
2094 | |
2095 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2096 | } | |
2097 | ||
2098 | static CPUReadMemoryFunc *ehci_readfn[3]={ | |
2099 | ehci_mem_readb, | |
2100 | ehci_mem_readw, | |
2101 | ehci_mem_readl | |
2102 | }; | |
2103 | ||
2104 | static CPUWriteMemoryFunc *ehci_writefn[3]={ | |
2105 | ehci_mem_writeb, | |
2106 | ehci_mem_writew, | |
2107 | ehci_mem_writel | |
2108 | }; | |
2109 | ||
2110 | static void ehci_map(PCIDevice *pci_dev, int region_num, | |
2111 | pcibus_t addr, pcibus_t size, int type) | |
2112 | { | |
2113 | EHCIState *s =(EHCIState *)pci_dev; | |
2114 | ||
2115 | DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n", | |
2116 | region_num, addr, size, s->mem); | |
2117 | s->mem_base = addr; | |
2118 | cpu_register_physical_memory(addr, size, s->mem); | |
2119 | } | |
2120 | ||
2121 | static int usb_ehci_initfn(PCIDevice *dev); | |
2122 | ||
2123 | static USBPortOps ehci_port_ops = { | |
2124 | .attach = ehci_attach, | |
2125 | .detach = ehci_detach, | |
4706ab6c | 2126 | .child_detach = ehci_child_detach, |
94527ead GH |
2127 | .complete = ehci_async_complete_packet, |
2128 | }; | |
2129 | ||
07771f6f | 2130 | static USBBusOps ehci_bus_ops = { |
07771f6f GH |
2131 | }; |
2132 | ||
94527ead GH |
2133 | static PCIDeviceInfo ehci_info = { |
2134 | .qdev.name = "usb-ehci", | |
2135 | .qdev.size = sizeof(EHCIState), | |
2136 | .init = usb_ehci_initfn, | |
9047c0b4 MT |
2137 | .vendor_id = PCI_VENDOR_ID_INTEL, |
2138 | .device_id = PCI_DEVICE_ID_INTEL_82801D, | |
2139 | .revision = 0x10, | |
2140 | .class_id = PCI_CLASS_SERIAL_USB, | |
16a2dee6 GH |
2141 | .qdev.props = (Property[]) { |
2142 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2143 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2144 | DEFINE_PROP_END_OF_LIST(), | |
2145 | }, | |
94527ead GH |
2146 | }; |
2147 | ||
2148 | static int usb_ehci_initfn(PCIDevice *dev) | |
2149 | { | |
2150 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2151 | uint8_t *pci_conf = s->dev.config; | |
2152 | int i; | |
2153 | ||
94527ead | 2154 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2155 | |
2156 | /* capabilities pointer */ | |
2157 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2158 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2159 | ||
2160 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3 | |
2161 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); | |
2162 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2163 | ||
2164 | // pci_conf[0x50] = 0x01; // power management caps | |
2165 | ||
4001f22f | 2166 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2167 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2168 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2169 | ||
2170 | pci_conf[0x64] = 0x00; | |
2171 | pci_conf[0x65] = 0x00; | |
2172 | pci_conf[0x66] = 0x00; | |
2173 | pci_conf[0x67] = 0x00; | |
2174 | pci_conf[0x68] = 0x01; | |
2175 | pci_conf[0x69] = 0x00; | |
2176 | pci_conf[0x6a] = 0x00; | |
2177 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2178 | pci_conf[0x6c] = 0x00; | |
2179 | pci_conf[0x6d] = 0x00; | |
2180 | pci_conf[0x6e] = 0x00; | |
2181 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2182 | ||
2183 | // 2.2 host controller interface version | |
2184 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2185 | s->mmio[0x01] = 0x00; | |
2186 | s->mmio[0x02] = 0x00; | |
2187 | s->mmio[0x03] = 0x01; // HC version | |
2188 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2189 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2190 | s->mmio[0x06] = 0x00; | |
2191 | s->mmio[0x07] = 0x00; | |
2192 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2193 | s->mmio[0x09] = 0x68; // EECP | |
2194 | s->mmio[0x0a] = 0x00; | |
2195 | s->mmio[0x0b] = 0x00; | |
2196 | ||
2197 | s->irq = s->dev.irq[3]; | |
2198 | ||
07771f6f | 2199 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2200 | for(i = 0; i < NB_PORTS; i++) { |
2201 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2202 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2203 | s->ports[i].dev = 0; |
2204 | } | |
2205 | ||
2206 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
8ac6d699 | 2207 | QTAILQ_INIT(&s->queues); |
94527ead GH |
2208 | |
2209 | qemu_register_reset(ehci_reset, s); | |
2210 | ||
2211 | s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s, | |
2212 | DEVICE_LITTLE_ENDIAN); | |
2213 | ||
2214 | pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2215 | ehci_map); | |
2216 | ||
2217 | fprintf(stderr, "*** EHCI support is under development ***\n"); | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | static void ehci_register(void) | |
2223 | { | |
2224 | pci_qdev_register(&ehci_info); | |
2225 | } | |
2226 | device_init(ehci_register); | |
2227 | ||
2228 | /* | |
2229 | * vim: expandtab ts=4 | |
2230 | */ |