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xhci: remote wakeup support
[mirror_qemu.git] / hw / usb-xhci.c
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62c6ae04
HM		 1/*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21#include "hw.h"
22#include "qemu-timer.h"
23#include "usb.h"
24#include "pci.h"
25#include "qdev-addr.h"
26#include "msi.h"
27
28//#define DEBUG_XHCI
29//#define DEBUG_DATA
30
31#ifdef DEBUG_XHCI
32#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33#else
34#define DPRINTF(...) do {} while (0)
35#endif
36#define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
38
39#define MAXSLOTS 8
40#define MAXINTRS 1
41
42#define USB2_PORTS 4
43#define USB3_PORTS 4
44
45#define MAXPORTS (USB2_PORTS+USB3_PORTS)
46
47#define TD_QUEUE 24
48#define BG_XFERS 8
49#define BG_PKTS 8
50
51/* Very pessimistic, let's hope it's enough for all cases */
52#define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
53/* Do not deliver ER Full events. NEC's driver does some things not bound
54 * to the specs when it gets them */
55#define ER_FULL_HACK
56
57#define LEN_CAP 0x40
58#define OFF_OPER LEN_CAP
59#define LEN_OPER (0x400 + 0x10 * MAXPORTS)
60#define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
61#define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
62#define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
63#define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
64
65/* must be power of 2 */
66#define LEN_REGS 0x2000
67
68#if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
69# error Increase LEN_REGS
70#endif
71
72#if MAXINTRS > 1
73# error TODO: only one interrupter supported
74#endif
75
76/* bit definitions */
77#define USBCMD_RS (1<<0)
78#define USBCMD_HCRST (1<<1)
79#define USBCMD_INTE (1<<2)
80#define USBCMD_HSEE (1<<3)
81#define USBCMD_LHCRST (1<<7)
82#define USBCMD_CSS (1<<8)
83#define USBCMD_CRS (1<<9)
84#define USBCMD_EWE (1<<10)
85#define USBCMD_EU3S (1<<11)
86
87#define USBSTS_HCH (1<<0)
88#define USBSTS_HSE (1<<2)
89#define USBSTS_EINT (1<<3)
90#define USBSTS_PCD (1<<4)
91#define USBSTS_SSS (1<<8)
92#define USBSTS_RSS (1<<9)
93#define USBSTS_SRE (1<<10)
94#define USBSTS_CNR (1<<11)
95#define USBSTS_HCE (1<<12)
96
97
98#define PORTSC_CCS (1<<0)
99#define PORTSC_PED (1<<1)
100#define PORTSC_OCA (1<<3)
101#define PORTSC_PR (1<<4)
102#define PORTSC_PLS_SHIFT 5
103#define PORTSC_PLS_MASK 0xf
104#define PORTSC_PP (1<<9)
105#define PORTSC_SPEED_SHIFT 10
106#define PORTSC_SPEED_MASK 0xf
107#define PORTSC_SPEED_FULL (1<<10)
108#define PORTSC_SPEED_LOW (2<<10)
109#define PORTSC_SPEED_HIGH (3<<10)
110#define PORTSC_SPEED_SUPER (4<<10)
111#define PORTSC_PIC_SHIFT 14
112#define PORTSC_PIC_MASK 0x3
113#define PORTSC_LWS (1<<16)
114#define PORTSC_CSC (1<<17)
115#define PORTSC_PEC (1<<18)
116#define PORTSC_WRC (1<<19)
117#define PORTSC_OCC (1<<20)
118#define PORTSC_PRC (1<<21)
119#define PORTSC_PLC (1<<22)
120#define PORTSC_CEC (1<<23)
121#define PORTSC_CAS (1<<24)
122#define PORTSC_WCE (1<<25)
123#define PORTSC_WDE (1<<26)
124#define PORTSC_WOE (1<<27)
125#define PORTSC_DR (1<<30)
126#define PORTSC_WPR (1<<31)
127
128#define CRCR_RCS (1<<0)
129#define CRCR_CS (1<<1)
130#define CRCR_CA (1<<2)
131#define CRCR_CRR (1<<3)
132
133#define IMAN_IP (1<<0)
134#define IMAN_IE (1<<1)
135
136#define ERDP_EHB (1<<3)
137
138#define TRB_SIZE 16
139typedef struct XHCITRB {
140 uint64_t parameter;
141 uint32_t status;
142 uint32_t control;
143 target_phys_addr_t addr;
144 bool ccs;
145} XHCITRB;
146
147
148typedef enum TRBType {
149 TRB_RESERVED = 0,
150 TR_NORMAL,
151 TR_SETUP,
152 TR_DATA,
153 TR_STATUS,
154 TR_ISOCH,
155 TR_LINK,
156 TR_EVDATA,
157 TR_NOOP,
158 CR_ENABLE_SLOT,
159 CR_DISABLE_SLOT,
160 CR_ADDRESS_DEVICE,
161 CR_CONFIGURE_ENDPOINT,
162 CR_EVALUATE_CONTEXT,
163 CR_RESET_ENDPOINT,
164 CR_STOP_ENDPOINT,
165 CR_SET_TR_DEQUEUE,
166 CR_RESET_DEVICE,
167 CR_FORCE_EVENT,
168 CR_NEGOTIATE_BW,
169 CR_SET_LATENCY_TOLERANCE,
170 CR_GET_PORT_BANDWIDTH,
171 CR_FORCE_HEADER,
172 CR_NOOP,
173 ER_TRANSFER = 32,
174 ER_COMMAND_COMPLETE,
175 ER_PORT_STATUS_CHANGE,
176 ER_BANDWIDTH_REQUEST,
177 ER_DOORBELL,
178 ER_HOST_CONTROLLER,
179 ER_DEVICE_NOTIFICATION,
180 ER_MFINDEX_WRAP,
181 /* vendor specific bits */
182 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
183 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
184 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
185} TRBType;
186
187#define CR_LINK TR_LINK
188
189typedef enum TRBCCode {
190 CC_INVALID = 0,
191 CC_SUCCESS,
192 CC_DATA_BUFFER_ERROR,
193 CC_BABBLE_DETECTED,
194 CC_USB_TRANSACTION_ERROR,
195 CC_TRB_ERROR,
196 CC_STALL_ERROR,
197 CC_RESOURCE_ERROR,
198 CC_BANDWIDTH_ERROR,
199 CC_NO_SLOTS_ERROR,
200 CC_INVALID_STREAM_TYPE_ERROR,
201 CC_SLOT_NOT_ENABLED_ERROR,
202 CC_EP_NOT_ENABLED_ERROR,
203 CC_SHORT_PACKET,
204 CC_RING_UNDERRUN,
205 CC_RING_OVERRUN,
206 CC_VF_ER_FULL,
207 CC_PARAMETER_ERROR,
208 CC_BANDWIDTH_OVERRUN,
209 CC_CONTEXT_STATE_ERROR,
210 CC_NO_PING_RESPONSE_ERROR,
211 CC_EVENT_RING_FULL_ERROR,
212 CC_INCOMPATIBLE_DEVICE_ERROR,
213 CC_MISSED_SERVICE_ERROR,
214 CC_COMMAND_RING_STOPPED,
215 CC_COMMAND_ABORTED,
216 CC_STOPPED,
217 CC_STOPPED_LENGTH_INVALID,
218 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
219 CC_ISOCH_BUFFER_OVERRUN = 31,
220 CC_EVENT_LOST_ERROR,
221 CC_UNDEFINED_ERROR,
222 CC_INVALID_STREAM_ID_ERROR,
223 CC_SECONDARY_BANDWIDTH_ERROR,
224 CC_SPLIT_TRANSACTION_ERROR
225} TRBCCode;
226
227#define TRB_C (1<<0)
228#define TRB_TYPE_SHIFT 10
229#define TRB_TYPE_MASK 0x3f
230#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
231
232#define TRB_EV_ED (1<<2)
233
234#define TRB_TR_ENT (1<<1)
235#define TRB_TR_ISP (1<<2)
236#define TRB_TR_NS (1<<3)
237#define TRB_TR_CH (1<<4)
238#define TRB_TR_IOC (1<<5)
239#define TRB_TR_IDT (1<<6)
240#define TRB_TR_TBC_SHIFT 7
241#define TRB_TR_TBC_MASK 0x3
242#define TRB_TR_BEI (1<<9)
243#define TRB_TR_TLBPC_SHIFT 16
244#define TRB_TR_TLBPC_MASK 0xf
245#define TRB_TR_FRAMEID_SHIFT 20
246#define TRB_TR_FRAMEID_MASK 0x7ff
247#define TRB_TR_SIA (1<<31)
248
249#define TRB_TR_DIR (1<<16)
250
251#define TRB_CR_SLOTID_SHIFT 24
252#define TRB_CR_SLOTID_MASK 0xff
253#define TRB_CR_EPID_SHIFT 16
254#define TRB_CR_EPID_MASK 0x1f
255
256#define TRB_CR_BSR (1<<9)
257#define TRB_CR_DC (1<<9)
258
259#define TRB_LK_TC (1<<1)
260
261#define EP_TYPE_MASK 0x7
262#define EP_TYPE_SHIFT 3
263
264#define EP_STATE_MASK 0x7
265#define EP_DISABLED (0<<0)
266#define EP_RUNNING (1<<0)
267#define EP_HALTED (2<<0)
268#define EP_STOPPED (3<<0)
269#define EP_ERROR (4<<0)
270
271#define SLOT_STATE_MASK 0x1f
272#define SLOT_STATE_SHIFT 27
273#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
274#define SLOT_ENABLED 0
275#define SLOT_DEFAULT 1
276#define SLOT_ADDRESSED 2
277#define SLOT_CONFIGURED 3
278
279#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
280#define SLOT_CONTEXT_ENTRIES_SHIFT 27
281
282typedef enum EPType {
283 ET_INVALID = 0,
284 ET_ISO_OUT,
285 ET_BULK_OUT,
286 ET_INTR_OUT,
287 ET_CONTROL,
288 ET_ISO_IN,
289 ET_BULK_IN,
290 ET_INTR_IN,
291} EPType;
292
293typedef struct XHCIRing {
294 target_phys_addr_t base;
295 target_phys_addr_t dequeue;
296 bool ccs;
297} XHCIRing;
298
299typedef struct XHCIPort {
300 USBPort port;
301 uint32_t portsc;
302} XHCIPort;
303
304struct XHCIState;
305typedef struct XHCIState XHCIState;
306
307typedef struct XHCITransfer {
308 XHCIState *xhci;
309 USBPacket packet;
310 bool running;
311 bool cancelled;
312 bool complete;
313 bool backgrounded;
314 unsigned int iso_pkts;
315 unsigned int slotid;
316 unsigned int epid;
317 bool in_xfer;
318 bool iso_xfer;
319 bool bg_xfer;
320
321 unsigned int trb_count;
322 unsigned int trb_alloced;
323 XHCITRB *trbs;
324
325 unsigned int data_length;
326 unsigned int data_alloced;
327 uint8_t *data;
328
329 TRBCCode status;
330
331 unsigned int pkts;
332 unsigned int pktsize;
333 unsigned int cur_pkt;
334} XHCITransfer;
335
336typedef struct XHCIEPContext {
337 XHCIRing ring;
338 unsigned int next_xfer;
339 unsigned int comp_xfer;
340 XHCITransfer transfers[TD_QUEUE];
341 bool bg_running;
342 bool bg_updating;
343 unsigned int next_bg;
344 XHCITransfer bg_transfers[BG_XFERS];
345 EPType type;
346 target_phys_addr_t pctx;
347 unsigned int max_psize;
348 bool has_bg;
349 uint32_t state;
350} XHCIEPContext;
351
352typedef struct XHCISlot {
353 bool enabled;
354 target_phys_addr_t ctx;
355 unsigned int port;
356 unsigned int devaddr;
357 XHCIEPContext * eps[31];
358} XHCISlot;
359
360typedef struct XHCIEvent {
361 TRBType type;
362 TRBCCode ccode;
363 uint64_t ptr;
364 uint32_t length;
365 uint32_t flags;
366 uint8_t slotid;
367 uint8_t epid;
368} XHCIEvent;
369
370struct XHCIState {
371 PCIDevice pci_dev;
372 USBBus bus;
373 qemu_irq irq;
374 MemoryRegion mem;
375 const char *name;
376 uint32_t msi;
377 unsigned int devaddr;
378
379 /* Operational Registers */
380 uint32_t usbcmd;
381 uint32_t usbsts;
382 uint32_t dnctrl;
383 uint32_t crcr_low;
384 uint32_t crcr_high;
385 uint32_t dcbaap_low;
386 uint32_t dcbaap_high;
387 uint32_t config;
388
389 XHCIPort ports[MAXPORTS];
390 XHCISlot slots[MAXSLOTS];
391
392 /* Runtime Registers */
393 uint32_t mfindex;
394 /* note: we only support one interrupter */
395 uint32_t iman;
396 uint32_t imod;
397 uint32_t erstsz;
398 uint32_t erstba_low;
399 uint32_t erstba_high;
400 uint32_t erdp_low;
401 uint32_t erdp_high;
402
403 target_phys_addr_t er_start;
404 uint32_t er_size;
405 bool er_pcs;
406 unsigned int er_ep_idx;
407 bool er_full;
408
409 XHCIEvent ev_buffer[EV_QUEUE];
410 unsigned int ev_buffer_put;
411 unsigned int ev_buffer_get;
412
413 XHCIRing cmd_ring;
414};
415
416typedef struct XHCIEvRingSeg {
417 uint32_t addr_low;
418 uint32_t addr_high;
419 uint32_t size;
420 uint32_t rsvd;
421} XHCIEvRingSeg;
422
f10de44e
GH		 423#ifdef DEBUG_XHCI
424static const char *TRBType_names[] = {
425 [TRB_RESERVED] = "TRB_RESERVED",
426 [TR_NORMAL] = "TR_NORMAL",
427 [TR_SETUP] = "TR_SETUP",
428 [TR_DATA] = "TR_DATA",
429 [TR_STATUS] = "TR_STATUS",
430 [TR_ISOCH] = "TR_ISOCH",
431 [TR_LINK] = "TR_LINK",
432 [TR_EVDATA] = "TR_EVDATA",
433 [TR_NOOP] = "TR_NOOP",
434 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
435 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
436 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
437 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
438 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
439 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
440 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
441 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
442 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
443 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
444 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
445 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
446 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
447 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
448 [CR_NOOP] = "CR_NOOP",
449 [ER_TRANSFER] = "ER_TRANSFER",
450 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
451 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
452 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
453 [ER_DOORBELL] = "ER_DOORBELL",
454 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
455 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
456 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
457 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
458 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
459 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
460};
461
462static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
463{
464 if (index >= llen || list[index] == NULL) {
465 return "???";
466 }
467 return list[index];
468}
469
470static const char *trb_name(XHCITRB *trb)
471{
472 return lookup_name(TRB_TYPE(*trb), TRBType_names,
473 ARRAY_SIZE(TRBType_names));
474}
475#endif
476
62c6ae04
HM		 477static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
478 unsigned int epid);
479
480static inline target_phys_addr_t xhci_addr64(uint32_t low, uint32_t high)
481{
482#if TARGET_PHYS_ADDR_BITS > 32
483 return low | ((target_phys_addr_t)high << 32);
484#else
485 return low;
486#endif
487}
488
489static inline target_phys_addr_t xhci_mask64(uint64_t addr)
490{
491#if TARGET_PHYS_ADDR_BITS > 32
492 return addr;
493#else
494 return addr & 0xffffffff;
495#endif
496}
497
498static void xhci_irq_update(XHCIState *xhci)
499{
500 int level = 0;
501
502 if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
503 xhci->usbcmd && USBCMD_INTE) {
504 level = 1;
505 }
506
507 DPRINTF("xhci_irq_update(): %d\n", level);
508
509 if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
510 if (level) {
511 DPRINTF("xhci_irq_update(): MSI signal\n");
512 msi_notify(&xhci->pci_dev, 0);
513 }
514 } else {
515 qemu_set_irq(xhci->irq, level);
516 }
517}
518
519static inline int xhci_running(XHCIState *xhci)
520{
521 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
522}
523
524static void xhci_die(XHCIState *xhci)
525{
526 xhci->usbsts |= USBSTS_HCE;
527 fprintf(stderr, "xhci: asserted controller error\n");
528}
529
530static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
531{
532 XHCITRB ev_trb;
533 target_phys_addr_t addr;
534
535 ev_trb.parameter = cpu_to_le64(event->ptr);
536 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
537 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
538 event->flags | (event->type << TRB_TYPE_SHIFT);
539 if (xhci->er_pcs) {
540 ev_trb.control |= TRB_C;
541 }
542 ev_trb.control = cpu_to_le32(ev_trb.control);
543
f10de44e
GH		 544 DPRINTF("xhci_write_event(): [%d] %016"PRIx64" %08x %08x %s\n",
545 xhci->er_ep_idx, ev_trb.parameter, ev_trb.status, ev_trb.control,
546 trb_name(&ev_trb));
62c6ae04
HM		 547
548 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx;
549 cpu_physical_memory_write(addr, (uint8_t *) &ev_trb, TRB_SIZE);
550
551 xhci->er_ep_idx++;
552 if (xhci->er_ep_idx >= xhci->er_size) {
553 xhci->er_ep_idx = 0;
554 xhci->er_pcs = !xhci->er_pcs;
555 }
556}
557
558static void xhci_events_update(XHCIState *xhci)
559{
560 target_phys_addr_t erdp;
561 unsigned int dp_idx;
562 bool do_irq = 0;
563
564 if (xhci->usbsts & USBSTS_HCH) {
565 return;
566 }
567
568 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
569 if (erdp < xhci->er_start ||
570 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
571 fprintf(stderr, "xhci: ERDP out of bounds: "TARGET_FMT_plx"\n", erdp);
572 fprintf(stderr, "xhci: ER at "TARGET_FMT_plx" len %d\n",
573 xhci->er_start, xhci->er_size);
574 xhci_die(xhci);
575 return;
576 }
577 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
578 assert(dp_idx < xhci->er_size);
579
580 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
581 * deadlocks when the ER is full. Hack it by holding off events until
582 * the driver decides to free at least half of the ring */
583 if (xhci->er_full) {
584 int er_free = dp_idx - xhci->er_ep_idx;
585 if (er_free <= 0) {
586 er_free += xhci->er_size;
587 }
588 if (er_free < (xhci->er_size/2)) {
589 DPRINTF("xhci_events_update(): event ring still "
590 "more than half full (hack)\n");
591 return;
592 }
593 }
594
595 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
596 assert(xhci->er_full);
597 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
598 DPRINTF("xhci_events_update(): event ring full again\n");
599#ifndef ER_FULL_HACK
600 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
601 xhci_write_event(xhci, &full);
602#endif
603 do_irq = 1;
604 break;
605 }
606 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
607 xhci_write_event(xhci, event);
608 xhci->ev_buffer_get++;
609 do_irq = 1;
610 if (xhci->ev_buffer_get == EV_QUEUE) {
611 xhci->ev_buffer_get = 0;
612 }
613 }
614
615 if (do_irq) {
616 xhci->erdp_low |= ERDP_EHB;
617 xhci->iman |= IMAN_IP;
618 xhci->usbsts |= USBSTS_EINT;
619 xhci_irq_update(xhci);
620 }
621
622 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
623 DPRINTF("xhci_events_update(): event ring no longer full\n");
624 xhci->er_full = 0;
625 }
626 return;
627}
628
629static void xhci_event(XHCIState *xhci, XHCIEvent *event)
630{
631 target_phys_addr_t erdp;
632 unsigned int dp_idx;
633
634 if (xhci->er_full) {
635 DPRINTF("xhci_event(): ER full, queueing\n");
636 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
637 fprintf(stderr, "xhci: event queue full, dropping event!\n");
638 return;
639 }
640 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
641 if (xhci->ev_buffer_put == EV_QUEUE) {
642 xhci->ev_buffer_put = 0;
643 }
644 return;
645 }
646
647 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
648 if (erdp < xhci->er_start ||
649 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
650 fprintf(stderr, "xhci: ERDP out of bounds: "TARGET_FMT_plx"\n", erdp);
651 fprintf(stderr, "xhci: ER at "TARGET_FMT_plx" len %d\n",
652 xhci->er_start, xhci->er_size);
653 xhci_die(xhci);
654 return;
655 }
656
657 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
658 assert(dp_idx < xhci->er_size);
659
660 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
661 DPRINTF("xhci_event(): ER full, queueing\n");
662#ifndef ER_FULL_HACK
663 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
664 xhci_write_event(xhci, &full);
665#endif
666 xhci->er_full = 1;
667 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
668 fprintf(stderr, "xhci: event queue full, dropping event!\n");
669 return;
670 }
671 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
672 if (xhci->ev_buffer_put == EV_QUEUE) {
673 xhci->ev_buffer_put = 0;
674 }
675 } else {
676 xhci_write_event(xhci, event);
677 }
678
679 xhci->erdp_low |= ERDP_EHB;
680 xhci->iman |= IMAN_IP;
681 xhci->usbsts |= USBSTS_EINT;
682
683 xhci_irq_update(xhci);
684}
685
686static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
687 target_phys_addr_t base)
688{
689 ring->base = base;
690 ring->dequeue = base;
691 ring->ccs = 1;
692}
693
694static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
695 target_phys_addr_t *addr)
696{
697 while (1) {
698 TRBType type;
699 cpu_physical_memory_read(ring->dequeue, (uint8_t *) trb, TRB_SIZE);
700 trb->addr = ring->dequeue;
701 trb->ccs = ring->ccs;
702 le64_to_cpus(&trb->parameter);
703 le32_to_cpus(&trb->status);
704 le32_to_cpus(&trb->control);
705
706 DPRINTF("xhci: TRB fetched [" TARGET_FMT_plx "]: "
f10de44e
GH		 707 "%016" PRIx64 " %08x %08x %s\n",
708 ring->dequeue, trb->parameter, trb->status, trb->control,
709 trb_name(trb));
62c6ae04
HM		 710
711 if ((trb->control & TRB_C) != ring->ccs) {
712 return 0;
713 }
714
715 type = TRB_TYPE(*trb);
716
717 if (type != TR_LINK) {
718 if (addr) {
719 *addr = ring->dequeue;
720 }
721 ring->dequeue += TRB_SIZE;
722 return type;
723 } else {
724 ring->dequeue = xhci_mask64(trb->parameter);
725 if (trb->control & TRB_LK_TC) {
726 ring->ccs = !ring->ccs;
727 }
728 }
729 }
730}
731
732static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
733{
734 XHCITRB trb;
735 int length = 0;
736 target_phys_addr_t dequeue = ring->dequeue;
737 bool ccs = ring->ccs;
738 /* hack to bundle together the two/three TDs that make a setup transfer */
739 bool control_td_set = 0;
740
741 while (1) {
742 TRBType type;
743 cpu_physical_memory_read(dequeue, (uint8_t *) &trb, TRB_SIZE);
744 le64_to_cpus(&trb.parameter);
745 le32_to_cpus(&trb.status);
746 le32_to_cpus(&trb.control);
747
748 DPRINTF("xhci: TRB peeked [" TARGET_FMT_plx "]: "
749 "%016" PRIx64 " %08x %08x\n",
750 dequeue, trb.parameter, trb.status, trb.control);
751
752 if ((trb.control & TRB_C) != ccs) {
753 return -length;
754 }
755
756 type = TRB_TYPE(trb);
757
758 if (type == TR_LINK) {
759 dequeue = xhci_mask64(trb.parameter);
760 if (trb.control & TRB_LK_TC) {
761 ccs = !ccs;
762 }
763 continue;
764 }
765
766 length += 1;
767 dequeue += TRB_SIZE;
768
769 if (type == TR_SETUP) {
770 control_td_set = 1;
771 } else if (type == TR_STATUS) {
772 control_td_set = 0;
773 }
774
775 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
776 return length;
777 }
778 }
779}
780
781static void xhci_er_reset(XHCIState *xhci)
782{
783 XHCIEvRingSeg seg;
784
785 /* cache the (sole) event ring segment location */
786 if (xhci->erstsz != 1) {
787 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
788 xhci_die(xhci);
789 return;
790 }
791 target_phys_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
792 cpu_physical_memory_read(erstba, (uint8_t *) &seg, sizeof(seg));
793 le32_to_cpus(&seg.addr_low);
794 le32_to_cpus(&seg.addr_high);
795 le32_to_cpus(&seg.size);
796 if (seg.size < 16 || seg.size > 4096) {
797 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
798 xhci_die(xhci);
799 return;
800 }
801 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
802 xhci->er_size = seg.size;
803
804 xhci->er_ep_idx = 0;
805 xhci->er_pcs = 1;
806 xhci->er_full = 0;
807
808 DPRINTF("xhci: event ring:" TARGET_FMT_plx " [%d]\n",
809 xhci->er_start, xhci->er_size);
810}
811
812static void xhci_run(XHCIState *xhci)
813{
814 DPRINTF("xhci_run()\n");
815
816 xhci->usbsts &= ~USBSTS_HCH;
817}
818
819static void xhci_stop(XHCIState *xhci)
820{
821 DPRINTF("xhci_stop()\n");
822 xhci->usbsts |= USBSTS_HCH;
823 xhci->crcr_low &= ~CRCR_CRR;
824}
825
826static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
827 uint32_t state)
828{
829 uint32_t ctx[5];
830 if (epctx->state == state) {
831 return;
832 }
833
834 cpu_physical_memory_read(epctx->pctx, (uint8_t *) ctx, sizeof(ctx));
835 ctx[0] &= ~EP_STATE_MASK;
836 ctx[0] |= state;
837 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
838 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
839 DPRINTF("xhci: set epctx: " TARGET_FMT_plx " state=%d dequeue=%08x%08x\n",
840 epctx->pctx, state, ctx[3], ctx[2]);
841 cpu_physical_memory_write(epctx->pctx, (uint8_t *) ctx, sizeof(ctx));
842 epctx->state = state;
843}
844
845static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
846 unsigned int epid, target_phys_addr_t pctx,
847 uint32_t *ctx)
848{
849 XHCISlot *slot;
850 XHCIEPContext *epctx;
851 target_phys_addr_t dequeue;
852 int i;
853
854 assert(slotid >= 1 && slotid <= MAXSLOTS);
855 assert(epid >= 1 && epid <= 31);
856
857 DPRINTF("xhci_enable_ep(%d, %d)\n", slotid, epid);
858
859 slot = &xhci->slots[slotid-1];
860 if (slot->eps[epid-1]) {
861 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
862 return CC_TRB_ERROR;
863 }
864
865 epctx = g_malloc(sizeof(XHCIEPContext));
866 memset(epctx, 0, sizeof(XHCIEPContext));
867
868 slot->eps[epid-1] = epctx;
869
870 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
871 xhci_ring_init(xhci, &epctx->ring, dequeue);
872 epctx->ring.ccs = ctx[2] & 1;
873
874 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
875 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
876 epctx->pctx = pctx;
877 epctx->max_psize = ctx[1]>>16;
878 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
879 epctx->has_bg = false;
880 if (epctx->type == ET_ISO_IN) {
881 epctx->has_bg = true;
882 }
883 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
884 epid/2, epid%2, epctx->max_psize);
885 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
886 usb_packet_init(&epctx->transfers[i].packet);
887 }
888
889 epctx->state = EP_RUNNING;
890 ctx[0] &= ~EP_STATE_MASK;
891 ctx[0] |= EP_RUNNING;
892
893 return CC_SUCCESS;
894}
895
896static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
897 unsigned int epid)
898{
899 XHCISlot *slot;
900 XHCIEPContext *epctx;
901 int i, xferi, killed = 0;
902 assert(slotid >= 1 && slotid <= MAXSLOTS);
903 assert(epid >= 1 && epid <= 31);
904
905 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
906
907 slot = &xhci->slots[slotid-1];
908
909 if (!slot->eps[epid-1]) {
910 return 0;
911 }
912
913 epctx = slot->eps[epid-1];
914
915 xferi = epctx->next_xfer;
916 for (i = 0; i < TD_QUEUE; i++) {
917 XHCITransfer *t = &epctx->transfers[xferi];
918 if (t->running) {
919 t->cancelled = 1;
920 /* libusb_cancel_transfer(t->usbxfer) */
921 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
922 killed++;
923 }
924 if (t->backgrounded) {
925 t->backgrounded = 0;
926 }
927 if (t->trbs) {
928 g_free(t->trbs);
929 }
930 if (t->data) {
931 g_free(t->data);
932 }
933
934 t->trbs = NULL;
935 t->data = NULL;
936 t->trb_count = t->trb_alloced = 0;
937 t->data_length = t->data_alloced = 0;
938 xferi = (xferi + 1) % TD_QUEUE;
939 }
940 if (epctx->has_bg) {
941 xferi = epctx->next_bg;
942 for (i = 0; i < BG_XFERS; i++) {
943 XHCITransfer *t = &epctx->bg_transfers[xferi];
944 if (t->running) {
945 t->cancelled = 1;
946 /* libusb_cancel_transfer(t->usbxfer); */
947 DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i);
948 killed++;
949 }
950 if (t->data) {
951 g_free(t->data);
952 }
953
954 t->data = NULL;
955 xferi = (xferi + 1) % BG_XFERS;
956 }
957 }
958 return killed;
959}
960
961static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
962 unsigned int epid)
963{
964 XHCISlot *slot;
965 XHCIEPContext *epctx;
966
967 assert(slotid >= 1 && slotid <= MAXSLOTS);
968 assert(epid >= 1 && epid <= 31);
969
970 DPRINTF("xhci_disable_ep(%d, %d)\n", slotid, epid);
971
972 slot = &xhci->slots[slotid-1];
973
974 if (!slot->eps[epid-1]) {
975 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
976 return CC_SUCCESS;
977 }
978
979 xhci_ep_nuke_xfers(xhci, slotid, epid);
980
981 epctx = slot->eps[epid-1];
982
983 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
984
985 g_free(epctx);
986 slot->eps[epid-1] = NULL;
987
988 return CC_SUCCESS;
989}
990
991static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
992 unsigned int epid)
993{
994 XHCISlot *slot;
995 XHCIEPContext *epctx;
996
997 DPRINTF("xhci_stop_ep(%d, %d)\n", slotid, epid);
998
999 assert(slotid >= 1 && slotid <= MAXSLOTS);
1000
1001 if (epid < 1 || epid > 31) {
1002 fprintf(stderr, "xhci: bad ep %d\n", epid);
1003 return CC_TRB_ERROR;
1004 }
1005
1006 slot = &xhci->slots[slotid-1];
1007
1008 if (!slot->eps[epid-1]) {
1009 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1010 return CC_EP_NOT_ENABLED_ERROR;
1011 }
1012
1013 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1014 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1015 "data might be lost\n");
1016 }
1017
1018 epctx = slot->eps[epid-1];
1019
1020 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1021
1022 return CC_SUCCESS;
1023}
1024
1025static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1026 unsigned int epid)
1027{
1028 XHCISlot *slot;
1029 XHCIEPContext *epctx;
1030 USBDevice *dev;
1031
1032 assert(slotid >= 1 && slotid <= MAXSLOTS);
1033
1034 DPRINTF("xhci_reset_ep(%d, %d)\n", slotid, epid);
1035
1036 if (epid < 1 || epid > 31) {
1037 fprintf(stderr, "xhci: bad ep %d\n", epid);
1038 return CC_TRB_ERROR;
1039 }
1040
1041 slot = &xhci->slots[slotid-1];
1042
1043 if (!slot->eps[epid-1]) {
1044 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1045 return CC_EP_NOT_ENABLED_ERROR;
1046 }
1047
1048 epctx = slot->eps[epid-1];
1049
1050 if (epctx->state != EP_HALTED) {
1051 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1052 epid, epctx->state);
1053 return CC_CONTEXT_STATE_ERROR;
1054 }
1055
1056 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1057 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1058 "data might be lost\n");
1059 }
1060
1061 uint8_t ep = epid>>1;
1062
1063 if (epid & 1) {
1064 ep |= 0x80;
1065 }
1066
1067 dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
1068 if (!dev) {
1069 return CC_USB_TRANSACTION_ERROR;
1070 }
1071
1072 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1073
1074 return CC_SUCCESS;
1075}
1076
1077static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1078 unsigned int epid, uint64_t pdequeue)
1079{
1080 XHCISlot *slot;
1081 XHCIEPContext *epctx;
1082 target_phys_addr_t dequeue;
1083
1084 assert(slotid >= 1 && slotid <= MAXSLOTS);
1085
1086 if (epid < 1 || epid > 31) {
1087 fprintf(stderr, "xhci: bad ep %d\n", epid);
1088 return CC_TRB_ERROR;
1089 }
1090
1091 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue);
1092 dequeue = xhci_mask64(pdequeue);
1093
1094 slot = &xhci->slots[slotid-1];
1095
1096 if (!slot->eps[epid-1]) {
1097 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1098 return CC_EP_NOT_ENABLED_ERROR;
1099 }
1100
1101 epctx = slot->eps[epid-1];
1102
1103
1104 if (epctx->state != EP_STOPPED) {
1105 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1106 return CC_CONTEXT_STATE_ERROR;
1107 }
1108
1109 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1110 epctx->ring.ccs = dequeue & 1;
1111
1112 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1113
1114 return CC_SUCCESS;
1115}
1116
1117static int xhci_xfer_data(XHCITransfer *xfer, uint8_t *data,
1118 unsigned int length, bool in_xfer, bool out_xfer,
1119 bool report)
1120{
1121 int i;
1122 uint32_t edtla = 0;
1123 unsigned int transferred = 0;
1124 unsigned int left = length;
1125 bool reported = 0;
1126 bool shortpkt = 0;
1127 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1128 XHCIState *xhci = xfer->xhci;
1129
1130 DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",
1131 length, in_xfer, out_xfer, report);
1132
1133 assert(!(in_xfer && out_xfer));
1134
1135 for (i = 0; i < xfer->trb_count; i++) {
1136 XHCITRB *trb = &xfer->trbs[i];
1137 target_phys_addr_t addr;
1138 unsigned int chunk = 0;
1139
1140 switch (TRB_TYPE(*trb)) {
1141 case TR_DATA:
1142 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1143 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1144 xhci_die(xhci);
1145 return transferred;
1146 }
1147 /* fallthrough */
1148 case TR_NORMAL:
1149 case TR_ISOCH:
1150 addr = xhci_mask64(trb->parameter);
1151 chunk = trb->status & 0x1ffff;
1152 if (chunk > left) {
1153 chunk = left;
1154 shortpkt = 1;
1155 }
1156 if (in_xfer || out_xfer) {
1157 if (trb->control & TRB_TR_IDT) {
1158 uint64_t idata;
1159 if (chunk > 8 || in_xfer) {
1160 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1161 xhci_die(xhci);
1162 return transferred;
1163 }
1164 idata = le64_to_cpu(trb->parameter);
1165 memcpy(data, &idata, chunk);
1166 } else {
1167 DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "
1168 TARGET_FMT_plx "\n", in_xfer, chunk, addr);
1169 if (in_xfer) {
1170 cpu_physical_memory_write(addr, data, chunk);
1171 } else {
1172 cpu_physical_memory_read(addr, data, chunk);
1173 }
1174#ifdef DEBUG_DATA
1175 unsigned int count = chunk;
1176 int i;
1177 if (count > 16) {
1178 count = 16;
1179 }
1180 DPRINTF(" ::");
1181 for (i = 0; i < count; i++) {
1182 DPRINTF(" %02x", data[i]);
1183 }
1184 DPRINTF("\n");
1185#endif
1186 }
1187 }
1188 left -= chunk;
1189 data += chunk;
1190 edtla += chunk;
1191 transferred += chunk;
1192 break;
1193 case TR_STATUS:
1194 reported = 0;
1195 shortpkt = 0;
1196 break;
1197 }
1198
1199 if (report && !reported && (trb->control & TRB_TR_IOC ||
1200 (shortpkt && (trb->control & TRB_TR_ISP)))) {
1201 event.slotid = xfer->slotid;
1202 event.epid = xfer->epid;
1203 event.length = (trb->status & 0x1ffff) - chunk;
1204 event.flags = 0;
1205 event.ptr = trb->addr;
1206 if (xfer->status == CC_SUCCESS) {
1207 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1208 } else {
1209 event.ccode = xfer->status;
1210 }
1211 if (TRB_TYPE(*trb) == TR_EVDATA) {
1212 event.ptr = trb->parameter;
1213 event.flags |= TRB_EV_ED;
1214 event.length = edtla & 0xffffff;
1215 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1216 edtla = 0;
1217 }
1218 xhci_event(xhci, &event);
1219 reported = 1;
1220 }
1221 }
1222 return transferred;
1223}
1224
1225static void xhci_stall_ep(XHCITransfer *xfer)
1226{
1227 XHCIState *xhci = xfer->xhci;
1228 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1229 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1230
1231 epctx->ring.dequeue = xfer->trbs[0].addr;
1232 epctx->ring.ccs = xfer->trbs[0].ccs;
1233 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1234 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
1235 DPRINTF("xhci: will continue at "TARGET_FMT_plx"\n", epctx->ring.dequeue);
1236}
1237
1238static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1239 XHCIEPContext *epctx);
1240
1241static void xhci_bg_update(XHCIState *xhci, XHCIEPContext *epctx)
1242{
1243 if (epctx->bg_updating) {
1244 return;
1245 }
1246 DPRINTF("xhci_bg_update(%p, %p)\n", xhci, epctx);
1247 assert(epctx->has_bg);
1248 DPRINTF("xhci: fg=%d bg=%d\n", epctx->comp_xfer, epctx->next_bg);
1249 epctx->bg_updating = 1;
1250 while (epctx->transfers[epctx->comp_xfer].backgrounded &&
1251 epctx->bg_transfers[epctx->next_bg].complete) {
1252 XHCITransfer *fg = &epctx->transfers[epctx->comp_xfer];
1253 XHCITransfer *bg = &epctx->bg_transfers[epctx->next_bg];
1254#if 0
1255 DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",
1256 epctx->comp_xfer, epctx->next_bg, bg->cur_pkt,
1257 bg->usbxfer->iso_packet_desc[bg->cur_pkt].status
1258 );
1259#endif
1260 assert(epctx->type == ET_ISO_IN);
1261 assert(bg->iso_xfer);
1262 assert(bg->in_xfer);
1263 uint8_t *p = bg->data + bg->cur_pkt * bg->pktsize;
1264#if 0
1265 int len = bg->usbxfer->iso_packet_desc[bg->cur_pkt].actual_length;
1266 fg->status = libusb_to_ccode(bg->usbxfer->iso_packet_desc[bg->cur_pkt].status);
1267#else
1268 int len = 0;
1269 FIXME();
1270#endif
1271 fg->complete = 1;
1272 fg->backgrounded = 0;
1273
1274 if (fg->status == CC_STALL_ERROR) {
1275 xhci_stall_ep(fg);
1276 }
1277
1278 xhci_xfer_data(fg, p, len, 1, 0, 1);
1279
1280 epctx->comp_xfer++;
1281 if (epctx->comp_xfer == TD_QUEUE) {
1282 epctx->comp_xfer = 0;
1283 }
1284 DPRINTF("next fg xfer: %d\n", epctx->comp_xfer);
1285 bg->cur_pkt++;
1286 if (bg->cur_pkt == bg->pkts) {
1287 bg->complete = 0;
1288 if (xhci_submit(xhci, bg, epctx) < 0) {
1289 fprintf(stderr, "xhci: bg resubmit failed\n");
1290 }
1291 epctx->next_bg++;
1292 if (epctx->next_bg == BG_XFERS) {
1293 epctx->next_bg = 0;
1294 }
1295 DPRINTF("next bg xfer: %d\n", epctx->next_bg);
1296
1297 xhci_kick_ep(xhci, fg->slotid, fg->epid);
1298 }
1299 }
1300 epctx->bg_updating = 0;
1301}
1302
1303#if 0
1304static void xhci_xfer_cb(struct libusb_transfer *transfer)
1305{
1306 XHCIState *xhci;
1307 XHCITransfer *xfer;
1308
1309 xfer = (XHCITransfer *)transfer->user_data;
1310 xhci = xfer->xhci;
1311
1312 DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer->slotid,
1313 xfer->epid, transfer->status);
1314
1315 assert(xfer->slotid >= 1 && xfer->slotid <= MAXSLOTS);
1316 assert(xfer->epid >= 1 && xfer->epid <= 31);
1317
1318 if (xfer->cancelled) {
1319 DPRINTF("xhci: transfer cancelled, not reporting anything\n");
1320 xfer->running = 0;
1321 return;
1322 }
1323
1324 XHCIEPContext *epctx;
1325 XHCISlot *slot;
1326 slot = &xhci->slots[xfer->slotid-1];
1327 assert(slot->eps[xfer->epid-1]);
1328 epctx = slot->eps[xfer->epid-1];
1329
1330 if (xfer->bg_xfer) {
1331 DPRINTF("xhci: background transfer, updating\n");
1332 xfer->complete = 1;
1333 xfer->running = 0;
1334 xhci_bg_update(xhci, epctx);
1335 return;
1336 }
1337
1338 if (xfer->iso_xfer) {
1339 transfer->status = transfer->iso_packet_desc[0].status;
1340 transfer->actual_length = transfer->iso_packet_desc[0].actual_length;
1341 }
1342
1343 xfer->status = libusb_to_ccode(transfer->status);
1344
1345 xfer->complete = 1;
1346 xfer->running = 0;
1347
1348 if (transfer->status == LIBUSB_TRANSFER_STALL)
1349 xhci_stall_ep(xhci, epctx, xfer);
1350
1351 DPRINTF("xhci: transfer actual length = %d\n", transfer->actual_length);
1352
1353 if (xfer->in_xfer) {
1354 if (xfer->epid == 1) {
1355 xhci_xfer_data(xhci, xfer, xfer->data + 8,
1356 transfer->actual_length, 1, 0, 1);
1357 } else {
1358 xhci_xfer_data(xhci, xfer, xfer->data,
1359 transfer->actual_length, 1, 0, 1);
1360 }
1361 } else {
1362 xhci_xfer_data(xhci, xfer, NULL, transfer->actual_length, 0, 0, 1);
1363 }
1364
1365 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1366}
1367
1368static int xhci_hle_control(XHCIState *xhci, XHCITransfer *xfer,
1369 uint8_t bmRequestType, uint8_t bRequest,
1370 uint16_t wValue, uint16_t wIndex, uint16_t wLength)
1371{
1372 uint16_t type_req = (bmRequestType << 8) | bRequest;
1373
1374 switch (type_req) {
1375 case 0x0000 | USB_REQ_SET_CONFIGURATION:
1376 DPRINTF("xhci: HLE switch configuration\n");
1377 return xhci_switch_config(xhci, xfer->slotid, wValue) == 0;
1378 case 0x0100 | USB_REQ_SET_INTERFACE:
1379 DPRINTF("xhci: HLE set interface altsetting\n");
1380 return xhci_set_iface_alt(xhci, xfer->slotid, wIndex, wValue) == 0;
1381 case 0x0200 | USB_REQ_CLEAR_FEATURE:
1382 if (wValue == 0) { // endpoint halt
1383 DPRINTF("xhci: HLE clear halt\n");
1384 return xhci_clear_halt(xhci, xfer->slotid, wIndex);
1385 }
1386 case 0x0000 | USB_REQ_SET_ADDRESS:
1387 fprintf(stderr, "xhci: warn: illegal SET_ADDRESS request\n");
1388 return 0;
1389 default:
1390 return 0;
1391 }
1392}
1393#endif
1394
b819d716 1395static int xhci_setup_packet(XHCITransfer *xfer, USBDevice *dev)
62c6ae04 1396{
079d0b7f
GH		 1397 USBEndpoint *ep;
1398 int dir;
1399
1400 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1401 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1402 usb_packet_setup(&xfer->packet, dir, ep);
62c6ae04
HM		 1403 usb_packet_addbuf(&xfer->packet, xfer->data, xfer->data_length);
1404 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
079d0b7f 1405 xfer->packet.pid, dev->addr, ep->nr);
62c6ae04
HM		 1406 return 0;
1407}
1408
1409static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1410{
1411 if (ret == USB_RET_ASYNC) {
1412 xfer->running = 1;
1413 xfer->complete = 0;
1414 xfer->cancelled = 0;
1415 return 0;
1416 } else {
1417 xfer->running = 0;
1418 xfer->complete = 1;
1419 }
1420
1421 if (ret >= 0) {
1422 xfer->status = CC_SUCCESS;
1423 xhci_xfer_data(xfer, xfer->data, ret, xfer->in_xfer, 0, 1);
1424 return 0;
1425 }
1426
1427 /* error */
1428 switch (ret) {
1429 case USB_RET_NODEV:
1430 xfer->status = CC_USB_TRANSACTION_ERROR;
1431 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1432 xhci_stall_ep(xfer);
1433 break;
1434 case USB_RET_STALL:
1435 xfer->status = CC_STALL_ERROR;
1436 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1437 xhci_stall_ep(xfer);
1438 break;
1439 default:
1440 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1441 FIXME();
1442 }
1443 return 0;
1444}
1445
e74495e3
GH		 1446static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
1447{
1448 if (!(port->portsc & PORTSC_PED)) {
1449 return NULL;
1450 }
1451 return usb_find_device(&port->port, addr);
1452}
1453
62c6ae04
HM		 1454static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1455{
1456 XHCITRB *trb_setup, *trb_status;
1457 uint8_t bmRequestType, bRequest;
1458 uint16_t wValue, wLength, wIndex;
1459 XHCIPort *port;
1460 USBDevice *dev;
1461 int ret;
1462
1463 DPRINTF("xhci_fire_ctl_transfer(slot=%d)\n", xfer->slotid);
1464
1465 trb_setup = &xfer->trbs[0];
1466 trb_status = &xfer->trbs[xfer->trb_count-1];
1467
1468 /* at most one Event Data TRB allowed after STATUS */
1469 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1470 trb_status--;
1471 }
1472
1473 /* do some sanity checks */
1474 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1475 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1476 TRB_TYPE(*trb_setup));
1477 return -1;
1478 }
1479 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1480 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1481 TRB_TYPE(*trb_status));
1482 return -1;
1483 }
1484 if (!(trb_setup->control & TRB_TR_IDT)) {
1485 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1486 return -1;
1487 }
1488 if ((trb_setup->status & 0x1ffff) != 8) {
1489 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1490 (trb_setup->status & 0x1ffff));
1491 return -1;
1492 }
1493
1494 bmRequestType = trb_setup->parameter;
1495 bRequest = trb_setup->parameter >> 8;
1496 wValue = trb_setup->parameter >> 16;
1497 wIndex = trb_setup->parameter >> 32;
1498 wLength = trb_setup->parameter >> 48;
1499
1500 if (xfer->data && xfer->data_alloced < wLength) {
1501 xfer->data_alloced = 0;
1502 g_free(xfer->data);
1503 xfer->data = NULL;
1504 }
1505 if (!xfer->data) {
1506 DPRINTF("xhci: alloc %d bytes data\n", wLength);
1507 xfer->data = g_malloc(wLength+1);
1508 xfer->data_alloced = wLength;
1509 }
1510 xfer->data_length = wLength;
1511
1512 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
e74495e3 1513 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
62c6ae04
HM		 1514 if (!dev) {
1515 fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1516 xhci->slots[xfer->slotid-1].port);
1517 return -1;
1518 }
1519
1520 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1521 xfer->iso_xfer = false;
1522
b819d716 1523 xhci_setup_packet(xfer, dev);
62c6ae04
HM		 1524 if (!xfer->in_xfer) {
1525 xhci_xfer_data(xfer, xfer->data, wLength, 0, 1, 0);
1526 }
62aed765 1527 ret = usb_device_handle_control(dev, &xfer->packet,
62c6ae04
HM		 1528 (bmRequestType << 8) | bRequest,
1529 wValue, wIndex, wLength, xfer->data);
1530
1531 xhci_complete_packet(xfer, ret);
1532 if (!xfer->running) {
1533 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1534 }
1535 return 0;
1536}
1537
1538static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1539{
1540 XHCIPort *port;
1541 USBDevice *dev;
1542 int ret;
1543
1544 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
62c6ae04
HM		 1545
1546 xfer->in_xfer = epctx->type>>2;
62c6ae04
HM		 1547
1548 if (xfer->data && xfer->data_alloced < xfer->data_length) {
1549 xfer->data_alloced = 0;
1550 g_free(xfer->data);
1551 xfer->data = NULL;
1552 }
1553 if (!xfer->data && xfer->data_length) {
1554 DPRINTF("xhci: alloc %d bytes data\n", xfer->data_length);
1555 xfer->data = g_malloc(xfer->data_length);
1556 xfer->data_alloced = xfer->data_length;
1557 }
1558 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1559 if (!xfer->bg_xfer) {
1560 xfer->pkts = 1;
1561 }
1562 } else {
1563 xfer->pkts = 0;
1564 }
1565
1566 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
e74495e3 1567 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
62c6ae04
HM		 1568 if (!dev) {
1569 fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1570 xhci->slots[xfer->slotid-1].port);
1571 return -1;
1572 }
1573
b819d716 1574 xhci_setup_packet(xfer, dev);
62c6ae04
HM		 1575
1576 switch(epctx->type) {
1577 case ET_INTR_OUT:
1578 case ET_INTR_IN:
1579 case ET_BULK_OUT:
1580 case ET_BULK_IN:
1581 break;
1582 case ET_ISO_OUT:
1583 case ET_ISO_IN:
1584 FIXME();
1585 break;
1586 default:
079d0b7f
GH		 1587 fprintf(stderr, "xhci: unknown or unhandled EP "
1588 "(type %d, in %d, ep %02x)\n",
1589 epctx->type, xfer->in_xfer, xfer->epid);
62c6ae04
HM		 1590 return -1;
1591 }
1592
1593 if (!xfer->in_xfer) {
1594 xhci_xfer_data(xfer, xfer->data, xfer->data_length, 0, 1, 0);
1595 }
1596 ret = usb_handle_packet(dev, &xfer->packet);
1597
1598 xhci_complete_packet(xfer, ret);
1599 if (!xfer->running) {
1600 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1601 }
1602 return 0;
1603}
1604
1605static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1606{
1607 int i;
1608 unsigned int length = 0;
1609 XHCITRB *trb;
1610
1611 DPRINTF("xhci_fire_transfer(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1612
1613 for (i = 0; i < xfer->trb_count; i++) {
1614 trb = &xfer->trbs[i];
1615 if (TRB_TYPE(*trb) == TR_NORMAL || TRB_TYPE(*trb) == TR_ISOCH) {
1616 length += trb->status & 0x1ffff;
1617 }
1618 }
1619 DPRINTF("xhci: total TD length=%d\n", length);
1620
1621 if (!epctx->has_bg) {
1622 xfer->data_length = length;
1623 xfer->backgrounded = 0;
1624 return xhci_submit(xhci, xfer, epctx);
1625 } else {
1626 if (!epctx->bg_running) {
1627 for (i = 0; i < BG_XFERS; i++) {
1628 XHCITransfer *t = &epctx->bg_transfers[i];
1629 t->xhci = xhci;
1630 t->epid = xfer->epid;
1631 t->slotid = xfer->slotid;
1632 t->pkts = BG_PKTS;
1633 t->pktsize = epctx->max_psize;
1634 t->data_length = t->pkts * t->pktsize;
1635 t->bg_xfer = 1;
1636 if (xhci_submit(xhci, t, epctx) < 0) {
1637 fprintf(stderr, "xhci: bg submit failed\n");
1638 return -1;
1639 }
1640 }
1641 epctx->bg_running = 1;
1642 }
1643 xfer->backgrounded = 1;
1644 xhci_bg_update(xhci, epctx);
1645 return 0;
1646 }
1647}
1648
1649static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1650{
1651 XHCIEPContext *epctx;
1652 int length;
1653 int i;
1654
1655 assert(slotid >= 1 && slotid <= MAXSLOTS);
1656 assert(epid >= 1 && epid <= 31);
1657 DPRINTF("xhci_kick_ep(%d, %d)\n", slotid, epid);
1658
1659 if (!xhci->slots[slotid-1].enabled) {
1660 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1661 return;
1662 }
1663 epctx = xhci->slots[slotid-1].eps[epid-1];
1664 if (!epctx) {
1665 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1666 epid, slotid);
1667 return;
1668 }
1669
1670 if (epctx->state == EP_HALTED) {
1671 DPRINTF("xhci: ep halted, not running schedule\n");
1672 return;
1673 }
1674
1675 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1676
1677 while (1) {
1678 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1679 if (xfer->running || xfer->backgrounded) {
1680 DPRINTF("xhci: ep is busy\n");
1681 break;
1682 }
1683 length = xhci_ring_chain_length(xhci, &epctx->ring);
1684 if (length < 0) {
1685 DPRINTF("xhci: incomplete TD (%d TRBs)\n", -length);
1686 break;
1687 } else if (length == 0) {
1688 break;
1689 }
1690 DPRINTF("xhci: fetching %d-TRB TD\n", length);
1691 if (xfer->trbs && xfer->trb_alloced < length) {
1692 xfer->trb_count = 0;
1693 xfer->trb_alloced = 0;
1694 g_free(xfer->trbs);
1695 xfer->trbs = NULL;
1696 }
1697 if (!xfer->trbs) {
1698 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1699 xfer->trb_alloced = length;
1700 }
1701 xfer->trb_count = length;
1702
1703 for (i = 0; i < length; i++) {
1704 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1705 }
1706 xfer->xhci = xhci;
1707 xfer->epid = epid;
1708 xfer->slotid = slotid;
1709
1710 if (epid == 1) {
1711 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1712 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1713 } else {
1714 fprintf(stderr, "xhci: error firing CTL transfer\n");
1715 }
1716 } else {
1717 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1718 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1719 } else {
1720 fprintf(stderr, "xhci: error firing data transfer\n");
1721 }
1722 }
1723
3c4866e0
GH		 1724 if (epctx->state == EP_HALTED) {
1725 DPRINTF("xhci: ep halted, stopping schedule\n");
1726 break;
1727 }
1728
62c6ae04
HM		 1729 /*
1730 * Qemu usb can't handle multiple in-flight xfers.
3c4866e0 1731 * Stop here for now.
62c6ae04
HM		 1732 */
1733 break;
1734 }
1735}
1736
1737static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1738{
1739 assert(slotid >= 1 && slotid <= MAXSLOTS);
1740 DPRINTF("xhci_enable_slot(%d)\n", slotid);
1741 xhci->slots[slotid-1].enabled = 1;
1742 xhci->slots[slotid-1].port = 0;
1743 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1744
1745 return CC_SUCCESS;
1746}
1747
1748static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1749{
1750 int i;
1751
1752 assert(slotid >= 1 && slotid <= MAXSLOTS);
1753 DPRINTF("xhci_disable_slot(%d)\n", slotid);
1754
1755 for (i = 1; i <= 31; i++) {
1756 if (xhci->slots[slotid-1].eps[i-1]) {
1757 xhci_disable_ep(xhci, slotid, i);
1758 }
1759 }
1760
1761 xhci->slots[slotid-1].enabled = 0;
1762 return CC_SUCCESS;
1763}
1764
1765static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1766 uint64_t pictx, bool bsr)
1767{
1768 XHCISlot *slot;
1769 USBDevice *dev;
1770 target_phys_addr_t ictx, octx, dcbaap;
1771 uint64_t poctx;
1772 uint32_t ictl_ctx[2];
1773 uint32_t slot_ctx[4];
1774 uint32_t ep0_ctx[5];
1775 unsigned int port;
1776 int i;
1777 TRBCCode res;
1778
1779 assert(slotid >= 1 && slotid <= MAXSLOTS);
1780 DPRINTF("xhci_address_slot(%d)\n", slotid);
1781
1782 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
1783 cpu_physical_memory_read(dcbaap + 8*slotid,
1784 (uint8_t *) &poctx, sizeof(poctx));
1785 ictx = xhci_mask64(pictx);
1786 octx = xhci_mask64(le64_to_cpu(poctx));
1787
1788 DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx);
1789 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1790
1791 cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
1792
1793 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1794 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1795 ictl_ctx[0], ictl_ctx[1]);
1796 return CC_TRB_ERROR;
1797 }
1798
1799 cpu_physical_memory_read(ictx+32, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1800 cpu_physical_memory_read(ictx+64, (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
1801
1802 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1803 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1804
1805 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1806 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1807
1808 port = (slot_ctx[1]>>16) & 0xFF;
1809 dev = xhci->ports[port-1].port.dev;
1810
1811 if (port < 1 || port > MAXPORTS) {
1812 fprintf(stderr, "xhci: bad port %d\n", port);
1813 return CC_TRB_ERROR;
1814 } else if (!dev) {
1815 fprintf(stderr, "xhci: port %d not connected\n", port);
1816 return CC_USB_TRANSACTION_ERROR;
1817 }
1818
1819 for (i = 0; i < MAXSLOTS; i++) {
1820 if (xhci->slots[i].port == port) {
1821 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1822 port, i+1);
1823 return CC_TRB_ERROR;
1824 }
1825 }
1826
1827 slot = &xhci->slots[slotid-1];
1828 slot->port = port;
1829 slot->ctx = octx;
1830
1831 if (bsr) {
1832 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1833 } else {
1834 slot->devaddr = xhci->devaddr++;
1835 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1836 DPRINTF("xhci: device address is %d\n", slot->devaddr);
62aed765 1837 usb_device_handle_control(dev, NULL,
62c6ae04
HM		 1838 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1839 slot->devaddr, 0, 0, NULL);
1840 }
1841
1842 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1843
1844 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1845 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1846 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1847 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1848
1849 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1850 cpu_physical_memory_write(octx+32, (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
1851
1852 return res;
1853}
1854
1855
1856static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1857 uint64_t pictx, bool dc)
1858{
1859 target_phys_addr_t ictx, octx;
1860 uint32_t ictl_ctx[2];
1861 uint32_t slot_ctx[4];
1862 uint32_t islot_ctx[4];
1863 uint32_t ep_ctx[5];
1864 int i;
1865 TRBCCode res;
1866
1867 assert(slotid >= 1 && slotid <= MAXSLOTS);
1868 DPRINTF("xhci_configure_slot(%d)\n", slotid);
1869
1870 ictx = xhci_mask64(pictx);
1871 octx = xhci->slots[slotid-1].ctx;
1872
1873 DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx);
1874 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1875
1876 if (dc) {
1877 for (i = 2; i <= 31; i++) {
1878 if (xhci->slots[slotid-1].eps[i-1]) {
1879 xhci_disable_ep(xhci, slotid, i);
1880 }
1881 }
1882
1883 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1884 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1885 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1886 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1887 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1888 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1889
1890 return CC_SUCCESS;
1891 }
1892
1893 cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
1894
1895 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1896 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1897 ictl_ctx[0], ictl_ctx[1]);
1898 return CC_TRB_ERROR;
1899 }
1900
1901 cpu_physical_memory_read(ictx+32, (uint8_t *) islot_ctx, sizeof(islot_ctx));
1902 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1903
1904 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1905 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1906 return CC_CONTEXT_STATE_ERROR;
1907 }
1908
1909 for (i = 2; i <= 31; i++) {
1910 if (ictl_ctx[0] & (1<<i)) {
1911 xhci_disable_ep(xhci, slotid, i);
1912 }
1913 if (ictl_ctx[1] & (1<<i)) {
1914 cpu_physical_memory_read(ictx+32+(32*i),
1915 (uint8_t *) ep_ctx, sizeof(ep_ctx));
1916 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1917 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1918 ep_ctx[3], ep_ctx[4]);
1919 xhci_disable_ep(xhci, slotid, i);
1920 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1921 if (res != CC_SUCCESS) {
1922 return res;
1923 }
1924 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1925 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1926 ep_ctx[3], ep_ctx[4]);
1927 cpu_physical_memory_write(octx+(32*i),
1928 (uint8_t *) ep_ctx, sizeof(ep_ctx));
1929 }
1930 }
1931
1932 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1933 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1934 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1935 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1936 SLOT_CONTEXT_ENTRIES_SHIFT);
1937 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1938 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1939
1940 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1941
1942 return CC_SUCCESS;
1943}
1944
1945
1946static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1947 uint64_t pictx)
1948{
1949 target_phys_addr_t ictx, octx;
1950 uint32_t ictl_ctx[2];
1951 uint32_t iep0_ctx[5];
1952 uint32_t ep0_ctx[5];
1953 uint32_t islot_ctx[4];
1954 uint32_t slot_ctx[4];
1955
1956 assert(slotid >= 1 && slotid <= MAXSLOTS);
1957 DPRINTF("xhci_evaluate_slot(%d)\n", slotid);
1958
1959 ictx = xhci_mask64(pictx);
1960 octx = xhci->slots[slotid-1].ctx;
1961
1962 DPRINTF("xhci: input context at "TARGET_FMT_plx"\n", ictx);
1963 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
1964
1965 cpu_physical_memory_read(ictx, (uint8_t *) ictl_ctx, sizeof(ictl_ctx));
1966
1967 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1968 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1969 ictl_ctx[0], ictl_ctx[1]);
1970 return CC_TRB_ERROR;
1971 }
1972
1973 if (ictl_ctx[1] & 0x1) {
1974 cpu_physical_memory_read(ictx+32,
1975 (uint8_t *) islot_ctx, sizeof(islot_ctx));
1976
1977 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1978 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1979
1980 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1981
1982 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1983 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1984 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1985 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1986
1987 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1988 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1989
1990 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
1991 }
1992
1993 if (ictl_ctx[1] & 0x2) {
1994 cpu_physical_memory_read(ictx+64,
1995 (uint8_t *) iep0_ctx, sizeof(iep0_ctx));
1996
1997 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1998 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
1999 iep0_ctx[3], iep0_ctx[4]);
2000
2001 cpu_physical_memory_read(octx+32, (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
2002
2003 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2004 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2005
2006 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2007 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2008
2009 cpu_physical_memory_write(octx+32,
2010 (uint8_t *) ep0_ctx, sizeof(ep0_ctx));
2011 }
2012
2013 return CC_SUCCESS;
2014}
2015
2016static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2017{
2018 uint32_t slot_ctx[4];
2019 target_phys_addr_t octx;
2020 int i;
2021
2022 assert(slotid >= 1 && slotid <= MAXSLOTS);
2023 DPRINTF("xhci_reset_slot(%d)\n", slotid);
2024
2025 octx = xhci->slots[slotid-1].ctx;
2026
2027 DPRINTF("xhci: output context at "TARGET_FMT_plx"\n", octx);
2028
2029 for (i = 2; i <= 31; i++) {
2030 if (xhci->slots[slotid-1].eps[i-1]) {
2031 xhci_disable_ep(xhci, slotid, i);
2032 }
2033 }
2034
2035 cpu_physical_memory_read(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
2036 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2037 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2038 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2039 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2040 cpu_physical_memory_write(octx, (uint8_t *) slot_ctx, sizeof(slot_ctx));
2041
2042 return CC_SUCCESS;
2043}
2044
2045static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2046{
2047 unsigned int slotid;
2048 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2049 if (slotid < 1 || slotid > MAXSLOTS) {
2050 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2051 event->ccode = CC_TRB_ERROR;
2052 return 0;
2053 } else if (!xhci->slots[slotid-1].enabled) {
2054 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2055 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2056 return 0;
2057 }
2058 return slotid;
2059}
2060
2061static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2062{
2063 target_phys_addr_t ctx;
2064 uint8_t bw_ctx[MAXPORTS+1];
2065
2066 DPRINTF("xhci_get_port_bandwidth()\n");
2067
2068 ctx = xhci_mask64(pctx);
2069
2070 DPRINTF("xhci: bandwidth context at "TARGET_FMT_plx"\n", ctx);
2071
2072 /* TODO: actually implement real values here */
2073 bw_ctx[0] = 0;
2074 memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */
2075 cpu_physical_memory_write(ctx, bw_ctx, sizeof(bw_ctx));
2076
2077 return CC_SUCCESS;
2078}
2079
2080static uint32_t rotl(uint32_t v, unsigned count)
2081{
2082 count &= 31;
2083 return (v << count) | (v >> (32 - count));
2084}
2085
2086
2087static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2088{
2089 uint32_t val;
2090 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2091 val += rotl(lo + 0x49434878, hi & 0x1F);
2092 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2093 return ~val;
2094}
2095
2096static void xhci_via_challenge(uint64_t addr)
2097{
2098 uint32_t buf[8];
2099 uint32_t obuf[8];
2100 target_phys_addr_t paddr = xhci_mask64(addr);
2101
2102 cpu_physical_memory_read(paddr, (uint8_t *) &buf, 32);
2103
2104 memcpy(obuf, buf, sizeof(obuf));
2105
2106 if ((buf[0] & 0xff) == 2) {
2107 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2108 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2109 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2110 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2111 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2112 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2113 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2114 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2115 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2116 }
2117
2118 cpu_physical_memory_write(paddr, (uint8_t *) &obuf, 32);
2119}
2120
2121static void xhci_process_commands(XHCIState *xhci)
2122{
2123 XHCITRB trb;
2124 TRBType type;
2125 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2126 target_phys_addr_t addr;
2127 unsigned int i, slotid = 0;
2128
2129 DPRINTF("xhci_process_commands()\n");
2130 if (!xhci_running(xhci)) {
2131 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2132 return;
2133 }
2134
2135 xhci->crcr_low |= CRCR_CRR;
2136
2137 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2138 event.ptr = addr;
2139 switch (type) {
2140 case CR_ENABLE_SLOT:
2141 for (i = 0; i < MAXSLOTS; i++) {
2142 if (!xhci->slots[i].enabled) {
2143 break;
2144 }
2145 }
2146 if (i >= MAXSLOTS) {
2147 fprintf(stderr, "xhci: no device slots available\n");
2148 event.ccode = CC_NO_SLOTS_ERROR;
2149 } else {
2150 slotid = i+1;
2151 event.ccode = xhci_enable_slot(xhci, slotid);
2152 }
2153 break;
2154 case CR_DISABLE_SLOT:
2155 slotid = xhci_get_slot(xhci, &event, &trb);
2156 if (slotid) {
2157 event.ccode = xhci_disable_slot(xhci, slotid);
2158 }
2159 break;
2160 case CR_ADDRESS_DEVICE:
2161 slotid = xhci_get_slot(xhci, &event, &trb);
2162 if (slotid) {
2163 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2164 trb.control & TRB_CR_BSR);
2165 }
2166 break;
2167 case CR_CONFIGURE_ENDPOINT:
2168 slotid = xhci_get_slot(xhci, &event, &trb);
2169 if (slotid) {
2170 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2171 trb.control & TRB_CR_DC);
2172 }
2173 break;
2174 case CR_EVALUATE_CONTEXT:
2175 slotid = xhci_get_slot(xhci, &event, &trb);
2176 if (slotid) {
2177 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2178 }
2179 break;
2180 case CR_STOP_ENDPOINT:
2181 slotid = xhci_get_slot(xhci, &event, &trb);
2182 if (slotid) {
2183 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2184 & TRB_CR_EPID_MASK;
2185 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2186 }
2187 break;
2188 case CR_RESET_ENDPOINT:
2189 slotid = xhci_get_slot(xhci, &event, &trb);
2190 if (slotid) {
2191 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2192 & TRB_CR_EPID_MASK;
2193 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2194 }
2195 break;
2196 case CR_SET_TR_DEQUEUE:
2197 slotid = xhci_get_slot(xhci, &event, &trb);
2198 if (slotid) {
2199 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2200 & TRB_CR_EPID_MASK;
2201 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2202 trb.parameter);
2203 }
2204 break;
2205 case CR_RESET_DEVICE:
2206 slotid = xhci_get_slot(xhci, &event, &trb);
2207 if (slotid) {
2208 event.ccode = xhci_reset_slot(xhci, slotid);
2209 }
2210 break;
2211 case CR_GET_PORT_BANDWIDTH:
2212 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2213 break;
2214 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2215 xhci_via_challenge(trb.parameter);
2216 break;
2217 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2218 event.type = 48; /* NEC reply */
2219 event.length = 0x3025;
2220 break;
2221 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2222 {
2223 uint32_t chi = trb.parameter >> 32;
2224 uint32_t clo = trb.parameter;
2225 uint32_t val = xhci_nec_challenge(chi, clo);
2226 event.length = val & 0xFFFF;
2227 event.epid = val >> 16;
2228 slotid = val >> 24;
2229 event.type = 48; /* NEC reply */
2230 }
2231 break;
2232 default:
2233 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2234 event.ccode = CC_TRB_ERROR;
2235 break;
2236 }
2237 event.slotid = slotid;
2238 xhci_event(xhci, &event);
2239 }
2240}
2241
2242static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2243{
2244 int nr = port->port.index + 1;
2245
2246 port->portsc = PORTSC_PP;
2247 if (port->port.dev && !is_detach) {
2248 port->portsc |= PORTSC_CCS;
2249 switch (port->port.dev->speed) {
2250 case USB_SPEED_LOW:
2251 port->portsc |= PORTSC_SPEED_LOW;
2252 break;
2253 case USB_SPEED_FULL:
2254 port->portsc |= PORTSC_SPEED_FULL;
2255 break;
2256 case USB_SPEED_HIGH:
2257 port->portsc |= PORTSC_SPEED_HIGH;
2258 break;
2259 }
2260 }
2261
2262 if (xhci_running(xhci)) {
2263 port->portsc |= PORTSC_CSC;
2264 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2265 xhci_event(xhci, &ev);
2266 DPRINTF("xhci: port change event for port %d\n", nr);
2267 }
2268}
2269
2270static void xhci_reset(void *opaque)
2271{
2272 XHCIState *xhci = opaque;
2273 int i;
2274
2275 DPRINTF("xhci: full reset\n");
2276 if (!(xhci->usbsts & USBSTS_HCH)) {
2277 fprintf(stderr, "xhci: reset while running!\n");
2278 }
2279
2280 xhci->usbcmd = 0;
2281 xhci->usbsts = USBSTS_HCH;
2282 xhci->dnctrl = 0;
2283 xhci->crcr_low = 0;
2284 xhci->crcr_high = 0;
2285 xhci->dcbaap_low = 0;
2286 xhci->dcbaap_high = 0;
2287 xhci->config = 0;
2288 xhci->devaddr = 2;
2289
2290 for (i = 0; i < MAXSLOTS; i++) {
2291 xhci_disable_slot(xhci, i+1);
2292 }
2293
2294 for (i = 0; i < MAXPORTS; i++) {
2295 xhci_update_port(xhci, xhci->ports + i, 0);
2296 }
2297
2298 xhci->mfindex = 0;
2299 xhci->iman = 0;
2300 xhci->imod = 0;
2301 xhci->erstsz = 0;
2302 xhci->erstba_low = 0;
2303 xhci->erstba_high = 0;
2304 xhci->erdp_low = 0;
2305 xhci->erdp_high = 0;
2306
2307 xhci->er_ep_idx = 0;
2308 xhci->er_pcs = 1;
2309 xhci->er_full = 0;
2310 xhci->ev_buffer_put = 0;
2311 xhci->ev_buffer_get = 0;
2312}
2313
2314static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2315{
2316 DPRINTF("xhci_cap_read(0x%x)\n", reg);
2317
2318 switch (reg) {
2319 case 0x00: /* HCIVERSION, CAPLENGTH */
2320 return 0x01000000 | LEN_CAP;
2321 case 0x04: /* HCSPARAMS 1 */
2322 return (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS;
2323 case 0x08: /* HCSPARAMS 2 */
2324 return 0x0000000f;
2325 case 0x0c: /* HCSPARAMS 3 */
2326 return 0x00000000;
2327 case 0x10: /* HCCPARAMS */
2328#if TARGET_PHYS_ADDR_BITS > 32
2329 return 0x00081001;
2330#else
2331 return 0x00081000;
2332#endif
2333 case 0x14: /* DBOFF */
2334 return OFF_DOORBELL;
2335 case 0x18: /* RTSOFF */
2336 return OFF_RUNTIME;
2337
2338 /* extended capabilities */
2339 case 0x20: /* Supported Protocol:00 */
2340#if USB3_PORTS > 0
2341 return 0x02000402; /* USB 2.0 */
2342#else
2343 return 0x02000002; /* USB 2.0 */
2344#endif
2345 case 0x24: /* Supported Protocol:04 */
2346 return 0x20425455; /* "USB " */
2347 case 0x28: /* Supported Protocol:08 */
2348 return 0x00000001 | (USB2_PORTS<<8);
2349 case 0x2c: /* Supported Protocol:0c */
2350 return 0x00000000; /* reserved */
2351#if USB3_PORTS > 0
2352 case 0x30: /* Supported Protocol:00 */
2353 return 0x03000002; /* USB 3.0 */
2354 case 0x34: /* Supported Protocol:04 */
2355 return 0x20425455; /* "USB " */
2356 case 0x38: /* Supported Protocol:08 */
2357 return 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8);
2358 case 0x3c: /* Supported Protocol:0c */
2359 return 0x00000000; /* reserved */
2360#endif
2361 default:
2362 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2363 }
2364 return 0;
2365}
2366
2367static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2368{
2369 uint32_t port = reg >> 4;
2370 if (port >= MAXPORTS) {
2371 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2372 return 0;
2373 }
2374
2375 switch (reg & 0xf) {
2376 case 0x00: /* PORTSC */
2377 return xhci->ports[port].portsc;
2378 case 0x04: /* PORTPMSC */
2379 case 0x08: /* PORTLI */
2380 return 0;
2381 case 0x0c: /* reserved */
2382 default:
2383 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2384 port, reg);
2385 return 0;
2386 }
2387}
2388
2389static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2390{
2391 uint32_t port = reg >> 4;
2392 uint32_t portsc;
2393
2394 if (port >= MAXPORTS) {
2395 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2396 return;
2397 }
2398
2399 switch (reg & 0xf) {
2400 case 0x00: /* PORTSC */
2401 portsc = xhci->ports[port].portsc;
2402 /* write-1-to-clear bits*/
2403 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2404 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2405 if (val & PORTSC_LWS) {
2406 /* overwrite PLS only when LWS=1 */
2407 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2408 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2409 }
2410 /* read/write bits */
2411 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2412 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2413 /* write-1-to-start bits */
2414 if (val & PORTSC_PR) {
2415 DPRINTF("xhci: port %d reset\n", port);
d28f4e2d 2416 usb_device_reset(xhci->ports[port].port.dev);
62c6ae04
HM		 2417 portsc |= PORTSC_PRC | PORTSC_PED;
2418 }
2419 xhci->ports[port].portsc = portsc;
2420 break;
2421 case 0x04: /* PORTPMSC */
2422 case 0x08: /* PORTLI */
2423 default:
2424 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2425 port, reg);
2426 }
2427}
2428
2429static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2430{
2431 DPRINTF("xhci_oper_read(0x%x)\n", reg);
2432
2433 if (reg >= 0x400) {
2434 return xhci_port_read(xhci, reg - 0x400);
2435 }
2436
2437 switch (reg) {
2438 case 0x00: /* USBCMD */
2439 return xhci->usbcmd;
2440 case 0x04: /* USBSTS */
2441 return xhci->usbsts;
2442 case 0x08: /* PAGESIZE */
2443 return 1; /* 4KiB */
2444 case 0x14: /* DNCTRL */
2445 return xhci->dnctrl;
2446 case 0x18: /* CRCR low */
2447 return xhci->crcr_low & ~0xe;
2448 case 0x1c: /* CRCR high */
2449 return xhci->crcr_high;
2450 case 0x30: /* DCBAAP low */
2451 return xhci->dcbaap_low;
2452 case 0x34: /* DCBAAP high */
2453 return xhci->dcbaap_high;
2454 case 0x38: /* CONFIG */
2455 return xhci->config;
2456 default:
2457 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2458 }
2459 return 0;
2460}
2461
2462static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2463{
2464 DPRINTF("xhci_oper_write(0x%x, 0x%08x)\n", reg, val);
2465
2466 if (reg >= 0x400) {
2467 xhci_port_write(xhci, reg - 0x400, val);
2468 return;
2469 }
2470
2471 switch (reg) {
2472 case 0x00: /* USBCMD */
2473 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2474 xhci_run(xhci);
2475 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2476 xhci_stop(xhci);
2477 }
2478 xhci->usbcmd = val & 0xc0f;
2479 if (val & USBCMD_HCRST) {
2480 xhci_reset(xhci);
2481 }
2482 xhci_irq_update(xhci);
2483 break;
2484
2485 case 0x04: /* USBSTS */
2486 /* these bits are write-1-to-clear */
2487 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2488 xhci_irq_update(xhci);
2489 break;
2490
2491 case 0x14: /* DNCTRL */
2492 xhci->dnctrl = val & 0xffff;
2493 break;
2494 case 0x18: /* CRCR low */
2495 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2496 break;
2497 case 0x1c: /* CRCR high */
2498 xhci->crcr_high = val;
2499 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2500 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2501 xhci->crcr_low &= ~CRCR_CRR;
2502 xhci_event(xhci, &event);
2503 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2504 } else {
2505 target_phys_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2506 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2507 }
2508 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2509 break;
2510 case 0x30: /* DCBAAP low */
2511 xhci->dcbaap_low = val & 0xffffffc0;
2512 break;
2513 case 0x34: /* DCBAAP high */
2514 xhci->dcbaap_high = val;
2515 break;
2516 case 0x38: /* CONFIG */
2517 xhci->config = val & 0xff;
2518 break;
2519 default:
2520 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2521 }
2522}
2523
2524static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2525{
2526 DPRINTF("xhci_runtime_read(0x%x)\n", reg);
2527
2528 switch (reg) {
2529 case 0x00: /* MFINDEX */
2530 fprintf(stderr, "xhci_runtime_read: MFINDEX not yet implemented\n");
2531 return xhci->mfindex;
2532 case 0x20: /* IMAN */
2533 return xhci->iman;
2534 case 0x24: /* IMOD */
2535 return xhci->imod;
2536 case 0x28: /* ERSTSZ */
2537 return xhci->erstsz;
2538 case 0x30: /* ERSTBA low */
2539 return xhci->erstba_low;
2540 case 0x34: /* ERSTBA high */
2541 return xhci->erstba_high;
2542 case 0x38: /* ERDP low */
2543 return xhci->erdp_low;
2544 case 0x3c: /* ERDP high */
2545 return xhci->erdp_high;
2546 default:
2547 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2548 }
2549 return 0;
2550}
2551
2552static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2553{
2554 DPRINTF("xhci_runtime_write(0x%x, 0x%08x)\n", reg, val);
2555
2556 switch (reg) {
2557 case 0x20: /* IMAN */
2558 if (val & IMAN_IP) {
2559 xhci->iman &= ~IMAN_IP;
2560 }
2561 xhci->iman &= ~IMAN_IE;
2562 xhci->iman |= val & IMAN_IE;
2563 xhci_irq_update(xhci);
2564 break;
2565 case 0x24: /* IMOD */
2566 xhci->imod = val;
2567 break;
2568 case 0x28: /* ERSTSZ */
2569 xhci->erstsz = val & 0xffff;
2570 break;
2571 case 0x30: /* ERSTBA low */
2572 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2573 xhci->erstba_low = val & 0xffffffc0; */
2574 xhci->erstba_low = val & 0xfffffff0;
2575 break;
2576 case 0x34: /* ERSTBA high */
2577 xhci->erstba_high = val;
2578 xhci_er_reset(xhci);
2579 break;
2580 case 0x38: /* ERDP low */
2581 if (val & ERDP_EHB) {
2582 xhci->erdp_low &= ~ERDP_EHB;
2583 }
2584 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB);
2585 break;
2586 case 0x3c: /* ERDP high */
2587 xhci->erdp_high = val;
2588 xhci_events_update(xhci);
2589 break;
2590 default:
2591 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2592 }
2593}
2594
2595static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2596{
2597 DPRINTF("xhci_doorbell_read(0x%x)\n", reg);
2598 /* doorbells always read as 0 */
2599 return 0;
2600}
2601
2602static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2603{
2604 DPRINTF("xhci_doorbell_write(0x%x, 0x%08x)\n", reg, val);
2605
2606 if (!xhci_running(xhci)) {
2607 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2608 return;
2609 }
2610
2611 reg >>= 2;
2612
2613 if (reg == 0) {
2614 if (val == 0) {
2615 xhci_process_commands(xhci);
2616 } else {
2617 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2618 }
2619 } else {
2620 if (reg > MAXSLOTS) {
2621 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2622 } else if (val > 31) {
2623 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2624 } else {
2625 xhci_kick_ep(xhci, reg, val);
2626 }
2627 }
2628}
2629
2630static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2631 unsigned size)
2632{
2633 XHCIState *xhci = ptr;
2634
2635 /* Only aligned reads are allowed on xHCI */
2636 if (addr & 3) {
2637 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2638 return 0;
2639 }
2640
2641 if (addr < LEN_CAP) {
2642 return xhci_cap_read(xhci, addr);
2643 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2644 return xhci_oper_read(xhci, addr - OFF_OPER);
2645 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2646 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2647 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2648 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2649 } else {
2650 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2651 return 0;
2652 }
2653}
2654
2655static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2656 uint64_t val, unsigned size)
2657{
2658 XHCIState *xhci = ptr;
2659
2660 /* Only aligned writes are allowed on xHCI */
2661 if (addr & 3) {
2662 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2663 return;
2664 }
2665
2666 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2667 xhci_oper_write(xhci, addr - OFF_OPER, val);
2668 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2669 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2670 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2671 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2672 } else {
2673 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2674 }
2675}
2676
2677static const MemoryRegionOps xhci_mem_ops = {
2678 .read = xhci_mem_read,
2679 .write = xhci_mem_write,
2680 .valid.min_access_size = 4,
2681 .valid.max_access_size = 4,
2682 .endianness = DEVICE_LITTLE_ENDIAN,
2683};
2684
2685static void xhci_attach(USBPort *usbport)
2686{
2687 XHCIState *xhci = usbport->opaque;
2688 XHCIPort *port = &xhci->ports[usbport->index];
2689
2690 xhci_update_port(xhci, port, 0);
2691}
2692
2693static void xhci_detach(USBPort *usbport)
2694{
2695 XHCIState *xhci = usbport->opaque;
2696 XHCIPort *port = &xhci->ports[usbport->index];
2697
2698 xhci_update_port(xhci, port, 1);
2699}
2700
8c735e43
GH		 2701static void xhci_wakeup(USBPort *usbport)
2702{
2703 XHCIState *xhci = usbport->opaque;
2704 XHCIPort *port = &xhci->ports[usbport->index];
2705 int nr = port->port.index + 1;
2706 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2707 uint32_t pls;
2708
2709 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
2710 if (pls != 3) {
2711 return;
2712 }
2713 port->portsc |= 0xf << PORTSC_PLS_SHIFT;
2714 if (port->portsc & PORTSC_PLC) {
2715 return;
2716 }
2717 port->portsc |= PORTSC_PLC;
2718 xhci_event(xhci, &ev);
2719}
2720
62c6ae04
HM		 2721static void xhci_complete(USBPort *port, USBPacket *packet)
2722{
2723 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2724
2725 xhci_complete_packet(xfer, packet->result);
2726 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2727}
2728
2729static void xhci_child_detach(USBPort *port, USBDevice *child)
2730{
2731 FIXME();
2732}
2733
2734static USBPortOps xhci_port_ops = {
2735 .attach = xhci_attach,
2736 .detach = xhci_detach,
8c735e43 2737 .wakeup = xhci_wakeup,
62c6ae04
HM		 2738 .complete = xhci_complete,
2739 .child_detach = xhci_child_detach,
2740};
2741
2742static USBBusOps xhci_bus_ops = {
2743};
2744
2745static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2746{
2747 int i;
2748
2749 xhci->usbsts = USBSTS_HCH;
2750
2751 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2752
2753 for (i = 0; i < MAXPORTS; i++) {
2754 memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
2755 usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
606352b7
GH		 2756 &xhci_port_ops,
2757 USB_SPEED_MASK_LOW |
2758 USB_SPEED_MASK_FULL |
2759 USB_SPEED_MASK_HIGH);
62c6ae04
HM		 2760 }
2761 for (i = 0; i < MAXSLOTS; i++) {
2762 xhci->slots[i].enabled = 0;
2763 }
2764
2765 qemu_register_reset(xhci_reset, xhci);
2766}
2767
2768static int usb_xhci_initfn(struct PCIDevice *dev)
2769{
2770 int ret;
2771
2772 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2773
2774 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2775 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2776 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2777 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2778
2779 usb_xhci_init(xhci, &dev->qdev);
2780
2781 xhci->irq = xhci->pci_dev.irq[0];
2782
2783 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2784 "xhci", LEN_REGS);
2785 pci_register_bar(&xhci->pci_dev, 0,
2786 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2787 &xhci->mem);
2788
2789 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2790 assert(ret >= 0);
2791
2792 if (xhci->msi) {
2793 ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false);
2794 assert(ret >= 0);
2795 }
2796
2797 return 0;
2798}
2799
2800static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
2801 int len)
2802{
2803 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2804
2805 pci_default_write_config(dev, addr, val, len);
2806 if (xhci->msi) {
2807 msi_write_config(dev, addr, val, len);
2808 }
2809}
2810
2811static const VMStateDescription vmstate_xhci = {
2812 .name = "xhci",
2813 .unmigratable = 1,
2814};
2815
39bffca2
AL		 2816static Property xhci_properties[] = {
2817 DEFINE_PROP_UINT32("msi", XHCIState, msi, 0),
2818 DEFINE_PROP_END_OF_LIST(),
2819};
2820
40021f08
AL		 2821static void xhci_class_init(ObjectClass *klass, void *data)
2822{
2823 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2 2824 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 2825
39bffca2
AL		 2826 dc->vmsd = &vmstate_xhci;
2827 dc->props = xhci_properties;
40021f08
AL		 2828 k->init = usb_xhci_initfn;
2829 k->vendor_id = PCI_VENDOR_ID_NEC;
2830 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2831 k->class_id = PCI_CLASS_SERIAL_USB;
2832 k->revision = 0x03;
2833 k->is_express = 1;
2834 k->config_write = xhci_write_config;
2835}
2836
39bffca2
AL		 2837static TypeInfo xhci_info = {
2838 .name = "nec-usb-xhci",
2839 .parent = TYPE_PCI_DEVICE,
2840 .instance_size = sizeof(XHCIState),
2841 .class_init = xhci_class_init,
62c6ae04
HM		 2842};
2843
2844static void xhci_register(void)
2845{
39bffca2 2846 type_register_static(&xhci_info);
62c6ae04
HM		 2847}
2848device_init(xhci_register);
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