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Commit | Line | Data |
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5fafdf24 | 1 | /* |
502a5395 PB |
2 | * ARM Versatile/PB PCI host controller |
3 | * | |
0027b06d | 4 | * Copyright (c) 2006-2009 CodeSourcery. |
502a5395 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the LGPL. |
502a5395 PB |
8 | */ |
9 | ||
0027b06d | 10 | #include "sysbus.h" |
87ecb68b | 11 | #include "pci.h" |
b6243d99 | 12 | #include "pci_host.h" |
1e39101c | 13 | #include "exec-memory.h" |
0027b06d PB |
14 | |
15 | typedef struct { | |
16 | SysBusDevice busdev; | |
17 | qemu_irq irq[4]; | |
18 | int realview; | |
19 | int mem_config; | |
20 | } PCIVPBState; | |
502a5395 | 21 | |
c227f099 | 22 | static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) |
502a5395 | 23 | { |
80b3ada7 | 24 | return addr & 0xffffff; |
502a5395 PB |
25 | } |
26 | ||
c227f099 | 27 | static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
28 | uint32_t val) |
29 | { | |
30 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1); | |
31 | } | |
32 | ||
c227f099 | 33 | static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
34 | uint32_t val) |
35 | { | |
502a5395 PB |
36 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2); |
37 | } | |
38 | ||
c227f099 | 39 | static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
40 | uint32_t val) |
41 | { | |
502a5395 PB |
42 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4); |
43 | } | |
44 | ||
c227f099 | 45 | static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
46 | { |
47 | uint32_t val; | |
48 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1); | |
49 | return val; | |
50 | } | |
51 | ||
c227f099 | 52 | static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
53 | { |
54 | uint32_t val; | |
55 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2); | |
502a5395 PB |
56 | return val; |
57 | } | |
58 | ||
c227f099 | 59 | static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
60 | { |
61 | uint32_t val; | |
62 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4); | |
502a5395 PB |
63 | return val; |
64 | } | |
65 | ||
d60efc6b | 66 | static CPUWriteMemoryFunc * const pci_vpb_config_write[] = { |
502a5395 PB |
67 | &pci_vpb_config_writeb, |
68 | &pci_vpb_config_writew, | |
69 | &pci_vpb_config_writel, | |
70 | }; | |
71 | ||
d60efc6b | 72 | static CPUReadMemoryFunc * const pci_vpb_config_read[] = { |
502a5395 PB |
73 | &pci_vpb_config_readb, |
74 | &pci_vpb_config_readw, | |
75 | &pci_vpb_config_readl, | |
76 | }; | |
77 | ||
d2b59317 PB |
78 | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
79 | { | |
80 | return irq_num; | |
81 | } | |
82 | ||
5d4e84c8 | 83 | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 84 | { |
5d4e84c8 JQ |
85 | qemu_irq *pic = opaque; |
86 | ||
97aff481 | 87 | qemu_set_irq(pic[irq_num], level); |
502a5395 PB |
88 | } |
89 | ||
c227f099 | 90 | static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) |
502a5395 | 91 | { |
0027b06d PB |
92 | PCIVPBState *s = (PCIVPBState *)dev; |
93 | /* Selfconfig area. */ | |
94 | cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config); | |
95 | /* Normal config area. */ | |
96 | cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config); | |
97 | ||
98 | if (s->realview) { | |
99 | /* IO memory area. */ | |
968d683c | 100 | isa_mmio_init(base + 0x03000000, 0x00100000); |
0027b06d PB |
101 | } |
102 | } | |
103 | ||
81a322d4 | 104 | static int pci_vpb_init(SysBusDevice *dev) |
0027b06d PB |
105 | { |
106 | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); | |
107 | PCIBus *bus; | |
97aff481 | 108 | int i; |
e69954b9 | 109 | |
97aff481 | 110 | for (i = 0; i < 4; i++) { |
0027b06d | 111 | sysbus_init_irq(dev, &s->irq[i]); |
e69954b9 | 112 | } |
02e2da45 PB |
113 | bus = pci_register_bus(&dev->qdev, "pci", |
114 | pci_vpb_set_irq, pci_vpb_map_irq, s->irq, | |
1e39101c | 115 | get_system_memory(), |
520128bd | 116 | PCI_DEVFN(11, 0), 4); |
0027b06d | 117 | |
502a5395 PB |
118 | /* ??? Register memory space. */ |
119 | ||
1eed09cb | 120 | s->mem_config = cpu_register_io_memory(pci_vpb_config_read, |
2507c12a | 121 | pci_vpb_config_write, bus, |
387c3e96 | 122 | DEVICE_LITTLE_ENDIAN); |
0027b06d | 123 | sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map); |
e69954b9 | 124 | |
0027b06d | 125 | pci_create_simple(bus, -1, "versatile_pci_host"); |
81a322d4 | 126 | return 0; |
0027b06d | 127 | } |
e69954b9 | 128 | |
81a322d4 | 129 | static int pci_realview_init(SysBusDevice *dev) |
0027b06d PB |
130 | { |
131 | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); | |
132 | s->realview = 1; | |
81a322d4 | 133 | return pci_vpb_init(dev); |
0027b06d | 134 | } |
502a5395 | 135 | |
81a322d4 | 136 | static int versatile_pci_host_init(PCIDevice *d) |
0027b06d | 137 | { |
a408b1de MT |
138 | pci_set_word(d->config + PCI_STATUS, |
139 | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); | |
01764fe0 | 140 | pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10); |
81a322d4 | 141 | return 0; |
0027b06d | 142 | } |
502a5395 | 143 | |
0aab0d3a GH |
144 | static PCIDeviceInfo versatile_pci_host_info = { |
145 | .qdev.name = "versatile_pci_host", | |
146 | .qdev.size = sizeof(PCIDevice), | |
147 | .init = versatile_pci_host_init, | |
56fe6408 IY |
148 | .vendor_id = PCI_VENDOR_ID_XILINX, |
149 | /* Both boards have the same device ID. Oh well. */ | |
150 | .device_id = PCI_DEVICE_ID_XILINX_XC2VP30, | |
151 | .class_id = PCI_CLASS_PROCESSOR_CO, | |
0aab0d3a GH |
152 | }; |
153 | ||
0027b06d PB |
154 | static void versatile_pci_register_devices(void) |
155 | { | |
156 | sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init); | |
157 | sysbus_register_dev("realview_pci", sizeof(PCIVPBState), | |
158 | pci_realview_init); | |
0aab0d3a | 159 | pci_qdev_register(&versatile_pci_host_info); |
502a5395 | 160 | } |
0027b06d PB |
161 | |
162 | device_init(versatile_pci_register_devices) |