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Commit | Line | Data |
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65501a74 AW |
1 | /* |
2 | * vfio based device assignment support | |
3 | * | |
4 | * Copyright Red Hat, Inc. 2012 | |
5 | * | |
6 | * Authors: | |
7 | * Alex Williamson <alex.williamson@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
12 | * Based on qemu-kvm device-assignment: | |
13 | * Adapted for KVM by Qumranet. | |
14 | * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) | |
15 | * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) | |
16 | * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) | |
17 | * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) | |
18 | * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) | |
19 | */ | |
20 | ||
c6eacb1a | 21 | #include "qemu/osdep.h" |
6dcfdbad | 22 | #include <linux/vfio.h> |
65501a74 | 23 | #include <sys/ioctl.h> |
65501a74 | 24 | |
83c9f4ca PB |
25 | #include "hw/pci/msi.h" |
26 | #include "hw/pci/msix.h" | |
0282abf0 | 27 | #include "hw/pci/pci_bridge.h" |
1de7afc9 | 28 | #include "qemu/error-report.h" |
1de7afc9 | 29 | #include "qemu/range.h" |
6dcfdbad AW |
30 | #include "sysemu/kvm.h" |
31 | #include "sysemu/sysemu.h" | |
78f33d2b | 32 | #include "pci.h" |
385f57cf | 33 | #include "trace.h" |
1108b2f8 | 34 | #include "qapi/error.h" |
4b943029 | 35 | |
65501a74 AW |
36 | #define MSIX_CAP_LENGTH 12 |
37 | ||
9ee27d73 | 38 | static void vfio_disable_interrupts(VFIOPCIDevice *vdev); |
9ee27d73 | 39 | static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); |
65501a74 | 40 | |
ea486926 AW |
41 | /* |
42 | * Disabling BAR mmaping can be slow, but toggling it around INTx can | |
43 | * also be a huge overhead. We try to get the best of both worlds by | |
44 | * waiting until an interrupt to disable mmaps (subsequent transitions | |
45 | * to the same state are effectively no overhead). If the interrupt has | |
46 | * been serviced and the time gap is long enough, we re-enable mmaps for | |
47 | * performance. This works well for things like graphics cards, which | |
48 | * may not use their interrupt at all and are penalized to an unusable | |
49 | * level by read/write BAR traps. Other devices, like NICs, have more | |
50 | * regular interrupts and see much better latency by staying in non-mmap | |
51 | * mode. We therefore set the default mmap_timeout such that a ping | |
52 | * is just enough to keep the mmap disabled. Users can experiment with | |
53 | * other options with the x-intx-mmap-timeout-ms parameter (a value of | |
54 | * zero disables the timer). | |
55 | */ | |
56 | static void vfio_intx_mmap_enable(void *opaque) | |
57 | { | |
9ee27d73 | 58 | VFIOPCIDevice *vdev = opaque; |
ea486926 AW |
59 | |
60 | if (vdev->intx.pending) { | |
bc72ad67 AB |
61 | timer_mod(vdev->intx.mmap_timer, |
62 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); | |
ea486926 AW |
63 | return; |
64 | } | |
65 | ||
66 | vfio_mmap_set_enabled(vdev, true); | |
67 | } | |
68 | ||
65501a74 AW |
69 | static void vfio_intx_interrupt(void *opaque) |
70 | { | |
9ee27d73 | 71 | VFIOPCIDevice *vdev = opaque; |
65501a74 AW |
72 | |
73 | if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { | |
74 | return; | |
75 | } | |
76 | ||
df92ee44 | 77 | trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); |
65501a74 AW |
78 | |
79 | vdev->intx.pending = true; | |
68919cac | 80 | pci_irq_assert(&vdev->pdev); |
ea486926 AW |
81 | vfio_mmap_set_enabled(vdev, false); |
82 | if (vdev->intx.mmap_timeout) { | |
bc72ad67 AB |
83 | timer_mod(vdev->intx.mmap_timer, |
84 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); | |
ea486926 | 85 | } |
65501a74 AW |
86 | } |
87 | ||
870cb6f1 | 88 | static void vfio_intx_eoi(VFIODevice *vbasedev) |
65501a74 | 89 | { |
a664477d EA |
90 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); |
91 | ||
65501a74 AW |
92 | if (!vdev->intx.pending) { |
93 | return; | |
94 | } | |
95 | ||
870cb6f1 | 96 | trace_vfio_intx_eoi(vbasedev->name); |
65501a74 AW |
97 | |
98 | vdev->intx.pending = false; | |
68919cac | 99 | pci_irq_deassert(&vdev->pdev); |
a664477d | 100 | vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
65501a74 AW |
101 | } |
102 | ||
7dfb3424 | 103 | static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp) |
e1d1e586 AW |
104 | { |
105 | #ifdef CONFIG_KVM | |
106 | struct kvm_irqfd irqfd = { | |
107 | .fd = event_notifier_get_fd(&vdev->intx.interrupt), | |
108 | .gsi = vdev->intx.route.irq, | |
109 | .flags = KVM_IRQFD_FLAG_RESAMPLE, | |
110 | }; | |
111 | struct vfio_irq_set *irq_set; | |
112 | int ret, argsz; | |
113 | int32_t *pfd; | |
114 | ||
46746dba | 115 | if (vdev->no_kvm_intx || !kvm_irqfds_enabled() || |
e1d1e586 | 116 | vdev->intx.route.mode != PCI_INTX_ENABLED || |
9fc0e2d8 | 117 | !kvm_resamplefds_enabled()) { |
e1d1e586 AW |
118 | return; |
119 | } | |
120 | ||
121 | /* Get to a known interrupt state */ | |
122 | qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); | |
5546a621 | 123 | vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 124 | vdev->intx.pending = false; |
68919cac | 125 | pci_irq_deassert(&vdev->pdev); |
e1d1e586 AW |
126 | |
127 | /* Get an eventfd for resample/unmask */ | |
128 | if (event_notifier_init(&vdev->intx.unmask, 0)) { | |
7dfb3424 | 129 | error_setg(errp, "event_notifier_init failed eoi"); |
e1d1e586 AW |
130 | goto fail; |
131 | } | |
132 | ||
133 | /* KVM triggers it, VFIO listens for it */ | |
134 | irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); | |
135 | ||
136 | if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { | |
7dfb3424 | 137 | error_setg_errno(errp, errno, "failed to setup resample irqfd"); |
e1d1e586 AW |
138 | goto fail_irqfd; |
139 | } | |
140 | ||
141 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
142 | ||
143 | irq_set = g_malloc0(argsz); | |
144 | irq_set->argsz = argsz; | |
145 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; | |
146 | irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; | |
147 | irq_set->start = 0; | |
148 | irq_set->count = 1; | |
149 | pfd = (int32_t *)&irq_set->data; | |
150 | ||
151 | *pfd = irqfd.resamplefd; | |
152 | ||
5546a621 | 153 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
e1d1e586 AW |
154 | g_free(irq_set); |
155 | if (ret) { | |
7dfb3424 | 156 | error_setg_errno(errp, -ret, "failed to setup INTx unmask fd"); |
e1d1e586 AW |
157 | goto fail_vfio; |
158 | } | |
159 | ||
160 | /* Let'em rip */ | |
5546a621 | 161 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 AW |
162 | |
163 | vdev->intx.kvm_accel = true; | |
164 | ||
870cb6f1 | 165 | trace_vfio_intx_enable_kvm(vdev->vbasedev.name); |
e1d1e586 AW |
166 | |
167 | return; | |
168 | ||
169 | fail_vfio: | |
170 | irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; | |
171 | kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); | |
172 | fail_irqfd: | |
173 | event_notifier_cleanup(&vdev->intx.unmask); | |
174 | fail: | |
175 | qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); | |
5546a621 | 176 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 AW |
177 | #endif |
178 | } | |
179 | ||
870cb6f1 | 180 | static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev) |
e1d1e586 AW |
181 | { |
182 | #ifdef CONFIG_KVM | |
183 | struct kvm_irqfd irqfd = { | |
184 | .fd = event_notifier_get_fd(&vdev->intx.interrupt), | |
185 | .gsi = vdev->intx.route.irq, | |
186 | .flags = KVM_IRQFD_FLAG_DEASSIGN, | |
187 | }; | |
188 | ||
189 | if (!vdev->intx.kvm_accel) { | |
190 | return; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Get to a known state, hardware masked, QEMU ready to accept new | |
195 | * interrupts, QEMU IRQ de-asserted. | |
196 | */ | |
5546a621 | 197 | vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 198 | vdev->intx.pending = false; |
68919cac | 199 | pci_irq_deassert(&vdev->pdev); |
e1d1e586 AW |
200 | |
201 | /* Tell KVM to stop listening for an INTx irqfd */ | |
202 | if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { | |
312fd5f2 | 203 | error_report("vfio: Error: Failed to disable INTx irqfd: %m"); |
e1d1e586 AW |
204 | } |
205 | ||
206 | /* We only need to close the eventfd for VFIO to cleanup the kernel side */ | |
207 | event_notifier_cleanup(&vdev->intx.unmask); | |
208 | ||
209 | /* QEMU starts listening for interrupt events. */ | |
210 | qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); | |
211 | ||
212 | vdev->intx.kvm_accel = false; | |
213 | ||
214 | /* If we've missed an event, let it re-fire through QEMU */ | |
5546a621 | 215 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 216 | |
870cb6f1 | 217 | trace_vfio_intx_disable_kvm(vdev->vbasedev.name); |
e1d1e586 AW |
218 | #endif |
219 | } | |
220 | ||
870cb6f1 | 221 | static void vfio_intx_update(PCIDevice *pdev) |
e1d1e586 | 222 | { |
9ee27d73 | 223 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
e1d1e586 | 224 | PCIINTxRoute route; |
7dfb3424 | 225 | Error *err = NULL; |
e1d1e586 AW |
226 | |
227 | if (vdev->interrupt != VFIO_INT_INTx) { | |
228 | return; | |
229 | } | |
230 | ||
231 | route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); | |
232 | ||
233 | if (!pci_intx_route_changed(&vdev->intx.route, &route)) { | |
234 | return; /* Nothing changed */ | |
235 | } | |
236 | ||
870cb6f1 AW |
237 | trace_vfio_intx_update(vdev->vbasedev.name, |
238 | vdev->intx.route.irq, route.irq); | |
e1d1e586 | 239 | |
870cb6f1 | 240 | vfio_intx_disable_kvm(vdev); |
e1d1e586 AW |
241 | |
242 | vdev->intx.route = route; | |
243 | ||
244 | if (route.mode != PCI_INTX_ENABLED) { | |
245 | return; | |
246 | } | |
247 | ||
7dfb3424 EA |
248 | vfio_intx_enable_kvm(vdev, &err); |
249 | if (err) { | |
250 | error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); | |
251 | } | |
e1d1e586 AW |
252 | |
253 | /* Re-enable the interrupt in cased we missed an EOI */ | |
870cb6f1 | 254 | vfio_intx_eoi(&vdev->vbasedev); |
e1d1e586 AW |
255 | } |
256 | ||
7dfb3424 | 257 | static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp) |
65501a74 | 258 | { |
65501a74 | 259 | uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); |
1a403133 AW |
260 | int ret, argsz; |
261 | struct vfio_irq_set *irq_set; | |
262 | int32_t *pfd; | |
7dfb3424 | 263 | Error *err = NULL; |
65501a74 | 264 | |
ea486926 | 265 | if (!pin) { |
65501a74 AW |
266 | return 0; |
267 | } | |
268 | ||
269 | vfio_disable_interrupts(vdev); | |
270 | ||
271 | vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ | |
68919cac | 272 | pci_config_set_interrupt_pin(vdev->pdev.config, pin); |
e1d1e586 AW |
273 | |
274 | #ifdef CONFIG_KVM | |
275 | /* | |
276 | * Only conditional to avoid generating error messages on platforms | |
277 | * where we won't actually use the result anyway. | |
278 | */ | |
9fc0e2d8 | 279 | if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { |
e1d1e586 AW |
280 | vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, |
281 | vdev->intx.pin); | |
282 | } | |
283 | #endif | |
284 | ||
65501a74 AW |
285 | ret = event_notifier_init(&vdev->intx.interrupt, 0); |
286 | if (ret) { | |
7dfb3424 | 287 | error_setg_errno(errp, -ret, "event_notifier_init failed"); |
65501a74 AW |
288 | return ret; |
289 | } | |
290 | ||
1a403133 AW |
291 | argsz = sizeof(*irq_set) + sizeof(*pfd); |
292 | ||
293 | irq_set = g_malloc0(argsz); | |
294 | irq_set->argsz = argsz; | |
295 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; | |
296 | irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; | |
297 | irq_set->start = 0; | |
298 | irq_set->count = 1; | |
299 | pfd = (int32_t *)&irq_set->data; | |
300 | ||
301 | *pfd = event_notifier_get_fd(&vdev->intx.interrupt); | |
302 | qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); | |
65501a74 | 303 | |
5546a621 | 304 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
1a403133 AW |
305 | g_free(irq_set); |
306 | if (ret) { | |
7dfb3424 | 307 | error_setg_errno(errp, -ret, "failed to setup INTx fd"); |
1a403133 | 308 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); |
ce59af2d | 309 | event_notifier_cleanup(&vdev->intx.interrupt); |
65501a74 AW |
310 | return -errno; |
311 | } | |
312 | ||
7dfb3424 EA |
313 | vfio_intx_enable_kvm(vdev, &err); |
314 | if (err) { | |
315 | error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); | |
316 | } | |
e1d1e586 | 317 | |
65501a74 AW |
318 | vdev->interrupt = VFIO_INT_INTx; |
319 | ||
870cb6f1 | 320 | trace_vfio_intx_enable(vdev->vbasedev.name); |
65501a74 AW |
321 | |
322 | return 0; | |
323 | } | |
324 | ||
870cb6f1 | 325 | static void vfio_intx_disable(VFIOPCIDevice *vdev) |
65501a74 AW |
326 | { |
327 | int fd; | |
328 | ||
bc72ad67 | 329 | timer_del(vdev->intx.mmap_timer); |
870cb6f1 | 330 | vfio_intx_disable_kvm(vdev); |
5546a621 | 331 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
65501a74 | 332 | vdev->intx.pending = false; |
68919cac | 333 | pci_irq_deassert(&vdev->pdev); |
65501a74 AW |
334 | vfio_mmap_set_enabled(vdev, true); |
335 | ||
336 | fd = event_notifier_get_fd(&vdev->intx.interrupt); | |
337 | qemu_set_fd_handler(fd, NULL, NULL, vdev); | |
338 | event_notifier_cleanup(&vdev->intx.interrupt); | |
339 | ||
340 | vdev->interrupt = VFIO_INT_NONE; | |
341 | ||
870cb6f1 | 342 | trace_vfio_intx_disable(vdev->vbasedev.name); |
65501a74 AW |
343 | } |
344 | ||
345 | /* | |
346 | * MSI/X | |
347 | */ | |
348 | static void vfio_msi_interrupt(void *opaque) | |
349 | { | |
350 | VFIOMSIVector *vector = opaque; | |
9ee27d73 | 351 | VFIOPCIDevice *vdev = vector->vdev; |
0de70dc7 AW |
352 | MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector); |
353 | void (*notify)(PCIDevice *dev, unsigned vector); | |
354 | MSIMessage msg; | |
65501a74 AW |
355 | int nr = vector - vdev->msi_vectors; |
356 | ||
357 | if (!event_notifier_test_and_clear(&vector->interrupt)) { | |
358 | return; | |
359 | } | |
360 | ||
b3ebc10c | 361 | if (vdev->interrupt == VFIO_INT_MSIX) { |
0de70dc7 AW |
362 | get_msg = msix_get_message; |
363 | notify = msix_notify; | |
95239e16 AW |
364 | |
365 | /* A masked vector firing needs to use the PBA, enable it */ | |
366 | if (msix_is_masked(&vdev->pdev, nr)) { | |
367 | set_bit(nr, vdev->msix->pending); | |
368 | memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true); | |
369 | trace_vfio_msix_pba_enable(vdev->vbasedev.name); | |
370 | } | |
9035f8c0 | 371 | } else if (vdev->interrupt == VFIO_INT_MSI) { |
0de70dc7 AW |
372 | get_msg = msi_get_message; |
373 | notify = msi_notify; | |
b3ebc10c AW |
374 | } else { |
375 | abort(); | |
376 | } | |
377 | ||
0de70dc7 | 378 | msg = get_msg(&vdev->pdev, nr); |
bc5baffa | 379 | trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); |
0de70dc7 | 380 | notify(&vdev->pdev, nr); |
65501a74 AW |
381 | } |
382 | ||
9ee27d73 | 383 | static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) |
65501a74 AW |
384 | { |
385 | struct vfio_irq_set *irq_set; | |
386 | int ret = 0, i, argsz; | |
387 | int32_t *fds; | |
388 | ||
389 | argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); | |
390 | ||
391 | irq_set = g_malloc0(argsz); | |
392 | irq_set->argsz = argsz; | |
393 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; | |
394 | irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; | |
395 | irq_set->start = 0; | |
396 | irq_set->count = vdev->nr_vectors; | |
397 | fds = (int32_t *)&irq_set->data; | |
398 | ||
399 | for (i = 0; i < vdev->nr_vectors; i++) { | |
c048be5c AW |
400 | int fd = -1; |
401 | ||
402 | /* | |
403 | * MSI vs MSI-X - The guest has direct access to MSI mask and pending | |
404 | * bits, therefore we always use the KVM signaling path when setup. | |
405 | * MSI-X mask and pending bits are emulated, so we want to use the | |
406 | * KVM signaling path only when configured and unmasked. | |
407 | */ | |
408 | if (vdev->msi_vectors[i].use) { | |
409 | if (vdev->msi_vectors[i].virq < 0 || | |
410 | (msix && msix_is_masked(&vdev->pdev, i))) { | |
411 | fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); | |
412 | } else { | |
413 | fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); | |
414 | } | |
65501a74 | 415 | } |
c048be5c AW |
416 | |
417 | fds[i] = fd; | |
65501a74 AW |
418 | } |
419 | ||
5546a621 | 420 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
65501a74 AW |
421 | |
422 | g_free(irq_set); | |
423 | ||
65501a74 AW |
424 | return ret; |
425 | } | |
426 | ||
46746dba | 427 | static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, |
d1f6af6a | 428 | int vector_n, bool msix) |
f4d45d47 AW |
429 | { |
430 | int virq; | |
431 | ||
d1f6af6a | 432 | if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) { |
f4d45d47 AW |
433 | return; |
434 | } | |
435 | ||
436 | if (event_notifier_init(&vector->kvm_interrupt, 0)) { | |
437 | return; | |
438 | } | |
439 | ||
d1f6af6a | 440 | virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev); |
f4d45d47 AW |
441 | if (virq < 0) { |
442 | event_notifier_cleanup(&vector->kvm_interrupt); | |
443 | return; | |
444 | } | |
445 | ||
1c9b71a7 | 446 | if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, |
f4d45d47 AW |
447 | NULL, virq) < 0) { |
448 | kvm_irqchip_release_virq(kvm_state, virq); | |
449 | event_notifier_cleanup(&vector->kvm_interrupt); | |
450 | return; | |
451 | } | |
452 | ||
f4d45d47 AW |
453 | vector->virq = virq; |
454 | } | |
455 | ||
456 | static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) | |
457 | { | |
1c9b71a7 EA |
458 | kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, |
459 | vector->virq); | |
f4d45d47 AW |
460 | kvm_irqchip_release_virq(kvm_state, vector->virq); |
461 | vector->virq = -1; | |
462 | event_notifier_cleanup(&vector->kvm_interrupt); | |
463 | } | |
464 | ||
dc9f06ca PF |
465 | static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg, |
466 | PCIDevice *pdev) | |
f4d45d47 | 467 | { |
dc9f06ca | 468 | kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev); |
3f1fea0f | 469 | kvm_irqchip_commit_routes(kvm_state); |
f4d45d47 AW |
470 | } |
471 | ||
b0223e29 AW |
472 | static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, |
473 | MSIMessage *msg, IOHandler *handler) | |
65501a74 | 474 | { |
9ee27d73 | 475 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 AW |
476 | VFIOMSIVector *vector; |
477 | int ret; | |
478 | ||
df92ee44 | 479 | trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); |
65501a74 | 480 | |
65501a74 | 481 | vector = &vdev->msi_vectors[nr]; |
65501a74 | 482 | |
f4d45d47 AW |
483 | if (!vector->use) { |
484 | vector->vdev = vdev; | |
485 | vector->virq = -1; | |
486 | if (event_notifier_init(&vector->interrupt, 0)) { | |
487 | error_report("vfio: Error: event_notifier_init failed"); | |
488 | } | |
489 | vector->use = true; | |
490 | msix_vector_use(pdev, nr); | |
65501a74 AW |
491 | } |
492 | ||
f4d45d47 AW |
493 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
494 | handler, NULL, vector); | |
495 | ||
65501a74 AW |
496 | /* |
497 | * Attempt to enable route through KVM irqchip, | |
498 | * default to userspace handling if unavailable. | |
499 | */ | |
f4d45d47 AW |
500 | if (vector->virq >= 0) { |
501 | if (!msg) { | |
502 | vfio_remove_kvm_msi_virq(vector); | |
503 | } else { | |
dc9f06ca | 504 | vfio_update_kvm_msi_virq(vector, *msg, pdev); |
65501a74 | 505 | } |
f4d45d47 | 506 | } else { |
6d17a018 DG |
507 | if (msg) { |
508 | vfio_add_kvm_msi_virq(vdev, vector, nr, true); | |
509 | } | |
65501a74 AW |
510 | } |
511 | ||
512 | /* | |
513 | * We don't want to have the host allocate all possible MSI vectors | |
514 | * for a device if they're not in use, so we shutdown and incrementally | |
515 | * increase them as needed. | |
516 | */ | |
517 | if (vdev->nr_vectors < nr + 1) { | |
5546a621 | 518 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); |
65501a74 AW |
519 | vdev->nr_vectors = nr + 1; |
520 | ret = vfio_enable_vectors(vdev, true); | |
521 | if (ret) { | |
312fd5f2 | 522 | error_report("vfio: failed to enable vectors, %d", ret); |
65501a74 | 523 | } |
65501a74 | 524 | } else { |
1a403133 AW |
525 | int argsz; |
526 | struct vfio_irq_set *irq_set; | |
527 | int32_t *pfd; | |
528 | ||
529 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
530 | ||
531 | irq_set = g_malloc0(argsz); | |
532 | irq_set->argsz = argsz; | |
533 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
534 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
535 | irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; | |
536 | irq_set->start = nr; | |
537 | irq_set->count = 1; | |
538 | pfd = (int32_t *)&irq_set->data; | |
539 | ||
f4d45d47 AW |
540 | if (vector->virq >= 0) { |
541 | *pfd = event_notifier_get_fd(&vector->kvm_interrupt); | |
542 | } else { | |
543 | *pfd = event_notifier_get_fd(&vector->interrupt); | |
544 | } | |
1a403133 | 545 | |
5546a621 | 546 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
1a403133 | 547 | g_free(irq_set); |
65501a74 | 548 | if (ret) { |
312fd5f2 | 549 | error_report("vfio: failed to modify vector, %d", ret); |
65501a74 | 550 | } |
65501a74 AW |
551 | } |
552 | ||
95239e16 AW |
553 | /* Disable PBA emulation when nothing more is pending. */ |
554 | clear_bit(nr, vdev->msix->pending); | |
555 | if (find_first_bit(vdev->msix->pending, | |
556 | vdev->nr_vectors) == vdev->nr_vectors) { | |
557 | memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); | |
558 | trace_vfio_msix_pba_disable(vdev->vbasedev.name); | |
559 | } | |
560 | ||
65501a74 AW |
561 | return 0; |
562 | } | |
563 | ||
b0223e29 AW |
564 | static int vfio_msix_vector_use(PCIDevice *pdev, |
565 | unsigned int nr, MSIMessage msg) | |
566 | { | |
567 | return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); | |
568 | } | |
569 | ||
65501a74 AW |
570 | static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) |
571 | { | |
9ee27d73 | 572 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 573 | VFIOMSIVector *vector = &vdev->msi_vectors[nr]; |
65501a74 | 574 | |
df92ee44 | 575 | trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); |
65501a74 AW |
576 | |
577 | /* | |
f4d45d47 AW |
578 | * There are still old guests that mask and unmask vectors on every |
579 | * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of | |
580 | * the KVM setup in place, simply switch VFIO to use the non-bypass | |
581 | * eventfd. We'll then fire the interrupt through QEMU and the MSI-X | |
582 | * core will mask the interrupt and set pending bits, allowing it to | |
583 | * be re-asserted on unmask. Nothing to do if already using QEMU mode. | |
65501a74 | 584 | */ |
f4d45d47 AW |
585 | if (vector->virq >= 0) { |
586 | int argsz; | |
587 | struct vfio_irq_set *irq_set; | |
588 | int32_t *pfd; | |
1a403133 | 589 | |
f4d45d47 | 590 | argsz = sizeof(*irq_set) + sizeof(*pfd); |
1a403133 | 591 | |
f4d45d47 AW |
592 | irq_set = g_malloc0(argsz); |
593 | irq_set->argsz = argsz; | |
594 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
595 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
596 | irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; | |
597 | irq_set->start = nr; | |
598 | irq_set->count = 1; | |
599 | pfd = (int32_t *)&irq_set->data; | |
1a403133 | 600 | |
f4d45d47 | 601 | *pfd = event_notifier_get_fd(&vector->interrupt); |
1a403133 | 602 | |
5546a621 | 603 | ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
65501a74 | 604 | |
f4d45d47 | 605 | g_free(irq_set); |
65501a74 | 606 | } |
65501a74 AW |
607 | } |
608 | ||
0de70dc7 | 609 | static void vfio_msix_enable(VFIOPCIDevice *vdev) |
fd704adc AW |
610 | { |
611 | vfio_disable_interrupts(vdev); | |
612 | ||
bdd81add | 613 | vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); |
fd704adc AW |
614 | |
615 | vdev->interrupt = VFIO_INT_MSIX; | |
616 | ||
b0223e29 AW |
617 | /* |
618 | * Some communication channels between VF & PF or PF & fw rely on the | |
619 | * physical state of the device and expect that enabling MSI-X from the | |
620 | * guest enables the same on the host. When our guest is Linux, the | |
621 | * guest driver call to pci_enable_msix() sets the enabling bit in the | |
622 | * MSI-X capability, but leaves the vector table masked. We therefore | |
623 | * can't rely on a vector_use callback (from request_irq() in the guest) | |
624 | * to switch the physical device into MSI-X mode because that may come a | |
625 | * long time after pci_enable_msix(). This code enables vector 0 with | |
626 | * triggering to userspace, then immediately release the vector, leaving | |
627 | * the physical device with no vectors enabled, but MSI-X enabled, just | |
628 | * like the guest view. | |
629 | */ | |
630 | vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); | |
631 | vfio_msix_vector_release(&vdev->pdev, 0); | |
632 | ||
fd704adc | 633 | if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, |
bbef882c | 634 | vfio_msix_vector_release, NULL)) { |
312fd5f2 | 635 | error_report("vfio: msix_set_vector_notifiers failed"); |
fd704adc AW |
636 | } |
637 | ||
0de70dc7 | 638 | trace_vfio_msix_enable(vdev->vbasedev.name); |
fd704adc AW |
639 | } |
640 | ||
0de70dc7 | 641 | static void vfio_msi_enable(VFIOPCIDevice *vdev) |
65501a74 AW |
642 | { |
643 | int ret, i; | |
644 | ||
645 | vfio_disable_interrupts(vdev); | |
646 | ||
647 | vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); | |
648 | retry: | |
bdd81add | 649 | vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors); |
65501a74 AW |
650 | |
651 | for (i = 0; i < vdev->nr_vectors; i++) { | |
65501a74 AW |
652 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; |
653 | ||
654 | vector->vdev = vdev; | |
f4d45d47 | 655 | vector->virq = -1; |
65501a74 AW |
656 | vector->use = true; |
657 | ||
658 | if (event_notifier_init(&vector->interrupt, 0)) { | |
312fd5f2 | 659 | error_report("vfio: Error: event_notifier_init failed"); |
65501a74 AW |
660 | } |
661 | ||
f4d45d47 AW |
662 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
663 | vfio_msi_interrupt, NULL, vector); | |
664 | ||
65501a74 AW |
665 | /* |
666 | * Attempt to enable route through KVM irqchip, | |
667 | * default to userspace handling if unavailable. | |
668 | */ | |
d1f6af6a | 669 | vfio_add_kvm_msi_virq(vdev, vector, i, false); |
65501a74 AW |
670 | } |
671 | ||
f4d45d47 AW |
672 | /* Set interrupt type prior to possible interrupts */ |
673 | vdev->interrupt = VFIO_INT_MSI; | |
674 | ||
65501a74 AW |
675 | ret = vfio_enable_vectors(vdev, false); |
676 | if (ret) { | |
677 | if (ret < 0) { | |
312fd5f2 | 678 | error_report("vfio: Error: Failed to setup MSI fds: %m"); |
65501a74 AW |
679 | } else if (ret != vdev->nr_vectors) { |
680 | error_report("vfio: Error: Failed to enable %d " | |
312fd5f2 | 681 | "MSI vectors, retry with %d", vdev->nr_vectors, ret); |
65501a74 AW |
682 | } |
683 | ||
684 | for (i = 0; i < vdev->nr_vectors; i++) { | |
685 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
686 | if (vector->virq >= 0) { | |
f4d45d47 | 687 | vfio_remove_kvm_msi_virq(vector); |
65501a74 | 688 | } |
f4d45d47 AW |
689 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
690 | NULL, NULL, NULL); | |
65501a74 AW |
691 | event_notifier_cleanup(&vector->interrupt); |
692 | } | |
693 | ||
694 | g_free(vdev->msi_vectors); | |
695 | ||
696 | if (ret > 0 && ret != vdev->nr_vectors) { | |
697 | vdev->nr_vectors = ret; | |
698 | goto retry; | |
699 | } | |
700 | vdev->nr_vectors = 0; | |
701 | ||
f4d45d47 AW |
702 | /* |
703 | * Failing to setup MSI doesn't really fall within any specification. | |
704 | * Let's try leaving interrupts disabled and hope the guest figures | |
705 | * out to fall back to INTx for this device. | |
706 | */ | |
707 | error_report("vfio: Error: Failed to enable MSI"); | |
708 | vdev->interrupt = VFIO_INT_NONE; | |
709 | ||
65501a74 AW |
710 | return; |
711 | } | |
712 | ||
0de70dc7 | 713 | trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors); |
65501a74 AW |
714 | } |
715 | ||
0de70dc7 | 716 | static void vfio_msi_disable_common(VFIOPCIDevice *vdev) |
fd704adc | 717 | { |
7dfb3424 | 718 | Error *err = NULL; |
f4d45d47 AW |
719 | int i; |
720 | ||
721 | for (i = 0; i < vdev->nr_vectors; i++) { | |
722 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
723 | if (vdev->msi_vectors[i].use) { | |
724 | if (vector->virq >= 0) { | |
725 | vfio_remove_kvm_msi_virq(vector); | |
726 | } | |
727 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), | |
728 | NULL, NULL, NULL); | |
729 | event_notifier_cleanup(&vector->interrupt); | |
730 | } | |
731 | } | |
732 | ||
fd704adc AW |
733 | g_free(vdev->msi_vectors); |
734 | vdev->msi_vectors = NULL; | |
735 | vdev->nr_vectors = 0; | |
736 | vdev->interrupt = VFIO_INT_NONE; | |
737 | ||
7dfb3424 EA |
738 | vfio_intx_enable(vdev, &err); |
739 | if (err) { | |
740 | error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); | |
741 | } | |
fd704adc AW |
742 | } |
743 | ||
0de70dc7 | 744 | static void vfio_msix_disable(VFIOPCIDevice *vdev) |
fd704adc | 745 | { |
3e40ba0f AW |
746 | int i; |
747 | ||
fd704adc AW |
748 | msix_unset_vector_notifiers(&vdev->pdev); |
749 | ||
3e40ba0f AW |
750 | /* |
751 | * MSI-X will only release vectors if MSI-X is still enabled on the | |
752 | * device, check through the rest and release it ourselves if necessary. | |
753 | */ | |
754 | for (i = 0; i < vdev->nr_vectors; i++) { | |
755 | if (vdev->msi_vectors[i].use) { | |
756 | vfio_msix_vector_release(&vdev->pdev, i); | |
f4d45d47 | 757 | msix_vector_unuse(&vdev->pdev, i); |
3e40ba0f AW |
758 | } |
759 | } | |
760 | ||
fd704adc | 761 | if (vdev->nr_vectors) { |
5546a621 | 762 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); |
fd704adc AW |
763 | } |
764 | ||
0de70dc7 | 765 | vfio_msi_disable_common(vdev); |
fd704adc | 766 | |
95239e16 AW |
767 | memset(vdev->msix->pending, 0, |
768 | BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); | |
769 | ||
0de70dc7 | 770 | trace_vfio_msix_disable(vdev->vbasedev.name); |
fd704adc AW |
771 | } |
772 | ||
0de70dc7 | 773 | static void vfio_msi_disable(VFIOPCIDevice *vdev) |
65501a74 | 774 | { |
5546a621 | 775 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); |
0de70dc7 | 776 | vfio_msi_disable_common(vdev); |
65501a74 | 777 | |
0de70dc7 | 778 | trace_vfio_msi_disable(vdev->vbasedev.name); |
65501a74 AW |
779 | } |
780 | ||
9ee27d73 | 781 | static void vfio_update_msi(VFIOPCIDevice *vdev) |
c7679d45 AW |
782 | { |
783 | int i; | |
784 | ||
785 | for (i = 0; i < vdev->nr_vectors; i++) { | |
786 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
787 | MSIMessage msg; | |
788 | ||
789 | if (!vector->use || vector->virq < 0) { | |
790 | continue; | |
791 | } | |
792 | ||
793 | msg = msi_get_message(&vdev->pdev, i); | |
dc9f06ca | 794 | vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev); |
c7679d45 AW |
795 | } |
796 | } | |
797 | ||
9ee27d73 | 798 | static void vfio_pci_load_rom(VFIOPCIDevice *vdev) |
6f864e6e | 799 | { |
46900226 | 800 | struct vfio_region_info *reg_info; |
6f864e6e AW |
801 | uint64_t size; |
802 | off_t off = 0; | |
7d489dcd | 803 | ssize_t bytes; |
6f864e6e | 804 | |
46900226 AW |
805 | if (vfio_get_region_info(&vdev->vbasedev, |
806 | VFIO_PCI_ROM_REGION_INDEX, ®_info)) { | |
6f864e6e AW |
807 | error_report("vfio: Error getting ROM info: %m"); |
808 | return; | |
809 | } | |
810 | ||
46900226 AW |
811 | trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size, |
812 | (unsigned long)reg_info->offset, | |
813 | (unsigned long)reg_info->flags); | |
814 | ||
815 | vdev->rom_size = size = reg_info->size; | |
816 | vdev->rom_offset = reg_info->offset; | |
6f864e6e | 817 | |
46900226 | 818 | g_free(reg_info); |
6f864e6e AW |
819 | |
820 | if (!vdev->rom_size) { | |
e638073c | 821 | vdev->rom_read_failed = true; |
d20b43df | 822 | error_report("vfio-pci: Cannot read device rom at " |
df92ee44 | 823 | "%s", vdev->vbasedev.name); |
d20b43df BD |
824 | error_printf("Device option ROM contents are probably invalid " |
825 | "(check dmesg).\nSkip option ROM probe with rombar=0, " | |
826 | "or load from file with romfile=\n"); | |
6f864e6e AW |
827 | return; |
828 | } | |
829 | ||
830 | vdev->rom = g_malloc(size); | |
831 | memset(vdev->rom, 0xff, size); | |
832 | ||
833 | while (size) { | |
5546a621 EA |
834 | bytes = pread(vdev->vbasedev.fd, vdev->rom + off, |
835 | size, vdev->rom_offset + off); | |
6f864e6e AW |
836 | if (bytes == 0) { |
837 | break; | |
838 | } else if (bytes > 0) { | |
839 | off += bytes; | |
840 | size -= bytes; | |
841 | } else { | |
842 | if (errno == EINTR || errno == EAGAIN) { | |
843 | continue; | |
844 | } | |
845 | error_report("vfio: Error reading device ROM: %m"); | |
846 | break; | |
847 | } | |
848 | } | |
e2e5ee9c AW |
849 | |
850 | /* | |
851 | * Test the ROM signature against our device, if the vendor is correct | |
852 | * but the device ID doesn't match, store the correct device ID and | |
853 | * recompute the checksum. Intel IGD devices need this and are known | |
854 | * to have bogus checksums so we can't simply adjust the checksum. | |
855 | */ | |
856 | if (pci_get_word(vdev->rom) == 0xaa55 && | |
857 | pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size && | |
858 | !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) { | |
859 | uint16_t vid, did; | |
860 | ||
861 | vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4); | |
862 | did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6); | |
863 | ||
864 | if (vid == vdev->vendor_id && did != vdev->device_id) { | |
865 | int i; | |
866 | uint8_t csum, *data = vdev->rom; | |
867 | ||
868 | pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6, | |
869 | vdev->device_id); | |
870 | data[6] = 0; | |
871 | ||
872 | for (csum = 0, i = 0; i < vdev->rom_size; i++) { | |
873 | csum += data[i]; | |
874 | } | |
875 | ||
876 | data[6] = -csum; | |
877 | } | |
878 | } | |
6f864e6e AW |
879 | } |
880 | ||
881 | static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) | |
882 | { | |
9ee27d73 | 883 | VFIOPCIDevice *vdev = opaque; |
75bd0c72 ND |
884 | union { |
885 | uint8_t byte; | |
886 | uint16_t word; | |
887 | uint32_t dword; | |
888 | uint64_t qword; | |
889 | } val; | |
890 | uint64_t data = 0; | |
6f864e6e AW |
891 | |
892 | /* Load the ROM lazily when the guest tries to read it */ | |
db01eedb | 893 | if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { |
6f864e6e AW |
894 | vfio_pci_load_rom(vdev); |
895 | } | |
896 | ||
6758008e | 897 | memcpy(&val, vdev->rom + addr, |
6f864e6e AW |
898 | (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); |
899 | ||
75bd0c72 ND |
900 | switch (size) { |
901 | case 1: | |
902 | data = val.byte; | |
903 | break; | |
904 | case 2: | |
905 | data = le16_to_cpu(val.word); | |
906 | break; | |
907 | case 4: | |
908 | data = le32_to_cpu(val.dword); | |
909 | break; | |
910 | default: | |
911 | hw_error("vfio: unsupported read size, %d bytes\n", size); | |
912 | break; | |
913 | } | |
914 | ||
df92ee44 | 915 | trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); |
6f864e6e | 916 | |
75bd0c72 | 917 | return data; |
6f864e6e AW |
918 | } |
919 | ||
64fa25a0 AW |
920 | static void vfio_rom_write(void *opaque, hwaddr addr, |
921 | uint64_t data, unsigned size) | |
922 | { | |
923 | } | |
924 | ||
6f864e6e AW |
925 | static const MemoryRegionOps vfio_rom_ops = { |
926 | .read = vfio_rom_read, | |
64fa25a0 | 927 | .write = vfio_rom_write, |
6758008e | 928 | .endianness = DEVICE_LITTLE_ENDIAN, |
6f864e6e AW |
929 | }; |
930 | ||
9ee27d73 | 931 | static void vfio_pci_size_rom(VFIOPCIDevice *vdev) |
6f864e6e | 932 | { |
b1c50c5f | 933 | uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); |
6f864e6e | 934 | off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; |
4b943029 | 935 | DeviceState *dev = DEVICE(vdev); |
062ed5d8 | 936 | char *name; |
5546a621 | 937 | int fd = vdev->vbasedev.fd; |
6f864e6e AW |
938 | |
939 | if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { | |
4b943029 BD |
940 | /* Since pci handles romfile, just print a message and return */ |
941 | if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { | |
7df9381b AW |
942 | error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified romfile\n", |
943 | vdev->vbasedev.name); | |
4b943029 | 944 | } |
6f864e6e AW |
945 | return; |
946 | } | |
947 | ||
948 | /* | |
949 | * Use the same size ROM BAR as the physical device. The contents | |
950 | * will get filled in later when the guest tries to read it. | |
951 | */ | |
5546a621 EA |
952 | if (pread(fd, &orig, 4, offset) != 4 || |
953 | pwrite(fd, &size, 4, offset) != 4 || | |
954 | pread(fd, &size, 4, offset) != 4 || | |
955 | pwrite(fd, &orig, 4, offset) != 4) { | |
7df9381b | 956 | error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name); |
6f864e6e AW |
957 | return; |
958 | } | |
959 | ||
b1c50c5f | 960 | size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; |
6f864e6e AW |
961 | |
962 | if (!size) { | |
963 | return; | |
964 | } | |
965 | ||
4b943029 BD |
966 | if (vfio_blacklist_opt_rom(vdev)) { |
967 | if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { | |
7df9381b AW |
968 | error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified non zero value for rombar\n", |
969 | vdev->vbasedev.name); | |
4b943029 | 970 | } else { |
7df9381b AW |
971 | error_printf("Warning : Rom loading for device at %s has been disabled due to system instability issues. Specify rombar=1 or romfile to force\n", |
972 | vdev->vbasedev.name); | |
4b943029 BD |
973 | return; |
974 | } | |
975 | } | |
976 | ||
df92ee44 | 977 | trace_vfio_pci_size_rom(vdev->vbasedev.name, size); |
6f864e6e | 978 | |
062ed5d8 | 979 | name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name); |
6f864e6e AW |
980 | |
981 | memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), | |
982 | &vfio_rom_ops, vdev, name, size); | |
062ed5d8 | 983 | g_free(name); |
6f864e6e AW |
984 | |
985 | pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, | |
986 | PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); | |
987 | ||
988 | vdev->pdev.has_rom = true; | |
e638073c | 989 | vdev->rom_read_failed = false; |
6f864e6e AW |
990 | } |
991 | ||
c00d61d8 | 992 | void vfio_vga_write(void *opaque, hwaddr addr, |
f15689c7 AW |
993 | uint64_t data, unsigned size) |
994 | { | |
995 | VFIOVGARegion *region = opaque; | |
996 | VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); | |
997 | union { | |
998 | uint8_t byte; | |
999 | uint16_t word; | |
1000 | uint32_t dword; | |
1001 | uint64_t qword; | |
1002 | } buf; | |
1003 | off_t offset = vga->fd_offset + region->offset + addr; | |
1004 | ||
1005 | switch (size) { | |
1006 | case 1: | |
1007 | buf.byte = data; | |
1008 | break; | |
1009 | case 2: | |
1010 | buf.word = cpu_to_le16(data); | |
1011 | break; | |
1012 | case 4: | |
1013 | buf.dword = cpu_to_le32(data); | |
1014 | break; | |
1015 | default: | |
4e505ddd | 1016 | hw_error("vfio: unsupported write size, %d bytes", size); |
f15689c7 AW |
1017 | break; |
1018 | } | |
1019 | ||
1020 | if (pwrite(vga->fd, &buf, size, offset) != size) { | |
1021 | error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", | |
1022 | __func__, region->offset + addr, data, size); | |
1023 | } | |
1024 | ||
385f57cf | 1025 | trace_vfio_vga_write(region->offset + addr, data, size); |
f15689c7 AW |
1026 | } |
1027 | ||
c00d61d8 | 1028 | uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) |
f15689c7 AW |
1029 | { |
1030 | VFIOVGARegion *region = opaque; | |
1031 | VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); | |
1032 | union { | |
1033 | uint8_t byte; | |
1034 | uint16_t word; | |
1035 | uint32_t dword; | |
1036 | uint64_t qword; | |
1037 | } buf; | |
1038 | uint64_t data = 0; | |
1039 | off_t offset = vga->fd_offset + region->offset + addr; | |
1040 | ||
1041 | if (pread(vga->fd, &buf, size, offset) != size) { | |
1042 | error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", | |
1043 | __func__, region->offset + addr, size); | |
1044 | return (uint64_t)-1; | |
1045 | } | |
1046 | ||
1047 | switch (size) { | |
1048 | case 1: | |
1049 | data = buf.byte; | |
1050 | break; | |
1051 | case 2: | |
1052 | data = le16_to_cpu(buf.word); | |
1053 | break; | |
1054 | case 4: | |
1055 | data = le32_to_cpu(buf.dword); | |
1056 | break; | |
1057 | default: | |
4e505ddd | 1058 | hw_error("vfio: unsupported read size, %d bytes", size); |
f15689c7 AW |
1059 | break; |
1060 | } | |
1061 | ||
385f57cf | 1062 | trace_vfio_vga_read(region->offset + addr, size, data); |
f15689c7 AW |
1063 | |
1064 | return data; | |
1065 | } | |
1066 | ||
1067 | static const MemoryRegionOps vfio_vga_ops = { | |
1068 | .read = vfio_vga_read, | |
1069 | .write = vfio_vga_write, | |
1070 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1071 | }; | |
1072 | ||
65501a74 AW |
1073 | /* |
1074 | * PCI config space | |
1075 | */ | |
c00d61d8 | 1076 | uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) |
65501a74 | 1077 | { |
9ee27d73 | 1078 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
4b5d5e87 | 1079 | uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; |
65501a74 | 1080 | |
4b5d5e87 AW |
1081 | memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); |
1082 | emu_bits = le32_to_cpu(emu_bits); | |
65501a74 | 1083 | |
4b5d5e87 AW |
1084 | if (emu_bits) { |
1085 | emu_val = pci_default_read_config(pdev, addr, len); | |
1086 | } | |
1087 | ||
1088 | if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { | |
1089 | ssize_t ret; | |
1090 | ||
5546a621 EA |
1091 | ret = pread(vdev->vbasedev.fd, &phys_val, len, |
1092 | vdev->config_offset + addr); | |
4b5d5e87 | 1093 | if (ret != len) { |
7df9381b AW |
1094 | error_report("%s(%s, 0x%x, 0x%x) failed: %m", |
1095 | __func__, vdev->vbasedev.name, addr, len); | |
65501a74 AW |
1096 | return -errno; |
1097 | } | |
4b5d5e87 | 1098 | phys_val = le32_to_cpu(phys_val); |
65501a74 AW |
1099 | } |
1100 | ||
4b5d5e87 | 1101 | val = (emu_val & emu_bits) | (phys_val & ~emu_bits); |
65501a74 | 1102 | |
df92ee44 | 1103 | trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); |
65501a74 AW |
1104 | |
1105 | return val; | |
1106 | } | |
1107 | ||
c00d61d8 AW |
1108 | void vfio_pci_write_config(PCIDevice *pdev, |
1109 | uint32_t addr, uint32_t val, int len) | |
65501a74 | 1110 | { |
9ee27d73 | 1111 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 AW |
1112 | uint32_t val_le = cpu_to_le32(val); |
1113 | ||
df92ee44 | 1114 | trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); |
65501a74 AW |
1115 | |
1116 | /* Write everything to VFIO, let it filter out what we can't write */ | |
5546a621 EA |
1117 | if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) |
1118 | != len) { | |
7df9381b AW |
1119 | error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m", |
1120 | __func__, vdev->vbasedev.name, addr, val, len); | |
65501a74 AW |
1121 | } |
1122 | ||
65501a74 AW |
1123 | /* MSI/MSI-X Enabling/Disabling */ |
1124 | if (pdev->cap_present & QEMU_PCI_CAP_MSI && | |
1125 | ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { | |
1126 | int is_enabled, was_enabled = msi_enabled(pdev); | |
1127 | ||
1128 | pci_default_write_config(pdev, addr, val, len); | |
1129 | ||
1130 | is_enabled = msi_enabled(pdev); | |
1131 | ||
c7679d45 AW |
1132 | if (!was_enabled) { |
1133 | if (is_enabled) { | |
0de70dc7 | 1134 | vfio_msi_enable(vdev); |
c7679d45 AW |
1135 | } |
1136 | } else { | |
1137 | if (!is_enabled) { | |
0de70dc7 | 1138 | vfio_msi_disable(vdev); |
c7679d45 AW |
1139 | } else { |
1140 | vfio_update_msi(vdev); | |
1141 | } | |
65501a74 | 1142 | } |
4b5d5e87 | 1143 | } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && |
65501a74 AW |
1144 | ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { |
1145 | int is_enabled, was_enabled = msix_enabled(pdev); | |
1146 | ||
1147 | pci_default_write_config(pdev, addr, val, len); | |
1148 | ||
1149 | is_enabled = msix_enabled(pdev); | |
1150 | ||
1151 | if (!was_enabled && is_enabled) { | |
0de70dc7 | 1152 | vfio_msix_enable(vdev); |
65501a74 | 1153 | } else if (was_enabled && !is_enabled) { |
0de70dc7 | 1154 | vfio_msix_disable(vdev); |
65501a74 | 1155 | } |
4b5d5e87 AW |
1156 | } else { |
1157 | /* Write everything to QEMU to keep emulated bits correct */ | |
1158 | pci_default_write_config(pdev, addr, val, len); | |
65501a74 AW |
1159 | } |
1160 | } | |
1161 | ||
65501a74 AW |
1162 | /* |
1163 | * Interrupt setup | |
1164 | */ | |
9ee27d73 | 1165 | static void vfio_disable_interrupts(VFIOPCIDevice *vdev) |
65501a74 | 1166 | { |
b3e27c3a AW |
1167 | /* |
1168 | * More complicated than it looks. Disabling MSI/X transitions the | |
1169 | * device to INTx mode (if supported). Therefore we need to first | |
1170 | * disable MSI/X and then cleanup by disabling INTx. | |
1171 | */ | |
1172 | if (vdev->interrupt == VFIO_INT_MSIX) { | |
0de70dc7 | 1173 | vfio_msix_disable(vdev); |
b3e27c3a | 1174 | } else if (vdev->interrupt == VFIO_INT_MSI) { |
0de70dc7 | 1175 | vfio_msi_disable(vdev); |
b3e27c3a AW |
1176 | } |
1177 | ||
1178 | if (vdev->interrupt == VFIO_INT_INTx) { | |
870cb6f1 | 1179 | vfio_intx_disable(vdev); |
65501a74 AW |
1180 | } |
1181 | } | |
1182 | ||
7ef165b9 | 1183 | static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) |
65501a74 AW |
1184 | { |
1185 | uint16_t ctrl; | |
1186 | bool msi_64bit, msi_maskbit; | |
1187 | int ret, entries; | |
1108b2f8 | 1188 | Error *err = NULL; |
65501a74 | 1189 | |
5546a621 | 1190 | if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), |
65501a74 | 1191 | vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { |
7ef165b9 | 1192 | error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS"); |
65501a74 AW |
1193 | return -errno; |
1194 | } | |
1195 | ctrl = le16_to_cpu(ctrl); | |
1196 | ||
1197 | msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); | |
1198 | msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); | |
1199 | entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); | |
1200 | ||
0de70dc7 | 1201 | trace_vfio_msi_setup(vdev->vbasedev.name, pos); |
65501a74 | 1202 | |
1108b2f8 | 1203 | ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err); |
65501a74 | 1204 | if (ret < 0) { |
e43b9a5a AW |
1205 | if (ret == -ENOTSUP) { |
1206 | return 0; | |
1207 | } | |
7ef165b9 EA |
1208 | error_prepend(&err, "msi_init failed: "); |
1209 | error_propagate(errp, err); | |
65501a74 AW |
1210 | return ret; |
1211 | } | |
1212 | vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
db0da029 AW |
1217 | static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev) |
1218 | { | |
1219 | off_t start, end; | |
1220 | VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region; | |
1221 | ||
1222 | /* | |
1223 | * We expect to find a single mmap covering the whole BAR, anything else | |
1224 | * means it's either unsupported or already setup. | |
1225 | */ | |
1226 | if (region->nr_mmaps != 1 || region->mmaps[0].offset || | |
1227 | region->size != region->mmaps[0].size) { | |
1228 | return; | |
1229 | } | |
1230 | ||
1231 | /* MSI-X table start and end aligned to host page size */ | |
1232 | start = vdev->msix->table_offset & qemu_real_host_page_mask; | |
1233 | end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + | |
1234 | (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); | |
1235 | ||
1236 | /* | |
1237 | * Does the MSI-X table cover the beginning of the BAR? The whole BAR? | |
1238 | * NB - Host page size is necessarily a power of two and so is the PCI | |
1239 | * BAR (not counting EA yet), therefore if we have host page aligned | |
1240 | * @start and @end, then any remainder of the BAR before or after those | |
1241 | * must be at least host page sized and therefore mmap'able. | |
1242 | */ | |
1243 | if (!start) { | |
1244 | if (end >= region->size) { | |
1245 | region->nr_mmaps = 0; | |
1246 | g_free(region->mmaps); | |
1247 | region->mmaps = NULL; | |
1248 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1249 | vdev->msix->table_bar, 0, 0); | |
1250 | } else { | |
1251 | region->mmaps[0].offset = end; | |
1252 | region->mmaps[0].size = region->size - end; | |
1253 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1254 | vdev->msix->table_bar, region->mmaps[0].offset, | |
1255 | region->mmaps[0].offset + region->mmaps[0].size); | |
1256 | } | |
1257 | ||
1258 | /* Maybe it's aligned at the end of the BAR */ | |
1259 | } else if (end >= region->size) { | |
1260 | region->mmaps[0].size = start; | |
1261 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1262 | vdev->msix->table_bar, region->mmaps[0].offset, | |
1263 | region->mmaps[0].offset + region->mmaps[0].size); | |
1264 | ||
1265 | /* Otherwise it must split the BAR */ | |
1266 | } else { | |
1267 | region->nr_mmaps = 2; | |
1268 | region->mmaps = g_renew(VFIOMmap, region->mmaps, 2); | |
1269 | ||
1270 | memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap)); | |
1271 | ||
1272 | region->mmaps[0].size = start; | |
1273 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1274 | vdev->msix->table_bar, region->mmaps[0].offset, | |
1275 | region->mmaps[0].offset + region->mmaps[0].size); | |
1276 | ||
1277 | region->mmaps[1].offset = end; | |
1278 | region->mmaps[1].size = region->size - end; | |
1279 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1280 | vdev->msix->table_bar, region->mmaps[1].offset, | |
1281 | region->mmaps[1].offset + region->mmaps[1].size); | |
1282 | } | |
1283 | } | |
1284 | ||
65501a74 AW |
1285 | /* |
1286 | * We don't have any control over how pci_add_capability() inserts | |
1287 | * capabilities into the chain. In order to setup MSI-X we need a | |
1288 | * MemoryRegion for the BAR. In order to setup the BAR and not | |
1289 | * attempt to mmap the MSI-X table area, which VFIO won't allow, we | |
1290 | * need to first look for where the MSI-X table lives. So we | |
1291 | * unfortunately split MSI-X setup across two functions. | |
1292 | */ | |
008d0e2d | 1293 | static int vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp) |
65501a74 AW |
1294 | { |
1295 | uint8_t pos; | |
1296 | uint16_t ctrl; | |
1297 | uint32_t table, pba; | |
5546a621 | 1298 | int fd = vdev->vbasedev.fd; |
b5bd049f | 1299 | VFIOMSIXInfo *msix; |
65501a74 AW |
1300 | |
1301 | pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); | |
1302 | if (!pos) { | |
1303 | return 0; | |
1304 | } | |
1305 | ||
5546a621 | 1306 | if (pread(fd, &ctrl, sizeof(ctrl), |
b58b17f7 | 1307 | vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) { |
008d0e2d | 1308 | error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS"); |
65501a74 AW |
1309 | return -errno; |
1310 | } | |
1311 | ||
5546a621 | 1312 | if (pread(fd, &table, sizeof(table), |
65501a74 | 1313 | vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { |
008d0e2d | 1314 | error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE"); |
65501a74 AW |
1315 | return -errno; |
1316 | } | |
1317 | ||
5546a621 | 1318 | if (pread(fd, &pba, sizeof(pba), |
65501a74 | 1319 | vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { |
008d0e2d | 1320 | error_setg_errno(errp, errno, "failed to read PCI MSIX PBA"); |
65501a74 AW |
1321 | return -errno; |
1322 | } | |
1323 | ||
1324 | ctrl = le16_to_cpu(ctrl); | |
1325 | table = le32_to_cpu(table); | |
1326 | pba = le32_to_cpu(pba); | |
1327 | ||
b5bd049f AW |
1328 | msix = g_malloc0(sizeof(*msix)); |
1329 | msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; | |
1330 | msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; | |
1331 | msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; | |
1332 | msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; | |
1333 | msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
65501a74 | 1334 | |
43302969 GL |
1335 | /* |
1336 | * Test the size of the pba_offset variable and catch if it extends outside | |
1337 | * of the specified BAR. If it is the case, we need to apply a hardware | |
1338 | * specific quirk if the device is known or we have a broken configuration. | |
1339 | */ | |
b5bd049f | 1340 | if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) { |
43302969 GL |
1341 | /* |
1342 | * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5 | |
1343 | * adapters. The T5 hardware returns an incorrect value of 0x8000 for | |
1344 | * the VF PBA offset while the BAR itself is only 8k. The correct value | |
1345 | * is 0x1000, so we hard code that here. | |
1346 | */ | |
ff635e37 AW |
1347 | if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO && |
1348 | (vdev->device_id & 0xff00) == 0x5800) { | |
b5bd049f | 1349 | msix->pba_offset = 0x1000; |
43302969 | 1350 | } else { |
008d0e2d EA |
1351 | error_setg(errp, "hardware reports invalid configuration, " |
1352 | "MSIX PBA outside of specified BAR"); | |
b5bd049f | 1353 | g_free(msix); |
43302969 GL |
1354 | return -EINVAL; |
1355 | } | |
1356 | } | |
1357 | ||
0de70dc7 | 1358 | trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar, |
b5bd049f AW |
1359 | msix->table_offset, msix->entries); |
1360 | vdev->msix = msix; | |
65501a74 | 1361 | |
db0da029 AW |
1362 | vfio_pci_fixup_msix_region(vdev); |
1363 | ||
65501a74 AW |
1364 | return 0; |
1365 | } | |
1366 | ||
7ef165b9 | 1367 | static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp) |
65501a74 AW |
1368 | { |
1369 | int ret; | |
1370 | ||
95239e16 AW |
1371 | vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * |
1372 | sizeof(unsigned long)); | |
65501a74 | 1373 | ret = msix_init(&vdev->pdev, vdev->msix->entries, |
db0da029 | 1374 | vdev->bars[vdev->msix->table_bar].region.mem, |
65501a74 | 1375 | vdev->msix->table_bar, vdev->msix->table_offset, |
db0da029 | 1376 | vdev->bars[vdev->msix->pba_bar].region.mem, |
65501a74 AW |
1377 | vdev->msix->pba_bar, vdev->msix->pba_offset, pos); |
1378 | if (ret < 0) { | |
e43b9a5a AW |
1379 | if (ret == -ENOTSUP) { |
1380 | return 0; | |
1381 | } | |
7ef165b9 | 1382 | error_setg(errp, "msix_init failed"); |
65501a74 AW |
1383 | return ret; |
1384 | } | |
1385 | ||
95239e16 AW |
1386 | /* |
1387 | * The PCI spec suggests that devices provide additional alignment for | |
1388 | * MSI-X structures and avoid overlapping non-MSI-X related registers. | |
1389 | * For an assigned device, this hopefully means that emulation of MSI-X | |
1390 | * structures does not affect the performance of the device. If devices | |
1391 | * fail to provide that alignment, a significant performance penalty may | |
1392 | * result, for instance Mellanox MT27500 VFs: | |
1393 | * http://www.spinics.net/lists/kvm/msg125881.html | |
1394 | * | |
1395 | * The PBA is simply not that important for such a serious regression and | |
1396 | * most drivers do not appear to look at it. The solution for this is to | |
1397 | * disable the PBA MemoryRegion unless it's being used. We disable it | |
1398 | * here and only enable it if a masked vector fires through QEMU. As the | |
1399 | * vector-use notifier is called, which occurs on unmask, we test whether | |
1400 | * PBA emulation is needed and again disable if not. | |
1401 | */ | |
1402 | memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); | |
1403 | ||
65501a74 AW |
1404 | return 0; |
1405 | } | |
1406 | ||
9ee27d73 | 1407 | static void vfio_teardown_msi(VFIOPCIDevice *vdev) |
65501a74 AW |
1408 | { |
1409 | msi_uninit(&vdev->pdev); | |
1410 | ||
1411 | if (vdev->msix) { | |
a664477d | 1412 | msix_uninit(&vdev->pdev, |
db0da029 AW |
1413 | vdev->bars[vdev->msix->table_bar].region.mem, |
1414 | vdev->bars[vdev->msix->pba_bar].region.mem); | |
95239e16 | 1415 | g_free(vdev->msix->pending); |
65501a74 AW |
1416 | } |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * Resource setup | |
1421 | */ | |
9ee27d73 | 1422 | static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) |
65501a74 AW |
1423 | { |
1424 | int i; | |
1425 | ||
1426 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
db0da029 | 1427 | vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled); |
65501a74 AW |
1428 | } |
1429 | } | |
1430 | ||
2d82f8a3 | 1431 | static void vfio_bar_setup(VFIOPCIDevice *vdev, int nr) |
65501a74 AW |
1432 | { |
1433 | VFIOBAR *bar = &vdev->bars[nr]; | |
1434 | ||
65501a74 AW |
1435 | uint32_t pci_bar; |
1436 | uint8_t type; | |
1437 | int ret; | |
1438 | ||
1439 | /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ | |
2d82f8a3 | 1440 | if (!bar->region.size) { |
65501a74 AW |
1441 | return; |
1442 | } | |
1443 | ||
65501a74 | 1444 | /* Determine what type of BAR this is for registration */ |
5546a621 | 1445 | ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), |
65501a74 AW |
1446 | vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); |
1447 | if (ret != sizeof(pci_bar)) { | |
312fd5f2 | 1448 | error_report("vfio: Failed to read BAR %d (%m)", nr); |
65501a74 AW |
1449 | return; |
1450 | } | |
1451 | ||
1452 | pci_bar = le32_to_cpu(pci_bar); | |
39360f0b AW |
1453 | bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); |
1454 | bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
1455 | type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : | |
1456 | ~PCI_BASE_ADDRESS_MEM_MASK); | |
65501a74 | 1457 | |
db0da029 AW |
1458 | if (vfio_region_mmap(&bar->region)) { |
1459 | error_report("Failed to mmap %s BAR %d. Performance may be slow", | |
1460 | vdev->vbasedev.name, nr); | |
65501a74 | 1461 | } |
7076eabc | 1462 | |
2d82f8a3 | 1463 | pci_register_bar(&vdev->pdev, nr, type, bar->region.mem); |
65501a74 AW |
1464 | } |
1465 | ||
2d82f8a3 | 1466 | static void vfio_bars_setup(VFIOPCIDevice *vdev) |
65501a74 AW |
1467 | { |
1468 | int i; | |
1469 | ||
1470 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2d82f8a3 | 1471 | vfio_bar_setup(vdev, i); |
65501a74 AW |
1472 | } |
1473 | } | |
1474 | ||
2d82f8a3 | 1475 | static void vfio_bars_exit(VFIOPCIDevice *vdev) |
65501a74 AW |
1476 | { |
1477 | int i; | |
1478 | ||
1479 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2d82f8a3 AW |
1480 | vfio_bar_quirk_exit(vdev, i); |
1481 | vfio_region_exit(&vdev->bars[i].region); | |
65501a74 | 1482 | } |
f15689c7 | 1483 | |
2d82f8a3 | 1484 | if (vdev->vga) { |
f15689c7 | 1485 | pci_unregister_vga(&vdev->pdev); |
2d82f8a3 | 1486 | vfio_vga_quirk_exit(vdev); |
f15689c7 | 1487 | } |
65501a74 AW |
1488 | } |
1489 | ||
2d82f8a3 | 1490 | static void vfio_bars_finalize(VFIOPCIDevice *vdev) |
ba5e6bfa PB |
1491 | { |
1492 | int i; | |
1493 | ||
1494 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2d82f8a3 AW |
1495 | vfio_bar_quirk_finalize(vdev, i); |
1496 | vfio_region_finalize(&vdev->bars[i].region); | |
ba5e6bfa PB |
1497 | } |
1498 | ||
2d82f8a3 AW |
1499 | if (vdev->vga) { |
1500 | vfio_vga_quirk_finalize(vdev); | |
1501 | for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { | |
1502 | object_unparent(OBJECT(&vdev->vga->region[i].mem)); | |
1503 | } | |
1504 | g_free(vdev->vga); | |
ba5e6bfa PB |
1505 | } |
1506 | } | |
1507 | ||
65501a74 AW |
1508 | /* |
1509 | * General setup | |
1510 | */ | |
1511 | static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) | |
1512 | { | |
88caf177 CF |
1513 | uint8_t tmp; |
1514 | uint16_t next = PCI_CONFIG_SPACE_SIZE; | |
65501a74 AW |
1515 | |
1516 | for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; | |
3fc1c182 | 1517 | tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) { |
65501a74 AW |
1518 | if (tmp > pos && tmp < next) { |
1519 | next = tmp; | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | return next - pos; | |
1524 | } | |
1525 | ||
325ae8d5 CF |
1526 | |
1527 | static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos) | |
1528 | { | |
1529 | uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE; | |
1530 | ||
1531 | for (tmp = PCI_CONFIG_SPACE_SIZE; tmp; | |
1532 | tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { | |
1533 | if (tmp > pos && tmp < next) { | |
1534 | next = tmp; | |
1535 | } | |
1536 | } | |
1537 | ||
1538 | return next - pos; | |
1539 | } | |
1540 | ||
96adc5c7 AW |
1541 | static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) |
1542 | { | |
1543 | pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); | |
1544 | } | |
1545 | ||
9ee27d73 | 1546 | static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, |
96adc5c7 AW |
1547 | uint16_t val, uint16_t mask) |
1548 | { | |
1549 | vfio_set_word_bits(vdev->pdev.config + pos, val, mask); | |
1550 | vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); | |
1551 | vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); | |
1552 | } | |
1553 | ||
1554 | static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) | |
1555 | { | |
1556 | pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); | |
1557 | } | |
1558 | ||
9ee27d73 | 1559 | static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, |
96adc5c7 AW |
1560 | uint32_t val, uint32_t mask) |
1561 | { | |
1562 | vfio_set_long_bits(vdev->pdev.config + pos, val, mask); | |
1563 | vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); | |
1564 | vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); | |
1565 | } | |
1566 | ||
7ef165b9 EA |
1567 | static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, |
1568 | Error **errp) | |
96adc5c7 AW |
1569 | { |
1570 | uint16_t flags; | |
1571 | uint8_t type; | |
1572 | ||
1573 | flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); | |
1574 | type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; | |
1575 | ||
1576 | if (type != PCI_EXP_TYPE_ENDPOINT && | |
1577 | type != PCI_EXP_TYPE_LEG_END && | |
1578 | type != PCI_EXP_TYPE_RC_END) { | |
1579 | ||
7ef165b9 EA |
1580 | error_setg(errp, "assignment of PCIe type 0x%x " |
1581 | "devices is not currently supported", type); | |
96adc5c7 AW |
1582 | return -EINVAL; |
1583 | } | |
1584 | ||
1585 | if (!pci_bus_is_express(vdev->pdev.bus)) { | |
0282abf0 AW |
1586 | PCIBus *bus = vdev->pdev.bus; |
1587 | PCIDevice *bridge; | |
1588 | ||
96adc5c7 | 1589 | /* |
0282abf0 AW |
1590 | * Traditionally PCI device assignment exposes the PCIe capability |
1591 | * as-is on non-express buses. The reason being that some drivers | |
1592 | * simply assume that it's there, for example tg3. However when | |
1593 | * we're running on a native PCIe machine type, like Q35, we need | |
1594 | * to hide the PCIe capability. The reason for this is twofold; | |
1595 | * first Windows guests get a Code 10 error when the PCIe capability | |
1596 | * is exposed in this configuration. Therefore express devices won't | |
1597 | * work at all unless they're attached to express buses in the VM. | |
1598 | * Second, a native PCIe machine introduces the possibility of fine | |
1599 | * granularity IOMMUs supporting both translation and isolation. | |
1600 | * Guest code to discover the IOMMU visibility of a device, such as | |
1601 | * IOMMU grouping code on Linux, is very aware of device types and | |
1602 | * valid transitions between bus types. An express device on a non- | |
1603 | * express bus is not a valid combination on bare metal systems. | |
1604 | * | |
1605 | * Drivers that require a PCIe capability to make the device | |
1606 | * functional are simply going to need to have their devices placed | |
1607 | * on a PCIe bus in the VM. | |
96adc5c7 | 1608 | */ |
0282abf0 AW |
1609 | while (!pci_bus_is_root(bus)) { |
1610 | bridge = pci_bridge_get_device(bus); | |
1611 | bus = bridge->bus; | |
1612 | } | |
1613 | ||
1614 | if (pci_bus_is_express(bus)) { | |
1615 | return 0; | |
1616 | } | |
1617 | ||
96adc5c7 AW |
1618 | } else if (pci_bus_is_root(vdev->pdev.bus)) { |
1619 | /* | |
1620 | * On a Root Complex bus Endpoints become Root Complex Integrated | |
1621 | * Endpoints, which changes the type and clears the LNK & LNK2 fields. | |
1622 | */ | |
1623 | if (type == PCI_EXP_TYPE_ENDPOINT) { | |
1624 | vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, | |
1625 | PCI_EXP_TYPE_RC_END << 4, | |
1626 | PCI_EXP_FLAGS_TYPE); | |
1627 | ||
1628 | /* Link Capabilities, Status, and Control goes away */ | |
1629 | if (size > PCI_EXP_LNKCTL) { | |
1630 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); | |
1631 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); | |
1632 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); | |
1633 | ||
1634 | #ifndef PCI_EXP_LNKCAP2 | |
1635 | #define PCI_EXP_LNKCAP2 44 | |
1636 | #endif | |
1637 | #ifndef PCI_EXP_LNKSTA2 | |
1638 | #define PCI_EXP_LNKSTA2 50 | |
1639 | #endif | |
1640 | /* Link 2 Capabilities, Status, and Control goes away */ | |
1641 | if (size > PCI_EXP_LNKCAP2) { | |
1642 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); | |
1643 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); | |
1644 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); | |
1645 | } | |
1646 | } | |
1647 | ||
1648 | } else if (type == PCI_EXP_TYPE_LEG_END) { | |
1649 | /* | |
1650 | * Legacy endpoints don't belong on the root complex. Windows | |
1651 | * seems to be happier with devices if we skip the capability. | |
1652 | */ | |
1653 | return 0; | |
1654 | } | |
1655 | ||
1656 | } else { | |
1657 | /* | |
1658 | * Convert Root Complex Integrated Endpoints to regular endpoints. | |
1659 | * These devices don't support LNK/LNK2 capabilities, so make them up. | |
1660 | */ | |
1661 | if (type == PCI_EXP_TYPE_RC_END) { | |
1662 | vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, | |
1663 | PCI_EXP_TYPE_ENDPOINT << 4, | |
1664 | PCI_EXP_FLAGS_TYPE); | |
1665 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, | |
1666 | PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); | |
1667 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); | |
1668 | } | |
1669 | ||
1670 | /* Mark the Link Status bits as emulated to allow virtual negotiation */ | |
1671 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, | |
1672 | pci_get_word(vdev->pdev.config + pos + | |
1673 | PCI_EXP_LNKSTA), | |
1674 | PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); | |
1675 | } | |
1676 | ||
1677 | pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); | |
1678 | if (pos >= 0) { | |
1679 | vdev->pdev.exp.exp_cap = pos; | |
1680 | } | |
1681 | ||
1682 | return pos; | |
1683 | } | |
1684 | ||
9ee27d73 | 1685 | static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
1686 | { |
1687 | uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); | |
1688 | ||
1689 | if (cap & PCI_EXP_DEVCAP_FLR) { | |
df92ee44 | 1690 | trace_vfio_check_pcie_flr(vdev->vbasedev.name); |
befe5176 AW |
1691 | vdev->has_flr = true; |
1692 | } | |
1693 | } | |
1694 | ||
9ee27d73 | 1695 | static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
1696 | { |
1697 | uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); | |
1698 | ||
1699 | if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { | |
df92ee44 | 1700 | trace_vfio_check_pm_reset(vdev->vbasedev.name); |
befe5176 AW |
1701 | vdev->has_pm_reset = true; |
1702 | } | |
1703 | } | |
1704 | ||
9ee27d73 | 1705 | static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
1706 | { |
1707 | uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); | |
1708 | ||
1709 | if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { | |
df92ee44 | 1710 | trace_vfio_check_af_flr(vdev->vbasedev.name); |
befe5176 AW |
1711 | vdev->has_flr = true; |
1712 | } | |
1713 | } | |
1714 | ||
7ef165b9 | 1715 | static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) |
65501a74 AW |
1716 | { |
1717 | PCIDevice *pdev = &vdev->pdev; | |
1718 | uint8_t cap_id, next, size; | |
1719 | int ret; | |
1720 | ||
1721 | cap_id = pdev->config[pos]; | |
3fc1c182 | 1722 | next = pdev->config[pos + PCI_CAP_LIST_NEXT]; |
65501a74 AW |
1723 | |
1724 | /* | |
1725 | * If it becomes important to configure capabilities to their actual | |
1726 | * size, use this as the default when it's something we don't recognize. | |
1727 | * Since QEMU doesn't actually handle many of the config accesses, | |
1728 | * exact size doesn't seem worthwhile. | |
1729 | */ | |
1730 | size = vfio_std_cap_max_size(pdev, pos); | |
1731 | ||
1732 | /* | |
1733 | * pci_add_capability always inserts the new capability at the head | |
1734 | * of the chain. Therefore to end up with a chain that matches the | |
1735 | * physical device, we insert from the end by making this recursive. | |
3fc1c182 | 1736 | * This is also why we pre-calculate size above as cached config space |
65501a74 AW |
1737 | * will be changed as we unwind the stack. |
1738 | */ | |
1739 | if (next) { | |
7ef165b9 | 1740 | ret = vfio_add_std_cap(vdev, next, errp); |
65501a74 | 1741 | if (ret) { |
7ef165b9 | 1742 | goto out; |
65501a74 AW |
1743 | } |
1744 | } else { | |
96adc5c7 AW |
1745 | /* Begin the rebuild, use QEMU emulated list bits */ |
1746 | pdev->config[PCI_CAPABILITY_LIST] = 0; | |
1747 | vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; | |
1748 | vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
65501a74 AW |
1749 | } |
1750 | ||
96adc5c7 | 1751 | /* Use emulated next pointer to allow dropping caps */ |
3fc1c182 | 1752 | pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); |
96adc5c7 | 1753 | |
65501a74 AW |
1754 | switch (cap_id) { |
1755 | case PCI_CAP_ID_MSI: | |
7ef165b9 | 1756 | ret = vfio_msi_setup(vdev, pos, errp); |
65501a74 | 1757 | break; |
96adc5c7 | 1758 | case PCI_CAP_ID_EXP: |
befe5176 | 1759 | vfio_check_pcie_flr(vdev, pos); |
7ef165b9 | 1760 | ret = vfio_setup_pcie_cap(vdev, pos, size, errp); |
96adc5c7 | 1761 | break; |
65501a74 | 1762 | case PCI_CAP_ID_MSIX: |
7ef165b9 | 1763 | ret = vfio_msix_setup(vdev, pos, errp); |
65501a74 | 1764 | break; |
ba661818 | 1765 | case PCI_CAP_ID_PM: |
befe5176 | 1766 | vfio_check_pm_reset(vdev, pos); |
ba661818 | 1767 | vdev->pm_cap = pos; |
7ef165b9 | 1768 | ret = pci_add_capability2(pdev, cap_id, pos, size, errp); |
befe5176 AW |
1769 | break; |
1770 | case PCI_CAP_ID_AF: | |
1771 | vfio_check_af_flr(vdev, pos); | |
7ef165b9 | 1772 | ret = pci_add_capability2(pdev, cap_id, pos, size, errp); |
befe5176 | 1773 | break; |
65501a74 | 1774 | default: |
7ef165b9 | 1775 | ret = pci_add_capability2(pdev, cap_id, pos, size, errp); |
65501a74 AW |
1776 | break; |
1777 | } | |
7ef165b9 | 1778 | out: |
65501a74 | 1779 | if (ret < 0) { |
7ef165b9 EA |
1780 | error_prepend(errp, |
1781 | "failed to add PCI capability 0x%x[0x%x]@0x%x: ", | |
1782 | cap_id, size, pos); | |
65501a74 AW |
1783 | return ret; |
1784 | } | |
1785 | ||
1786 | return 0; | |
1787 | } | |
1788 | ||
7ef165b9 | 1789 | static void vfio_add_ext_cap(VFIOPCIDevice *vdev) |
325ae8d5 CF |
1790 | { |
1791 | PCIDevice *pdev = &vdev->pdev; | |
1792 | uint32_t header; | |
1793 | uint16_t cap_id, next, size; | |
1794 | uint8_t cap_ver; | |
1795 | uint8_t *config; | |
1796 | ||
e37dac06 AW |
1797 | /* Only add extended caps if we have them and the guest can see them */ |
1798 | if (!pci_is_express(pdev) || !pci_bus_is_express(pdev->bus) || | |
1799 | !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { | |
7ef165b9 | 1800 | return; |
e37dac06 AW |
1801 | } |
1802 | ||
325ae8d5 CF |
1803 | /* |
1804 | * pcie_add_capability always inserts the new capability at the tail | |
1805 | * of the chain. Therefore to end up with a chain that matches the | |
1806 | * physical device, we cache the config space to avoid overwriting | |
1807 | * the original config space when we parse the extended capabilities. | |
1808 | */ | |
1809 | config = g_memdup(pdev->config, vdev->config_size); | |
1810 | ||
e37dac06 AW |
1811 | /* |
1812 | * Extended capabilities are chained with each pointing to the next, so we | |
1813 | * can drop anything other than the head of the chain simply by modifying | |
1814 | * the previous next pointer. For the head of the chain, we can modify the | |
1815 | * capability ID to something that cannot match a valid capability. ID | |
1816 | * 0 is reserved for this since absence of capabilities is indicated by | |
1817 | * 0 for the ID, version, AND next pointer. However, pcie_add_capability() | |
1818 | * uses ID 0 as reserved for list management and will incorrectly match and | |
1819 | * assert if we attempt to pre-load the head of the chain with with this | |
1820 | * ID. Use ID 0xFFFF temporarily since it is also seems to be reserved in | |
1821 | * part for identifying absence of capabilities in a root complex register | |
1822 | * block. If the ID still exists after adding capabilities, switch back to | |
1823 | * zero. We'll mark this entire first dword as emulated for this purpose. | |
1824 | */ | |
1825 | pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE, | |
1826 | PCI_EXT_CAP(0xFFFF, 0, 0)); | |
1827 | pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); | |
1828 | pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); | |
1829 | ||
325ae8d5 CF |
1830 | for (next = PCI_CONFIG_SPACE_SIZE; next; |
1831 | next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { | |
1832 | header = pci_get_long(config + next); | |
1833 | cap_id = PCI_EXT_CAP_ID(header); | |
1834 | cap_ver = PCI_EXT_CAP_VER(header); | |
1835 | ||
1836 | /* | |
1837 | * If it becomes important to configure extended capabilities to their | |
1838 | * actual size, use this as the default when it's something we don't | |
1839 | * recognize. Since QEMU doesn't actually handle many of the config | |
1840 | * accesses, exact size doesn't seem worthwhile. | |
1841 | */ | |
1842 | size = vfio_ext_cap_max_size(config, next); | |
1843 | ||
325ae8d5 CF |
1844 | /* Use emulated next pointer to allow dropping extended caps */ |
1845 | pci_long_test_and_set_mask(vdev->emulated_config_bits + next, | |
1846 | PCI_EXT_CAP_NEXT_MASK); | |
e37dac06 AW |
1847 | |
1848 | switch (cap_id) { | |
1849 | case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */ | |
383a7af7 | 1850 | case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */ |
e37dac06 AW |
1851 | trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next); |
1852 | break; | |
1853 | default: | |
1854 | pcie_add_capability(pdev, cap_id, cap_ver, next, size); | |
1855 | } | |
1856 | ||
1857 | } | |
1858 | ||
1859 | /* Cleanup chain head ID if necessary */ | |
1860 | if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { | |
1861 | pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); | |
325ae8d5 CF |
1862 | } |
1863 | ||
1864 | g_free(config); | |
7ef165b9 | 1865 | return; |
325ae8d5 CF |
1866 | } |
1867 | ||
7ef165b9 | 1868 | static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp) |
65501a74 AW |
1869 | { |
1870 | PCIDevice *pdev = &vdev->pdev; | |
325ae8d5 | 1871 | int ret; |
65501a74 AW |
1872 | |
1873 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || | |
1874 | !pdev->config[PCI_CAPABILITY_LIST]) { | |
1875 | return 0; /* Nothing to add */ | |
1876 | } | |
1877 | ||
7ef165b9 | 1878 | ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp); |
325ae8d5 CF |
1879 | if (ret) { |
1880 | return ret; | |
1881 | } | |
1882 | ||
7ef165b9 EA |
1883 | vfio_add_ext_cap(vdev); |
1884 | return 0; | |
65501a74 AW |
1885 | } |
1886 | ||
9ee27d73 | 1887 | static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) |
f16f39c3 AW |
1888 | { |
1889 | PCIDevice *pdev = &vdev->pdev; | |
1890 | uint16_t cmd; | |
1891 | ||
1892 | vfio_disable_interrupts(vdev); | |
1893 | ||
1894 | /* Make sure the device is in D0 */ | |
1895 | if (vdev->pm_cap) { | |
1896 | uint16_t pmcsr; | |
1897 | uint8_t state; | |
1898 | ||
1899 | pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); | |
1900 | state = pmcsr & PCI_PM_CTRL_STATE_MASK; | |
1901 | if (state) { | |
1902 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
1903 | vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); | |
1904 | /* vfio handles the necessary delay here */ | |
1905 | pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); | |
1906 | state = pmcsr & PCI_PM_CTRL_STATE_MASK; | |
1907 | if (state) { | |
4e505ddd | 1908 | error_report("vfio: Unable to power on device, stuck in D%d", |
f16f39c3 AW |
1909 | state); |
1910 | } | |
1911 | } | |
1912 | } | |
1913 | ||
1914 | /* | |
1915 | * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. | |
1916 | * Also put INTx Disable in known state. | |
1917 | */ | |
1918 | cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); | |
1919 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | | |
1920 | PCI_COMMAND_INTX_DISABLE); | |
1921 | vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); | |
1922 | } | |
1923 | ||
9ee27d73 | 1924 | static void vfio_pci_post_reset(VFIOPCIDevice *vdev) |
f16f39c3 | 1925 | { |
7dfb3424 EA |
1926 | Error *err = NULL; |
1927 | ||
1928 | vfio_intx_enable(vdev, &err); | |
1929 | if (err) { | |
1930 | error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); | |
1931 | } | |
f16f39c3 AW |
1932 | } |
1933 | ||
7df9381b | 1934 | static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name) |
f16f39c3 | 1935 | { |
7df9381b AW |
1936 | char tmp[13]; |
1937 | ||
1938 | sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain, | |
1939 | addr->bus, addr->slot, addr->function); | |
1940 | ||
1941 | return (strcmp(tmp, name) == 0); | |
f16f39c3 AW |
1942 | } |
1943 | ||
9ee27d73 | 1944 | static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) |
f16f39c3 AW |
1945 | { |
1946 | VFIOGroup *group; | |
1947 | struct vfio_pci_hot_reset_info *info; | |
1948 | struct vfio_pci_dependent_device *devices; | |
1949 | struct vfio_pci_hot_reset *reset; | |
1950 | int32_t *fds; | |
1951 | int ret, i, count; | |
1952 | bool multi = false; | |
1953 | ||
df92ee44 | 1954 | trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); |
f16f39c3 AW |
1955 | |
1956 | vfio_pci_pre_reset(vdev); | |
b47d8efa | 1957 | vdev->vbasedev.needs_reset = false; |
f16f39c3 AW |
1958 | |
1959 | info = g_malloc0(sizeof(*info)); | |
1960 | info->argsz = sizeof(*info); | |
1961 | ||
5546a621 | 1962 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); |
f16f39c3 AW |
1963 | if (ret && errno != ENOSPC) { |
1964 | ret = -errno; | |
1965 | if (!vdev->has_pm_reset) { | |
7df9381b AW |
1966 | error_report("vfio: Cannot reset device %s, " |
1967 | "no available reset mechanism.", vdev->vbasedev.name); | |
f16f39c3 AW |
1968 | } |
1969 | goto out_single; | |
1970 | } | |
1971 | ||
1972 | count = info->count; | |
1973 | info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); | |
1974 | info->argsz = sizeof(*info) + (count * sizeof(*devices)); | |
1975 | devices = &info->devices[0]; | |
1976 | ||
5546a621 | 1977 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); |
f16f39c3 AW |
1978 | if (ret) { |
1979 | ret = -errno; | |
1980 | error_report("vfio: hot reset info failed: %m"); | |
1981 | goto out_single; | |
1982 | } | |
1983 | ||
df92ee44 | 1984 | trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); |
f16f39c3 AW |
1985 | |
1986 | /* Verify that we have all the groups required */ | |
1987 | for (i = 0; i < info->count; i++) { | |
1988 | PCIHostDeviceAddress host; | |
9ee27d73 | 1989 | VFIOPCIDevice *tmp; |
b47d8efa | 1990 | VFIODevice *vbasedev_iter; |
f16f39c3 AW |
1991 | |
1992 | host.domain = devices[i].segment; | |
1993 | host.bus = devices[i].bus; | |
1994 | host.slot = PCI_SLOT(devices[i].devfn); | |
1995 | host.function = PCI_FUNC(devices[i].devfn); | |
1996 | ||
385f57cf | 1997 | trace_vfio_pci_hot_reset_dep_devices(host.domain, |
f16f39c3 AW |
1998 | host.bus, host.slot, host.function, devices[i].group_id); |
1999 | ||
7df9381b | 2000 | if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { |
f16f39c3 AW |
2001 | continue; |
2002 | } | |
2003 | ||
62356b72 | 2004 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2005 | if (group->groupid == devices[i].group_id) { |
2006 | break; | |
2007 | } | |
2008 | } | |
2009 | ||
2010 | if (!group) { | |
2011 | if (!vdev->has_pm_reset) { | |
df92ee44 | 2012 | error_report("vfio: Cannot reset device %s, " |
f16f39c3 | 2013 | "depends on group %d which is not owned.", |
df92ee44 | 2014 | vdev->vbasedev.name, devices[i].group_id); |
f16f39c3 AW |
2015 | } |
2016 | ret = -EPERM; | |
2017 | goto out; | |
2018 | } | |
2019 | ||
2020 | /* Prep dependent devices for reset and clear our marker. */ | |
b47d8efa EA |
2021 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2022 | if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { | |
2023 | continue; | |
2024 | } | |
2025 | tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); | |
7df9381b | 2026 | if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { |
f16f39c3 | 2027 | if (single) { |
f16f39c3 AW |
2028 | ret = -EINVAL; |
2029 | goto out_single; | |
2030 | } | |
2031 | vfio_pci_pre_reset(tmp); | |
b47d8efa | 2032 | tmp->vbasedev.needs_reset = false; |
f16f39c3 AW |
2033 | multi = true; |
2034 | break; | |
2035 | } | |
2036 | } | |
2037 | } | |
2038 | ||
2039 | if (!single && !multi) { | |
f16f39c3 AW |
2040 | ret = -EINVAL; |
2041 | goto out_single; | |
2042 | } | |
2043 | ||
2044 | /* Determine how many group fds need to be passed */ | |
2045 | count = 0; | |
62356b72 | 2046 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2047 | for (i = 0; i < info->count; i++) { |
2048 | if (group->groupid == devices[i].group_id) { | |
2049 | count++; | |
2050 | break; | |
2051 | } | |
2052 | } | |
2053 | } | |
2054 | ||
2055 | reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); | |
2056 | reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); | |
2057 | fds = &reset->group_fds[0]; | |
2058 | ||
2059 | /* Fill in group fds */ | |
62356b72 | 2060 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2061 | for (i = 0; i < info->count; i++) { |
2062 | if (group->groupid == devices[i].group_id) { | |
2063 | fds[reset->count++] = group->fd; | |
2064 | break; | |
2065 | } | |
2066 | } | |
2067 | } | |
2068 | ||
2069 | /* Bus reset! */ | |
5546a621 | 2070 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); |
f16f39c3 AW |
2071 | g_free(reset); |
2072 | ||
df92ee44 | 2073 | trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, |
385f57cf | 2074 | ret ? "%m" : "Success"); |
f16f39c3 AW |
2075 | |
2076 | out: | |
2077 | /* Re-enable INTx on affected devices */ | |
2078 | for (i = 0; i < info->count; i++) { | |
2079 | PCIHostDeviceAddress host; | |
9ee27d73 | 2080 | VFIOPCIDevice *tmp; |
b47d8efa | 2081 | VFIODevice *vbasedev_iter; |
f16f39c3 AW |
2082 | |
2083 | host.domain = devices[i].segment; | |
2084 | host.bus = devices[i].bus; | |
2085 | host.slot = PCI_SLOT(devices[i].devfn); | |
2086 | host.function = PCI_FUNC(devices[i].devfn); | |
2087 | ||
7df9381b | 2088 | if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { |
f16f39c3 AW |
2089 | continue; |
2090 | } | |
2091 | ||
62356b72 | 2092 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2093 | if (group->groupid == devices[i].group_id) { |
2094 | break; | |
2095 | } | |
2096 | } | |
2097 | ||
2098 | if (!group) { | |
2099 | break; | |
2100 | } | |
2101 | ||
b47d8efa EA |
2102 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2103 | if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { | |
2104 | continue; | |
2105 | } | |
2106 | tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); | |
7df9381b | 2107 | if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { |
f16f39c3 AW |
2108 | vfio_pci_post_reset(tmp); |
2109 | break; | |
2110 | } | |
2111 | } | |
2112 | } | |
2113 | out_single: | |
2114 | vfio_pci_post_reset(vdev); | |
2115 | g_free(info); | |
2116 | ||
2117 | return ret; | |
2118 | } | |
2119 | ||
2120 | /* | |
2121 | * We want to differentiate hot reset of mulitple in-use devices vs hot reset | |
2122 | * of a single in-use device. VFIO_DEVICE_RESET will already handle the case | |
2123 | * of doing hot resets when there is only a single device per bus. The in-use | |
2124 | * here refers to how many VFIODevices are affected. A hot reset that affects | |
2125 | * multiple devices, but only a single in-use device, means that we can call | |
2126 | * it from our bus ->reset() callback since the extent is effectively a single | |
2127 | * device. This allows us to make use of it in the hotplug path. When there | |
2128 | * are multiple in-use devices, we can only trigger the hot reset during a | |
2129 | * system reset and thus from our reset handler. We separate _one vs _multi | |
2130 | * here so that we don't overlap and do a double reset on the system reset | |
2131 | * path where both our reset handler and ->reset() callback are used. Calling | |
2132 | * _one() will only do a hot reset for the one in-use devices case, calling | |
2133 | * _multi() will do nothing if a _one() would have been sufficient. | |
2134 | */ | |
9ee27d73 | 2135 | static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) |
f16f39c3 AW |
2136 | { |
2137 | return vfio_pci_hot_reset(vdev, true); | |
2138 | } | |
2139 | ||
b47d8efa | 2140 | static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) |
f16f39c3 | 2141 | { |
b47d8efa | 2142 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); |
f16f39c3 AW |
2143 | return vfio_pci_hot_reset(vdev, false); |
2144 | } | |
2145 | ||
b47d8efa EA |
2146 | static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) |
2147 | { | |
2148 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); | |
2149 | if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { | |
2150 | vbasedev->needs_reset = true; | |
2151 | } | |
2152 | } | |
2153 | ||
2154 | static VFIODeviceOps vfio_pci_ops = { | |
2155 | .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, | |
2156 | .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, | |
870cb6f1 | 2157 | .vfio_eoi = vfio_intx_eoi, |
b47d8efa EA |
2158 | }; |
2159 | ||
cde4279b | 2160 | int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp) |
e593c021 AW |
2161 | { |
2162 | VFIODevice *vbasedev = &vdev->vbasedev; | |
2163 | struct vfio_region_info *reg_info; | |
2164 | int ret; | |
2165 | ||
4225f2b6 AW |
2166 | ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info); |
2167 | if (ret) { | |
cde4279b EA |
2168 | error_setg_errno(errp, -ret, |
2169 | "failed getting region info for VGA region index %d", | |
2170 | VFIO_PCI_VGA_REGION_INDEX); | |
4225f2b6 AW |
2171 | return ret; |
2172 | } | |
e593c021 | 2173 | |
4225f2b6 AW |
2174 | if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) || |
2175 | !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) || | |
2176 | reg_info->size < 0xbffff + 1) { | |
cde4279b EA |
2177 | error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx", |
2178 | (unsigned long)reg_info->flags, | |
2179 | (unsigned long)reg_info->size); | |
4225f2b6 AW |
2180 | g_free(reg_info); |
2181 | return -EINVAL; | |
2182 | } | |
e593c021 | 2183 | |
4225f2b6 | 2184 | vdev->vga = g_new0(VFIOVGA, 1); |
e593c021 | 2185 | |
4225f2b6 AW |
2186 | vdev->vga->fd_offset = reg_info->offset; |
2187 | vdev->vga->fd = vdev->vbasedev.fd; | |
e593c021 | 2188 | |
4225f2b6 | 2189 | g_free(reg_info); |
e593c021 | 2190 | |
4225f2b6 AW |
2191 | vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; |
2192 | vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; | |
2193 | QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks); | |
e593c021 | 2194 | |
182bca45 AW |
2195 | memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem, |
2196 | OBJECT(vdev), &vfio_vga_ops, | |
2197 | &vdev->vga->region[QEMU_PCI_VGA_MEM], | |
2198 | "vfio-vga-mmio@0xa0000", | |
2199 | QEMU_PCI_VGA_MEM_SIZE); | |
2200 | ||
4225f2b6 AW |
2201 | vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; |
2202 | vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; | |
2203 | QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks); | |
e593c021 | 2204 | |
182bca45 AW |
2205 | memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, |
2206 | OBJECT(vdev), &vfio_vga_ops, | |
2207 | &vdev->vga->region[QEMU_PCI_VGA_IO_LO], | |
2208 | "vfio-vga-io@0x3b0", | |
2209 | QEMU_PCI_VGA_IO_LO_SIZE); | |
2210 | ||
4225f2b6 AW |
2211 | vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; |
2212 | vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; | |
2213 | QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks); | |
e593c021 | 2214 | |
182bca45 AW |
2215 | memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, |
2216 | OBJECT(vdev), &vfio_vga_ops, | |
2217 | &vdev->vga->region[QEMU_PCI_VGA_IO_HI], | |
2218 | "vfio-vga-io@0x3c0", | |
2219 | QEMU_PCI_VGA_IO_HI_SIZE); | |
2220 | ||
2221 | pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem, | |
2222 | &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, | |
2223 | &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem); | |
2224 | ||
e593c021 AW |
2225 | return 0; |
2226 | } | |
2227 | ||
2312d907 | 2228 | static int vfio_populate_device(VFIOPCIDevice *vdev, Error **errp) |
65501a74 | 2229 | { |
217e9fdc | 2230 | VFIODevice *vbasedev = &vdev->vbasedev; |
46900226 | 2231 | struct vfio_region_info *reg_info; |
7b4b0e9e | 2232 | struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; |
d13dd2d7 | 2233 | int i, ret = -1; |
65501a74 AW |
2234 | |
2235 | /* Sanity check device */ | |
d13dd2d7 | 2236 | if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { |
2312d907 | 2237 | error_setg(errp, "this isn't a PCI device"); |
65501a74 AW |
2238 | goto error; |
2239 | } | |
2240 | ||
d13dd2d7 | 2241 | if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { |
2312d907 EA |
2242 | error_setg(errp, "unexpected number of io regions %u", |
2243 | vbasedev->num_regions); | |
65501a74 AW |
2244 | goto error; |
2245 | } | |
2246 | ||
d13dd2d7 | 2247 | if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { |
2312d907 | 2248 | error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs); |
65501a74 AW |
2249 | goto error; |
2250 | } | |
2251 | ||
2252 | for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { | |
db0da029 AW |
2253 | char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i); |
2254 | ||
2255 | ret = vfio_region_setup(OBJECT(vdev), vbasedev, | |
2256 | &vdev->bars[i].region, i, name); | |
2257 | g_free(name); | |
2258 | ||
65501a74 | 2259 | if (ret) { |
2312d907 | 2260 | error_setg_errno(errp, -ret, "failed to get region %d info", i); |
65501a74 AW |
2261 | goto error; |
2262 | } | |
2263 | ||
7076eabc | 2264 | QLIST_INIT(&vdev->bars[i].quirks); |
46900226 | 2265 | } |
65501a74 | 2266 | |
46900226 AW |
2267 | ret = vfio_get_region_info(vbasedev, |
2268 | VFIO_PCI_CONFIG_REGION_INDEX, ®_info); | |
65501a74 | 2269 | if (ret) { |
2312d907 | 2270 | error_setg_errno(errp, -ret, "failed to get config info"); |
65501a74 AW |
2271 | goto error; |
2272 | } | |
2273 | ||
d13dd2d7 | 2274 | trace_vfio_populate_device_config(vdev->vbasedev.name, |
46900226 AW |
2275 | (unsigned long)reg_info->size, |
2276 | (unsigned long)reg_info->offset, | |
2277 | (unsigned long)reg_info->flags); | |
65501a74 | 2278 | |
46900226 | 2279 | vdev->config_size = reg_info->size; |
6a659bbf AW |
2280 | if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { |
2281 | vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; | |
2282 | } | |
46900226 AW |
2283 | vdev->config_offset = reg_info->offset; |
2284 | ||
2285 | g_free(reg_info); | |
65501a74 | 2286 | |
e593c021 | 2287 | if (vdev->features & VFIO_FEATURE_ENABLE_VGA) { |
2312d907 | 2288 | ret = vfio_populate_vga(vdev, errp); |
f15689c7 | 2289 | if (ret) { |
2312d907 | 2290 | error_append_hint(errp, "device does not support " |
cde4279b | 2291 | "requested feature x-vga\n"); |
f15689c7 AW |
2292 | goto error; |
2293 | } | |
f15689c7 | 2294 | } |
47cbe50c | 2295 | |
7b4b0e9e VMP |
2296 | irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; |
2297 | ||
5546a621 | 2298 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); |
7b4b0e9e VMP |
2299 | if (ret) { |
2300 | /* This can fail for an old kernel or legacy PCI dev */ | |
d13dd2d7 | 2301 | trace_vfio_populate_device_get_irq_info_failure(); |
7b4b0e9e VMP |
2302 | ret = 0; |
2303 | } else if (irq_info.count == 1) { | |
2304 | vdev->pci_aer = true; | |
2305 | } else { | |
2312d907 | 2306 | error_report(WARN_PREFIX |
8fbf47c3 | 2307 | "Could not enable error recovery for the device", |
df92ee44 | 2308 | vbasedev->name); |
7b4b0e9e | 2309 | } |
f15689c7 | 2310 | |
d13dd2d7 EA |
2311 | error: |
2312 | return ret; | |
2313 | } | |
2314 | ||
9ee27d73 | 2315 | static void vfio_put_device(VFIOPCIDevice *vdev) |
65501a74 | 2316 | { |
462037c9 | 2317 | g_free(vdev->vbasedev.name); |
db0da029 AW |
2318 | g_free(vdev->msix); |
2319 | ||
d13dd2d7 | 2320 | vfio_put_base_device(&vdev->vbasedev); |
65501a74 AW |
2321 | } |
2322 | ||
7b4b0e9e VMP |
2323 | static void vfio_err_notifier_handler(void *opaque) |
2324 | { | |
9ee27d73 | 2325 | VFIOPCIDevice *vdev = opaque; |
7b4b0e9e VMP |
2326 | |
2327 | if (!event_notifier_test_and_clear(&vdev->err_notifier)) { | |
2328 | return; | |
2329 | } | |
2330 | ||
2331 | /* | |
2332 | * TBD. Retrieve the error details and decide what action | |
2333 | * needs to be taken. One of the actions could be to pass | |
2334 | * the error to the guest and have the guest driver recover | |
2335 | * from the error. This requires that PCIe capabilities be | |
2336 | * exposed to the guest. For now, we just terminate the | |
2337 | * guest to contain the error. | |
2338 | */ | |
2339 | ||
7df9381b | 2340 | error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name); |
7b4b0e9e | 2341 | |
ba29776f | 2342 | vm_stop(RUN_STATE_INTERNAL_ERROR); |
7b4b0e9e VMP |
2343 | } |
2344 | ||
2345 | /* | |
2346 | * Registers error notifier for devices supporting error recovery. | |
2347 | * If we encounter a failure in this function, we report an error | |
2348 | * and continue after disabling error recovery support for the | |
2349 | * device. | |
2350 | */ | |
9ee27d73 | 2351 | static void vfio_register_err_notifier(VFIOPCIDevice *vdev) |
7b4b0e9e VMP |
2352 | { |
2353 | int ret; | |
2354 | int argsz; | |
2355 | struct vfio_irq_set *irq_set; | |
2356 | int32_t *pfd; | |
2357 | ||
2358 | if (!vdev->pci_aer) { | |
2359 | return; | |
2360 | } | |
2361 | ||
2362 | if (event_notifier_init(&vdev->err_notifier, 0)) { | |
8fbf47c3 | 2363 | error_report("vfio: Unable to init event notifier for error detection"); |
7b4b0e9e VMP |
2364 | vdev->pci_aer = false; |
2365 | return; | |
2366 | } | |
2367 | ||
2368 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2369 | ||
2370 | irq_set = g_malloc0(argsz); | |
2371 | irq_set->argsz = argsz; | |
2372 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2373 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2374 | irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; | |
2375 | irq_set->start = 0; | |
2376 | irq_set->count = 1; | |
2377 | pfd = (int32_t *)&irq_set->data; | |
2378 | ||
2379 | *pfd = event_notifier_get_fd(&vdev->err_notifier); | |
2380 | qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); | |
2381 | ||
5546a621 | 2382 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
7b4b0e9e | 2383 | if (ret) { |
8fbf47c3 | 2384 | error_report("vfio: Failed to set up error notification"); |
7b4b0e9e VMP |
2385 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); |
2386 | event_notifier_cleanup(&vdev->err_notifier); | |
2387 | vdev->pci_aer = false; | |
2388 | } | |
2389 | g_free(irq_set); | |
2390 | } | |
2391 | ||
9ee27d73 | 2392 | static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) |
7b4b0e9e VMP |
2393 | { |
2394 | int argsz; | |
2395 | struct vfio_irq_set *irq_set; | |
2396 | int32_t *pfd; | |
2397 | int ret; | |
2398 | ||
2399 | if (!vdev->pci_aer) { | |
2400 | return; | |
2401 | } | |
2402 | ||
2403 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2404 | ||
2405 | irq_set = g_malloc0(argsz); | |
2406 | irq_set->argsz = argsz; | |
2407 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2408 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2409 | irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; | |
2410 | irq_set->start = 0; | |
2411 | irq_set->count = 1; | |
2412 | pfd = (int32_t *)&irq_set->data; | |
2413 | *pfd = -1; | |
2414 | ||
5546a621 | 2415 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
7b4b0e9e | 2416 | if (ret) { |
8fbf47c3 | 2417 | error_report("vfio: Failed to de-assign error fd: %m"); |
7b4b0e9e VMP |
2418 | } |
2419 | g_free(irq_set); | |
2420 | qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), | |
2421 | NULL, NULL, vdev); | |
2422 | event_notifier_cleanup(&vdev->err_notifier); | |
2423 | } | |
2424 | ||
47cbe50c AW |
2425 | static void vfio_req_notifier_handler(void *opaque) |
2426 | { | |
2427 | VFIOPCIDevice *vdev = opaque; | |
2428 | ||
2429 | if (!event_notifier_test_and_clear(&vdev->req_notifier)) { | |
2430 | return; | |
2431 | } | |
2432 | ||
2433 | qdev_unplug(&vdev->pdev.qdev, NULL); | |
2434 | } | |
2435 | ||
2436 | static void vfio_register_req_notifier(VFIOPCIDevice *vdev) | |
2437 | { | |
2438 | struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), | |
2439 | .index = VFIO_PCI_REQ_IRQ_INDEX }; | |
2440 | int argsz; | |
2441 | struct vfio_irq_set *irq_set; | |
2442 | int32_t *pfd; | |
2443 | ||
2444 | if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { | |
2445 | return; | |
2446 | } | |
2447 | ||
2448 | if (ioctl(vdev->vbasedev.fd, | |
2449 | VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { | |
2450 | return; | |
2451 | } | |
2452 | ||
2453 | if (event_notifier_init(&vdev->req_notifier, 0)) { | |
2454 | error_report("vfio: Unable to init event notifier for device request"); | |
2455 | return; | |
2456 | } | |
2457 | ||
2458 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2459 | ||
2460 | irq_set = g_malloc0(argsz); | |
2461 | irq_set->argsz = argsz; | |
2462 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2463 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2464 | irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; | |
2465 | irq_set->start = 0; | |
2466 | irq_set->count = 1; | |
2467 | pfd = (int32_t *)&irq_set->data; | |
2468 | ||
2469 | *pfd = event_notifier_get_fd(&vdev->req_notifier); | |
2470 | qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); | |
2471 | ||
2472 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { | |
2473 | error_report("vfio: Failed to set up device request notification"); | |
2474 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); | |
2475 | event_notifier_cleanup(&vdev->req_notifier); | |
2476 | } else { | |
2477 | vdev->req_enabled = true; | |
2478 | } | |
2479 | ||
2480 | g_free(irq_set); | |
2481 | } | |
2482 | ||
2483 | static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) | |
2484 | { | |
2485 | int argsz; | |
2486 | struct vfio_irq_set *irq_set; | |
2487 | int32_t *pfd; | |
2488 | ||
2489 | if (!vdev->req_enabled) { | |
2490 | return; | |
2491 | } | |
2492 | ||
2493 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2494 | ||
2495 | irq_set = g_malloc0(argsz); | |
2496 | irq_set->argsz = argsz; | |
2497 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2498 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2499 | irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; | |
2500 | irq_set->start = 0; | |
2501 | irq_set->count = 1; | |
2502 | pfd = (int32_t *)&irq_set->data; | |
2503 | *pfd = -1; | |
2504 | ||
2505 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { | |
2506 | error_report("vfio: Failed to de-assign device request fd: %m"); | |
2507 | } | |
2508 | g_free(irq_set); | |
2509 | qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), | |
2510 | NULL, NULL, vdev); | |
2511 | event_notifier_cleanup(&vdev->req_notifier); | |
2512 | ||
2513 | vdev->req_enabled = false; | |
2514 | } | |
2515 | ||
65501a74 AW |
2516 | static int vfio_initfn(PCIDevice *pdev) |
2517 | { | |
b47d8efa EA |
2518 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
2519 | VFIODevice *vbasedev_iter; | |
65501a74 | 2520 | VFIOGroup *group; |
7df9381b | 2521 | char *tmp, group_path[PATH_MAX], *group_name; |
426ec904 | 2522 | Error *err = NULL; |
65501a74 AW |
2523 | ssize_t len; |
2524 | struct stat st; | |
2525 | int groupid; | |
581406e0 | 2526 | int i, ret; |
65501a74 | 2527 | |
7df9381b AW |
2528 | if (!vdev->vbasedev.sysfsdev) { |
2529 | vdev->vbasedev.sysfsdev = | |
2530 | g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x", | |
2531 | vdev->host.domain, vdev->host.bus, | |
2532 | vdev->host.slot, vdev->host.function); | |
2533 | } | |
2534 | ||
2535 | if (stat(vdev->vbasedev.sysfsdev, &st) < 0) { | |
426ec904 EA |
2536 | error_setg_errno(&err, errno, "no such host device"); |
2537 | ret = -errno; | |
2538 | goto error; | |
65501a74 AW |
2539 | } |
2540 | ||
7df9381b | 2541 | vdev->vbasedev.name = g_strdup(basename(vdev->vbasedev.sysfsdev)); |
b47d8efa | 2542 | vdev->vbasedev.ops = &vfio_pci_ops; |
462037c9 | 2543 | vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; |
462037c9 | 2544 | |
7df9381b AW |
2545 | tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev); |
2546 | len = readlink(tmp, group_path, sizeof(group_path)); | |
2547 | g_free(tmp); | |
65501a74 | 2548 | |
7df9381b | 2549 | if (len <= 0 || len >= sizeof(group_path)) { |
426ec904 EA |
2550 | ret = len < 0 ? -errno : -ENAMETOOLONG; |
2551 | error_setg_errno(&err, -ret, "no iommu_group found"); | |
2552 | goto error; | |
65501a74 AW |
2553 | } |
2554 | ||
7df9381b | 2555 | group_path[len] = 0; |
65501a74 | 2556 | |
7df9381b | 2557 | group_name = basename(group_path); |
65501a74 | 2558 | if (sscanf(group_name, "%d", &groupid) != 1) { |
426ec904 EA |
2559 | error_setg_errno(&err, errno, "failed to read %s", group_path); |
2560 | ret = -errno; | |
2561 | goto error; | |
65501a74 AW |
2562 | } |
2563 | ||
df92ee44 | 2564 | trace_vfio_initfn(vdev->vbasedev.name, groupid); |
65501a74 | 2565 | |
0688448b | 2566 | group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev)); |
65501a74 | 2567 | if (!group) { |
426ec904 EA |
2568 | error_setg(&err, "failed to get group %d", groupid); |
2569 | ret = -ENOENT; | |
2570 | goto error; | |
65501a74 AW |
2571 | } |
2572 | ||
b47d8efa EA |
2573 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2574 | if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { | |
426ec904 | 2575 | error_setg(&err, "device is already attached"); |
65501a74 | 2576 | vfio_put_group(group); |
426ec904 EA |
2577 | ret = -EBUSY; |
2578 | goto error; | |
65501a74 AW |
2579 | } |
2580 | } | |
2581 | ||
7df9381b | 2582 | ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev); |
65501a74 | 2583 | if (ret) { |
426ec904 | 2584 | error_setg_errno(&err, -ret, "failed to get device"); |
65501a74 | 2585 | vfio_put_group(group); |
426ec904 | 2586 | goto error; |
65501a74 AW |
2587 | } |
2588 | ||
2312d907 | 2589 | ret = vfio_populate_device(vdev, &err); |
217e9fdc | 2590 | if (ret) { |
2312d907 | 2591 | goto error; |
217e9fdc PB |
2592 | } |
2593 | ||
65501a74 | 2594 | /* Get a copy of config space */ |
5546a621 | 2595 | ret = pread(vdev->vbasedev.fd, vdev->pdev.config, |
65501a74 AW |
2596 | MIN(pci_config_size(&vdev->pdev), vdev->config_size), |
2597 | vdev->config_offset); | |
2598 | if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { | |
2599 | ret = ret < 0 ? -errno : -EFAULT; | |
426ec904 EA |
2600 | error_setg_errno(&err, -ret, "failed to read device config space"); |
2601 | goto error; | |
65501a74 AW |
2602 | } |
2603 | ||
4b5d5e87 AW |
2604 | /* vfio emulates a lot for us, but some bits need extra love */ |
2605 | vdev->emulated_config_bits = g_malloc0(vdev->config_size); | |
2606 | ||
2607 | /* QEMU can choose to expose the ROM or not */ | |
2608 | memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); | |
2609 | ||
89dcccc5 AW |
2610 | /* |
2611 | * The PCI spec reserves vendor ID 0xffff as an invalid value. The | |
2612 | * device ID is managed by the vendor and need only be a 16-bit value. | |
2613 | * Allow any 16-bit value for subsystem so they can be hidden or changed. | |
2614 | */ | |
2615 | if (vdev->vendor_id != PCI_ANY_ID) { | |
2616 | if (vdev->vendor_id >= 0xffff) { | |
426ec904 EA |
2617 | error_setg(&err, "invalid PCI vendor ID provided"); |
2618 | ret = -EINVAL; | |
2619 | goto error; | |
89dcccc5 AW |
2620 | } |
2621 | vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); | |
2622 | trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); | |
2623 | } else { | |
2624 | vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
2625 | } | |
2626 | ||
2627 | if (vdev->device_id != PCI_ANY_ID) { | |
2628 | if (vdev->device_id > 0xffff) { | |
426ec904 EA |
2629 | error_setg(&err, "invalid PCI device ID provided"); |
2630 | ret = -EINVAL; | |
2631 | goto error; | |
89dcccc5 AW |
2632 | } |
2633 | vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); | |
2634 | trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); | |
2635 | } else { | |
2636 | vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
2637 | } | |
2638 | ||
2639 | if (vdev->sub_vendor_id != PCI_ANY_ID) { | |
2640 | if (vdev->sub_vendor_id > 0xffff) { | |
426ec904 EA |
2641 | error_setg(&err, "invalid PCI subsystem vendor ID provided"); |
2642 | ret = -EINVAL; | |
2643 | goto error; | |
89dcccc5 AW |
2644 | } |
2645 | vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, | |
2646 | vdev->sub_vendor_id, ~0); | |
2647 | trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, | |
2648 | vdev->sub_vendor_id); | |
2649 | } | |
2650 | ||
2651 | if (vdev->sub_device_id != PCI_ANY_ID) { | |
2652 | if (vdev->sub_device_id > 0xffff) { | |
426ec904 EA |
2653 | error_setg(&err, "invalid PCI subsystem device ID provided"); |
2654 | ret = -EINVAL; | |
2655 | goto error; | |
89dcccc5 AW |
2656 | } |
2657 | vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); | |
2658 | trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, | |
2659 | vdev->sub_device_id); | |
2660 | } | |
ff635e37 | 2661 | |
4b5d5e87 AW |
2662 | /* QEMU can change multi-function devices to single function, or reverse */ |
2663 | vdev->emulated_config_bits[PCI_HEADER_TYPE] = | |
2664 | PCI_HEADER_TYPE_MULTI_FUNCTION; | |
2665 | ||
187d6232 AW |
2666 | /* Restore or clear multifunction, this is always controlled by QEMU */ |
2667 | if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
2668 | vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
2669 | } else { | |
2670 | vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
2671 | } | |
2672 | ||
65501a74 AW |
2673 | /* |
2674 | * Clear host resource mapping info. If we choose not to register a | |
2675 | * BAR, such as might be the case with the option ROM, we can get | |
2676 | * confusing, unwritable, residual addresses from the host here. | |
2677 | */ | |
2678 | memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); | |
2679 | memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); | |
2680 | ||
6f864e6e | 2681 | vfio_pci_size_rom(vdev); |
65501a74 | 2682 | |
008d0e2d | 2683 | ret = vfio_msix_early_setup(vdev, &err); |
65501a74 | 2684 | if (ret) { |
008d0e2d | 2685 | goto error; |
65501a74 AW |
2686 | } |
2687 | ||
2d82f8a3 | 2688 | vfio_bars_setup(vdev); |
65501a74 | 2689 | |
7ef165b9 | 2690 | ret = vfio_add_capabilities(vdev, &err); |
65501a74 AW |
2691 | if (ret) { |
2692 | goto out_teardown; | |
2693 | } | |
2694 | ||
182bca45 AW |
2695 | if (vdev->vga) { |
2696 | vfio_vga_quirk_setup(vdev); | |
2697 | } | |
2698 | ||
581406e0 AW |
2699 | for (i = 0; i < PCI_ROM_SLOT; i++) { |
2700 | vfio_bar_quirk_setup(vdev, i); | |
2701 | } | |
2702 | ||
6ced0bba AW |
2703 | if (!vdev->igd_opregion && |
2704 | vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) { | |
2705 | struct vfio_region_info *opregion; | |
2706 | ||
2707 | if (vdev->pdev.qdev.hotplugged) { | |
426ec904 EA |
2708 | error_setg(&err, |
2709 | "cannot support IGD OpRegion feature on hotplugged " | |
2710 | "device"); | |
6ced0bba AW |
2711 | ret = -EINVAL; |
2712 | goto out_teardown; | |
2713 | } | |
2714 | ||
2715 | ret = vfio_get_dev_region_info(&vdev->vbasedev, | |
2716 | VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, | |
2717 | VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); | |
2718 | if (ret) { | |
426ec904 EA |
2719 | error_setg_errno(&err, -ret, |
2720 | "does not support requested IGD OpRegion feature"); | |
6ced0bba AW |
2721 | goto out_teardown; |
2722 | } | |
2723 | ||
2724 | ret = vfio_pci_igd_opregion_init(vdev, opregion); | |
2725 | g_free(opregion); | |
2726 | if (ret) { | |
426ec904 | 2727 | error_setg_errno(&err, -ret, "IGD OpRegion initialization failed"); |
6ced0bba AW |
2728 | goto out_teardown; |
2729 | } | |
2730 | } | |
2731 | ||
4b5d5e87 AW |
2732 | /* QEMU emulates all of MSI & MSIX */ |
2733 | if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { | |
2734 | memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, | |
2735 | MSIX_CAP_LENGTH); | |
2736 | } | |
2737 | ||
2738 | if (pdev->cap_present & QEMU_PCI_CAP_MSI) { | |
2739 | memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, | |
2740 | vdev->msi_cap_size); | |
2741 | } | |
2742 | ||
65501a74 | 2743 | if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { |
bc72ad67 | 2744 | vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, |
ea486926 | 2745 | vfio_intx_mmap_enable, vdev); |
870cb6f1 | 2746 | pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); |
7dfb3424 | 2747 | ret = vfio_intx_enable(vdev, &err); |
65501a74 AW |
2748 | if (ret) { |
2749 | goto out_teardown; | |
2750 | } | |
2751 | } | |
2752 | ||
7b4b0e9e | 2753 | vfio_register_err_notifier(vdev); |
47cbe50c | 2754 | vfio_register_req_notifier(vdev); |
c9c50009 | 2755 | vfio_setup_resetfn_quirk(vdev); |
c29029dd | 2756 | |
65501a74 AW |
2757 | return 0; |
2758 | ||
2759 | out_teardown: | |
2760 | pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); | |
2761 | vfio_teardown_msi(vdev); | |
2d82f8a3 | 2762 | vfio_bars_exit(vdev); |
426ec904 EA |
2763 | error: |
2764 | if (err) { | |
2765 | error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); | |
2766 | } | |
77a10d04 PB |
2767 | return ret; |
2768 | } | |
2769 | ||
2770 | static void vfio_instance_finalize(Object *obj) | |
2771 | { | |
2772 | PCIDevice *pci_dev = PCI_DEVICE(obj); | |
2773 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pci_dev); | |
2774 | VFIOGroup *group = vdev->vbasedev.group; | |
2775 | ||
2d82f8a3 | 2776 | vfio_bars_finalize(vdev); |
4b5d5e87 | 2777 | g_free(vdev->emulated_config_bits); |
77a10d04 | 2778 | g_free(vdev->rom); |
c4c45e94 AW |
2779 | /* |
2780 | * XXX Leaking igd_opregion is not an oversight, we can't remove the | |
2781 | * fw_cfg entry therefore leaking this allocation seems like the safest | |
2782 | * option. | |
2783 | * | |
2784 | * g_free(vdev->igd_opregion); | |
2785 | */ | |
65501a74 AW |
2786 | vfio_put_device(vdev); |
2787 | vfio_put_group(group); | |
65501a74 AW |
2788 | } |
2789 | ||
2790 | static void vfio_exitfn(PCIDevice *pdev) | |
2791 | { | |
9ee27d73 | 2792 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 2793 | |
47cbe50c | 2794 | vfio_unregister_req_notifier(vdev); |
7b4b0e9e | 2795 | vfio_unregister_err_notifier(vdev); |
65501a74 AW |
2796 | pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); |
2797 | vfio_disable_interrupts(vdev); | |
ea486926 | 2798 | if (vdev->intx.mmap_timer) { |
bc72ad67 | 2799 | timer_free(vdev->intx.mmap_timer); |
ea486926 | 2800 | } |
65501a74 | 2801 | vfio_teardown_msi(vdev); |
2d82f8a3 | 2802 | vfio_bars_exit(vdev); |
65501a74 AW |
2803 | } |
2804 | ||
2805 | static void vfio_pci_reset(DeviceState *dev) | |
2806 | { | |
2807 | PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev); | |
9ee27d73 | 2808 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 2809 | |
df92ee44 | 2810 | trace_vfio_pci_reset(vdev->vbasedev.name); |
5834a83f | 2811 | |
f16f39c3 | 2812 | vfio_pci_pre_reset(vdev); |
ba661818 | 2813 | |
5655f931 AW |
2814 | if (vdev->resetfn && !vdev->resetfn(vdev)) { |
2815 | goto post_reset; | |
2816 | } | |
2817 | ||
b47d8efa EA |
2818 | if (vdev->vbasedev.reset_works && |
2819 | (vdev->has_flr || !vdev->has_pm_reset) && | |
5546a621 | 2820 | !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { |
df92ee44 | 2821 | trace_vfio_pci_reset_flr(vdev->vbasedev.name); |
f16f39c3 | 2822 | goto post_reset; |
ba661818 AW |
2823 | } |
2824 | ||
f16f39c3 AW |
2825 | /* See if we can do our own bus reset */ |
2826 | if (!vfio_pci_hot_reset_one(vdev)) { | |
2827 | goto post_reset; | |
2828 | } | |
5834a83f | 2829 | |
f16f39c3 | 2830 | /* If nothing else works and the device supports PM reset, use it */ |
b47d8efa | 2831 | if (vdev->vbasedev.reset_works && vdev->has_pm_reset && |
5546a621 | 2832 | !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { |
df92ee44 | 2833 | trace_vfio_pci_reset_pm(vdev->vbasedev.name); |
f16f39c3 | 2834 | goto post_reset; |
65501a74 | 2835 | } |
5834a83f | 2836 | |
f16f39c3 AW |
2837 | post_reset: |
2838 | vfio_pci_post_reset(vdev); | |
65501a74 AW |
2839 | } |
2840 | ||
abc5b3bf GA |
2841 | static void vfio_instance_init(Object *obj) |
2842 | { | |
2843 | PCIDevice *pci_dev = PCI_DEVICE(obj); | |
9ee27d73 | 2844 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, PCI_DEVICE(obj)); |
abc5b3bf GA |
2845 | |
2846 | device_add_bootindex_property(obj, &vdev->bootindex, | |
2847 | "bootindex", NULL, | |
2848 | &pci_dev->qdev, NULL); | |
2849 | } | |
2850 | ||
65501a74 | 2851 | static Property vfio_pci_dev_properties[] = { |
9ee27d73 | 2852 | DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), |
7df9381b | 2853 | DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev), |
9ee27d73 | 2854 | DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, |
ea486926 | 2855 | intx.mmap_timeout, 1100), |
9ee27d73 | 2856 | DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, |
f15689c7 | 2857 | VFIO_FEATURE_ENABLE_VGA_BIT, false), |
47cbe50c AW |
2858 | DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, |
2859 | VFIO_FEATURE_ENABLE_REQ_BIT, true), | |
6ced0bba AW |
2860 | DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features, |
2861 | VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false), | |
5e15d79b | 2862 | DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false), |
46746dba AW |
2863 | DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false), |
2864 | DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false), | |
2865 | DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false), | |
89dcccc5 AW |
2866 | DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID), |
2867 | DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID), | |
2868 | DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice, | |
2869 | sub_vendor_id, PCI_ANY_ID), | |
2870 | DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, | |
2871 | sub_device_id, PCI_ANY_ID), | |
c4c45e94 | 2872 | DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), |
65501a74 AW |
2873 | /* |
2874 | * TODO - support passed fds... is this necessary? | |
9ee27d73 EA |
2875 | * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), |
2876 | * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), | |
65501a74 AW |
2877 | */ |
2878 | DEFINE_PROP_END_OF_LIST(), | |
2879 | }; | |
2880 | ||
d9f0e638 AW |
2881 | static const VMStateDescription vfio_pci_vmstate = { |
2882 | .name = "vfio-pci", | |
2883 | .unmigratable = 1, | |
2884 | }; | |
65501a74 AW |
2885 | |
2886 | static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) | |
2887 | { | |
2888 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2889 | PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); | |
2890 | ||
2891 | dc->reset = vfio_pci_reset; | |
2892 | dc->props = vfio_pci_dev_properties; | |
d9f0e638 AW |
2893 | dc->vmsd = &vfio_pci_vmstate; |
2894 | dc->desc = "VFIO-based PCI device assignment"; | |
125ee0ed | 2895 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
65501a74 AW |
2896 | pdc->init = vfio_initfn; |
2897 | pdc->exit = vfio_exitfn; | |
2898 | pdc->config_read = vfio_pci_read_config; | |
2899 | pdc->config_write = vfio_pci_write_config; | |
6a659bbf | 2900 | pdc->is_express = 1; /* We might be */ |
65501a74 AW |
2901 | } |
2902 | ||
2903 | static const TypeInfo vfio_pci_dev_info = { | |
2904 | .name = "vfio-pci", | |
2905 | .parent = TYPE_PCI_DEVICE, | |
9ee27d73 | 2906 | .instance_size = sizeof(VFIOPCIDevice), |
65501a74 | 2907 | .class_init = vfio_pci_dev_class_init, |
abc5b3bf | 2908 | .instance_init = vfio_instance_init, |
77a10d04 | 2909 | .instance_finalize = vfio_instance_finalize, |
65501a74 AW |
2910 | }; |
2911 | ||
2912 | static void register_vfio_pci_dev_type(void) | |
2913 | { | |
2914 | type_register_static(&vfio_pci_dev_info); | |
2915 | } | |
2916 | ||
2917 | type_init(register_vfio_pci_dev_type) |