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Commit | Line | Data |
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65501a74 AW |
1 | /* |
2 | * vfio based device assignment support | |
3 | * | |
4 | * Copyright Red Hat, Inc. 2012 | |
5 | * | |
6 | * Authors: | |
7 | * Alex Williamson <alex.williamson@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
12 | * Based on qemu-kvm device-assignment: | |
13 | * Adapted for KVM by Qumranet. | |
14 | * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) | |
15 | * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) | |
16 | * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) | |
17 | * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) | |
18 | * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) | |
19 | */ | |
20 | ||
21 | #include <dirent.h> | |
6dcfdbad | 22 | #include <linux/vfio.h> |
65501a74 AW |
23 | #include <sys/ioctl.h> |
24 | #include <sys/mman.h> | |
25 | #include <sys/stat.h> | |
26 | #include <sys/types.h> | |
6dcfdbad | 27 | #include <unistd.h> |
65501a74 AW |
28 | |
29 | #include "config.h" | |
022c62cb | 30 | #include "exec/address-spaces.h" |
022c62cb | 31 | #include "exec/memory.h" |
83c9f4ca PB |
32 | #include "hw/pci/msi.h" |
33 | #include "hw/pci/msix.h" | |
34 | #include "hw/pci/pci.h" | |
5c97e5eb | 35 | #include "qemu-common.h" |
1de7afc9 | 36 | #include "qemu/error-report.h" |
6dcfdbad | 37 | #include "qemu/event_notifier.h" |
1de7afc9 PB |
38 | #include "qemu/queue.h" |
39 | #include "qemu/range.h" | |
6dcfdbad AW |
40 | #include "sysemu/kvm.h" |
41 | #include "sysemu/sysemu.h" | |
385f57cf | 42 | #include "trace.h" |
cf7087db | 43 | #include "hw/vfio/vfio.h" |
e2c7d025 | 44 | #include "hw/vfio/vfio-common.h" |
462037c9 | 45 | |
9ee27d73 | 46 | struct VFIOPCIDevice; |
7076eabc AW |
47 | |
48 | typedef struct VFIOQuirk { | |
49 | MemoryRegion mem; | |
9ee27d73 | 50 | struct VFIOPCIDevice *vdev; |
7076eabc | 51 | QLIST_ENTRY(VFIOQuirk) next; |
39360f0b AW |
52 | struct { |
53 | uint32_t base_offset:TARGET_PAGE_BITS; | |
54 | uint32_t address_offset:TARGET_PAGE_BITS; | |
55 | uint32_t address_size:3; | |
56 | uint32_t bar:3; | |
57 | ||
58 | uint32_t address_match; | |
59 | uint32_t address_mask; | |
60 | ||
61 | uint32_t address_val:TARGET_PAGE_BITS; | |
62 | uint32_t data_offset:TARGET_PAGE_BITS; | |
63 | uint32_t data_size:3; | |
64 | ||
65 | uint8_t flags; | |
66 | uint8_t read_flags; | |
67 | uint8_t write_flags; | |
68 | } data; | |
7076eabc AW |
69 | } VFIOQuirk; |
70 | ||
a664477d EA |
71 | typedef struct VFIOBAR { |
72 | VFIORegion region; | |
39360f0b AW |
73 | bool ioport; |
74 | bool mem64; | |
7076eabc | 75 | QLIST_HEAD(, VFIOQuirk) quirks; |
5c97e5eb AW |
76 | } VFIOBAR; |
77 | ||
f15689c7 AW |
78 | typedef struct VFIOVGARegion { |
79 | MemoryRegion mem; | |
80 | off_t offset; | |
81 | int nr; | |
7076eabc | 82 | QLIST_HEAD(, VFIOQuirk) quirks; |
f15689c7 AW |
83 | } VFIOVGARegion; |
84 | ||
85 | typedef struct VFIOVGA { | |
86 | off_t fd_offset; | |
87 | int fd; | |
88 | VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS]; | |
89 | } VFIOVGA; | |
90 | ||
5c97e5eb AW |
91 | typedef struct VFIOINTx { |
92 | bool pending; /* interrupt pending */ | |
93 | bool kvm_accel; /* set when QEMU bypass through KVM enabled */ | |
94 | uint8_t pin; /* which pin to pull for qemu_set_irq */ | |
95 | EventNotifier interrupt; /* eventfd triggered on interrupt */ | |
96 | EventNotifier unmask; /* eventfd for unmask on QEMU bypass */ | |
97 | PCIINTxRoute route; /* routing info for QEMU bypass */ | |
98 | uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */ | |
99 | QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */ | |
100 | } VFIOINTx; | |
101 | ||
5c97e5eb | 102 | typedef struct VFIOMSIVector { |
c048be5c AW |
103 | /* |
104 | * Two interrupt paths are configured per vector. The first, is only used | |
105 | * for interrupts injected via QEMU. This is typically the non-accel path, | |
106 | * but may also be used when we want QEMU to handle masking and pending | |
107 | * bits. The KVM path bypasses QEMU and is therefore higher performance, | |
108 | * but requires masking at the device. virq is used to track the MSI route | |
109 | * through KVM, thus kvm_interrupt is only available when virq is set to a | |
110 | * valid (>= 0) value. | |
111 | */ | |
112 | EventNotifier interrupt; | |
113 | EventNotifier kvm_interrupt; | |
9ee27d73 | 114 | struct VFIOPCIDevice *vdev; /* back pointer to device */ |
c048be5c | 115 | int virq; |
5c97e5eb AW |
116 | bool use; |
117 | } VFIOMSIVector; | |
118 | ||
119 | enum { | |
120 | VFIO_INT_NONE = 0, | |
121 | VFIO_INT_INTx = 1, | |
122 | VFIO_INT_MSI = 2, | |
123 | VFIO_INT_MSIX = 3, | |
124 | }; | |
125 | ||
5c97e5eb AW |
126 | /* Cache of MSI-X setup plus extra mmap and memory region for split BAR map */ |
127 | typedef struct VFIOMSIXInfo { | |
128 | uint8_t table_bar; | |
129 | uint8_t pba_bar; | |
130 | uint16_t entries; | |
131 | uint32_t table_offset; | |
132 | uint32_t pba_offset; | |
133 | MemoryRegion mmap_mem; | |
134 | void *mmap; | |
135 | } VFIOMSIXInfo; | |
136 | ||
9ee27d73 | 137 | typedef struct VFIOPCIDevice { |
5c97e5eb | 138 | PCIDevice pdev; |
5546a621 | 139 | VFIODevice vbasedev; |
5c97e5eb AW |
140 | VFIOINTx intx; |
141 | unsigned int config_size; | |
4b5d5e87 | 142 | uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */ |
5c97e5eb AW |
143 | off_t config_offset; /* Offset of config space region within device fd */ |
144 | unsigned int rom_size; | |
145 | off_t rom_offset; /* Offset of ROM region within device fd */ | |
6f864e6e | 146 | void *rom; |
5c97e5eb AW |
147 | int msi_cap_size; |
148 | VFIOMSIVector *msi_vectors; | |
149 | VFIOMSIXInfo *msix; | |
150 | int nr_vectors; /* Number of MSI/MSIX vectors currently in use */ | |
151 | int interrupt; /* Current interrupt type */ | |
152 | VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */ | |
f15689c7 | 153 | VFIOVGA vga; /* 0xa0000, 0x3b0, 0x3c0 */ |
5c97e5eb | 154 | PCIHostDeviceAddress host; |
7b4b0e9e | 155 | EventNotifier err_notifier; |
47cbe50c | 156 | EventNotifier req_notifier; |
f15689c7 AW |
157 | uint32_t features; |
158 | #define VFIO_FEATURE_ENABLE_VGA_BIT 0 | |
159 | #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) | |
47cbe50c AW |
160 | #define VFIO_FEATURE_ENABLE_REQ_BIT 1 |
161 | #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) | |
c29029dd | 162 | int32_t bootindex; |
ba661818 | 163 | uint8_t pm_cap; |
f15689c7 | 164 | bool has_vga; |
7b4b0e9e | 165 | bool pci_aer; |
47cbe50c | 166 | bool req_enabled; |
befe5176 AW |
167 | bool has_flr; |
168 | bool has_pm_reset; | |
e638073c | 169 | bool rom_read_failed; |
9ee27d73 | 170 | } VFIOPCIDevice; |
5c97e5eb | 171 | |
4b943029 BD |
172 | typedef struct VFIORomBlacklistEntry { |
173 | uint16_t vendor_id; | |
174 | uint16_t device_id; | |
175 | } VFIORomBlacklistEntry; | |
176 | ||
177 | /* | |
178 | * List of device ids/vendor ids for which to disable | |
179 | * option rom loading. This avoids the guest hangs during rom | |
180 | * execution as noticed with the BCM 57810 card for lack of a | |
181 | * more better way to handle such issues. | |
182 | * The user can still override by specifying a romfile or | |
183 | * rombar=1. | |
184 | * Please see https://bugs.launchpad.net/qemu/+bug/1284874 | |
185 | * for an analysis of the 57810 card hang. When adding | |
186 | * a new vendor id/device id combination below, please also add | |
187 | * your card/environment details and information that could | |
188 | * help in debugging to the bug tracking this issue | |
189 | */ | |
190 | static const VFIORomBlacklistEntry romblacklist[] = { | |
191 | /* Broadcom BCM 57810 */ | |
192 | { 0x14e4, 0x168e } | |
193 | }; | |
194 | ||
65501a74 AW |
195 | #define MSIX_CAP_LENGTH 12 |
196 | ||
9ee27d73 | 197 | static void vfio_disable_interrupts(VFIOPCIDevice *vdev); |
65501a74 | 198 | static uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len); |
7076eabc AW |
199 | static void vfio_pci_write_config(PCIDevice *pdev, uint32_t addr, |
200 | uint32_t val, int len); | |
9ee27d73 | 201 | static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); |
65501a74 | 202 | |
ea486926 AW |
203 | /* |
204 | * Disabling BAR mmaping can be slow, but toggling it around INTx can | |
205 | * also be a huge overhead. We try to get the best of both worlds by | |
206 | * waiting until an interrupt to disable mmaps (subsequent transitions | |
207 | * to the same state are effectively no overhead). If the interrupt has | |
208 | * been serviced and the time gap is long enough, we re-enable mmaps for | |
209 | * performance. This works well for things like graphics cards, which | |
210 | * may not use their interrupt at all and are penalized to an unusable | |
211 | * level by read/write BAR traps. Other devices, like NICs, have more | |
212 | * regular interrupts and see much better latency by staying in non-mmap | |
213 | * mode. We therefore set the default mmap_timeout such that a ping | |
214 | * is just enough to keep the mmap disabled. Users can experiment with | |
215 | * other options with the x-intx-mmap-timeout-ms parameter (a value of | |
216 | * zero disables the timer). | |
217 | */ | |
218 | static void vfio_intx_mmap_enable(void *opaque) | |
219 | { | |
9ee27d73 | 220 | VFIOPCIDevice *vdev = opaque; |
ea486926 AW |
221 | |
222 | if (vdev->intx.pending) { | |
bc72ad67 AB |
223 | timer_mod(vdev->intx.mmap_timer, |
224 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); | |
ea486926 AW |
225 | return; |
226 | } | |
227 | ||
228 | vfio_mmap_set_enabled(vdev, true); | |
229 | } | |
230 | ||
65501a74 AW |
231 | static void vfio_intx_interrupt(void *opaque) |
232 | { | |
9ee27d73 | 233 | VFIOPCIDevice *vdev = opaque; |
65501a74 AW |
234 | |
235 | if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { | |
236 | return; | |
237 | } | |
238 | ||
df92ee44 | 239 | trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); |
65501a74 AW |
240 | |
241 | vdev->intx.pending = true; | |
68919cac | 242 | pci_irq_assert(&vdev->pdev); |
ea486926 AW |
243 | vfio_mmap_set_enabled(vdev, false); |
244 | if (vdev->intx.mmap_timeout) { | |
bc72ad67 AB |
245 | timer_mod(vdev->intx.mmap_timer, |
246 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); | |
ea486926 | 247 | } |
65501a74 AW |
248 | } |
249 | ||
a664477d | 250 | static void vfio_eoi(VFIODevice *vbasedev) |
65501a74 | 251 | { |
a664477d EA |
252 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); |
253 | ||
65501a74 AW |
254 | if (!vdev->intx.pending) { |
255 | return; | |
256 | } | |
257 | ||
df92ee44 | 258 | trace_vfio_eoi(vbasedev->name); |
65501a74 AW |
259 | |
260 | vdev->intx.pending = false; | |
68919cac | 261 | pci_irq_deassert(&vdev->pdev); |
a664477d | 262 | vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
65501a74 AW |
263 | } |
264 | ||
9ee27d73 | 265 | static void vfio_enable_intx_kvm(VFIOPCIDevice *vdev) |
e1d1e586 AW |
266 | { |
267 | #ifdef CONFIG_KVM | |
268 | struct kvm_irqfd irqfd = { | |
269 | .fd = event_notifier_get_fd(&vdev->intx.interrupt), | |
270 | .gsi = vdev->intx.route.irq, | |
271 | .flags = KVM_IRQFD_FLAG_RESAMPLE, | |
272 | }; | |
273 | struct vfio_irq_set *irq_set; | |
274 | int ret, argsz; | |
275 | int32_t *pfd; | |
276 | ||
82ca8912 | 277 | if (!VFIO_ALLOW_KVM_INTX || !kvm_irqfds_enabled() || |
e1d1e586 | 278 | vdev->intx.route.mode != PCI_INTX_ENABLED || |
9fc0e2d8 | 279 | !kvm_resamplefds_enabled()) { |
e1d1e586 AW |
280 | return; |
281 | } | |
282 | ||
283 | /* Get to a known interrupt state */ | |
284 | qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); | |
5546a621 | 285 | vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 286 | vdev->intx.pending = false; |
68919cac | 287 | pci_irq_deassert(&vdev->pdev); |
e1d1e586 AW |
288 | |
289 | /* Get an eventfd for resample/unmask */ | |
290 | if (event_notifier_init(&vdev->intx.unmask, 0)) { | |
312fd5f2 | 291 | error_report("vfio: Error: event_notifier_init failed eoi"); |
e1d1e586 AW |
292 | goto fail; |
293 | } | |
294 | ||
295 | /* KVM triggers it, VFIO listens for it */ | |
296 | irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); | |
297 | ||
298 | if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { | |
312fd5f2 | 299 | error_report("vfio: Error: Failed to setup resample irqfd: %m"); |
e1d1e586 AW |
300 | goto fail_irqfd; |
301 | } | |
302 | ||
303 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
304 | ||
305 | irq_set = g_malloc0(argsz); | |
306 | irq_set->argsz = argsz; | |
307 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; | |
308 | irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; | |
309 | irq_set->start = 0; | |
310 | irq_set->count = 1; | |
311 | pfd = (int32_t *)&irq_set->data; | |
312 | ||
313 | *pfd = irqfd.resamplefd; | |
314 | ||
5546a621 | 315 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
e1d1e586 AW |
316 | g_free(irq_set); |
317 | if (ret) { | |
312fd5f2 | 318 | error_report("vfio: Error: Failed to setup INTx unmask fd: %m"); |
e1d1e586 AW |
319 | goto fail_vfio; |
320 | } | |
321 | ||
322 | /* Let'em rip */ | |
5546a621 | 323 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 AW |
324 | |
325 | vdev->intx.kvm_accel = true; | |
326 | ||
df92ee44 | 327 | trace_vfio_enable_intx_kvm(vdev->vbasedev.name); |
e1d1e586 AW |
328 | |
329 | return; | |
330 | ||
331 | fail_vfio: | |
332 | irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; | |
333 | kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); | |
334 | fail_irqfd: | |
335 | event_notifier_cleanup(&vdev->intx.unmask); | |
336 | fail: | |
337 | qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); | |
5546a621 | 338 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 AW |
339 | #endif |
340 | } | |
341 | ||
9ee27d73 | 342 | static void vfio_disable_intx_kvm(VFIOPCIDevice *vdev) |
e1d1e586 AW |
343 | { |
344 | #ifdef CONFIG_KVM | |
345 | struct kvm_irqfd irqfd = { | |
346 | .fd = event_notifier_get_fd(&vdev->intx.interrupt), | |
347 | .gsi = vdev->intx.route.irq, | |
348 | .flags = KVM_IRQFD_FLAG_DEASSIGN, | |
349 | }; | |
350 | ||
351 | if (!vdev->intx.kvm_accel) { | |
352 | return; | |
353 | } | |
354 | ||
355 | /* | |
356 | * Get to a known state, hardware masked, QEMU ready to accept new | |
357 | * interrupts, QEMU IRQ de-asserted. | |
358 | */ | |
5546a621 | 359 | vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 360 | vdev->intx.pending = false; |
68919cac | 361 | pci_irq_deassert(&vdev->pdev); |
e1d1e586 AW |
362 | |
363 | /* Tell KVM to stop listening for an INTx irqfd */ | |
364 | if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { | |
312fd5f2 | 365 | error_report("vfio: Error: Failed to disable INTx irqfd: %m"); |
e1d1e586 AW |
366 | } |
367 | ||
368 | /* We only need to close the eventfd for VFIO to cleanup the kernel side */ | |
369 | event_notifier_cleanup(&vdev->intx.unmask); | |
370 | ||
371 | /* QEMU starts listening for interrupt events. */ | |
372 | qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); | |
373 | ||
374 | vdev->intx.kvm_accel = false; | |
375 | ||
376 | /* If we've missed an event, let it re-fire through QEMU */ | |
5546a621 | 377 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 378 | |
df92ee44 | 379 | trace_vfio_disable_intx_kvm(vdev->vbasedev.name); |
e1d1e586 AW |
380 | #endif |
381 | } | |
382 | ||
383 | static void vfio_update_irq(PCIDevice *pdev) | |
384 | { | |
9ee27d73 | 385 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
e1d1e586 AW |
386 | PCIINTxRoute route; |
387 | ||
388 | if (vdev->interrupt != VFIO_INT_INTx) { | |
389 | return; | |
390 | } | |
391 | ||
392 | route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); | |
393 | ||
394 | if (!pci_intx_route_changed(&vdev->intx.route, &route)) { | |
395 | return; /* Nothing changed */ | |
396 | } | |
397 | ||
df92ee44 | 398 | trace_vfio_update_irq(vdev->vbasedev.name, |
385f57cf | 399 | vdev->intx.route.irq, route.irq); |
e1d1e586 AW |
400 | |
401 | vfio_disable_intx_kvm(vdev); | |
402 | ||
403 | vdev->intx.route = route; | |
404 | ||
405 | if (route.mode != PCI_INTX_ENABLED) { | |
406 | return; | |
407 | } | |
408 | ||
409 | vfio_enable_intx_kvm(vdev); | |
410 | ||
411 | /* Re-enable the interrupt in cased we missed an EOI */ | |
a664477d | 412 | vfio_eoi(&vdev->vbasedev); |
e1d1e586 AW |
413 | } |
414 | ||
9ee27d73 | 415 | static int vfio_enable_intx(VFIOPCIDevice *vdev) |
65501a74 | 416 | { |
65501a74 | 417 | uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); |
1a403133 AW |
418 | int ret, argsz; |
419 | struct vfio_irq_set *irq_set; | |
420 | int32_t *pfd; | |
65501a74 | 421 | |
ea486926 | 422 | if (!pin) { |
65501a74 AW |
423 | return 0; |
424 | } | |
425 | ||
426 | vfio_disable_interrupts(vdev); | |
427 | ||
428 | vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ | |
68919cac | 429 | pci_config_set_interrupt_pin(vdev->pdev.config, pin); |
e1d1e586 AW |
430 | |
431 | #ifdef CONFIG_KVM | |
432 | /* | |
433 | * Only conditional to avoid generating error messages on platforms | |
434 | * where we won't actually use the result anyway. | |
435 | */ | |
9fc0e2d8 | 436 | if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { |
e1d1e586 AW |
437 | vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, |
438 | vdev->intx.pin); | |
439 | } | |
440 | #endif | |
441 | ||
65501a74 AW |
442 | ret = event_notifier_init(&vdev->intx.interrupt, 0); |
443 | if (ret) { | |
312fd5f2 | 444 | error_report("vfio: Error: event_notifier_init failed"); |
65501a74 AW |
445 | return ret; |
446 | } | |
447 | ||
1a403133 AW |
448 | argsz = sizeof(*irq_set) + sizeof(*pfd); |
449 | ||
450 | irq_set = g_malloc0(argsz); | |
451 | irq_set->argsz = argsz; | |
452 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; | |
453 | irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; | |
454 | irq_set->start = 0; | |
455 | irq_set->count = 1; | |
456 | pfd = (int32_t *)&irq_set->data; | |
457 | ||
458 | *pfd = event_notifier_get_fd(&vdev->intx.interrupt); | |
459 | qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); | |
65501a74 | 460 | |
5546a621 | 461 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
1a403133 AW |
462 | g_free(irq_set); |
463 | if (ret) { | |
312fd5f2 | 464 | error_report("vfio: Error: Failed to setup INTx fd: %m"); |
1a403133 | 465 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); |
ce59af2d | 466 | event_notifier_cleanup(&vdev->intx.interrupt); |
65501a74 AW |
467 | return -errno; |
468 | } | |
469 | ||
e1d1e586 AW |
470 | vfio_enable_intx_kvm(vdev); |
471 | ||
65501a74 AW |
472 | vdev->interrupt = VFIO_INT_INTx; |
473 | ||
df92ee44 | 474 | trace_vfio_enable_intx(vdev->vbasedev.name); |
65501a74 AW |
475 | |
476 | return 0; | |
477 | } | |
478 | ||
9ee27d73 | 479 | static void vfio_disable_intx(VFIOPCIDevice *vdev) |
65501a74 AW |
480 | { |
481 | int fd; | |
482 | ||
bc72ad67 | 483 | timer_del(vdev->intx.mmap_timer); |
e1d1e586 | 484 | vfio_disable_intx_kvm(vdev); |
5546a621 | 485 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
65501a74 | 486 | vdev->intx.pending = false; |
68919cac | 487 | pci_irq_deassert(&vdev->pdev); |
65501a74 AW |
488 | vfio_mmap_set_enabled(vdev, true); |
489 | ||
490 | fd = event_notifier_get_fd(&vdev->intx.interrupt); | |
491 | qemu_set_fd_handler(fd, NULL, NULL, vdev); | |
492 | event_notifier_cleanup(&vdev->intx.interrupt); | |
493 | ||
494 | vdev->interrupt = VFIO_INT_NONE; | |
495 | ||
df92ee44 | 496 | trace_vfio_disable_intx(vdev->vbasedev.name); |
65501a74 AW |
497 | } |
498 | ||
499 | /* | |
500 | * MSI/X | |
501 | */ | |
502 | static void vfio_msi_interrupt(void *opaque) | |
503 | { | |
504 | VFIOMSIVector *vector = opaque; | |
9ee27d73 | 505 | VFIOPCIDevice *vdev = vector->vdev; |
65501a74 AW |
506 | int nr = vector - vdev->msi_vectors; |
507 | ||
508 | if (!event_notifier_test_and_clear(&vector->interrupt)) { | |
509 | return; | |
510 | } | |
511 | ||
8b6d1408 | 512 | #ifdef DEBUG_VFIO |
b3ebc10c AW |
513 | MSIMessage msg; |
514 | ||
515 | if (vdev->interrupt == VFIO_INT_MSIX) { | |
b3ebc10c | 516 | msg = msix_get_message(&vdev->pdev, nr); |
9035f8c0 AW |
517 | } else if (vdev->interrupt == VFIO_INT_MSI) { |
518 | msg = msi_get_message(&vdev->pdev, nr); | |
b3ebc10c AW |
519 | } else { |
520 | abort(); | |
521 | } | |
522 | ||
bc5baffa | 523 | trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); |
b3ebc10c | 524 | #endif |
65501a74 AW |
525 | |
526 | if (vdev->interrupt == VFIO_INT_MSIX) { | |
527 | msix_notify(&vdev->pdev, nr); | |
528 | } else if (vdev->interrupt == VFIO_INT_MSI) { | |
529 | msi_notify(&vdev->pdev, nr); | |
530 | } else { | |
312fd5f2 | 531 | error_report("vfio: MSI interrupt receieved, but not enabled?"); |
65501a74 AW |
532 | } |
533 | } | |
534 | ||
9ee27d73 | 535 | static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) |
65501a74 AW |
536 | { |
537 | struct vfio_irq_set *irq_set; | |
538 | int ret = 0, i, argsz; | |
539 | int32_t *fds; | |
540 | ||
541 | argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); | |
542 | ||
543 | irq_set = g_malloc0(argsz); | |
544 | irq_set->argsz = argsz; | |
545 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; | |
546 | irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; | |
547 | irq_set->start = 0; | |
548 | irq_set->count = vdev->nr_vectors; | |
549 | fds = (int32_t *)&irq_set->data; | |
550 | ||
551 | for (i = 0; i < vdev->nr_vectors; i++) { | |
c048be5c AW |
552 | int fd = -1; |
553 | ||
554 | /* | |
555 | * MSI vs MSI-X - The guest has direct access to MSI mask and pending | |
556 | * bits, therefore we always use the KVM signaling path when setup. | |
557 | * MSI-X mask and pending bits are emulated, so we want to use the | |
558 | * KVM signaling path only when configured and unmasked. | |
559 | */ | |
560 | if (vdev->msi_vectors[i].use) { | |
561 | if (vdev->msi_vectors[i].virq < 0 || | |
562 | (msix && msix_is_masked(&vdev->pdev, i))) { | |
563 | fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); | |
564 | } else { | |
565 | fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); | |
566 | } | |
65501a74 | 567 | } |
c048be5c AW |
568 | |
569 | fds[i] = fd; | |
65501a74 AW |
570 | } |
571 | ||
5546a621 | 572 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
65501a74 AW |
573 | |
574 | g_free(irq_set); | |
575 | ||
65501a74 AW |
576 | return ret; |
577 | } | |
578 | ||
f4d45d47 AW |
579 | static void vfio_add_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage *msg, |
580 | bool msix) | |
581 | { | |
582 | int virq; | |
583 | ||
584 | if ((msix && !VFIO_ALLOW_KVM_MSIX) || | |
585 | (!msix && !VFIO_ALLOW_KVM_MSI) || !msg) { | |
586 | return; | |
587 | } | |
588 | ||
589 | if (event_notifier_init(&vector->kvm_interrupt, 0)) { | |
590 | return; | |
591 | } | |
592 | ||
593 | virq = kvm_irqchip_add_msi_route(kvm_state, *msg); | |
594 | if (virq < 0) { | |
595 | event_notifier_cleanup(&vector->kvm_interrupt); | |
596 | return; | |
597 | } | |
598 | ||
599 | if (kvm_irqchip_add_irqfd_notifier(kvm_state, &vector->kvm_interrupt, | |
600 | NULL, virq) < 0) { | |
601 | kvm_irqchip_release_virq(kvm_state, virq); | |
602 | event_notifier_cleanup(&vector->kvm_interrupt); | |
603 | return; | |
604 | } | |
605 | ||
f4d45d47 AW |
606 | vector->virq = virq; |
607 | } | |
608 | ||
609 | static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) | |
610 | { | |
611 | kvm_irqchip_remove_irqfd_notifier(kvm_state, &vector->kvm_interrupt, | |
612 | vector->virq); | |
613 | kvm_irqchip_release_virq(kvm_state, vector->virq); | |
614 | vector->virq = -1; | |
615 | event_notifier_cleanup(&vector->kvm_interrupt); | |
616 | } | |
617 | ||
618 | static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg) | |
619 | { | |
620 | kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg); | |
f4d45d47 AW |
621 | } |
622 | ||
b0223e29 AW |
623 | static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, |
624 | MSIMessage *msg, IOHandler *handler) | |
65501a74 | 625 | { |
9ee27d73 | 626 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 AW |
627 | VFIOMSIVector *vector; |
628 | int ret; | |
629 | ||
df92ee44 | 630 | trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); |
65501a74 | 631 | |
65501a74 | 632 | vector = &vdev->msi_vectors[nr]; |
65501a74 | 633 | |
f4d45d47 AW |
634 | if (!vector->use) { |
635 | vector->vdev = vdev; | |
636 | vector->virq = -1; | |
637 | if (event_notifier_init(&vector->interrupt, 0)) { | |
638 | error_report("vfio: Error: event_notifier_init failed"); | |
639 | } | |
640 | vector->use = true; | |
641 | msix_vector_use(pdev, nr); | |
65501a74 AW |
642 | } |
643 | ||
f4d45d47 AW |
644 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
645 | handler, NULL, vector); | |
646 | ||
65501a74 AW |
647 | /* |
648 | * Attempt to enable route through KVM irqchip, | |
649 | * default to userspace handling if unavailable. | |
650 | */ | |
f4d45d47 AW |
651 | if (vector->virq >= 0) { |
652 | if (!msg) { | |
653 | vfio_remove_kvm_msi_virq(vector); | |
654 | } else { | |
655 | vfio_update_kvm_msi_virq(vector, *msg); | |
65501a74 | 656 | } |
f4d45d47 AW |
657 | } else { |
658 | vfio_add_kvm_msi_virq(vector, msg, true); | |
65501a74 AW |
659 | } |
660 | ||
661 | /* | |
662 | * We don't want to have the host allocate all possible MSI vectors | |
663 | * for a device if they're not in use, so we shutdown and incrementally | |
664 | * increase them as needed. | |
665 | */ | |
666 | if (vdev->nr_vectors < nr + 1) { | |
5546a621 | 667 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); |
65501a74 AW |
668 | vdev->nr_vectors = nr + 1; |
669 | ret = vfio_enable_vectors(vdev, true); | |
670 | if (ret) { | |
312fd5f2 | 671 | error_report("vfio: failed to enable vectors, %d", ret); |
65501a74 | 672 | } |
65501a74 | 673 | } else { |
1a403133 AW |
674 | int argsz; |
675 | struct vfio_irq_set *irq_set; | |
676 | int32_t *pfd; | |
677 | ||
678 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
679 | ||
680 | irq_set = g_malloc0(argsz); | |
681 | irq_set->argsz = argsz; | |
682 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
683 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
684 | irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; | |
685 | irq_set->start = nr; | |
686 | irq_set->count = 1; | |
687 | pfd = (int32_t *)&irq_set->data; | |
688 | ||
f4d45d47 AW |
689 | if (vector->virq >= 0) { |
690 | *pfd = event_notifier_get_fd(&vector->kvm_interrupt); | |
691 | } else { | |
692 | *pfd = event_notifier_get_fd(&vector->interrupt); | |
693 | } | |
1a403133 | 694 | |
5546a621 | 695 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
1a403133 | 696 | g_free(irq_set); |
65501a74 | 697 | if (ret) { |
312fd5f2 | 698 | error_report("vfio: failed to modify vector, %d", ret); |
65501a74 | 699 | } |
65501a74 AW |
700 | } |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
b0223e29 AW |
705 | static int vfio_msix_vector_use(PCIDevice *pdev, |
706 | unsigned int nr, MSIMessage msg) | |
707 | { | |
708 | return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); | |
709 | } | |
710 | ||
65501a74 AW |
711 | static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) |
712 | { | |
9ee27d73 | 713 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 714 | VFIOMSIVector *vector = &vdev->msi_vectors[nr]; |
65501a74 | 715 | |
df92ee44 | 716 | trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); |
65501a74 AW |
717 | |
718 | /* | |
f4d45d47 AW |
719 | * There are still old guests that mask and unmask vectors on every |
720 | * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of | |
721 | * the KVM setup in place, simply switch VFIO to use the non-bypass | |
722 | * eventfd. We'll then fire the interrupt through QEMU and the MSI-X | |
723 | * core will mask the interrupt and set pending bits, allowing it to | |
724 | * be re-asserted on unmask. Nothing to do if already using QEMU mode. | |
65501a74 | 725 | */ |
f4d45d47 AW |
726 | if (vector->virq >= 0) { |
727 | int argsz; | |
728 | struct vfio_irq_set *irq_set; | |
729 | int32_t *pfd; | |
1a403133 | 730 | |
f4d45d47 | 731 | argsz = sizeof(*irq_set) + sizeof(*pfd); |
1a403133 | 732 | |
f4d45d47 AW |
733 | irq_set = g_malloc0(argsz); |
734 | irq_set->argsz = argsz; | |
735 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
736 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
737 | irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; | |
738 | irq_set->start = nr; | |
739 | irq_set->count = 1; | |
740 | pfd = (int32_t *)&irq_set->data; | |
1a403133 | 741 | |
f4d45d47 | 742 | *pfd = event_notifier_get_fd(&vector->interrupt); |
1a403133 | 743 | |
5546a621 | 744 | ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
65501a74 | 745 | |
f4d45d47 | 746 | g_free(irq_set); |
65501a74 | 747 | } |
65501a74 AW |
748 | } |
749 | ||
9ee27d73 | 750 | static void vfio_enable_msix(VFIOPCIDevice *vdev) |
fd704adc AW |
751 | { |
752 | vfio_disable_interrupts(vdev); | |
753 | ||
754 | vdev->msi_vectors = g_malloc0(vdev->msix->entries * sizeof(VFIOMSIVector)); | |
755 | ||
756 | vdev->interrupt = VFIO_INT_MSIX; | |
757 | ||
b0223e29 AW |
758 | /* |
759 | * Some communication channels between VF & PF or PF & fw rely on the | |
760 | * physical state of the device and expect that enabling MSI-X from the | |
761 | * guest enables the same on the host. When our guest is Linux, the | |
762 | * guest driver call to pci_enable_msix() sets the enabling bit in the | |
763 | * MSI-X capability, but leaves the vector table masked. We therefore | |
764 | * can't rely on a vector_use callback (from request_irq() in the guest) | |
765 | * to switch the physical device into MSI-X mode because that may come a | |
766 | * long time after pci_enable_msix(). This code enables vector 0 with | |
767 | * triggering to userspace, then immediately release the vector, leaving | |
768 | * the physical device with no vectors enabled, but MSI-X enabled, just | |
769 | * like the guest view. | |
770 | */ | |
771 | vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); | |
772 | vfio_msix_vector_release(&vdev->pdev, 0); | |
773 | ||
fd704adc | 774 | if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, |
bbef882c | 775 | vfio_msix_vector_release, NULL)) { |
312fd5f2 | 776 | error_report("vfio: msix_set_vector_notifiers failed"); |
fd704adc AW |
777 | } |
778 | ||
df92ee44 | 779 | trace_vfio_enable_msix(vdev->vbasedev.name); |
fd704adc AW |
780 | } |
781 | ||
9ee27d73 | 782 | static void vfio_enable_msi(VFIOPCIDevice *vdev) |
65501a74 AW |
783 | { |
784 | int ret, i; | |
785 | ||
786 | vfio_disable_interrupts(vdev); | |
787 | ||
788 | vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); | |
789 | retry: | |
790 | vdev->msi_vectors = g_malloc0(vdev->nr_vectors * sizeof(VFIOMSIVector)); | |
791 | ||
792 | for (i = 0; i < vdev->nr_vectors; i++) { | |
65501a74 | 793 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; |
9b3af4c0 | 794 | MSIMessage msg = msi_get_message(&vdev->pdev, i); |
65501a74 AW |
795 | |
796 | vector->vdev = vdev; | |
f4d45d47 | 797 | vector->virq = -1; |
65501a74 AW |
798 | vector->use = true; |
799 | ||
800 | if (event_notifier_init(&vector->interrupt, 0)) { | |
312fd5f2 | 801 | error_report("vfio: Error: event_notifier_init failed"); |
65501a74 AW |
802 | } |
803 | ||
f4d45d47 AW |
804 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
805 | vfio_msi_interrupt, NULL, vector); | |
806 | ||
65501a74 AW |
807 | /* |
808 | * Attempt to enable route through KVM irqchip, | |
809 | * default to userspace handling if unavailable. | |
810 | */ | |
9b3af4c0 | 811 | vfio_add_kvm_msi_virq(vector, &msg, false); |
65501a74 AW |
812 | } |
813 | ||
f4d45d47 AW |
814 | /* Set interrupt type prior to possible interrupts */ |
815 | vdev->interrupt = VFIO_INT_MSI; | |
816 | ||
65501a74 AW |
817 | ret = vfio_enable_vectors(vdev, false); |
818 | if (ret) { | |
819 | if (ret < 0) { | |
312fd5f2 | 820 | error_report("vfio: Error: Failed to setup MSI fds: %m"); |
65501a74 AW |
821 | } else if (ret != vdev->nr_vectors) { |
822 | error_report("vfio: Error: Failed to enable %d " | |
312fd5f2 | 823 | "MSI vectors, retry with %d", vdev->nr_vectors, ret); |
65501a74 AW |
824 | } |
825 | ||
826 | for (i = 0; i < vdev->nr_vectors; i++) { | |
827 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
828 | if (vector->virq >= 0) { | |
f4d45d47 | 829 | vfio_remove_kvm_msi_virq(vector); |
65501a74 | 830 | } |
f4d45d47 AW |
831 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
832 | NULL, NULL, NULL); | |
65501a74 AW |
833 | event_notifier_cleanup(&vector->interrupt); |
834 | } | |
835 | ||
836 | g_free(vdev->msi_vectors); | |
837 | ||
838 | if (ret > 0 && ret != vdev->nr_vectors) { | |
839 | vdev->nr_vectors = ret; | |
840 | goto retry; | |
841 | } | |
842 | vdev->nr_vectors = 0; | |
843 | ||
f4d45d47 AW |
844 | /* |
845 | * Failing to setup MSI doesn't really fall within any specification. | |
846 | * Let's try leaving interrupts disabled and hope the guest figures | |
847 | * out to fall back to INTx for this device. | |
848 | */ | |
849 | error_report("vfio: Error: Failed to enable MSI"); | |
850 | vdev->interrupt = VFIO_INT_NONE; | |
851 | ||
65501a74 AW |
852 | return; |
853 | } | |
854 | ||
df92ee44 | 855 | trace_vfio_enable_msi(vdev->vbasedev.name, vdev->nr_vectors); |
65501a74 AW |
856 | } |
857 | ||
9ee27d73 | 858 | static void vfio_disable_msi_common(VFIOPCIDevice *vdev) |
fd704adc | 859 | { |
f4d45d47 AW |
860 | int i; |
861 | ||
862 | for (i = 0; i < vdev->nr_vectors; i++) { | |
863 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
864 | if (vdev->msi_vectors[i].use) { | |
865 | if (vector->virq >= 0) { | |
866 | vfio_remove_kvm_msi_virq(vector); | |
867 | } | |
868 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), | |
869 | NULL, NULL, NULL); | |
870 | event_notifier_cleanup(&vector->interrupt); | |
871 | } | |
872 | } | |
873 | ||
fd704adc AW |
874 | g_free(vdev->msi_vectors); |
875 | vdev->msi_vectors = NULL; | |
876 | vdev->nr_vectors = 0; | |
877 | vdev->interrupt = VFIO_INT_NONE; | |
878 | ||
879 | vfio_enable_intx(vdev); | |
880 | } | |
881 | ||
9ee27d73 | 882 | static void vfio_disable_msix(VFIOPCIDevice *vdev) |
fd704adc | 883 | { |
3e40ba0f AW |
884 | int i; |
885 | ||
fd704adc AW |
886 | msix_unset_vector_notifiers(&vdev->pdev); |
887 | ||
3e40ba0f AW |
888 | /* |
889 | * MSI-X will only release vectors if MSI-X is still enabled on the | |
890 | * device, check through the rest and release it ourselves if necessary. | |
891 | */ | |
892 | for (i = 0; i < vdev->nr_vectors; i++) { | |
893 | if (vdev->msi_vectors[i].use) { | |
894 | vfio_msix_vector_release(&vdev->pdev, i); | |
f4d45d47 | 895 | msix_vector_unuse(&vdev->pdev, i); |
3e40ba0f AW |
896 | } |
897 | } | |
898 | ||
fd704adc | 899 | if (vdev->nr_vectors) { |
5546a621 | 900 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); |
fd704adc AW |
901 | } |
902 | ||
903 | vfio_disable_msi_common(vdev); | |
904 | ||
df92ee44 | 905 | trace_vfio_disable_msix(vdev->vbasedev.name); |
fd704adc AW |
906 | } |
907 | ||
9ee27d73 | 908 | static void vfio_disable_msi(VFIOPCIDevice *vdev) |
65501a74 | 909 | { |
5546a621 | 910 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); |
fd704adc | 911 | vfio_disable_msi_common(vdev); |
65501a74 | 912 | |
df92ee44 | 913 | trace_vfio_disable_msi(vdev->vbasedev.name); |
65501a74 AW |
914 | } |
915 | ||
9ee27d73 | 916 | static void vfio_update_msi(VFIOPCIDevice *vdev) |
c7679d45 AW |
917 | { |
918 | int i; | |
919 | ||
920 | for (i = 0; i < vdev->nr_vectors; i++) { | |
921 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
922 | MSIMessage msg; | |
923 | ||
924 | if (!vector->use || vector->virq < 0) { | |
925 | continue; | |
926 | } | |
927 | ||
928 | msg = msi_get_message(&vdev->pdev, i); | |
f4d45d47 | 929 | vfio_update_kvm_msi_virq(vector, msg); |
c7679d45 AW |
930 | } |
931 | } | |
932 | ||
9ee27d73 | 933 | static void vfio_pci_load_rom(VFIOPCIDevice *vdev) |
6f864e6e AW |
934 | { |
935 | struct vfio_region_info reg_info = { | |
936 | .argsz = sizeof(reg_info), | |
937 | .index = VFIO_PCI_ROM_REGION_INDEX | |
938 | }; | |
939 | uint64_t size; | |
940 | off_t off = 0; | |
941 | size_t bytes; | |
942 | ||
5546a621 | 943 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { |
6f864e6e AW |
944 | error_report("vfio: Error getting ROM info: %m"); |
945 | return; | |
946 | } | |
947 | ||
df92ee44 | 948 | trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info.size, |
385f57cf EA |
949 | (unsigned long)reg_info.offset, |
950 | (unsigned long)reg_info.flags); | |
6f864e6e AW |
951 | |
952 | vdev->rom_size = size = reg_info.size; | |
953 | vdev->rom_offset = reg_info.offset; | |
954 | ||
955 | if (!vdev->rom_size) { | |
e638073c | 956 | vdev->rom_read_failed = true; |
d20b43df | 957 | error_report("vfio-pci: Cannot read device rom at " |
df92ee44 | 958 | "%s", vdev->vbasedev.name); |
d20b43df BD |
959 | error_printf("Device option ROM contents are probably invalid " |
960 | "(check dmesg).\nSkip option ROM probe with rombar=0, " | |
961 | "or load from file with romfile=\n"); | |
6f864e6e AW |
962 | return; |
963 | } | |
964 | ||
965 | vdev->rom = g_malloc(size); | |
966 | memset(vdev->rom, 0xff, size); | |
967 | ||
968 | while (size) { | |
5546a621 EA |
969 | bytes = pread(vdev->vbasedev.fd, vdev->rom + off, |
970 | size, vdev->rom_offset + off); | |
6f864e6e AW |
971 | if (bytes == 0) { |
972 | break; | |
973 | } else if (bytes > 0) { | |
974 | off += bytes; | |
975 | size -= bytes; | |
976 | } else { | |
977 | if (errno == EINTR || errno == EAGAIN) { | |
978 | continue; | |
979 | } | |
980 | error_report("vfio: Error reading device ROM: %m"); | |
981 | break; | |
982 | } | |
983 | } | |
984 | } | |
985 | ||
986 | static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) | |
987 | { | |
9ee27d73 | 988 | VFIOPCIDevice *vdev = opaque; |
75bd0c72 ND |
989 | union { |
990 | uint8_t byte; | |
991 | uint16_t word; | |
992 | uint32_t dword; | |
993 | uint64_t qword; | |
994 | } val; | |
995 | uint64_t data = 0; | |
6f864e6e AW |
996 | |
997 | /* Load the ROM lazily when the guest tries to read it */ | |
db01eedb | 998 | if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { |
6f864e6e AW |
999 | vfio_pci_load_rom(vdev); |
1000 | } | |
1001 | ||
6758008e | 1002 | memcpy(&val, vdev->rom + addr, |
6f864e6e AW |
1003 | (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); |
1004 | ||
75bd0c72 ND |
1005 | switch (size) { |
1006 | case 1: | |
1007 | data = val.byte; | |
1008 | break; | |
1009 | case 2: | |
1010 | data = le16_to_cpu(val.word); | |
1011 | break; | |
1012 | case 4: | |
1013 | data = le32_to_cpu(val.dword); | |
1014 | break; | |
1015 | default: | |
1016 | hw_error("vfio: unsupported read size, %d bytes\n", size); | |
1017 | break; | |
1018 | } | |
1019 | ||
df92ee44 | 1020 | trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); |
6f864e6e | 1021 | |
75bd0c72 | 1022 | return data; |
6f864e6e AW |
1023 | } |
1024 | ||
64fa25a0 AW |
1025 | static void vfio_rom_write(void *opaque, hwaddr addr, |
1026 | uint64_t data, unsigned size) | |
1027 | { | |
1028 | } | |
1029 | ||
6f864e6e AW |
1030 | static const MemoryRegionOps vfio_rom_ops = { |
1031 | .read = vfio_rom_read, | |
64fa25a0 | 1032 | .write = vfio_rom_write, |
6758008e | 1033 | .endianness = DEVICE_LITTLE_ENDIAN, |
6f864e6e AW |
1034 | }; |
1035 | ||
9ee27d73 | 1036 | static bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev) |
4b943029 BD |
1037 | { |
1038 | PCIDevice *pdev = &vdev->pdev; | |
1039 | uint16_t vendor_id, device_id; | |
1040 | int count = 0; | |
1041 | ||
1042 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
1043 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
1044 | ||
1045 | while (count < ARRAY_SIZE(romblacklist)) { | |
1046 | if (romblacklist[count].vendor_id == vendor_id && | |
1047 | romblacklist[count].device_id == device_id) { | |
1048 | return true; | |
1049 | } | |
1050 | count++; | |
1051 | } | |
1052 | ||
1053 | return false; | |
1054 | } | |
1055 | ||
9ee27d73 | 1056 | static void vfio_pci_size_rom(VFIOPCIDevice *vdev) |
6f864e6e | 1057 | { |
b1c50c5f | 1058 | uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); |
6f864e6e | 1059 | off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; |
4b943029 | 1060 | DeviceState *dev = DEVICE(vdev); |
6f864e6e | 1061 | char name[32]; |
5546a621 | 1062 | int fd = vdev->vbasedev.fd; |
6f864e6e AW |
1063 | |
1064 | if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { | |
4b943029 BD |
1065 | /* Since pci handles romfile, just print a message and return */ |
1066 | if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { | |
1067 | error_printf("Warning : Device at %04x:%02x:%02x.%x " | |
1068 | "is known to cause system instability issues during " | |
1069 | "option rom execution. " | |
1070 | "Proceeding anyway since user specified romfile\n", | |
1071 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
1072 | vdev->host.function); | |
1073 | } | |
6f864e6e AW |
1074 | return; |
1075 | } | |
1076 | ||
1077 | /* | |
1078 | * Use the same size ROM BAR as the physical device. The contents | |
1079 | * will get filled in later when the guest tries to read it. | |
1080 | */ | |
5546a621 EA |
1081 | if (pread(fd, &orig, 4, offset) != 4 || |
1082 | pwrite(fd, &size, 4, offset) != 4 || | |
1083 | pread(fd, &size, 4, offset) != 4 || | |
1084 | pwrite(fd, &orig, 4, offset) != 4) { | |
6f864e6e AW |
1085 | error_report("%s(%04x:%02x:%02x.%x) failed: %m", |
1086 | __func__, vdev->host.domain, vdev->host.bus, | |
1087 | vdev->host.slot, vdev->host.function); | |
1088 | return; | |
1089 | } | |
1090 | ||
b1c50c5f | 1091 | size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; |
6f864e6e AW |
1092 | |
1093 | if (!size) { | |
1094 | return; | |
1095 | } | |
1096 | ||
4b943029 BD |
1097 | if (vfio_blacklist_opt_rom(vdev)) { |
1098 | if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { | |
1099 | error_printf("Warning : Device at %04x:%02x:%02x.%x " | |
1100 | "is known to cause system instability issues during " | |
1101 | "option rom execution. " | |
1102 | "Proceeding anyway since user specified non zero value for " | |
1103 | "rombar\n", | |
1104 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
1105 | vdev->host.function); | |
1106 | } else { | |
1107 | error_printf("Warning : Rom loading for device at " | |
1108 | "%04x:%02x:%02x.%x has been disabled due to " | |
1109 | "system instability issues. " | |
1110 | "Specify rombar=1 or romfile to force\n", | |
1111 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
1112 | vdev->host.function); | |
1113 | return; | |
1114 | } | |
1115 | } | |
1116 | ||
df92ee44 | 1117 | trace_vfio_pci_size_rom(vdev->vbasedev.name, size); |
6f864e6e AW |
1118 | |
1119 | snprintf(name, sizeof(name), "vfio[%04x:%02x:%02x.%x].rom", | |
1120 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
1121 | vdev->host.function); | |
1122 | ||
1123 | memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), | |
1124 | &vfio_rom_ops, vdev, name, size); | |
1125 | ||
1126 | pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, | |
1127 | PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); | |
1128 | ||
1129 | vdev->pdev.has_rom = true; | |
e638073c | 1130 | vdev->rom_read_failed = false; |
6f864e6e AW |
1131 | } |
1132 | ||
f15689c7 AW |
1133 | static void vfio_vga_write(void *opaque, hwaddr addr, |
1134 | uint64_t data, unsigned size) | |
1135 | { | |
1136 | VFIOVGARegion *region = opaque; | |
1137 | VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); | |
1138 | union { | |
1139 | uint8_t byte; | |
1140 | uint16_t word; | |
1141 | uint32_t dword; | |
1142 | uint64_t qword; | |
1143 | } buf; | |
1144 | off_t offset = vga->fd_offset + region->offset + addr; | |
1145 | ||
1146 | switch (size) { | |
1147 | case 1: | |
1148 | buf.byte = data; | |
1149 | break; | |
1150 | case 2: | |
1151 | buf.word = cpu_to_le16(data); | |
1152 | break; | |
1153 | case 4: | |
1154 | buf.dword = cpu_to_le32(data); | |
1155 | break; | |
1156 | default: | |
4e505ddd | 1157 | hw_error("vfio: unsupported write size, %d bytes", size); |
f15689c7 AW |
1158 | break; |
1159 | } | |
1160 | ||
1161 | if (pwrite(vga->fd, &buf, size, offset) != size) { | |
1162 | error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", | |
1163 | __func__, region->offset + addr, data, size); | |
1164 | } | |
1165 | ||
385f57cf | 1166 | trace_vfio_vga_write(region->offset + addr, data, size); |
f15689c7 AW |
1167 | } |
1168 | ||
1169 | static uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) | |
1170 | { | |
1171 | VFIOVGARegion *region = opaque; | |
1172 | VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); | |
1173 | union { | |
1174 | uint8_t byte; | |
1175 | uint16_t word; | |
1176 | uint32_t dword; | |
1177 | uint64_t qword; | |
1178 | } buf; | |
1179 | uint64_t data = 0; | |
1180 | off_t offset = vga->fd_offset + region->offset + addr; | |
1181 | ||
1182 | if (pread(vga->fd, &buf, size, offset) != size) { | |
1183 | error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", | |
1184 | __func__, region->offset + addr, size); | |
1185 | return (uint64_t)-1; | |
1186 | } | |
1187 | ||
1188 | switch (size) { | |
1189 | case 1: | |
1190 | data = buf.byte; | |
1191 | break; | |
1192 | case 2: | |
1193 | data = le16_to_cpu(buf.word); | |
1194 | break; | |
1195 | case 4: | |
1196 | data = le32_to_cpu(buf.dword); | |
1197 | break; | |
1198 | default: | |
4e505ddd | 1199 | hw_error("vfio: unsupported read size, %d bytes", size); |
f15689c7 AW |
1200 | break; |
1201 | } | |
1202 | ||
385f57cf | 1203 | trace_vfio_vga_read(region->offset + addr, size, data); |
f15689c7 AW |
1204 | |
1205 | return data; | |
1206 | } | |
1207 | ||
1208 | static const MemoryRegionOps vfio_vga_ops = { | |
1209 | .read = vfio_vga_read, | |
1210 | .write = vfio_vga_write, | |
1211 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1212 | }; | |
1213 | ||
7076eabc AW |
1214 | /* |
1215 | * Device specific quirks | |
1216 | */ | |
1217 | ||
39360f0b AW |
1218 | /* Is range1 fully contained within range2? */ |
1219 | static bool vfio_range_contained(uint64_t first1, uint64_t len1, | |
1220 | uint64_t first2, uint64_t len2) { | |
1221 | return (first1 >= first2 && first1 + len1 <= first2 + len2); | |
1222 | } | |
7076eabc | 1223 | |
39360f0b AW |
1224 | static bool vfio_flags_enabled(uint8_t flags, uint8_t mask) |
1225 | { | |
1226 | return (mask && (flags & mask) == mask); | |
1227 | } | |
1228 | ||
1229 | static uint64_t vfio_generic_window_quirk_read(void *opaque, | |
1230 | hwaddr addr, unsigned size) | |
7076eabc AW |
1231 | { |
1232 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1233 | VFIOPCIDevice *vdev = quirk->vdev; |
39360f0b | 1234 | uint64_t data; |
7076eabc | 1235 | |
39360f0b AW |
1236 | if (vfio_flags_enabled(quirk->data.flags, quirk->data.read_flags) && |
1237 | ranges_overlap(addr, size, | |
1238 | quirk->data.data_offset, quirk->data.data_size)) { | |
1239 | hwaddr offset = addr - quirk->data.data_offset; | |
1240 | ||
1241 | if (!vfio_range_contained(addr, size, quirk->data.data_offset, | |
1242 | quirk->data.data_size)) { | |
4e505ddd | 1243 | hw_error("%s: window data read not fully contained: %s", |
39360f0b AW |
1244 | __func__, memory_region_name(&quirk->mem)); |
1245 | } | |
1246 | ||
1247 | data = vfio_pci_read_config(&vdev->pdev, | |
1248 | quirk->data.address_val + offset, size); | |
1249 | ||
385f57cf | 1250 | trace_vfio_generic_window_quirk_read(memory_region_name(&quirk->mem), |
df92ee44 | 1251 | vdev->vbasedev.name, |
385f57cf EA |
1252 | quirk->data.bar, |
1253 | addr, size, data); | |
39360f0b | 1254 | } else { |
a664477d EA |
1255 | data = vfio_region_read(&vdev->bars[quirk->data.bar].region, |
1256 | addr + quirk->data.base_offset, size); | |
7076eabc AW |
1257 | } |
1258 | ||
1259 | return data; | |
1260 | } | |
1261 | ||
39360f0b AW |
1262 | static void vfio_generic_window_quirk_write(void *opaque, hwaddr addr, |
1263 | uint64_t data, unsigned size) | |
7076eabc | 1264 | { |
39360f0b | 1265 | VFIOQuirk *quirk = opaque; |
9ee27d73 | 1266 | VFIOPCIDevice *vdev = quirk->vdev; |
7076eabc | 1267 | |
39360f0b AW |
1268 | if (ranges_overlap(addr, size, |
1269 | quirk->data.address_offset, quirk->data.address_size)) { | |
7076eabc | 1270 | |
39360f0b | 1271 | if (addr != quirk->data.address_offset) { |
4e505ddd | 1272 | hw_error("%s: offset write into address window: %s", |
39360f0b AW |
1273 | __func__, memory_region_name(&quirk->mem)); |
1274 | } | |
1275 | ||
1276 | if ((data & ~quirk->data.address_mask) == quirk->data.address_match) { | |
1277 | quirk->data.flags |= quirk->data.write_flags | | |
1278 | quirk->data.read_flags; | |
1279 | quirk->data.address_val = data & quirk->data.address_mask; | |
1280 | } else { | |
1281 | quirk->data.flags &= ~(quirk->data.write_flags | | |
1282 | quirk->data.read_flags); | |
1283 | } | |
7076eabc AW |
1284 | } |
1285 | ||
39360f0b AW |
1286 | if (vfio_flags_enabled(quirk->data.flags, quirk->data.write_flags) && |
1287 | ranges_overlap(addr, size, | |
1288 | quirk->data.data_offset, quirk->data.data_size)) { | |
1289 | hwaddr offset = addr - quirk->data.data_offset; | |
7076eabc | 1290 | |
39360f0b AW |
1291 | if (!vfio_range_contained(addr, size, quirk->data.data_offset, |
1292 | quirk->data.data_size)) { | |
4e505ddd | 1293 | hw_error("%s: window data write not fully contained: %s", |
39360f0b AW |
1294 | __func__, memory_region_name(&quirk->mem)); |
1295 | } | |
7076eabc | 1296 | |
39360f0b AW |
1297 | vfio_pci_write_config(&vdev->pdev, |
1298 | quirk->data.address_val + offset, data, size); | |
385f57cf | 1299 | trace_vfio_generic_window_quirk_write(memory_region_name(&quirk->mem), |
df92ee44 EA |
1300 | vdev->vbasedev.name, |
1301 | quirk->data.bar, | |
1302 | addr, data, size); | |
39360f0b AW |
1303 | return; |
1304 | } | |
7076eabc | 1305 | |
a664477d | 1306 | vfio_region_write(&vdev->bars[quirk->data.bar].region, |
39360f0b | 1307 | addr + quirk->data.base_offset, data, size); |
7076eabc AW |
1308 | } |
1309 | ||
39360f0b AW |
1310 | static const MemoryRegionOps vfio_generic_window_quirk = { |
1311 | .read = vfio_generic_window_quirk_read, | |
1312 | .write = vfio_generic_window_quirk_write, | |
1313 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1314 | }; | |
1315 | ||
1316 | static uint64_t vfio_generic_quirk_read(void *opaque, | |
1317 | hwaddr addr, unsigned size) | |
7076eabc AW |
1318 | { |
1319 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1320 | VFIOPCIDevice *vdev = quirk->vdev; |
39360f0b AW |
1321 | hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK; |
1322 | hwaddr offset = quirk->data.address_match & ~TARGET_PAGE_MASK; | |
1323 | uint64_t data; | |
7076eabc | 1324 | |
39360f0b AW |
1325 | if (vfio_flags_enabled(quirk->data.flags, quirk->data.read_flags) && |
1326 | ranges_overlap(addr, size, offset, quirk->data.address_mask + 1)) { | |
1327 | if (!vfio_range_contained(addr, size, offset, | |
1328 | quirk->data.address_mask + 1)) { | |
4e505ddd | 1329 | hw_error("%s: read not fully contained: %s", |
39360f0b AW |
1330 | __func__, memory_region_name(&quirk->mem)); |
1331 | } | |
7076eabc | 1332 | |
39360f0b AW |
1333 | data = vfio_pci_read_config(&vdev->pdev, addr - offset, size); |
1334 | ||
385f57cf | 1335 | trace_vfio_generic_quirk_read(memory_region_name(&quirk->mem), |
df92ee44 | 1336 | vdev->vbasedev.name, quirk->data.bar, |
385f57cf | 1337 | addr + base, size, data); |
39360f0b | 1338 | } else { |
a664477d EA |
1339 | data = vfio_region_read(&vdev->bars[quirk->data.bar].region, |
1340 | addr + base, size); | |
39360f0b | 1341 | } |
7076eabc AW |
1342 | |
1343 | return data; | |
1344 | } | |
1345 | ||
39360f0b AW |
1346 | static void vfio_generic_quirk_write(void *opaque, hwaddr addr, |
1347 | uint64_t data, unsigned size) | |
7076eabc AW |
1348 | { |
1349 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1350 | VFIOPCIDevice *vdev = quirk->vdev; |
39360f0b AW |
1351 | hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK; |
1352 | hwaddr offset = quirk->data.address_match & ~TARGET_PAGE_MASK; | |
1353 | ||
1354 | if (vfio_flags_enabled(quirk->data.flags, quirk->data.write_flags) && | |
1355 | ranges_overlap(addr, size, offset, quirk->data.address_mask + 1)) { | |
1356 | if (!vfio_range_contained(addr, size, offset, | |
1357 | quirk->data.address_mask + 1)) { | |
4e505ddd | 1358 | hw_error("%s: write not fully contained: %s", |
39360f0b AW |
1359 | __func__, memory_region_name(&quirk->mem)); |
1360 | } | |
7076eabc | 1361 | |
39360f0b | 1362 | vfio_pci_write_config(&vdev->pdev, addr - offset, data, size); |
7076eabc | 1363 | |
385f57cf | 1364 | trace_vfio_generic_quirk_write(memory_region_name(&quirk->mem), |
df92ee44 | 1365 | vdev->vbasedev.name, quirk->data.bar, |
385f57cf | 1366 | addr + base, data, size); |
39360f0b | 1367 | } else { |
a664477d EA |
1368 | vfio_region_write(&vdev->bars[quirk->data.bar].region, |
1369 | addr + base, data, size); | |
39360f0b | 1370 | } |
7076eabc AW |
1371 | } |
1372 | ||
39360f0b AW |
1373 | static const MemoryRegionOps vfio_generic_quirk = { |
1374 | .read = vfio_generic_quirk_read, | |
1375 | .write = vfio_generic_quirk_write, | |
7076eabc AW |
1376 | .endianness = DEVICE_LITTLE_ENDIAN, |
1377 | }; | |
1378 | ||
39360f0b AW |
1379 | #define PCI_VENDOR_ID_ATI 0x1002 |
1380 | ||
1381 | /* | |
1382 | * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR | |
1383 | * through VGA register 0x3c3. On newer cards, the I/O port BAR is always | |
1384 | * BAR4 (older cards like the X550 used BAR1, but we don't care to support | |
1385 | * those). Note that on bare metal, a read of 0x3c3 doesn't always return the | |
1386 | * I/O port BAR address. Originally this was coded to return the virtual BAR | |
1387 | * address only if the physical register read returns the actual BAR address, | |
1388 | * but users have reported greater success if we return the virtual address | |
1389 | * unconditionally. | |
1390 | */ | |
1391 | static uint64_t vfio_ati_3c3_quirk_read(void *opaque, | |
1392 | hwaddr addr, unsigned size) | |
1393 | { | |
1394 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1395 | VFIOPCIDevice *vdev = quirk->vdev; |
39360f0b AW |
1396 | uint64_t data = vfio_pci_read_config(&vdev->pdev, |
1397 | PCI_BASE_ADDRESS_0 + (4 * 4) + 1, | |
1398 | size); | |
385f57cf | 1399 | trace_vfio_ati_3c3_quirk_read(data); |
39360f0b AW |
1400 | |
1401 | return data; | |
1402 | } | |
1403 | ||
1404 | static const MemoryRegionOps vfio_ati_3c3_quirk = { | |
1405 | .read = vfio_ati_3c3_quirk_read, | |
1406 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1407 | }; | |
1408 | ||
9ee27d73 | 1409 | static void vfio_vga_probe_ati_3c3_quirk(VFIOPCIDevice *vdev) |
7076eabc AW |
1410 | { |
1411 | PCIDevice *pdev = &vdev->pdev; | |
7076eabc AW |
1412 | VFIOQuirk *quirk; |
1413 | ||
39360f0b | 1414 | if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) { |
7076eabc AW |
1415 | return; |
1416 | } | |
1417 | ||
39360f0b AW |
1418 | /* |
1419 | * As long as the BAR is >= 256 bytes it will be aligned such that the | |
1420 | * lower byte is always zero. Filter out anything else, if it exists. | |
1421 | */ | |
a664477d | 1422 | if (!vdev->bars[4].ioport || vdev->bars[4].region.size < 256) { |
7076eabc AW |
1423 | return; |
1424 | } | |
1425 | ||
1426 | quirk = g_malloc0(sizeof(*quirk)); | |
1427 | quirk->vdev = vdev; | |
1428 | ||
39360f0b AW |
1429 | memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_ati_3c3_quirk, quirk, |
1430 | "vfio-ati-3c3-quirk", 1); | |
1431 | memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem, | |
1432 | 3 /* offset 3 bytes from 0x3c0 */, &quirk->mem); | |
7076eabc | 1433 | |
39360f0b AW |
1434 | QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks, |
1435 | quirk, next); | |
7076eabc | 1436 | |
df92ee44 | 1437 | trace_vfio_vga_probe_ati_3c3_quirk(vdev->vbasedev.name); |
7076eabc AW |
1438 | } |
1439 | ||
1440 | /* | |
39360f0b AW |
1441 | * Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI |
1442 | * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access | |
1443 | * the MMIO space directly, but a window to this space is provided through | |
1444 | * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the | |
1445 | * data register. When the address is programmed to a range of 0x4000-0x4fff | |
1446 | * PCI configuration space is available. Experimentation seems to indicate | |
1447 | * that only read-only access is provided, but we drop writes when the window | |
1448 | * is enabled to config space nonetheless. | |
7076eabc | 1449 | */ |
9ee27d73 | 1450 | static void vfio_probe_ati_bar4_window_quirk(VFIOPCIDevice *vdev, int nr) |
7076eabc | 1451 | { |
7076eabc | 1452 | PCIDevice *pdev = &vdev->pdev; |
39360f0b | 1453 | VFIOQuirk *quirk; |
7076eabc | 1454 | |
39360f0b AW |
1455 | if (!vdev->has_vga || nr != 4 || |
1456 | pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) { | |
1457 | return; | |
7076eabc AW |
1458 | } |
1459 | ||
39360f0b AW |
1460 | quirk = g_malloc0(sizeof(*quirk)); |
1461 | quirk->vdev = vdev; | |
1462 | quirk->data.address_size = 4; | |
1463 | quirk->data.data_offset = 4; | |
1464 | quirk->data.data_size = 4; | |
1465 | quirk->data.address_match = 0x4000; | |
1466 | quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1; | |
1467 | quirk->data.bar = nr; | |
1468 | quirk->data.read_flags = quirk->data.write_flags = 1; | |
1469 | ||
1470 | memory_region_init_io(&quirk->mem, OBJECT(vdev), | |
1471 | &vfio_generic_window_quirk, quirk, | |
1472 | "vfio-ati-bar4-window-quirk", 8); | |
a664477d | 1473 | memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, |
39360f0b | 1474 | quirk->data.base_offset, &quirk->mem, 1); |
7076eabc | 1475 | |
39360f0b | 1476 | QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); |
7076eabc | 1477 | |
df92ee44 | 1478 | trace_vfio_probe_ati_bar4_window_quirk(vdev->vbasedev.name); |
7076eabc AW |
1479 | } |
1480 | ||
4cb47d28 AW |
1481 | #define PCI_VENDOR_ID_REALTEK 0x10ec |
1482 | ||
1483 | /* | |
1484 | * RTL8168 devices have a backdoor that can access the MSI-X table. At BAR2 | |
1485 | * offset 0x70 there is a dword data register, offset 0x74 is a dword address | |
1486 | * register. According to the Linux r8169 driver, the MSI-X table is addressed | |
1487 | * when the "type" portion of the address register is set to 0x1. This appears | |
1488 | * to be bits 16:30. Bit 31 is both a write indicator and some sort of | |
1489 | * "address latched" indicator. Bits 12:15 are a mask field, which we can | |
1490 | * ignore because the MSI-X table should always be accessed as a dword (full | |
1491 | * mask). Bits 0:11 is offset within the type. | |
1492 | * | |
1493 | * Example trace: | |
1494 | * | |
1495 | * Read from MSI-X table offset 0 | |
1496 | * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x1f000, 4) // store read addr | |
1497 | * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x8001f000 // latch | |
1498 | * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x70, 4) = 0xfee00398 // read data | |
1499 | * | |
1500 | * Write 0xfee00000 to MSI-X table offset 0 | |
1501 | * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x70, 0xfee00000, 4) // write data | |
1502 | * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x8001f000, 4) // do write | |
1503 | * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x1f000 // complete | |
1504 | */ | |
1505 | ||
1506 | static uint64_t vfio_rtl8168_window_quirk_read(void *opaque, | |
1507 | hwaddr addr, unsigned size) | |
1508 | { | |
1509 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1510 | VFIOPCIDevice *vdev = quirk->vdev; |
4cb47d28 AW |
1511 | |
1512 | switch (addr) { | |
1513 | case 4: /* address */ | |
1514 | if (quirk->data.flags) { | |
385f57cf EA |
1515 | trace_vfio_rtl8168_window_quirk_read_fake( |
1516 | memory_region_name(&quirk->mem), | |
df92ee44 | 1517 | vdev->vbasedev.name); |
4cb47d28 AW |
1518 | |
1519 | return quirk->data.address_match ^ 0x10000000U; | |
1520 | } | |
1521 | break; | |
1522 | case 0: /* data */ | |
1523 | if (quirk->data.flags) { | |
1524 | uint64_t val; | |
1525 | ||
385f57cf EA |
1526 | trace_vfio_rtl8168_window_quirk_read_table( |
1527 | memory_region_name(&quirk->mem), | |
df92ee44 | 1528 | vdev->vbasedev.name); |
4cb47d28 AW |
1529 | |
1530 | if (!(vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) { | |
1531 | return 0; | |
1532 | } | |
1533 | ||
3b643495 PM |
1534 | memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, |
1535 | (hwaddr)(quirk->data.address_match | |
1536 | & 0xfff), | |
1537 | &val, | |
1538 | size, | |
1539 | MEMTXATTRS_UNSPECIFIED); | |
4cb47d28 AW |
1540 | return val; |
1541 | } | |
1542 | } | |
1543 | ||
df92ee44 EA |
1544 | trace_vfio_rtl8168_window_quirk_read_direct(memory_region_name(&quirk->mem), |
1545 | vdev->vbasedev.name); | |
4cb47d28 | 1546 | |
a664477d EA |
1547 | return vfio_region_read(&vdev->bars[quirk->data.bar].region, |
1548 | addr + 0x70, size); | |
4cb47d28 AW |
1549 | } |
1550 | ||
1551 | static void vfio_rtl8168_window_quirk_write(void *opaque, hwaddr addr, | |
1552 | uint64_t data, unsigned size) | |
1553 | { | |
1554 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1555 | VFIOPCIDevice *vdev = quirk->vdev; |
4cb47d28 AW |
1556 | |
1557 | switch (addr) { | |
1558 | case 4: /* address */ | |
1559 | if ((data & 0x7fff0000) == 0x10000) { | |
1560 | if (data & 0x10000000U && | |
1561 | vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX) { | |
1562 | ||
385f57cf EA |
1563 | trace_vfio_rtl8168_window_quirk_write_table( |
1564 | memory_region_name(&quirk->mem), | |
df92ee44 | 1565 | vdev->vbasedev.name); |
4cb47d28 | 1566 | |
3b643495 PM |
1567 | memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, |
1568 | (hwaddr)(quirk->data.address_match | |
1569 | & 0xfff), | |
1570 | data, | |
1571 | size, | |
1572 | MEMTXATTRS_UNSPECIFIED); | |
4cb47d28 AW |
1573 | } |
1574 | ||
1575 | quirk->data.flags = 1; | |
1576 | quirk->data.address_match = data; | |
1577 | ||
1578 | return; | |
1579 | } | |
1580 | quirk->data.flags = 0; | |
1581 | break; | |
1582 | case 0: /* data */ | |
1583 | quirk->data.address_mask = data; | |
1584 | break; | |
1585 | } | |
1586 | ||
385f57cf EA |
1587 | trace_vfio_rtl8168_window_quirk_write_direct( |
1588 | memory_region_name(&quirk->mem), | |
df92ee44 | 1589 | vdev->vbasedev.name); |
4cb47d28 | 1590 | |
a664477d EA |
1591 | vfio_region_write(&vdev->bars[quirk->data.bar].region, |
1592 | addr + 0x70, data, size); | |
4cb47d28 AW |
1593 | } |
1594 | ||
1595 | static const MemoryRegionOps vfio_rtl8168_window_quirk = { | |
1596 | .read = vfio_rtl8168_window_quirk_read, | |
1597 | .write = vfio_rtl8168_window_quirk_write, | |
1598 | .valid = { | |
1599 | .min_access_size = 4, | |
1600 | .max_access_size = 4, | |
1601 | .unaligned = false, | |
1602 | }, | |
1603 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1604 | }; | |
1605 | ||
9ee27d73 | 1606 | static void vfio_probe_rtl8168_bar2_window_quirk(VFIOPCIDevice *vdev, int nr) |
4cb47d28 AW |
1607 | { |
1608 | PCIDevice *pdev = &vdev->pdev; | |
1609 | VFIOQuirk *quirk; | |
1610 | ||
1611 | if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_REALTEK || | |
1612 | pci_get_word(pdev->config + PCI_DEVICE_ID) != 0x8168 || nr != 2) { | |
1613 | return; | |
1614 | } | |
1615 | ||
1616 | quirk = g_malloc0(sizeof(*quirk)); | |
1617 | quirk->vdev = vdev; | |
1618 | quirk->data.bar = nr; | |
1619 | ||
1620 | memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_rtl8168_window_quirk, | |
1621 | quirk, "vfio-rtl8168-window-quirk", 8); | |
a664477d | 1622 | memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, |
4cb47d28 AW |
1623 | 0x70, &quirk->mem, 1); |
1624 | ||
1625 | QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); | |
1626 | ||
df92ee44 | 1627 | trace_vfio_probe_rtl8168_bar2_window_quirk(vdev->vbasedev.name); |
4cb47d28 | 1628 | } |
39360f0b AW |
1629 | /* |
1630 | * Trap the BAR2 MMIO window to config space as well. | |
1631 | */ | |
9ee27d73 | 1632 | static void vfio_probe_ati_bar2_4000_quirk(VFIOPCIDevice *vdev, int nr) |
7076eabc AW |
1633 | { |
1634 | PCIDevice *pdev = &vdev->pdev; | |
7076eabc AW |
1635 | VFIOQuirk *quirk; |
1636 | ||
39360f0b AW |
1637 | /* Only enable on newer devices where BAR2 is 64bit */ |
1638 | if (!vdev->has_vga || nr != 2 || !vdev->bars[2].mem64 || | |
7076eabc AW |
1639 | pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_ATI) { |
1640 | return; | |
1641 | } | |
1642 | ||
7076eabc AW |
1643 | quirk = g_malloc0(sizeof(*quirk)); |
1644 | quirk->vdev = vdev; | |
39360f0b AW |
1645 | quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1; |
1646 | quirk->data.address_match = 0x4000; | |
1647 | quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1; | |
1648 | quirk->data.bar = nr; | |
1649 | ||
1650 | memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk, quirk, | |
1651 | "vfio-ati-bar2-4000-quirk", | |
1652 | TARGET_PAGE_ALIGN(quirk->data.address_mask + 1)); | |
a664477d | 1653 | memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, |
39360f0b AW |
1654 | quirk->data.address_match & TARGET_PAGE_MASK, |
1655 | &quirk->mem, 1); | |
7076eabc AW |
1656 | |
1657 | QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); | |
1658 | ||
df92ee44 | 1659 | trace_vfio_probe_ati_bar2_4000_quirk(vdev->vbasedev.name); |
7076eabc AW |
1660 | } |
1661 | ||
39360f0b AW |
1662 | /* |
1663 | * Older ATI/AMD cards like the X550 have a similar window to that above. | |
1664 | * I/O port BAR1 provides a window to a mirror of PCI config space located | |
1665 | * in BAR2 at offset 0xf00. We don't care to support such older cards, but | |
1666 | * note it for future reference. | |
1667 | */ | |
1668 | ||
7076eabc AW |
1669 | #define PCI_VENDOR_ID_NVIDIA 0x10de |
1670 | ||
1671 | /* | |
1672 | * Nvidia has several different methods to get to config space, the | |
1673 | * nouveu project has several of these documented here: | |
1674 | * https://github.com/pathscale/envytools/tree/master/hwdocs | |
1675 | * | |
1676 | * The first quirk is actually not documented in envytools and is found | |
1677 | * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an | |
1678 | * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access | |
1679 | * the mirror of PCI config space found at BAR0 offset 0x1800. The access | |
1680 | * sequence first writes 0x338 to I/O port 0x3d4. The target offset is | |
1681 | * then written to 0x3d0. Finally 0x538 is written for a read and 0x738 | |
1682 | * is written for a write to 0x3d4. The BAR0 offset is then accessible | |
1683 | * through 0x3d0. This quirk doesn't seem to be necessary on newer cards | |
1684 | * that use the I/O port BAR5 window but it doesn't hurt to leave it. | |
1685 | */ | |
1686 | enum { | |
39360f0b | 1687 | NV_3D0_NONE = 0, |
7076eabc AW |
1688 | NV_3D0_SELECT, |
1689 | NV_3D0_WINDOW, | |
1690 | NV_3D0_READ, | |
1691 | NV_3D0_WRITE, | |
1692 | }; | |
1693 | ||
1694 | static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque, | |
1695 | hwaddr addr, unsigned size) | |
1696 | { | |
1697 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1698 | VFIOPCIDevice *vdev = quirk->vdev; |
7076eabc AW |
1699 | PCIDevice *pdev = &vdev->pdev; |
1700 | uint64_t data = vfio_vga_read(&vdev->vga.region[QEMU_PCI_VGA_IO_HI], | |
39360f0b | 1701 | addr + quirk->data.base_offset, size); |
7076eabc | 1702 | |
39360f0b AW |
1703 | if (quirk->data.flags == NV_3D0_READ && addr == quirk->data.data_offset) { |
1704 | data = vfio_pci_read_config(pdev, quirk->data.address_val, size); | |
385f57cf | 1705 | trace_vfio_nvidia_3d0_quirk_read(size, data); |
7076eabc AW |
1706 | } |
1707 | ||
39360f0b | 1708 | quirk->data.flags = NV_3D0_NONE; |
7076eabc AW |
1709 | |
1710 | return data; | |
1711 | } | |
1712 | ||
1713 | static void vfio_nvidia_3d0_quirk_write(void *opaque, hwaddr addr, | |
1714 | uint64_t data, unsigned size) | |
1715 | { | |
1716 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1717 | VFIOPCIDevice *vdev = quirk->vdev; |
7076eabc AW |
1718 | PCIDevice *pdev = &vdev->pdev; |
1719 | ||
39360f0b | 1720 | switch (quirk->data.flags) { |
7076eabc | 1721 | case NV_3D0_NONE: |
39360f0b AW |
1722 | if (addr == quirk->data.address_offset && data == 0x338) { |
1723 | quirk->data.flags = NV_3D0_SELECT; | |
7076eabc AW |
1724 | } |
1725 | break; | |
1726 | case NV_3D0_SELECT: | |
39360f0b AW |
1727 | quirk->data.flags = NV_3D0_NONE; |
1728 | if (addr == quirk->data.data_offset && | |
1729 | (data & ~quirk->data.address_mask) == quirk->data.address_match) { | |
1730 | quirk->data.flags = NV_3D0_WINDOW; | |
1731 | quirk->data.address_val = data & quirk->data.address_mask; | |
7076eabc AW |
1732 | } |
1733 | break; | |
1734 | case NV_3D0_WINDOW: | |
39360f0b AW |
1735 | quirk->data.flags = NV_3D0_NONE; |
1736 | if (addr == quirk->data.address_offset) { | |
7076eabc | 1737 | if (data == 0x538) { |
39360f0b | 1738 | quirk->data.flags = NV_3D0_READ; |
7076eabc | 1739 | } else if (data == 0x738) { |
39360f0b | 1740 | quirk->data.flags = NV_3D0_WRITE; |
7076eabc AW |
1741 | } |
1742 | } | |
1743 | break; | |
1744 | case NV_3D0_WRITE: | |
39360f0b AW |
1745 | quirk->data.flags = NV_3D0_NONE; |
1746 | if (addr == quirk->data.data_offset) { | |
1747 | vfio_pci_write_config(pdev, quirk->data.address_val, data, size); | |
385f57cf | 1748 | trace_vfio_nvidia_3d0_quirk_write(data, size); |
7076eabc AW |
1749 | return; |
1750 | } | |
1751 | break; | |
7076eabc AW |
1752 | } |
1753 | ||
1754 | vfio_vga_write(&vdev->vga.region[QEMU_PCI_VGA_IO_HI], | |
39360f0b | 1755 | addr + quirk->data.base_offset, data, size); |
7076eabc AW |
1756 | } |
1757 | ||
1758 | static const MemoryRegionOps vfio_nvidia_3d0_quirk = { | |
1759 | .read = vfio_nvidia_3d0_quirk_read, | |
1760 | .write = vfio_nvidia_3d0_quirk_write, | |
1761 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1762 | }; | |
1763 | ||
9ee27d73 | 1764 | static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice *vdev) |
7076eabc AW |
1765 | { |
1766 | PCIDevice *pdev = &vdev->pdev; | |
1767 | VFIOQuirk *quirk; | |
1768 | ||
1769 | if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA || | |
a664477d | 1770 | !vdev->bars[1].region.size) { |
7076eabc AW |
1771 | return; |
1772 | } | |
1773 | ||
1774 | quirk = g_malloc0(sizeof(*quirk)); | |
1775 | quirk->vdev = vdev; | |
39360f0b AW |
1776 | quirk->data.base_offset = 0x10; |
1777 | quirk->data.address_offset = 4; | |
1778 | quirk->data.address_size = 2; | |
1779 | quirk->data.address_match = 0x1800; | |
1780 | quirk->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1; | |
1781 | quirk->data.data_offset = 0; | |
1782 | quirk->data.data_size = 4; | |
1783 | ||
1784 | memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_3d0_quirk, | |
1785 | quirk, "vfio-nvidia-3d0-quirk", 6); | |
7076eabc | 1786 | memory_region_add_subregion(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem, |
39360f0b | 1787 | quirk->data.base_offset, &quirk->mem); |
7076eabc AW |
1788 | |
1789 | QLIST_INSERT_HEAD(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks, | |
1790 | quirk, next); | |
1791 | ||
df92ee44 | 1792 | trace_vfio_vga_probe_nvidia_3d0_quirk(vdev->vbasedev.name); |
7076eabc AW |
1793 | } |
1794 | ||
1795 | /* | |
1796 | * The second quirk is documented in envytools. The I/O port BAR5 is just | |
1797 | * a set of address/data ports to the MMIO BARs. The BAR we care about is | |
1798 | * again BAR0. This backdoor is apparently a bit newer than the one above | |
1799 | * so we need to not only trap 256 bytes @0x1800, but all of PCI config | |
1800 | * space, including extended space is available at the 4k @0x88000. | |
1801 | */ | |
1802 | enum { | |
1803 | NV_BAR5_ADDRESS = 0x1, | |
1804 | NV_BAR5_ENABLE = 0x2, | |
1805 | NV_BAR5_MASTER = 0x4, | |
1806 | NV_BAR5_VALID = 0x7, | |
1807 | }; | |
1808 | ||
7076eabc AW |
1809 | static void vfio_nvidia_bar5_window_quirk_write(void *opaque, hwaddr addr, |
1810 | uint64_t data, unsigned size) | |
1811 | { | |
1812 | VFIOQuirk *quirk = opaque; | |
7076eabc | 1813 | |
7076eabc AW |
1814 | switch (addr) { |
1815 | case 0x0: | |
1816 | if (data & 0x1) { | |
39360f0b | 1817 | quirk->data.flags |= NV_BAR5_MASTER; |
7076eabc | 1818 | } else { |
39360f0b | 1819 | quirk->data.flags &= ~NV_BAR5_MASTER; |
7076eabc AW |
1820 | } |
1821 | break; | |
1822 | case 0x4: | |
1823 | if (data & 0x1) { | |
39360f0b | 1824 | quirk->data.flags |= NV_BAR5_ENABLE; |
7076eabc | 1825 | } else { |
39360f0b | 1826 | quirk->data.flags &= ~NV_BAR5_ENABLE; |
7076eabc AW |
1827 | } |
1828 | break; | |
1829 | case 0x8: | |
39360f0b | 1830 | if (quirk->data.flags & NV_BAR5_MASTER) { |
7076eabc | 1831 | if ((data & ~0xfff) == 0x88000) { |
39360f0b AW |
1832 | quirk->data.flags |= NV_BAR5_ADDRESS; |
1833 | quirk->data.address_val = data & 0xfff; | |
7076eabc | 1834 | } else if ((data & ~0xff) == 0x1800) { |
39360f0b AW |
1835 | quirk->data.flags |= NV_BAR5_ADDRESS; |
1836 | quirk->data.address_val = data & 0xff; | |
7076eabc | 1837 | } else { |
39360f0b | 1838 | quirk->data.flags &= ~NV_BAR5_ADDRESS; |
7076eabc AW |
1839 | } |
1840 | } | |
1841 | break; | |
7076eabc AW |
1842 | } |
1843 | ||
39360f0b | 1844 | vfio_generic_window_quirk_write(opaque, addr, data, size); |
7076eabc AW |
1845 | } |
1846 | ||
1847 | static const MemoryRegionOps vfio_nvidia_bar5_window_quirk = { | |
39360f0b | 1848 | .read = vfio_generic_window_quirk_read, |
7076eabc AW |
1849 | .write = vfio_nvidia_bar5_window_quirk_write, |
1850 | .valid.min_access_size = 4, | |
1851 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1852 | }; | |
1853 | ||
9ee27d73 | 1854 | static void vfio_probe_nvidia_bar5_window_quirk(VFIOPCIDevice *vdev, int nr) |
7076eabc AW |
1855 | { |
1856 | PCIDevice *pdev = &vdev->pdev; | |
1857 | VFIOQuirk *quirk; | |
1858 | ||
1859 | if (!vdev->has_vga || nr != 5 || | |
1860 | pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA) { | |
1861 | return; | |
1862 | } | |
1863 | ||
1864 | quirk = g_malloc0(sizeof(*quirk)); | |
1865 | quirk->vdev = vdev; | |
39360f0b AW |
1866 | quirk->data.read_flags = quirk->data.write_flags = NV_BAR5_VALID; |
1867 | quirk->data.address_offset = 0x8; | |
1868 | quirk->data.address_size = 0; /* actually 4, but avoids generic code */ | |
1869 | quirk->data.data_offset = 0xc; | |
1870 | quirk->data.data_size = 4; | |
1871 | quirk->data.bar = nr; | |
1872 | ||
1873 | memory_region_init_io(&quirk->mem, OBJECT(vdev), | |
1874 | &vfio_nvidia_bar5_window_quirk, quirk, | |
7076eabc | 1875 | "vfio-nvidia-bar5-window-quirk", 16); |
a664477d EA |
1876 | memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, |
1877 | 0, &quirk->mem, 1); | |
7076eabc AW |
1878 | |
1879 | QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); | |
1880 | ||
df92ee44 | 1881 | trace_vfio_probe_nvidia_bar5_window_quirk(vdev->vbasedev.name); |
7076eabc AW |
1882 | } |
1883 | ||
96eeeba0 AW |
1884 | static void vfio_nvidia_88000_quirk_write(void *opaque, hwaddr addr, |
1885 | uint64_t data, unsigned size) | |
1886 | { | |
1887 | VFIOQuirk *quirk = opaque; | |
9ee27d73 | 1888 | VFIOPCIDevice *vdev = quirk->vdev; |
96eeeba0 AW |
1889 | PCIDevice *pdev = &vdev->pdev; |
1890 | hwaddr base = quirk->data.address_match & TARGET_PAGE_MASK; | |
1891 | ||
1892 | vfio_generic_quirk_write(opaque, addr, data, size); | |
1893 | ||
1894 | /* | |
1895 | * Nvidia seems to acknowledge MSI interrupts by writing 0xff to the | |
1896 | * MSI capability ID register. Both the ID and next register are | |
1897 | * read-only, so we allow writes covering either of those to real hw. | |
1898 | * NB - only fixed for the 0x88000 MMIO window. | |
1899 | */ | |
1900 | if ((pdev->cap_present & QEMU_PCI_CAP_MSI) && | |
1901 | vfio_range_contained(addr, size, pdev->msi_cap, PCI_MSI_FLAGS)) { | |
a664477d EA |
1902 | vfio_region_write(&vdev->bars[quirk->data.bar].region, |
1903 | addr + base, data, size); | |
96eeeba0 AW |
1904 | } |
1905 | } | |
1906 | ||
1907 | static const MemoryRegionOps vfio_nvidia_88000_quirk = { | |
1908 | .read = vfio_generic_quirk_read, | |
1909 | .write = vfio_nvidia_88000_quirk_write, | |
1910 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1911 | }; | |
1912 | ||
7076eabc AW |
1913 | /* |
1914 | * Finally, BAR0 itself. We want to redirect any accesses to either | |
1915 | * 0x1800 or 0x88000 through the PCI config space access functions. | |
1916 | * | |
1917 | * NB - quirk at a page granularity or else they don't seem to work when | |
1918 | * BARs are mmap'd | |
1919 | * | |
1920 | * Here's offset 0x88000... | |
1921 | */ | |
9ee27d73 | 1922 | static void vfio_probe_nvidia_bar0_88000_quirk(VFIOPCIDevice *vdev, int nr) |
7076eabc AW |
1923 | { |
1924 | PCIDevice *pdev = &vdev->pdev; | |
1925 | VFIOQuirk *quirk; | |
fe08275d | 1926 | uint16_t vendor, class; |
7076eabc | 1927 | |
fe08275d AW |
1928 | vendor = pci_get_word(pdev->config + PCI_VENDOR_ID); |
1929 | class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); | |
1930 | ||
1931 | if (nr != 0 || vendor != PCI_VENDOR_ID_NVIDIA || | |
1932 | class != PCI_CLASS_DISPLAY_VGA) { | |
7076eabc AW |
1933 | return; |
1934 | } | |
1935 | ||
1936 | quirk = g_malloc0(sizeof(*quirk)); | |
1937 | quirk->vdev = vdev; | |
39360f0b AW |
1938 | quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1; |
1939 | quirk->data.address_match = 0x88000; | |
1940 | quirk->data.address_mask = PCIE_CONFIG_SPACE_SIZE - 1; | |
1941 | quirk->data.bar = nr; | |
1942 | ||
96eeeba0 | 1943 | memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_nvidia_88000_quirk, |
39360f0b AW |
1944 | quirk, "vfio-nvidia-bar0-88000-quirk", |
1945 | TARGET_PAGE_ALIGN(quirk->data.address_mask + 1)); | |
a664477d | 1946 | memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, |
39360f0b AW |
1947 | quirk->data.address_match & TARGET_PAGE_MASK, |
1948 | &quirk->mem, 1); | |
7076eabc AW |
1949 | |
1950 | QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); | |
1951 | ||
df92ee44 | 1952 | trace_vfio_probe_nvidia_bar0_88000_quirk(vdev->vbasedev.name); |
7076eabc AW |
1953 | } |
1954 | ||
1955 | /* | |
1956 | * And here's the same for BAR0 offset 0x1800... | |
1957 | */ | |
9ee27d73 | 1958 | static void vfio_probe_nvidia_bar0_1800_quirk(VFIOPCIDevice *vdev, int nr) |
7076eabc AW |
1959 | { |
1960 | PCIDevice *pdev = &vdev->pdev; | |
1961 | VFIOQuirk *quirk; | |
1962 | ||
1963 | if (!vdev->has_vga || nr != 0 || | |
1964 | pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_NVIDIA) { | |
1965 | return; | |
1966 | } | |
1967 | ||
1968 | /* Log the chipset ID */ | |
385f57cf | 1969 | trace_vfio_probe_nvidia_bar0_1800_quirk_id( |
a664477d EA |
1970 | (unsigned int)(vfio_region_read(&vdev->bars[0].region, 0, 4) >> 20) |
1971 | & 0xff); | |
7076eabc AW |
1972 | |
1973 | quirk = g_malloc0(sizeof(*quirk)); | |
1974 | quirk->vdev = vdev; | |
39360f0b AW |
1975 | quirk->data.flags = quirk->data.read_flags = quirk->data.write_flags = 1; |
1976 | quirk->data.address_match = 0x1800; | |
1977 | quirk->data.address_mask = PCI_CONFIG_SPACE_SIZE - 1; | |
1978 | quirk->data.bar = nr; | |
7076eabc | 1979 | |
39360f0b | 1980 | memory_region_init_io(&quirk->mem, OBJECT(vdev), &vfio_generic_quirk, quirk, |
7076eabc | 1981 | "vfio-nvidia-bar0-1800-quirk", |
39360f0b | 1982 | TARGET_PAGE_ALIGN(quirk->data.address_mask + 1)); |
a664477d | 1983 | memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, |
39360f0b AW |
1984 | quirk->data.address_match & TARGET_PAGE_MASK, |
1985 | &quirk->mem, 1); | |
7076eabc AW |
1986 | |
1987 | QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); | |
1988 | ||
df92ee44 | 1989 | trace_vfio_probe_nvidia_bar0_1800_quirk(vdev->vbasedev.name); |
7076eabc AW |
1990 | } |
1991 | ||
1992 | /* | |
1993 | * TODO - Some Nvidia devices provide config access to their companion HDA | |
1994 | * device and even to their parent bridge via these config space mirrors. | |
1995 | * Add quirks for those regions. | |
1996 | */ | |
1997 | ||
1998 | /* | |
1999 | * Common quirk probe entry points. | |
2000 | */ | |
9ee27d73 | 2001 | static void vfio_vga_quirk_setup(VFIOPCIDevice *vdev) |
7076eabc AW |
2002 | { |
2003 | vfio_vga_probe_ati_3c3_quirk(vdev); | |
2004 | vfio_vga_probe_nvidia_3d0_quirk(vdev); | |
2005 | } | |
2006 | ||
9ee27d73 | 2007 | static void vfio_vga_quirk_teardown(VFIOPCIDevice *vdev) |
ba5e6bfa PB |
2008 | { |
2009 | VFIOQuirk *quirk; | |
2010 | int i; | |
2011 | ||
2012 | for (i = 0; i < ARRAY_SIZE(vdev->vga.region); i++) { | |
2013 | QLIST_FOREACH(quirk, &vdev->vga.region[i].quirks, next) { | |
2014 | memory_region_del_subregion(&vdev->vga.region[i].mem, &quirk->mem); | |
2015 | } | |
2016 | } | |
2017 | } | |
2018 | ||
2019 | static void vfio_vga_quirk_free(VFIOPCIDevice *vdev) | |
7076eabc AW |
2020 | { |
2021 | int i; | |
2022 | ||
2023 | for (i = 0; i < ARRAY_SIZE(vdev->vga.region); i++) { | |
2024 | while (!QLIST_EMPTY(&vdev->vga.region[i].quirks)) { | |
2025 | VFIOQuirk *quirk = QLIST_FIRST(&vdev->vga.region[i].quirks); | |
d8d95814 | 2026 | object_unparent(OBJECT(&quirk->mem)); |
7076eabc AW |
2027 | QLIST_REMOVE(quirk, next); |
2028 | g_free(quirk); | |
2029 | } | |
2030 | } | |
2031 | } | |
2032 | ||
9ee27d73 | 2033 | static void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr) |
7076eabc | 2034 | { |
39360f0b AW |
2035 | vfio_probe_ati_bar4_window_quirk(vdev, nr); |
2036 | vfio_probe_ati_bar2_4000_quirk(vdev, nr); | |
7076eabc AW |
2037 | vfio_probe_nvidia_bar5_window_quirk(vdev, nr); |
2038 | vfio_probe_nvidia_bar0_88000_quirk(vdev, nr); | |
2039 | vfio_probe_nvidia_bar0_1800_quirk(vdev, nr); | |
4cb47d28 | 2040 | vfio_probe_rtl8168_bar2_window_quirk(vdev, nr); |
7076eabc AW |
2041 | } |
2042 | ||
9ee27d73 | 2043 | static void vfio_bar_quirk_teardown(VFIOPCIDevice *vdev, int nr) |
ba5e6bfa PB |
2044 | { |
2045 | VFIOBAR *bar = &vdev->bars[nr]; | |
2046 | VFIOQuirk *quirk; | |
2047 | ||
2048 | QLIST_FOREACH(quirk, &bar->quirks, next) { | |
2049 | memory_region_del_subregion(&bar->region.mem, &quirk->mem); | |
2050 | } | |
2051 | } | |
2052 | ||
2053 | static void vfio_bar_quirk_free(VFIOPCIDevice *vdev, int nr) | |
7076eabc AW |
2054 | { |
2055 | VFIOBAR *bar = &vdev->bars[nr]; | |
2056 | ||
2057 | while (!QLIST_EMPTY(&bar->quirks)) { | |
2058 | VFIOQuirk *quirk = QLIST_FIRST(&bar->quirks); | |
d8d95814 | 2059 | object_unparent(OBJECT(&quirk->mem)); |
7076eabc AW |
2060 | QLIST_REMOVE(quirk, next); |
2061 | g_free(quirk); | |
2062 | } | |
2063 | } | |
2064 | ||
65501a74 AW |
2065 | /* |
2066 | * PCI config space | |
2067 | */ | |
2068 | static uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) | |
2069 | { | |
9ee27d73 | 2070 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
4b5d5e87 | 2071 | uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; |
65501a74 | 2072 | |
4b5d5e87 AW |
2073 | memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); |
2074 | emu_bits = le32_to_cpu(emu_bits); | |
65501a74 | 2075 | |
4b5d5e87 AW |
2076 | if (emu_bits) { |
2077 | emu_val = pci_default_read_config(pdev, addr, len); | |
2078 | } | |
2079 | ||
2080 | if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { | |
2081 | ssize_t ret; | |
2082 | ||
5546a621 EA |
2083 | ret = pread(vdev->vbasedev.fd, &phys_val, len, |
2084 | vdev->config_offset + addr); | |
4b5d5e87 | 2085 | if (ret != len) { |
312fd5f2 | 2086 | error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x) failed: %m", |
65501a74 AW |
2087 | __func__, vdev->host.domain, vdev->host.bus, |
2088 | vdev->host.slot, vdev->host.function, addr, len); | |
2089 | return -errno; | |
2090 | } | |
4b5d5e87 | 2091 | phys_val = le32_to_cpu(phys_val); |
65501a74 AW |
2092 | } |
2093 | ||
4b5d5e87 | 2094 | val = (emu_val & emu_bits) | (phys_val & ~emu_bits); |
65501a74 | 2095 | |
df92ee44 | 2096 | trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); |
65501a74 AW |
2097 | |
2098 | return val; | |
2099 | } | |
2100 | ||
2101 | static void vfio_pci_write_config(PCIDevice *pdev, uint32_t addr, | |
2102 | uint32_t val, int len) | |
2103 | { | |
9ee27d73 | 2104 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 AW |
2105 | uint32_t val_le = cpu_to_le32(val); |
2106 | ||
df92ee44 | 2107 | trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); |
65501a74 AW |
2108 | |
2109 | /* Write everything to VFIO, let it filter out what we can't write */ | |
5546a621 EA |
2110 | if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) |
2111 | != len) { | |
312fd5f2 | 2112 | error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x, 0x%x) failed: %m", |
65501a74 AW |
2113 | __func__, vdev->host.domain, vdev->host.bus, |
2114 | vdev->host.slot, vdev->host.function, addr, val, len); | |
2115 | } | |
2116 | ||
65501a74 AW |
2117 | /* MSI/MSI-X Enabling/Disabling */ |
2118 | if (pdev->cap_present & QEMU_PCI_CAP_MSI && | |
2119 | ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { | |
2120 | int is_enabled, was_enabled = msi_enabled(pdev); | |
2121 | ||
2122 | pci_default_write_config(pdev, addr, val, len); | |
2123 | ||
2124 | is_enabled = msi_enabled(pdev); | |
2125 | ||
c7679d45 AW |
2126 | if (!was_enabled) { |
2127 | if (is_enabled) { | |
2128 | vfio_enable_msi(vdev); | |
2129 | } | |
2130 | } else { | |
2131 | if (!is_enabled) { | |
2132 | vfio_disable_msi(vdev); | |
2133 | } else { | |
2134 | vfio_update_msi(vdev); | |
2135 | } | |
65501a74 | 2136 | } |
4b5d5e87 | 2137 | } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && |
65501a74 AW |
2138 | ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { |
2139 | int is_enabled, was_enabled = msix_enabled(pdev); | |
2140 | ||
2141 | pci_default_write_config(pdev, addr, val, len); | |
2142 | ||
2143 | is_enabled = msix_enabled(pdev); | |
2144 | ||
2145 | if (!was_enabled && is_enabled) { | |
fd704adc | 2146 | vfio_enable_msix(vdev); |
65501a74 | 2147 | } else if (was_enabled && !is_enabled) { |
fd704adc | 2148 | vfio_disable_msix(vdev); |
65501a74 | 2149 | } |
4b5d5e87 AW |
2150 | } else { |
2151 | /* Write everything to QEMU to keep emulated bits correct */ | |
2152 | pci_default_write_config(pdev, addr, val, len); | |
65501a74 AW |
2153 | } |
2154 | } | |
2155 | ||
65501a74 AW |
2156 | /* |
2157 | * Interrupt setup | |
2158 | */ | |
9ee27d73 | 2159 | static void vfio_disable_interrupts(VFIOPCIDevice *vdev) |
65501a74 | 2160 | { |
b3e27c3a AW |
2161 | /* |
2162 | * More complicated than it looks. Disabling MSI/X transitions the | |
2163 | * device to INTx mode (if supported). Therefore we need to first | |
2164 | * disable MSI/X and then cleanup by disabling INTx. | |
2165 | */ | |
2166 | if (vdev->interrupt == VFIO_INT_MSIX) { | |
fd704adc | 2167 | vfio_disable_msix(vdev); |
b3e27c3a AW |
2168 | } else if (vdev->interrupt == VFIO_INT_MSI) { |
2169 | vfio_disable_msi(vdev); | |
2170 | } | |
2171 | ||
2172 | if (vdev->interrupt == VFIO_INT_INTx) { | |
2173 | vfio_disable_intx(vdev); | |
65501a74 AW |
2174 | } |
2175 | } | |
2176 | ||
9ee27d73 | 2177 | static int vfio_setup_msi(VFIOPCIDevice *vdev, int pos) |
65501a74 AW |
2178 | { |
2179 | uint16_t ctrl; | |
2180 | bool msi_64bit, msi_maskbit; | |
2181 | int ret, entries; | |
2182 | ||
5546a621 | 2183 | if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), |
65501a74 AW |
2184 | vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { |
2185 | return -errno; | |
2186 | } | |
2187 | ctrl = le16_to_cpu(ctrl); | |
2188 | ||
2189 | msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); | |
2190 | msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); | |
2191 | entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); | |
2192 | ||
df92ee44 | 2193 | trace_vfio_setup_msi(vdev->vbasedev.name, pos); |
65501a74 AW |
2194 | |
2195 | ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit); | |
2196 | if (ret < 0) { | |
e43b9a5a AW |
2197 | if (ret == -ENOTSUP) { |
2198 | return 0; | |
2199 | } | |
312fd5f2 | 2200 | error_report("vfio: msi_init failed"); |
65501a74 AW |
2201 | return ret; |
2202 | } | |
2203 | vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); | |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | /* | |
2209 | * We don't have any control over how pci_add_capability() inserts | |
2210 | * capabilities into the chain. In order to setup MSI-X we need a | |
2211 | * MemoryRegion for the BAR. In order to setup the BAR and not | |
2212 | * attempt to mmap the MSI-X table area, which VFIO won't allow, we | |
2213 | * need to first look for where the MSI-X table lives. So we | |
2214 | * unfortunately split MSI-X setup across two functions. | |
2215 | */ | |
9ee27d73 | 2216 | static int vfio_early_setup_msix(VFIOPCIDevice *vdev) |
65501a74 AW |
2217 | { |
2218 | uint8_t pos; | |
2219 | uint16_t ctrl; | |
2220 | uint32_t table, pba; | |
5546a621 | 2221 | int fd = vdev->vbasedev.fd; |
65501a74 AW |
2222 | |
2223 | pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); | |
2224 | if (!pos) { | |
2225 | return 0; | |
2226 | } | |
2227 | ||
5546a621 | 2228 | if (pread(fd, &ctrl, sizeof(ctrl), |
65501a74 AW |
2229 | vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { |
2230 | return -errno; | |
2231 | } | |
2232 | ||
5546a621 | 2233 | if (pread(fd, &table, sizeof(table), |
65501a74 AW |
2234 | vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { |
2235 | return -errno; | |
2236 | } | |
2237 | ||
5546a621 | 2238 | if (pread(fd, &pba, sizeof(pba), |
65501a74 AW |
2239 | vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { |
2240 | return -errno; | |
2241 | } | |
2242 | ||
2243 | ctrl = le16_to_cpu(ctrl); | |
2244 | table = le32_to_cpu(table); | |
2245 | pba = le32_to_cpu(pba); | |
2246 | ||
2247 | vdev->msix = g_malloc0(sizeof(*(vdev->msix))); | |
2248 | vdev->msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; | |
2249 | vdev->msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; | |
2250 | vdev->msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; | |
2251 | vdev->msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; | |
2252 | vdev->msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
2253 | ||
df92ee44 EA |
2254 | trace_vfio_early_setup_msix(vdev->vbasedev.name, pos, |
2255 | vdev->msix->table_bar, | |
385f57cf EA |
2256 | vdev->msix->table_offset, |
2257 | vdev->msix->entries); | |
65501a74 AW |
2258 | |
2259 | return 0; | |
2260 | } | |
2261 | ||
9ee27d73 | 2262 | static int vfio_setup_msix(VFIOPCIDevice *vdev, int pos) |
65501a74 AW |
2263 | { |
2264 | int ret; | |
2265 | ||
65501a74 | 2266 | ret = msix_init(&vdev->pdev, vdev->msix->entries, |
a664477d | 2267 | &vdev->bars[vdev->msix->table_bar].region.mem, |
65501a74 | 2268 | vdev->msix->table_bar, vdev->msix->table_offset, |
a664477d | 2269 | &vdev->bars[vdev->msix->pba_bar].region.mem, |
65501a74 AW |
2270 | vdev->msix->pba_bar, vdev->msix->pba_offset, pos); |
2271 | if (ret < 0) { | |
e43b9a5a AW |
2272 | if (ret == -ENOTSUP) { |
2273 | return 0; | |
2274 | } | |
312fd5f2 | 2275 | error_report("vfio: msix_init failed"); |
65501a74 AW |
2276 | return ret; |
2277 | } | |
2278 | ||
65501a74 AW |
2279 | return 0; |
2280 | } | |
2281 | ||
9ee27d73 | 2282 | static void vfio_teardown_msi(VFIOPCIDevice *vdev) |
65501a74 AW |
2283 | { |
2284 | msi_uninit(&vdev->pdev); | |
2285 | ||
2286 | if (vdev->msix) { | |
a664477d EA |
2287 | msix_uninit(&vdev->pdev, |
2288 | &vdev->bars[vdev->msix->table_bar].region.mem, | |
2289 | &vdev->bars[vdev->msix->pba_bar].region.mem); | |
65501a74 AW |
2290 | } |
2291 | } | |
2292 | ||
2293 | /* | |
2294 | * Resource setup | |
2295 | */ | |
9ee27d73 | 2296 | static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) |
65501a74 AW |
2297 | { |
2298 | int i; | |
2299 | ||
2300 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2301 | VFIOBAR *bar = &vdev->bars[i]; | |
2302 | ||
a664477d | 2303 | if (!bar->region.size) { |
65501a74 AW |
2304 | continue; |
2305 | } | |
2306 | ||
a664477d | 2307 | memory_region_set_enabled(&bar->region.mmap_mem, enabled); |
65501a74 AW |
2308 | if (vdev->msix && vdev->msix->table_bar == i) { |
2309 | memory_region_set_enabled(&vdev->msix->mmap_mem, enabled); | |
2310 | } | |
2311 | } | |
2312 | } | |
2313 | ||
ba5e6bfa | 2314 | static void vfio_unregister_bar(VFIOPCIDevice *vdev, int nr) |
65501a74 AW |
2315 | { |
2316 | VFIOBAR *bar = &vdev->bars[nr]; | |
2317 | ||
a664477d | 2318 | if (!bar->region.size) { |
65501a74 AW |
2319 | return; |
2320 | } | |
2321 | ||
7076eabc AW |
2322 | vfio_bar_quirk_teardown(vdev, nr); |
2323 | ||
a664477d | 2324 | memory_region_del_subregion(&bar->region.mem, &bar->region.mmap_mem); |
65501a74 AW |
2325 | |
2326 | if (vdev->msix && vdev->msix->table_bar == nr) { | |
a664477d | 2327 | memory_region_del_subregion(&bar->region.mem, &vdev->msix->mmap_mem); |
ba5e6bfa PB |
2328 | } |
2329 | } | |
2330 | ||
2331 | static void vfio_unmap_bar(VFIOPCIDevice *vdev, int nr) | |
2332 | { | |
2333 | VFIOBAR *bar = &vdev->bars[nr]; | |
2334 | ||
2335 | if (!bar->region.size) { | |
2336 | return; | |
2337 | } | |
2338 | ||
2339 | vfio_bar_quirk_free(vdev, nr); | |
2340 | ||
2341 | munmap(bar->region.mmap, memory_region_size(&bar->region.mmap_mem)); | |
2342 | ||
2343 | if (vdev->msix && vdev->msix->table_bar == nr) { | |
65501a74 AW |
2344 | munmap(vdev->msix->mmap, memory_region_size(&vdev->msix->mmap_mem)); |
2345 | } | |
65501a74 AW |
2346 | } |
2347 | ||
9ee27d73 | 2348 | static void vfio_map_bar(VFIOPCIDevice *vdev, int nr) |
65501a74 AW |
2349 | { |
2350 | VFIOBAR *bar = &vdev->bars[nr]; | |
29c6e6df | 2351 | uint64_t size = bar->region.size; |
65501a74 AW |
2352 | char name[64]; |
2353 | uint32_t pci_bar; | |
2354 | uint8_t type; | |
2355 | int ret; | |
2356 | ||
2357 | /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ | |
2358 | if (!size) { | |
2359 | return; | |
2360 | } | |
2361 | ||
2362 | snprintf(name, sizeof(name), "VFIO %04x:%02x:%02x.%x BAR %d", | |
2363 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
2364 | vdev->host.function, nr); | |
2365 | ||
2366 | /* Determine what type of BAR this is for registration */ | |
5546a621 | 2367 | ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), |
65501a74 AW |
2368 | vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); |
2369 | if (ret != sizeof(pci_bar)) { | |
312fd5f2 | 2370 | error_report("vfio: Failed to read BAR %d (%m)", nr); |
65501a74 AW |
2371 | return; |
2372 | } | |
2373 | ||
2374 | pci_bar = le32_to_cpu(pci_bar); | |
39360f0b AW |
2375 | bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); |
2376 | bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
2377 | type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : | |
2378 | ~PCI_BASE_ADDRESS_MEM_MASK); | |
65501a74 AW |
2379 | |
2380 | /* A "slow" read/write mapping underlies all BARs */ | |
a664477d | 2381 | memory_region_init_io(&bar->region.mem, OBJECT(vdev), &vfio_region_ops, |
39360f0b | 2382 | bar, name, size); |
a664477d | 2383 | pci_register_bar(&vdev->pdev, nr, type, &bar->region.mem); |
65501a74 AW |
2384 | |
2385 | /* | |
2386 | * We can't mmap areas overlapping the MSIX vector table, so we | |
2387 | * potentially insert a direct-mapped subregion before and after it. | |
2388 | */ | |
2389 | if (vdev->msix && vdev->msix->table_bar == nr) { | |
8d7b5a1d | 2390 | size = vdev->msix->table_offset & qemu_host_page_mask; |
65501a74 AW |
2391 | } |
2392 | ||
2393 | strncat(name, " mmap", sizeof(name) - strlen(name) - 1); | |
a664477d EA |
2394 | if (vfio_mmap_region(OBJECT(vdev), &bar->region, &bar->region.mem, |
2395 | &bar->region.mmap_mem, &bar->region.mmap, | |
2396 | size, 0, name)) { | |
312fd5f2 | 2397 | error_report("%s unsupported. Performance may be slow", name); |
65501a74 AW |
2398 | } |
2399 | ||
2400 | if (vdev->msix && vdev->msix->table_bar == nr) { | |
29c6e6df | 2401 | uint64_t start; |
65501a74 | 2402 | |
07ceaf98 | 2403 | start = HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + |
8d7b5a1d | 2404 | (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); |
65501a74 | 2405 | |
a664477d | 2406 | size = start < bar->region.size ? bar->region.size - start : 0; |
65501a74 AW |
2407 | strncat(name, " msix-hi", sizeof(name) - strlen(name) - 1); |
2408 | /* VFIOMSIXInfo contains another MemoryRegion for this mapping */ | |
a664477d EA |
2409 | if (vfio_mmap_region(OBJECT(vdev), &bar->region, &bar->region.mem, |
2410 | &vdev->msix->mmap_mem, | |
65501a74 | 2411 | &vdev->msix->mmap, size, start, name)) { |
312fd5f2 | 2412 | error_report("%s unsupported. Performance may be slow", name); |
65501a74 AW |
2413 | } |
2414 | } | |
7076eabc AW |
2415 | |
2416 | vfio_bar_quirk_setup(vdev, nr); | |
65501a74 AW |
2417 | } |
2418 | ||
9ee27d73 | 2419 | static void vfio_map_bars(VFIOPCIDevice *vdev) |
65501a74 AW |
2420 | { |
2421 | int i; | |
2422 | ||
2423 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2424 | vfio_map_bar(vdev, i); | |
2425 | } | |
f15689c7 AW |
2426 | |
2427 | if (vdev->has_vga) { | |
3c161542 PB |
2428 | memory_region_init_io(&vdev->vga.region[QEMU_PCI_VGA_MEM].mem, |
2429 | OBJECT(vdev), &vfio_vga_ops, | |
f15689c7 AW |
2430 | &vdev->vga.region[QEMU_PCI_VGA_MEM], |
2431 | "vfio-vga-mmio@0xa0000", | |
2432 | QEMU_PCI_VGA_MEM_SIZE); | |
3c161542 PB |
2433 | memory_region_init_io(&vdev->vga.region[QEMU_PCI_VGA_IO_LO].mem, |
2434 | OBJECT(vdev), &vfio_vga_ops, | |
f15689c7 AW |
2435 | &vdev->vga.region[QEMU_PCI_VGA_IO_LO], |
2436 | "vfio-vga-io@0x3b0", | |
2437 | QEMU_PCI_VGA_IO_LO_SIZE); | |
3c161542 PB |
2438 | memory_region_init_io(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem, |
2439 | OBJECT(vdev), &vfio_vga_ops, | |
f15689c7 AW |
2440 | &vdev->vga.region[QEMU_PCI_VGA_IO_HI], |
2441 | "vfio-vga-io@0x3c0", | |
2442 | QEMU_PCI_VGA_IO_HI_SIZE); | |
2443 | ||
2444 | pci_register_vga(&vdev->pdev, &vdev->vga.region[QEMU_PCI_VGA_MEM].mem, | |
2445 | &vdev->vga.region[QEMU_PCI_VGA_IO_LO].mem, | |
2446 | &vdev->vga.region[QEMU_PCI_VGA_IO_HI].mem); | |
7076eabc | 2447 | vfio_vga_quirk_setup(vdev); |
f15689c7 | 2448 | } |
65501a74 AW |
2449 | } |
2450 | ||
ba5e6bfa | 2451 | static void vfio_unregister_bars(VFIOPCIDevice *vdev) |
65501a74 AW |
2452 | { |
2453 | int i; | |
2454 | ||
2455 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
ba5e6bfa | 2456 | vfio_unregister_bar(vdev, i); |
65501a74 | 2457 | } |
f15689c7 AW |
2458 | |
2459 | if (vdev->has_vga) { | |
7076eabc | 2460 | vfio_vga_quirk_teardown(vdev); |
f15689c7 | 2461 | pci_unregister_vga(&vdev->pdev); |
f15689c7 | 2462 | } |
65501a74 AW |
2463 | } |
2464 | ||
ba5e6bfa PB |
2465 | static void vfio_unmap_bars(VFIOPCIDevice *vdev) |
2466 | { | |
2467 | int i; | |
2468 | ||
2469 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2470 | vfio_unmap_bar(vdev, i); | |
2471 | } | |
2472 | ||
2473 | if (vdev->has_vga) { | |
2474 | vfio_vga_quirk_free(vdev); | |
2475 | } | |
2476 | } | |
2477 | ||
65501a74 AW |
2478 | /* |
2479 | * General setup | |
2480 | */ | |
2481 | static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) | |
2482 | { | |
2483 | uint8_t tmp, next = 0xff; | |
2484 | ||
2485 | for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; | |
2486 | tmp = pdev->config[tmp + 1]) { | |
2487 | if (tmp > pos && tmp < next) { | |
2488 | next = tmp; | |
2489 | } | |
2490 | } | |
2491 | ||
2492 | return next - pos; | |
2493 | } | |
2494 | ||
96adc5c7 AW |
2495 | static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) |
2496 | { | |
2497 | pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); | |
2498 | } | |
2499 | ||
9ee27d73 | 2500 | static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, |
96adc5c7 AW |
2501 | uint16_t val, uint16_t mask) |
2502 | { | |
2503 | vfio_set_word_bits(vdev->pdev.config + pos, val, mask); | |
2504 | vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); | |
2505 | vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); | |
2506 | } | |
2507 | ||
2508 | static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) | |
2509 | { | |
2510 | pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); | |
2511 | } | |
2512 | ||
9ee27d73 | 2513 | static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, |
96adc5c7 AW |
2514 | uint32_t val, uint32_t mask) |
2515 | { | |
2516 | vfio_set_long_bits(vdev->pdev.config + pos, val, mask); | |
2517 | vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); | |
2518 | vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); | |
2519 | } | |
2520 | ||
9ee27d73 | 2521 | static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size) |
96adc5c7 AW |
2522 | { |
2523 | uint16_t flags; | |
2524 | uint8_t type; | |
2525 | ||
2526 | flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); | |
2527 | type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; | |
2528 | ||
2529 | if (type != PCI_EXP_TYPE_ENDPOINT && | |
2530 | type != PCI_EXP_TYPE_LEG_END && | |
2531 | type != PCI_EXP_TYPE_RC_END) { | |
2532 | ||
2533 | error_report("vfio: Assignment of PCIe type 0x%x " | |
2534 | "devices is not currently supported", type); | |
2535 | return -EINVAL; | |
2536 | } | |
2537 | ||
2538 | if (!pci_bus_is_express(vdev->pdev.bus)) { | |
2539 | /* | |
2540 | * Use express capability as-is on PCI bus. It doesn't make much | |
2541 | * sense to even expose, but some drivers (ex. tg3) depend on it | |
2542 | * and guests don't seem to be particular about it. We'll need | |
2543 | * to revist this or force express devices to express buses if we | |
2544 | * ever expose an IOMMU to the guest. | |
2545 | */ | |
2546 | } else if (pci_bus_is_root(vdev->pdev.bus)) { | |
2547 | /* | |
2548 | * On a Root Complex bus Endpoints become Root Complex Integrated | |
2549 | * Endpoints, which changes the type and clears the LNK & LNK2 fields. | |
2550 | */ | |
2551 | if (type == PCI_EXP_TYPE_ENDPOINT) { | |
2552 | vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, | |
2553 | PCI_EXP_TYPE_RC_END << 4, | |
2554 | PCI_EXP_FLAGS_TYPE); | |
2555 | ||
2556 | /* Link Capabilities, Status, and Control goes away */ | |
2557 | if (size > PCI_EXP_LNKCTL) { | |
2558 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); | |
2559 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); | |
2560 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); | |
2561 | ||
2562 | #ifndef PCI_EXP_LNKCAP2 | |
2563 | #define PCI_EXP_LNKCAP2 44 | |
2564 | #endif | |
2565 | #ifndef PCI_EXP_LNKSTA2 | |
2566 | #define PCI_EXP_LNKSTA2 50 | |
2567 | #endif | |
2568 | /* Link 2 Capabilities, Status, and Control goes away */ | |
2569 | if (size > PCI_EXP_LNKCAP2) { | |
2570 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); | |
2571 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); | |
2572 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); | |
2573 | } | |
2574 | } | |
2575 | ||
2576 | } else if (type == PCI_EXP_TYPE_LEG_END) { | |
2577 | /* | |
2578 | * Legacy endpoints don't belong on the root complex. Windows | |
2579 | * seems to be happier with devices if we skip the capability. | |
2580 | */ | |
2581 | return 0; | |
2582 | } | |
2583 | ||
2584 | } else { | |
2585 | /* | |
2586 | * Convert Root Complex Integrated Endpoints to regular endpoints. | |
2587 | * These devices don't support LNK/LNK2 capabilities, so make them up. | |
2588 | */ | |
2589 | if (type == PCI_EXP_TYPE_RC_END) { | |
2590 | vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, | |
2591 | PCI_EXP_TYPE_ENDPOINT << 4, | |
2592 | PCI_EXP_FLAGS_TYPE); | |
2593 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, | |
2594 | PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); | |
2595 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); | |
2596 | } | |
2597 | ||
2598 | /* Mark the Link Status bits as emulated to allow virtual negotiation */ | |
2599 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, | |
2600 | pci_get_word(vdev->pdev.config + pos + | |
2601 | PCI_EXP_LNKSTA), | |
2602 | PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); | |
2603 | } | |
2604 | ||
2605 | pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); | |
2606 | if (pos >= 0) { | |
2607 | vdev->pdev.exp.exp_cap = pos; | |
2608 | } | |
2609 | ||
2610 | return pos; | |
2611 | } | |
2612 | ||
9ee27d73 | 2613 | static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
2614 | { |
2615 | uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); | |
2616 | ||
2617 | if (cap & PCI_EXP_DEVCAP_FLR) { | |
df92ee44 | 2618 | trace_vfio_check_pcie_flr(vdev->vbasedev.name); |
befe5176 AW |
2619 | vdev->has_flr = true; |
2620 | } | |
2621 | } | |
2622 | ||
9ee27d73 | 2623 | static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
2624 | { |
2625 | uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); | |
2626 | ||
2627 | if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { | |
df92ee44 | 2628 | trace_vfio_check_pm_reset(vdev->vbasedev.name); |
befe5176 AW |
2629 | vdev->has_pm_reset = true; |
2630 | } | |
2631 | } | |
2632 | ||
9ee27d73 | 2633 | static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
2634 | { |
2635 | uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); | |
2636 | ||
2637 | if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { | |
df92ee44 | 2638 | trace_vfio_check_af_flr(vdev->vbasedev.name); |
befe5176 AW |
2639 | vdev->has_flr = true; |
2640 | } | |
2641 | } | |
2642 | ||
9ee27d73 | 2643 | static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos) |
65501a74 AW |
2644 | { |
2645 | PCIDevice *pdev = &vdev->pdev; | |
2646 | uint8_t cap_id, next, size; | |
2647 | int ret; | |
2648 | ||
2649 | cap_id = pdev->config[pos]; | |
2650 | next = pdev->config[pos + 1]; | |
2651 | ||
2652 | /* | |
2653 | * If it becomes important to configure capabilities to their actual | |
2654 | * size, use this as the default when it's something we don't recognize. | |
2655 | * Since QEMU doesn't actually handle many of the config accesses, | |
2656 | * exact size doesn't seem worthwhile. | |
2657 | */ | |
2658 | size = vfio_std_cap_max_size(pdev, pos); | |
2659 | ||
2660 | /* | |
2661 | * pci_add_capability always inserts the new capability at the head | |
2662 | * of the chain. Therefore to end up with a chain that matches the | |
2663 | * physical device, we insert from the end by making this recursive. | |
2664 | * This is also why we pre-caclulate size above as cached config space | |
2665 | * will be changed as we unwind the stack. | |
2666 | */ | |
2667 | if (next) { | |
2668 | ret = vfio_add_std_cap(vdev, next); | |
2669 | if (ret) { | |
2670 | return ret; | |
2671 | } | |
2672 | } else { | |
96adc5c7 AW |
2673 | /* Begin the rebuild, use QEMU emulated list bits */ |
2674 | pdev->config[PCI_CAPABILITY_LIST] = 0; | |
2675 | vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; | |
2676 | vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
65501a74 AW |
2677 | } |
2678 | ||
96adc5c7 AW |
2679 | /* Use emulated next pointer to allow dropping caps */ |
2680 | pci_set_byte(vdev->emulated_config_bits + pos + 1, 0xff); | |
2681 | ||
65501a74 AW |
2682 | switch (cap_id) { |
2683 | case PCI_CAP_ID_MSI: | |
2684 | ret = vfio_setup_msi(vdev, pos); | |
2685 | break; | |
96adc5c7 | 2686 | case PCI_CAP_ID_EXP: |
befe5176 | 2687 | vfio_check_pcie_flr(vdev, pos); |
96adc5c7 AW |
2688 | ret = vfio_setup_pcie_cap(vdev, pos, size); |
2689 | break; | |
65501a74 AW |
2690 | case PCI_CAP_ID_MSIX: |
2691 | ret = vfio_setup_msix(vdev, pos); | |
2692 | break; | |
ba661818 | 2693 | case PCI_CAP_ID_PM: |
befe5176 | 2694 | vfio_check_pm_reset(vdev, pos); |
ba661818 | 2695 | vdev->pm_cap = pos; |
befe5176 AW |
2696 | ret = pci_add_capability(pdev, cap_id, pos, size); |
2697 | break; | |
2698 | case PCI_CAP_ID_AF: | |
2699 | vfio_check_af_flr(vdev, pos); | |
2700 | ret = pci_add_capability(pdev, cap_id, pos, size); | |
2701 | break; | |
65501a74 AW |
2702 | default: |
2703 | ret = pci_add_capability(pdev, cap_id, pos, size); | |
2704 | break; | |
2705 | } | |
2706 | ||
2707 | if (ret < 0) { | |
2708 | error_report("vfio: %04x:%02x:%02x.%x Error adding PCI capability " | |
312fd5f2 | 2709 | "0x%x[0x%x]@0x%x: %d", vdev->host.domain, |
65501a74 AW |
2710 | vdev->host.bus, vdev->host.slot, vdev->host.function, |
2711 | cap_id, size, pos, ret); | |
2712 | return ret; | |
2713 | } | |
2714 | ||
2715 | return 0; | |
2716 | } | |
2717 | ||
9ee27d73 | 2718 | static int vfio_add_capabilities(VFIOPCIDevice *vdev) |
65501a74 AW |
2719 | { |
2720 | PCIDevice *pdev = &vdev->pdev; | |
2721 | ||
2722 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || | |
2723 | !pdev->config[PCI_CAPABILITY_LIST]) { | |
2724 | return 0; /* Nothing to add */ | |
2725 | } | |
2726 | ||
2727 | return vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST]); | |
2728 | } | |
2729 | ||
9ee27d73 | 2730 | static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) |
f16f39c3 AW |
2731 | { |
2732 | PCIDevice *pdev = &vdev->pdev; | |
2733 | uint16_t cmd; | |
2734 | ||
2735 | vfio_disable_interrupts(vdev); | |
2736 | ||
2737 | /* Make sure the device is in D0 */ | |
2738 | if (vdev->pm_cap) { | |
2739 | uint16_t pmcsr; | |
2740 | uint8_t state; | |
2741 | ||
2742 | pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); | |
2743 | state = pmcsr & PCI_PM_CTRL_STATE_MASK; | |
2744 | if (state) { | |
2745 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
2746 | vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); | |
2747 | /* vfio handles the necessary delay here */ | |
2748 | pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); | |
2749 | state = pmcsr & PCI_PM_CTRL_STATE_MASK; | |
2750 | if (state) { | |
4e505ddd | 2751 | error_report("vfio: Unable to power on device, stuck in D%d", |
f16f39c3 AW |
2752 | state); |
2753 | } | |
2754 | } | |
2755 | } | |
2756 | ||
2757 | /* | |
2758 | * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. | |
2759 | * Also put INTx Disable in known state. | |
2760 | */ | |
2761 | cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); | |
2762 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | | |
2763 | PCI_COMMAND_INTX_DISABLE); | |
2764 | vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); | |
2765 | } | |
2766 | ||
9ee27d73 | 2767 | static void vfio_pci_post_reset(VFIOPCIDevice *vdev) |
f16f39c3 AW |
2768 | { |
2769 | vfio_enable_intx(vdev); | |
2770 | } | |
2771 | ||
2772 | static bool vfio_pci_host_match(PCIHostDeviceAddress *host1, | |
2773 | PCIHostDeviceAddress *host2) | |
2774 | { | |
2775 | return (host1->domain == host2->domain && host1->bus == host2->bus && | |
2776 | host1->slot == host2->slot && host1->function == host2->function); | |
2777 | } | |
2778 | ||
9ee27d73 | 2779 | static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) |
f16f39c3 AW |
2780 | { |
2781 | VFIOGroup *group; | |
2782 | struct vfio_pci_hot_reset_info *info; | |
2783 | struct vfio_pci_dependent_device *devices; | |
2784 | struct vfio_pci_hot_reset *reset; | |
2785 | int32_t *fds; | |
2786 | int ret, i, count; | |
2787 | bool multi = false; | |
2788 | ||
df92ee44 | 2789 | trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); |
f16f39c3 AW |
2790 | |
2791 | vfio_pci_pre_reset(vdev); | |
b47d8efa | 2792 | vdev->vbasedev.needs_reset = false; |
f16f39c3 AW |
2793 | |
2794 | info = g_malloc0(sizeof(*info)); | |
2795 | info->argsz = sizeof(*info); | |
2796 | ||
5546a621 | 2797 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); |
f16f39c3 AW |
2798 | if (ret && errno != ENOSPC) { |
2799 | ret = -errno; | |
2800 | if (!vdev->has_pm_reset) { | |
2801 | error_report("vfio: Cannot reset device %04x:%02x:%02x.%x, " | |
2802 | "no available reset mechanism.", vdev->host.domain, | |
2803 | vdev->host.bus, vdev->host.slot, vdev->host.function); | |
2804 | } | |
2805 | goto out_single; | |
2806 | } | |
2807 | ||
2808 | count = info->count; | |
2809 | info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); | |
2810 | info->argsz = sizeof(*info) + (count * sizeof(*devices)); | |
2811 | devices = &info->devices[0]; | |
2812 | ||
5546a621 | 2813 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); |
f16f39c3 AW |
2814 | if (ret) { |
2815 | ret = -errno; | |
2816 | error_report("vfio: hot reset info failed: %m"); | |
2817 | goto out_single; | |
2818 | } | |
2819 | ||
df92ee44 | 2820 | trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); |
f16f39c3 AW |
2821 | |
2822 | /* Verify that we have all the groups required */ | |
2823 | for (i = 0; i < info->count; i++) { | |
2824 | PCIHostDeviceAddress host; | |
9ee27d73 | 2825 | VFIOPCIDevice *tmp; |
b47d8efa | 2826 | VFIODevice *vbasedev_iter; |
f16f39c3 AW |
2827 | |
2828 | host.domain = devices[i].segment; | |
2829 | host.bus = devices[i].bus; | |
2830 | host.slot = PCI_SLOT(devices[i].devfn); | |
2831 | host.function = PCI_FUNC(devices[i].devfn); | |
2832 | ||
385f57cf | 2833 | trace_vfio_pci_hot_reset_dep_devices(host.domain, |
f16f39c3 AW |
2834 | host.bus, host.slot, host.function, devices[i].group_id); |
2835 | ||
2836 | if (vfio_pci_host_match(&host, &vdev->host)) { | |
2837 | continue; | |
2838 | } | |
2839 | ||
62356b72 | 2840 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2841 | if (group->groupid == devices[i].group_id) { |
2842 | break; | |
2843 | } | |
2844 | } | |
2845 | ||
2846 | if (!group) { | |
2847 | if (!vdev->has_pm_reset) { | |
df92ee44 | 2848 | error_report("vfio: Cannot reset device %s, " |
f16f39c3 | 2849 | "depends on group %d which is not owned.", |
df92ee44 | 2850 | vdev->vbasedev.name, devices[i].group_id); |
f16f39c3 AW |
2851 | } |
2852 | ret = -EPERM; | |
2853 | goto out; | |
2854 | } | |
2855 | ||
2856 | /* Prep dependent devices for reset and clear our marker. */ | |
b47d8efa EA |
2857 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2858 | if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { | |
2859 | continue; | |
2860 | } | |
2861 | tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); | |
f16f39c3 AW |
2862 | if (vfio_pci_host_match(&host, &tmp->host)) { |
2863 | if (single) { | |
f16f39c3 AW |
2864 | ret = -EINVAL; |
2865 | goto out_single; | |
2866 | } | |
2867 | vfio_pci_pre_reset(tmp); | |
b47d8efa | 2868 | tmp->vbasedev.needs_reset = false; |
f16f39c3 AW |
2869 | multi = true; |
2870 | break; | |
2871 | } | |
2872 | } | |
2873 | } | |
2874 | ||
2875 | if (!single && !multi) { | |
f16f39c3 AW |
2876 | ret = -EINVAL; |
2877 | goto out_single; | |
2878 | } | |
2879 | ||
2880 | /* Determine how many group fds need to be passed */ | |
2881 | count = 0; | |
62356b72 | 2882 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2883 | for (i = 0; i < info->count; i++) { |
2884 | if (group->groupid == devices[i].group_id) { | |
2885 | count++; | |
2886 | break; | |
2887 | } | |
2888 | } | |
2889 | } | |
2890 | ||
2891 | reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); | |
2892 | reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); | |
2893 | fds = &reset->group_fds[0]; | |
2894 | ||
2895 | /* Fill in group fds */ | |
62356b72 | 2896 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2897 | for (i = 0; i < info->count; i++) { |
2898 | if (group->groupid == devices[i].group_id) { | |
2899 | fds[reset->count++] = group->fd; | |
2900 | break; | |
2901 | } | |
2902 | } | |
2903 | } | |
2904 | ||
2905 | /* Bus reset! */ | |
5546a621 | 2906 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); |
f16f39c3 AW |
2907 | g_free(reset); |
2908 | ||
df92ee44 | 2909 | trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, |
385f57cf | 2910 | ret ? "%m" : "Success"); |
f16f39c3 AW |
2911 | |
2912 | out: | |
2913 | /* Re-enable INTx on affected devices */ | |
2914 | for (i = 0; i < info->count; i++) { | |
2915 | PCIHostDeviceAddress host; | |
9ee27d73 | 2916 | VFIOPCIDevice *tmp; |
b47d8efa | 2917 | VFIODevice *vbasedev_iter; |
f16f39c3 AW |
2918 | |
2919 | host.domain = devices[i].segment; | |
2920 | host.bus = devices[i].bus; | |
2921 | host.slot = PCI_SLOT(devices[i].devfn); | |
2922 | host.function = PCI_FUNC(devices[i].devfn); | |
2923 | ||
2924 | if (vfio_pci_host_match(&host, &vdev->host)) { | |
2925 | continue; | |
2926 | } | |
2927 | ||
62356b72 | 2928 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2929 | if (group->groupid == devices[i].group_id) { |
2930 | break; | |
2931 | } | |
2932 | } | |
2933 | ||
2934 | if (!group) { | |
2935 | break; | |
2936 | } | |
2937 | ||
b47d8efa EA |
2938 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2939 | if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { | |
2940 | continue; | |
2941 | } | |
2942 | tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); | |
f16f39c3 AW |
2943 | if (vfio_pci_host_match(&host, &tmp->host)) { |
2944 | vfio_pci_post_reset(tmp); | |
2945 | break; | |
2946 | } | |
2947 | } | |
2948 | } | |
2949 | out_single: | |
2950 | vfio_pci_post_reset(vdev); | |
2951 | g_free(info); | |
2952 | ||
2953 | return ret; | |
2954 | } | |
2955 | ||
2956 | /* | |
2957 | * We want to differentiate hot reset of mulitple in-use devices vs hot reset | |
2958 | * of a single in-use device. VFIO_DEVICE_RESET will already handle the case | |
2959 | * of doing hot resets when there is only a single device per bus. The in-use | |
2960 | * here refers to how many VFIODevices are affected. A hot reset that affects | |
2961 | * multiple devices, but only a single in-use device, means that we can call | |
2962 | * it from our bus ->reset() callback since the extent is effectively a single | |
2963 | * device. This allows us to make use of it in the hotplug path. When there | |
2964 | * are multiple in-use devices, we can only trigger the hot reset during a | |
2965 | * system reset and thus from our reset handler. We separate _one vs _multi | |
2966 | * here so that we don't overlap and do a double reset on the system reset | |
2967 | * path where both our reset handler and ->reset() callback are used. Calling | |
2968 | * _one() will only do a hot reset for the one in-use devices case, calling | |
2969 | * _multi() will do nothing if a _one() would have been sufficient. | |
2970 | */ | |
9ee27d73 | 2971 | static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) |
f16f39c3 AW |
2972 | { |
2973 | return vfio_pci_hot_reset(vdev, true); | |
2974 | } | |
2975 | ||
b47d8efa | 2976 | static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) |
f16f39c3 | 2977 | { |
b47d8efa | 2978 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); |
f16f39c3 AW |
2979 | return vfio_pci_hot_reset(vdev, false); |
2980 | } | |
2981 | ||
b47d8efa EA |
2982 | static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) |
2983 | { | |
2984 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); | |
2985 | if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { | |
2986 | vbasedev->needs_reset = true; | |
2987 | } | |
2988 | } | |
2989 | ||
2990 | static VFIODeviceOps vfio_pci_ops = { | |
2991 | .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, | |
2992 | .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, | |
a664477d | 2993 | .vfio_eoi = vfio_eoi, |
b47d8efa EA |
2994 | }; |
2995 | ||
217e9fdc | 2996 | static int vfio_populate_device(VFIOPCIDevice *vdev) |
65501a74 | 2997 | { |
217e9fdc | 2998 | VFIODevice *vbasedev = &vdev->vbasedev; |
65501a74 | 2999 | struct vfio_region_info reg_info = { .argsz = sizeof(reg_info) }; |
7b4b0e9e | 3000 | struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; |
d13dd2d7 | 3001 | int i, ret = -1; |
65501a74 AW |
3002 | |
3003 | /* Sanity check device */ | |
d13dd2d7 | 3004 | if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { |
312fd5f2 | 3005 | error_report("vfio: Um, this isn't a PCI device"); |
65501a74 AW |
3006 | goto error; |
3007 | } | |
3008 | ||
d13dd2d7 | 3009 | if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { |
312fd5f2 | 3010 | error_report("vfio: unexpected number of io regions %u", |
d13dd2d7 | 3011 | vbasedev->num_regions); |
65501a74 AW |
3012 | goto error; |
3013 | } | |
3014 | ||
d13dd2d7 EA |
3015 | if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { |
3016 | error_report("vfio: unexpected number of irqs %u", vbasedev->num_irqs); | |
65501a74 AW |
3017 | goto error; |
3018 | } | |
3019 | ||
3020 | for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { | |
3021 | reg_info.index = i; | |
3022 | ||
d13dd2d7 | 3023 | ret = ioctl(vbasedev->fd, VFIO_DEVICE_GET_REGION_INFO, ®_info); |
65501a74 | 3024 | if (ret) { |
312fd5f2 | 3025 | error_report("vfio: Error getting region %d info: %m", i); |
65501a74 AW |
3026 | goto error; |
3027 | } | |
3028 | ||
d13dd2d7 EA |
3029 | trace_vfio_populate_device_region(vbasedev->name, i, |
3030 | (unsigned long)reg_info.size, | |
3031 | (unsigned long)reg_info.offset, | |
3032 | (unsigned long)reg_info.flags); | |
65501a74 | 3033 | |
d13dd2d7 | 3034 | vdev->bars[i].region.vbasedev = vbasedev; |
a664477d EA |
3035 | vdev->bars[i].region.flags = reg_info.flags; |
3036 | vdev->bars[i].region.size = reg_info.size; | |
3037 | vdev->bars[i].region.fd_offset = reg_info.offset; | |
3038 | vdev->bars[i].region.nr = i; | |
7076eabc | 3039 | QLIST_INIT(&vdev->bars[i].quirks); |
65501a74 AW |
3040 | } |
3041 | ||
65501a74 AW |
3042 | reg_info.index = VFIO_PCI_CONFIG_REGION_INDEX; |
3043 | ||
5546a621 | 3044 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_REGION_INFO, ®_info); |
65501a74 | 3045 | if (ret) { |
312fd5f2 | 3046 | error_report("vfio: Error getting config info: %m"); |
65501a74 AW |
3047 | goto error; |
3048 | } | |
3049 | ||
d13dd2d7 EA |
3050 | trace_vfio_populate_device_config(vdev->vbasedev.name, |
3051 | (unsigned long)reg_info.size, | |
3052 | (unsigned long)reg_info.offset, | |
3053 | (unsigned long)reg_info.flags); | |
65501a74 AW |
3054 | |
3055 | vdev->config_size = reg_info.size; | |
6a659bbf AW |
3056 | if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { |
3057 | vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; | |
3058 | } | |
65501a74 AW |
3059 | vdev->config_offset = reg_info.offset; |
3060 | ||
f15689c7 | 3061 | if ((vdev->features & VFIO_FEATURE_ENABLE_VGA) && |
d13dd2d7 | 3062 | vbasedev->num_regions > VFIO_PCI_VGA_REGION_INDEX) { |
f15689c7 AW |
3063 | struct vfio_region_info vga_info = { |
3064 | .argsz = sizeof(vga_info), | |
3065 | .index = VFIO_PCI_VGA_REGION_INDEX, | |
3066 | }; | |
3067 | ||
5546a621 | 3068 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_REGION_INFO, &vga_info); |
f15689c7 AW |
3069 | if (ret) { |
3070 | error_report( | |
3071 | "vfio: Device does not support requested feature x-vga"); | |
3072 | goto error; | |
3073 | } | |
3074 | ||
3075 | if (!(vga_info.flags & VFIO_REGION_INFO_FLAG_READ) || | |
3076 | !(vga_info.flags & VFIO_REGION_INFO_FLAG_WRITE) || | |
3077 | vga_info.size < 0xbffff + 1) { | |
3078 | error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx", | |
3079 | (unsigned long)vga_info.flags, | |
3080 | (unsigned long)vga_info.size); | |
3081 | goto error; | |
3082 | } | |
3083 | ||
3084 | vdev->vga.fd_offset = vga_info.offset; | |
5546a621 | 3085 | vdev->vga.fd = vdev->vbasedev.fd; |
f15689c7 AW |
3086 | |
3087 | vdev->vga.region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; | |
3088 | vdev->vga.region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; | |
7076eabc | 3089 | QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_MEM].quirks); |
f15689c7 AW |
3090 | |
3091 | vdev->vga.region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; | |
3092 | vdev->vga.region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; | |
7076eabc | 3093 | QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_IO_LO].quirks); |
f15689c7 AW |
3094 | |
3095 | vdev->vga.region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; | |
3096 | vdev->vga.region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; | |
7076eabc | 3097 | QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks); |
f15689c7 AW |
3098 | |
3099 | vdev->has_vga = true; | |
3100 | } | |
47cbe50c | 3101 | |
7b4b0e9e VMP |
3102 | irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; |
3103 | ||
5546a621 | 3104 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); |
7b4b0e9e VMP |
3105 | if (ret) { |
3106 | /* This can fail for an old kernel or legacy PCI dev */ | |
d13dd2d7 | 3107 | trace_vfio_populate_device_get_irq_info_failure(); |
7b4b0e9e VMP |
3108 | ret = 0; |
3109 | } else if (irq_info.count == 1) { | |
3110 | vdev->pci_aer = true; | |
3111 | } else { | |
df92ee44 | 3112 | error_report("vfio: %s " |
8fbf47c3 | 3113 | "Could not enable error recovery for the device", |
df92ee44 | 3114 | vbasedev->name); |
7b4b0e9e | 3115 | } |
f15689c7 | 3116 | |
d13dd2d7 EA |
3117 | error: |
3118 | return ret; | |
3119 | } | |
3120 | ||
9ee27d73 | 3121 | static void vfio_put_device(VFIOPCIDevice *vdev) |
65501a74 | 3122 | { |
462037c9 | 3123 | g_free(vdev->vbasedev.name); |
65501a74 | 3124 | if (vdev->msix) { |
3a4dbe6a | 3125 | object_unparent(OBJECT(&vdev->msix->mmap_mem)); |
65501a74 AW |
3126 | g_free(vdev->msix); |
3127 | vdev->msix = NULL; | |
3128 | } | |
d13dd2d7 | 3129 | vfio_put_base_device(&vdev->vbasedev); |
65501a74 AW |
3130 | } |
3131 | ||
7b4b0e9e VMP |
3132 | static void vfio_err_notifier_handler(void *opaque) |
3133 | { | |
9ee27d73 | 3134 | VFIOPCIDevice *vdev = opaque; |
7b4b0e9e VMP |
3135 | |
3136 | if (!event_notifier_test_and_clear(&vdev->err_notifier)) { | |
3137 | return; | |
3138 | } | |
3139 | ||
3140 | /* | |
3141 | * TBD. Retrieve the error details and decide what action | |
3142 | * needs to be taken. One of the actions could be to pass | |
3143 | * the error to the guest and have the guest driver recover | |
3144 | * from the error. This requires that PCIe capabilities be | |
3145 | * exposed to the guest. For now, we just terminate the | |
3146 | * guest to contain the error. | |
3147 | */ | |
3148 | ||
8fbf47c3 AW |
3149 | error_report("%s(%04x:%02x:%02x.%x) Unrecoverable error detected. " |
3150 | "Please collect any data possible and then kill the guest", | |
3151 | __func__, vdev->host.domain, vdev->host.bus, | |
3152 | vdev->host.slot, vdev->host.function); | |
7b4b0e9e | 3153 | |
ba29776f | 3154 | vm_stop(RUN_STATE_INTERNAL_ERROR); |
7b4b0e9e VMP |
3155 | } |
3156 | ||
3157 | /* | |
3158 | * Registers error notifier for devices supporting error recovery. | |
3159 | * If we encounter a failure in this function, we report an error | |
3160 | * and continue after disabling error recovery support for the | |
3161 | * device. | |
3162 | */ | |
9ee27d73 | 3163 | static void vfio_register_err_notifier(VFIOPCIDevice *vdev) |
7b4b0e9e VMP |
3164 | { |
3165 | int ret; | |
3166 | int argsz; | |
3167 | struct vfio_irq_set *irq_set; | |
3168 | int32_t *pfd; | |
3169 | ||
3170 | if (!vdev->pci_aer) { | |
3171 | return; | |
3172 | } | |
3173 | ||
3174 | if (event_notifier_init(&vdev->err_notifier, 0)) { | |
8fbf47c3 | 3175 | error_report("vfio: Unable to init event notifier for error detection"); |
7b4b0e9e VMP |
3176 | vdev->pci_aer = false; |
3177 | return; | |
3178 | } | |
3179 | ||
3180 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
3181 | ||
3182 | irq_set = g_malloc0(argsz); | |
3183 | irq_set->argsz = argsz; | |
3184 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
3185 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
3186 | irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; | |
3187 | irq_set->start = 0; | |
3188 | irq_set->count = 1; | |
3189 | pfd = (int32_t *)&irq_set->data; | |
3190 | ||
3191 | *pfd = event_notifier_get_fd(&vdev->err_notifier); | |
3192 | qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); | |
3193 | ||
5546a621 | 3194 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
7b4b0e9e | 3195 | if (ret) { |
8fbf47c3 | 3196 | error_report("vfio: Failed to set up error notification"); |
7b4b0e9e VMP |
3197 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); |
3198 | event_notifier_cleanup(&vdev->err_notifier); | |
3199 | vdev->pci_aer = false; | |
3200 | } | |
3201 | g_free(irq_set); | |
3202 | } | |
3203 | ||
9ee27d73 | 3204 | static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) |
7b4b0e9e VMP |
3205 | { |
3206 | int argsz; | |
3207 | struct vfio_irq_set *irq_set; | |
3208 | int32_t *pfd; | |
3209 | int ret; | |
3210 | ||
3211 | if (!vdev->pci_aer) { | |
3212 | return; | |
3213 | } | |
3214 | ||
3215 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
3216 | ||
3217 | irq_set = g_malloc0(argsz); | |
3218 | irq_set->argsz = argsz; | |
3219 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
3220 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
3221 | irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; | |
3222 | irq_set->start = 0; | |
3223 | irq_set->count = 1; | |
3224 | pfd = (int32_t *)&irq_set->data; | |
3225 | *pfd = -1; | |
3226 | ||
5546a621 | 3227 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
7b4b0e9e | 3228 | if (ret) { |
8fbf47c3 | 3229 | error_report("vfio: Failed to de-assign error fd: %m"); |
7b4b0e9e VMP |
3230 | } |
3231 | g_free(irq_set); | |
3232 | qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), | |
3233 | NULL, NULL, vdev); | |
3234 | event_notifier_cleanup(&vdev->err_notifier); | |
3235 | } | |
3236 | ||
47cbe50c AW |
3237 | static void vfio_req_notifier_handler(void *opaque) |
3238 | { | |
3239 | VFIOPCIDevice *vdev = opaque; | |
3240 | ||
3241 | if (!event_notifier_test_and_clear(&vdev->req_notifier)) { | |
3242 | return; | |
3243 | } | |
3244 | ||
3245 | qdev_unplug(&vdev->pdev.qdev, NULL); | |
3246 | } | |
3247 | ||
3248 | static void vfio_register_req_notifier(VFIOPCIDevice *vdev) | |
3249 | { | |
3250 | struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), | |
3251 | .index = VFIO_PCI_REQ_IRQ_INDEX }; | |
3252 | int argsz; | |
3253 | struct vfio_irq_set *irq_set; | |
3254 | int32_t *pfd; | |
3255 | ||
3256 | if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { | |
3257 | return; | |
3258 | } | |
3259 | ||
3260 | if (ioctl(vdev->vbasedev.fd, | |
3261 | VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { | |
3262 | return; | |
3263 | } | |
3264 | ||
3265 | if (event_notifier_init(&vdev->req_notifier, 0)) { | |
3266 | error_report("vfio: Unable to init event notifier for device request"); | |
3267 | return; | |
3268 | } | |
3269 | ||
3270 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
3271 | ||
3272 | irq_set = g_malloc0(argsz); | |
3273 | irq_set->argsz = argsz; | |
3274 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
3275 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
3276 | irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; | |
3277 | irq_set->start = 0; | |
3278 | irq_set->count = 1; | |
3279 | pfd = (int32_t *)&irq_set->data; | |
3280 | ||
3281 | *pfd = event_notifier_get_fd(&vdev->req_notifier); | |
3282 | qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); | |
3283 | ||
3284 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { | |
3285 | error_report("vfio: Failed to set up device request notification"); | |
3286 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); | |
3287 | event_notifier_cleanup(&vdev->req_notifier); | |
3288 | } else { | |
3289 | vdev->req_enabled = true; | |
3290 | } | |
3291 | ||
3292 | g_free(irq_set); | |
3293 | } | |
3294 | ||
3295 | static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) | |
3296 | { | |
3297 | int argsz; | |
3298 | struct vfio_irq_set *irq_set; | |
3299 | int32_t *pfd; | |
3300 | ||
3301 | if (!vdev->req_enabled) { | |
3302 | return; | |
3303 | } | |
3304 | ||
3305 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
3306 | ||
3307 | irq_set = g_malloc0(argsz); | |
3308 | irq_set->argsz = argsz; | |
3309 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
3310 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
3311 | irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; | |
3312 | irq_set->start = 0; | |
3313 | irq_set->count = 1; | |
3314 | pfd = (int32_t *)&irq_set->data; | |
3315 | *pfd = -1; | |
3316 | ||
3317 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { | |
3318 | error_report("vfio: Failed to de-assign device request fd: %m"); | |
3319 | } | |
3320 | g_free(irq_set); | |
3321 | qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), | |
3322 | NULL, NULL, vdev); | |
3323 | event_notifier_cleanup(&vdev->req_notifier); | |
3324 | ||
3325 | vdev->req_enabled = false; | |
3326 | } | |
3327 | ||
65501a74 AW |
3328 | static int vfio_initfn(PCIDevice *pdev) |
3329 | { | |
b47d8efa EA |
3330 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
3331 | VFIODevice *vbasedev_iter; | |
65501a74 AW |
3332 | VFIOGroup *group; |
3333 | char path[PATH_MAX], iommu_group_path[PATH_MAX], *group_name; | |
3334 | ssize_t len; | |
3335 | struct stat st; | |
3336 | int groupid; | |
3337 | int ret; | |
3338 | ||
3339 | /* Check that the host device exists */ | |
3340 | snprintf(path, sizeof(path), | |
3341 | "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/", | |
3342 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
3343 | vdev->host.function); | |
3344 | if (stat(path, &st) < 0) { | |
312fd5f2 | 3345 | error_report("vfio: error: no such host device: %s", path); |
65501a74 AW |
3346 | return -errno; |
3347 | } | |
3348 | ||
b47d8efa EA |
3349 | vdev->vbasedev.ops = &vfio_pci_ops; |
3350 | ||
462037c9 EA |
3351 | vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; |
3352 | vdev->vbasedev.name = g_strdup_printf("%04x:%02x:%02x.%01x", | |
3353 | vdev->host.domain, vdev->host.bus, | |
3354 | vdev->host.slot, vdev->host.function); | |
3355 | ||
65501a74 AW |
3356 | strncat(path, "iommu_group", sizeof(path) - strlen(path) - 1); |
3357 | ||
13665a2d MA |
3358 | len = readlink(path, iommu_group_path, sizeof(path)); |
3359 | if (len <= 0 || len >= sizeof(path)) { | |
312fd5f2 | 3360 | error_report("vfio: error no iommu_group for device"); |
c6d231e2 | 3361 | return len < 0 ? -errno : -ENAMETOOLONG; |
65501a74 AW |
3362 | } |
3363 | ||
3364 | iommu_group_path[len] = 0; | |
3365 | group_name = basename(iommu_group_path); | |
3366 | ||
3367 | if (sscanf(group_name, "%d", &groupid) != 1) { | |
312fd5f2 | 3368 | error_report("vfio: error reading %s: %m", path); |
65501a74 AW |
3369 | return -errno; |
3370 | } | |
3371 | ||
df92ee44 | 3372 | trace_vfio_initfn(vdev->vbasedev.name, groupid); |
65501a74 | 3373 | |
0688448b | 3374 | group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev)); |
65501a74 | 3375 | if (!group) { |
312fd5f2 | 3376 | error_report("vfio: failed to get group %d", groupid); |
65501a74 AW |
3377 | return -ENOENT; |
3378 | } | |
3379 | ||
3380 | snprintf(path, sizeof(path), "%04x:%02x:%02x.%01x", | |
3381 | vdev->host.domain, vdev->host.bus, vdev->host.slot, | |
3382 | vdev->host.function); | |
3383 | ||
b47d8efa EA |
3384 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
3385 | if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { | |
312fd5f2 | 3386 | error_report("vfio: error: device %s is already attached", path); |
65501a74 AW |
3387 | vfio_put_group(group); |
3388 | return -EBUSY; | |
3389 | } | |
3390 | } | |
3391 | ||
d13dd2d7 | 3392 | ret = vfio_get_device(group, path, &vdev->vbasedev); |
65501a74 | 3393 | if (ret) { |
312fd5f2 | 3394 | error_report("vfio: failed to get device %s", path); |
65501a74 AW |
3395 | vfio_put_group(group); |
3396 | return ret; | |
3397 | } | |
3398 | ||
217e9fdc PB |
3399 | ret = vfio_populate_device(vdev); |
3400 | if (ret) { | |
77a10d04 | 3401 | return ret; |
217e9fdc PB |
3402 | } |
3403 | ||
65501a74 | 3404 | /* Get a copy of config space */ |
5546a621 | 3405 | ret = pread(vdev->vbasedev.fd, vdev->pdev.config, |
65501a74 AW |
3406 | MIN(pci_config_size(&vdev->pdev), vdev->config_size), |
3407 | vdev->config_offset); | |
3408 | if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { | |
3409 | ret = ret < 0 ? -errno : -EFAULT; | |
312fd5f2 | 3410 | error_report("vfio: Failed to read device config space"); |
77a10d04 | 3411 | return ret; |
65501a74 AW |
3412 | } |
3413 | ||
4b5d5e87 AW |
3414 | /* vfio emulates a lot for us, but some bits need extra love */ |
3415 | vdev->emulated_config_bits = g_malloc0(vdev->config_size); | |
3416 | ||
3417 | /* QEMU can choose to expose the ROM or not */ | |
3418 | memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); | |
3419 | ||
3420 | /* QEMU can change multi-function devices to single function, or reverse */ | |
3421 | vdev->emulated_config_bits[PCI_HEADER_TYPE] = | |
3422 | PCI_HEADER_TYPE_MULTI_FUNCTION; | |
3423 | ||
187d6232 AW |
3424 | /* Restore or clear multifunction, this is always controlled by QEMU */ |
3425 | if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
3426 | vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
3427 | } else { | |
3428 | vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
3429 | } | |
3430 | ||
65501a74 AW |
3431 | /* |
3432 | * Clear host resource mapping info. If we choose not to register a | |
3433 | * BAR, such as might be the case with the option ROM, we can get | |
3434 | * confusing, unwritable, residual addresses from the host here. | |
3435 | */ | |
3436 | memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); | |
3437 | memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); | |
3438 | ||
6f864e6e | 3439 | vfio_pci_size_rom(vdev); |
65501a74 AW |
3440 | |
3441 | ret = vfio_early_setup_msix(vdev); | |
3442 | if (ret) { | |
77a10d04 | 3443 | return ret; |
65501a74 AW |
3444 | } |
3445 | ||
3446 | vfio_map_bars(vdev); | |
3447 | ||
3448 | ret = vfio_add_capabilities(vdev); | |
3449 | if (ret) { | |
3450 | goto out_teardown; | |
3451 | } | |
3452 | ||
4b5d5e87 AW |
3453 | /* QEMU emulates all of MSI & MSIX */ |
3454 | if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { | |
3455 | memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, | |
3456 | MSIX_CAP_LENGTH); | |
3457 | } | |
3458 | ||
3459 | if (pdev->cap_present & QEMU_PCI_CAP_MSI) { | |
3460 | memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, | |
3461 | vdev->msi_cap_size); | |
3462 | } | |
3463 | ||
65501a74 | 3464 | if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { |
bc72ad67 | 3465 | vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, |
ea486926 | 3466 | vfio_intx_mmap_enable, vdev); |
e1d1e586 | 3467 | pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_update_irq); |
65501a74 AW |
3468 | ret = vfio_enable_intx(vdev); |
3469 | if (ret) { | |
3470 | goto out_teardown; | |
3471 | } | |
3472 | } | |
3473 | ||
7b4b0e9e | 3474 | vfio_register_err_notifier(vdev); |
47cbe50c | 3475 | vfio_register_req_notifier(vdev); |
c29029dd | 3476 | |
65501a74 AW |
3477 | return 0; |
3478 | ||
3479 | out_teardown: | |
3480 | pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); | |
3481 | vfio_teardown_msi(vdev); | |
ba5e6bfa | 3482 | vfio_unregister_bars(vdev); |
77a10d04 PB |
3483 | return ret; |
3484 | } | |
3485 | ||
3486 | static void vfio_instance_finalize(Object *obj) | |
3487 | { | |
3488 | PCIDevice *pci_dev = PCI_DEVICE(obj); | |
3489 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pci_dev); | |
3490 | VFIOGroup *group = vdev->vbasedev.group; | |
3491 | ||
ba5e6bfa | 3492 | vfio_unmap_bars(vdev); |
4b5d5e87 | 3493 | g_free(vdev->emulated_config_bits); |
77a10d04 | 3494 | g_free(vdev->rom); |
65501a74 AW |
3495 | vfio_put_device(vdev); |
3496 | vfio_put_group(group); | |
65501a74 AW |
3497 | } |
3498 | ||
3499 | static void vfio_exitfn(PCIDevice *pdev) | |
3500 | { | |
9ee27d73 | 3501 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 3502 | |
47cbe50c | 3503 | vfio_unregister_req_notifier(vdev); |
7b4b0e9e | 3504 | vfio_unregister_err_notifier(vdev); |
65501a74 AW |
3505 | pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); |
3506 | vfio_disable_interrupts(vdev); | |
ea486926 | 3507 | if (vdev->intx.mmap_timer) { |
bc72ad67 | 3508 | timer_free(vdev->intx.mmap_timer); |
ea486926 | 3509 | } |
65501a74 | 3510 | vfio_teardown_msi(vdev); |
ba5e6bfa | 3511 | vfio_unregister_bars(vdev); |
65501a74 AW |
3512 | } |
3513 | ||
3514 | static void vfio_pci_reset(DeviceState *dev) | |
3515 | { | |
3516 | PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev); | |
9ee27d73 | 3517 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 3518 | |
df92ee44 | 3519 | trace_vfio_pci_reset(vdev->vbasedev.name); |
5834a83f | 3520 | |
f16f39c3 | 3521 | vfio_pci_pre_reset(vdev); |
ba661818 | 3522 | |
b47d8efa EA |
3523 | if (vdev->vbasedev.reset_works && |
3524 | (vdev->has_flr || !vdev->has_pm_reset) && | |
5546a621 | 3525 | !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { |
df92ee44 | 3526 | trace_vfio_pci_reset_flr(vdev->vbasedev.name); |
f16f39c3 | 3527 | goto post_reset; |
ba661818 AW |
3528 | } |
3529 | ||
f16f39c3 AW |
3530 | /* See if we can do our own bus reset */ |
3531 | if (!vfio_pci_hot_reset_one(vdev)) { | |
3532 | goto post_reset; | |
3533 | } | |
5834a83f | 3534 | |
f16f39c3 | 3535 | /* If nothing else works and the device supports PM reset, use it */ |
b47d8efa | 3536 | if (vdev->vbasedev.reset_works && vdev->has_pm_reset && |
5546a621 | 3537 | !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { |
df92ee44 | 3538 | trace_vfio_pci_reset_pm(vdev->vbasedev.name); |
f16f39c3 | 3539 | goto post_reset; |
65501a74 | 3540 | } |
5834a83f | 3541 | |
f16f39c3 AW |
3542 | post_reset: |
3543 | vfio_pci_post_reset(vdev); | |
65501a74 AW |
3544 | } |
3545 | ||
abc5b3bf GA |
3546 | static void vfio_instance_init(Object *obj) |
3547 | { | |
3548 | PCIDevice *pci_dev = PCI_DEVICE(obj); | |
9ee27d73 | 3549 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, PCI_DEVICE(obj)); |
abc5b3bf GA |
3550 | |
3551 | device_add_bootindex_property(obj, &vdev->bootindex, | |
3552 | "bootindex", NULL, | |
3553 | &pci_dev->qdev, NULL); | |
3554 | } | |
3555 | ||
65501a74 | 3556 | static Property vfio_pci_dev_properties[] = { |
9ee27d73 EA |
3557 | DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), |
3558 | DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, | |
ea486926 | 3559 | intx.mmap_timeout, 1100), |
9ee27d73 | 3560 | DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, |
f15689c7 | 3561 | VFIO_FEATURE_ENABLE_VGA_BIT, false), |
47cbe50c AW |
3562 | DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, |
3563 | VFIO_FEATURE_ENABLE_REQ_BIT, true), | |
9ee27d73 | 3564 | DEFINE_PROP_INT32("bootindex", VFIOPCIDevice, bootindex, -1), |
6ee47c90 | 3565 | DEFINE_PROP_BOOL("x-mmap", VFIOPCIDevice, vbasedev.allow_mmap, true), |
65501a74 AW |
3566 | /* |
3567 | * TODO - support passed fds... is this necessary? | |
9ee27d73 EA |
3568 | * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), |
3569 | * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), | |
65501a74 AW |
3570 | */ |
3571 | DEFINE_PROP_END_OF_LIST(), | |
3572 | }; | |
3573 | ||
d9f0e638 AW |
3574 | static const VMStateDescription vfio_pci_vmstate = { |
3575 | .name = "vfio-pci", | |
3576 | .unmigratable = 1, | |
3577 | }; | |
65501a74 AW |
3578 | |
3579 | static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) | |
3580 | { | |
3581 | DeviceClass *dc = DEVICE_CLASS(klass); | |
3582 | PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); | |
3583 | ||
3584 | dc->reset = vfio_pci_reset; | |
3585 | dc->props = vfio_pci_dev_properties; | |
d9f0e638 AW |
3586 | dc->vmsd = &vfio_pci_vmstate; |
3587 | dc->desc = "VFIO-based PCI device assignment"; | |
125ee0ed | 3588 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
65501a74 AW |
3589 | pdc->init = vfio_initfn; |
3590 | pdc->exit = vfio_exitfn; | |
3591 | pdc->config_read = vfio_pci_read_config; | |
3592 | pdc->config_write = vfio_pci_write_config; | |
6a659bbf | 3593 | pdc->is_express = 1; /* We might be */ |
65501a74 AW |
3594 | } |
3595 | ||
3596 | static const TypeInfo vfio_pci_dev_info = { | |
3597 | .name = "vfio-pci", | |
3598 | .parent = TYPE_PCI_DEVICE, | |
9ee27d73 | 3599 | .instance_size = sizeof(VFIOPCIDevice), |
65501a74 | 3600 | .class_init = vfio_pci_dev_class_init, |
abc5b3bf | 3601 | .instance_init = vfio_instance_init, |
77a10d04 | 3602 | .instance_finalize = vfio_instance_finalize, |
65501a74 AW |
3603 | }; |
3604 | ||
3605 | static void register_vfio_pci_dev_type(void) | |
3606 | { | |
3607 | type_register_static(&vfio_pci_dev_info); | |
3608 | } | |
3609 | ||
3610 | type_init(register_vfio_pci_dev_type) |