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Commit | Line | Data |
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65501a74 AW |
1 | /* |
2 | * vfio based device assignment support | |
3 | * | |
4 | * Copyright Red Hat, Inc. 2012 | |
5 | * | |
6 | * Authors: | |
7 | * Alex Williamson <alex.williamson@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
10 | * the COPYING file in the top-level directory. | |
11 | * | |
12 | * Based on qemu-kvm device-assignment: | |
13 | * Adapted for KVM by Qumranet. | |
14 | * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) | |
15 | * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) | |
16 | * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) | |
17 | * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) | |
18 | * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) | |
19 | */ | |
20 | ||
c6eacb1a | 21 | #include "qemu/osdep.h" |
6dcfdbad | 22 | #include <linux/vfio.h> |
65501a74 | 23 | #include <sys/ioctl.h> |
65501a74 | 24 | |
83c9f4ca PB |
25 | #include "hw/pci/msi.h" |
26 | #include "hw/pci/msix.h" | |
0282abf0 | 27 | #include "hw/pci/pci_bridge.h" |
1de7afc9 | 28 | #include "qemu/error-report.h" |
1de7afc9 | 29 | #include "qemu/range.h" |
6dcfdbad AW |
30 | #include "sysemu/kvm.h" |
31 | #include "sysemu/sysemu.h" | |
78f33d2b | 32 | #include "pci.h" |
385f57cf | 33 | #include "trace.h" |
4b943029 | 34 | |
65501a74 AW |
35 | #define MSIX_CAP_LENGTH 12 |
36 | ||
9ee27d73 | 37 | static void vfio_disable_interrupts(VFIOPCIDevice *vdev); |
9ee27d73 | 38 | static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); |
65501a74 | 39 | |
ea486926 AW |
40 | /* |
41 | * Disabling BAR mmaping can be slow, but toggling it around INTx can | |
42 | * also be a huge overhead. We try to get the best of both worlds by | |
43 | * waiting until an interrupt to disable mmaps (subsequent transitions | |
44 | * to the same state are effectively no overhead). If the interrupt has | |
45 | * been serviced and the time gap is long enough, we re-enable mmaps for | |
46 | * performance. This works well for things like graphics cards, which | |
47 | * may not use their interrupt at all and are penalized to an unusable | |
48 | * level by read/write BAR traps. Other devices, like NICs, have more | |
49 | * regular interrupts and see much better latency by staying in non-mmap | |
50 | * mode. We therefore set the default mmap_timeout such that a ping | |
51 | * is just enough to keep the mmap disabled. Users can experiment with | |
52 | * other options with the x-intx-mmap-timeout-ms parameter (a value of | |
53 | * zero disables the timer). | |
54 | */ | |
55 | static void vfio_intx_mmap_enable(void *opaque) | |
56 | { | |
9ee27d73 | 57 | VFIOPCIDevice *vdev = opaque; |
ea486926 AW |
58 | |
59 | if (vdev->intx.pending) { | |
bc72ad67 AB |
60 | timer_mod(vdev->intx.mmap_timer, |
61 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); | |
ea486926 AW |
62 | return; |
63 | } | |
64 | ||
65 | vfio_mmap_set_enabled(vdev, true); | |
66 | } | |
67 | ||
65501a74 AW |
68 | static void vfio_intx_interrupt(void *opaque) |
69 | { | |
9ee27d73 | 70 | VFIOPCIDevice *vdev = opaque; |
65501a74 AW |
71 | |
72 | if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { | |
73 | return; | |
74 | } | |
75 | ||
df92ee44 | 76 | trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); |
65501a74 AW |
77 | |
78 | vdev->intx.pending = true; | |
68919cac | 79 | pci_irq_assert(&vdev->pdev); |
ea486926 AW |
80 | vfio_mmap_set_enabled(vdev, false); |
81 | if (vdev->intx.mmap_timeout) { | |
bc72ad67 AB |
82 | timer_mod(vdev->intx.mmap_timer, |
83 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); | |
ea486926 | 84 | } |
65501a74 AW |
85 | } |
86 | ||
870cb6f1 | 87 | static void vfio_intx_eoi(VFIODevice *vbasedev) |
65501a74 | 88 | { |
a664477d EA |
89 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); |
90 | ||
65501a74 AW |
91 | if (!vdev->intx.pending) { |
92 | return; | |
93 | } | |
94 | ||
870cb6f1 | 95 | trace_vfio_intx_eoi(vbasedev->name); |
65501a74 AW |
96 | |
97 | vdev->intx.pending = false; | |
68919cac | 98 | pci_irq_deassert(&vdev->pdev); |
a664477d | 99 | vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
65501a74 AW |
100 | } |
101 | ||
870cb6f1 | 102 | static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev) |
e1d1e586 AW |
103 | { |
104 | #ifdef CONFIG_KVM | |
105 | struct kvm_irqfd irqfd = { | |
106 | .fd = event_notifier_get_fd(&vdev->intx.interrupt), | |
107 | .gsi = vdev->intx.route.irq, | |
108 | .flags = KVM_IRQFD_FLAG_RESAMPLE, | |
109 | }; | |
110 | struct vfio_irq_set *irq_set; | |
111 | int ret, argsz; | |
112 | int32_t *pfd; | |
113 | ||
46746dba | 114 | if (vdev->no_kvm_intx || !kvm_irqfds_enabled() || |
e1d1e586 | 115 | vdev->intx.route.mode != PCI_INTX_ENABLED || |
9fc0e2d8 | 116 | !kvm_resamplefds_enabled()) { |
e1d1e586 AW |
117 | return; |
118 | } | |
119 | ||
120 | /* Get to a known interrupt state */ | |
121 | qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); | |
5546a621 | 122 | vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 123 | vdev->intx.pending = false; |
68919cac | 124 | pci_irq_deassert(&vdev->pdev); |
e1d1e586 AW |
125 | |
126 | /* Get an eventfd for resample/unmask */ | |
127 | if (event_notifier_init(&vdev->intx.unmask, 0)) { | |
312fd5f2 | 128 | error_report("vfio: Error: event_notifier_init failed eoi"); |
e1d1e586 AW |
129 | goto fail; |
130 | } | |
131 | ||
132 | /* KVM triggers it, VFIO listens for it */ | |
133 | irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); | |
134 | ||
135 | if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { | |
312fd5f2 | 136 | error_report("vfio: Error: Failed to setup resample irqfd: %m"); |
e1d1e586 AW |
137 | goto fail_irqfd; |
138 | } | |
139 | ||
140 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
141 | ||
142 | irq_set = g_malloc0(argsz); | |
143 | irq_set->argsz = argsz; | |
144 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; | |
145 | irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; | |
146 | irq_set->start = 0; | |
147 | irq_set->count = 1; | |
148 | pfd = (int32_t *)&irq_set->data; | |
149 | ||
150 | *pfd = irqfd.resamplefd; | |
151 | ||
5546a621 | 152 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
e1d1e586 AW |
153 | g_free(irq_set); |
154 | if (ret) { | |
312fd5f2 | 155 | error_report("vfio: Error: Failed to setup INTx unmask fd: %m"); |
e1d1e586 AW |
156 | goto fail_vfio; |
157 | } | |
158 | ||
159 | /* Let'em rip */ | |
5546a621 | 160 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 AW |
161 | |
162 | vdev->intx.kvm_accel = true; | |
163 | ||
870cb6f1 | 164 | trace_vfio_intx_enable_kvm(vdev->vbasedev.name); |
e1d1e586 AW |
165 | |
166 | return; | |
167 | ||
168 | fail_vfio: | |
169 | irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; | |
170 | kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); | |
171 | fail_irqfd: | |
172 | event_notifier_cleanup(&vdev->intx.unmask); | |
173 | fail: | |
174 | qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); | |
5546a621 | 175 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 AW |
176 | #endif |
177 | } | |
178 | ||
870cb6f1 | 179 | static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev) |
e1d1e586 AW |
180 | { |
181 | #ifdef CONFIG_KVM | |
182 | struct kvm_irqfd irqfd = { | |
183 | .fd = event_notifier_get_fd(&vdev->intx.interrupt), | |
184 | .gsi = vdev->intx.route.irq, | |
185 | .flags = KVM_IRQFD_FLAG_DEASSIGN, | |
186 | }; | |
187 | ||
188 | if (!vdev->intx.kvm_accel) { | |
189 | return; | |
190 | } | |
191 | ||
192 | /* | |
193 | * Get to a known state, hardware masked, QEMU ready to accept new | |
194 | * interrupts, QEMU IRQ de-asserted. | |
195 | */ | |
5546a621 | 196 | vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 197 | vdev->intx.pending = false; |
68919cac | 198 | pci_irq_deassert(&vdev->pdev); |
e1d1e586 AW |
199 | |
200 | /* Tell KVM to stop listening for an INTx irqfd */ | |
201 | if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { | |
312fd5f2 | 202 | error_report("vfio: Error: Failed to disable INTx irqfd: %m"); |
e1d1e586 AW |
203 | } |
204 | ||
205 | /* We only need to close the eventfd for VFIO to cleanup the kernel side */ | |
206 | event_notifier_cleanup(&vdev->intx.unmask); | |
207 | ||
208 | /* QEMU starts listening for interrupt events. */ | |
209 | qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); | |
210 | ||
211 | vdev->intx.kvm_accel = false; | |
212 | ||
213 | /* If we've missed an event, let it re-fire through QEMU */ | |
5546a621 | 214 | vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
e1d1e586 | 215 | |
870cb6f1 | 216 | trace_vfio_intx_disable_kvm(vdev->vbasedev.name); |
e1d1e586 AW |
217 | #endif |
218 | } | |
219 | ||
870cb6f1 | 220 | static void vfio_intx_update(PCIDevice *pdev) |
e1d1e586 | 221 | { |
9ee27d73 | 222 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
e1d1e586 AW |
223 | PCIINTxRoute route; |
224 | ||
225 | if (vdev->interrupt != VFIO_INT_INTx) { | |
226 | return; | |
227 | } | |
228 | ||
229 | route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); | |
230 | ||
231 | if (!pci_intx_route_changed(&vdev->intx.route, &route)) { | |
232 | return; /* Nothing changed */ | |
233 | } | |
234 | ||
870cb6f1 AW |
235 | trace_vfio_intx_update(vdev->vbasedev.name, |
236 | vdev->intx.route.irq, route.irq); | |
e1d1e586 | 237 | |
870cb6f1 | 238 | vfio_intx_disable_kvm(vdev); |
e1d1e586 AW |
239 | |
240 | vdev->intx.route = route; | |
241 | ||
242 | if (route.mode != PCI_INTX_ENABLED) { | |
243 | return; | |
244 | } | |
245 | ||
870cb6f1 | 246 | vfio_intx_enable_kvm(vdev); |
e1d1e586 AW |
247 | |
248 | /* Re-enable the interrupt in cased we missed an EOI */ | |
870cb6f1 | 249 | vfio_intx_eoi(&vdev->vbasedev); |
e1d1e586 AW |
250 | } |
251 | ||
870cb6f1 | 252 | static int vfio_intx_enable(VFIOPCIDevice *vdev) |
65501a74 | 253 | { |
65501a74 | 254 | uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); |
1a403133 AW |
255 | int ret, argsz; |
256 | struct vfio_irq_set *irq_set; | |
257 | int32_t *pfd; | |
65501a74 | 258 | |
ea486926 | 259 | if (!pin) { |
65501a74 AW |
260 | return 0; |
261 | } | |
262 | ||
263 | vfio_disable_interrupts(vdev); | |
264 | ||
265 | vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ | |
68919cac | 266 | pci_config_set_interrupt_pin(vdev->pdev.config, pin); |
e1d1e586 AW |
267 | |
268 | #ifdef CONFIG_KVM | |
269 | /* | |
270 | * Only conditional to avoid generating error messages on platforms | |
271 | * where we won't actually use the result anyway. | |
272 | */ | |
9fc0e2d8 | 273 | if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { |
e1d1e586 AW |
274 | vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, |
275 | vdev->intx.pin); | |
276 | } | |
277 | #endif | |
278 | ||
65501a74 AW |
279 | ret = event_notifier_init(&vdev->intx.interrupt, 0); |
280 | if (ret) { | |
312fd5f2 | 281 | error_report("vfio: Error: event_notifier_init failed"); |
65501a74 AW |
282 | return ret; |
283 | } | |
284 | ||
1a403133 AW |
285 | argsz = sizeof(*irq_set) + sizeof(*pfd); |
286 | ||
287 | irq_set = g_malloc0(argsz); | |
288 | irq_set->argsz = argsz; | |
289 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; | |
290 | irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; | |
291 | irq_set->start = 0; | |
292 | irq_set->count = 1; | |
293 | pfd = (int32_t *)&irq_set->data; | |
294 | ||
295 | *pfd = event_notifier_get_fd(&vdev->intx.interrupt); | |
296 | qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); | |
65501a74 | 297 | |
5546a621 | 298 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
1a403133 AW |
299 | g_free(irq_set); |
300 | if (ret) { | |
312fd5f2 | 301 | error_report("vfio: Error: Failed to setup INTx fd: %m"); |
1a403133 | 302 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); |
ce59af2d | 303 | event_notifier_cleanup(&vdev->intx.interrupt); |
65501a74 AW |
304 | return -errno; |
305 | } | |
306 | ||
870cb6f1 | 307 | vfio_intx_enable_kvm(vdev); |
e1d1e586 | 308 | |
65501a74 AW |
309 | vdev->interrupt = VFIO_INT_INTx; |
310 | ||
870cb6f1 | 311 | trace_vfio_intx_enable(vdev->vbasedev.name); |
65501a74 AW |
312 | |
313 | return 0; | |
314 | } | |
315 | ||
870cb6f1 | 316 | static void vfio_intx_disable(VFIOPCIDevice *vdev) |
65501a74 AW |
317 | { |
318 | int fd; | |
319 | ||
bc72ad67 | 320 | timer_del(vdev->intx.mmap_timer); |
870cb6f1 | 321 | vfio_intx_disable_kvm(vdev); |
5546a621 | 322 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); |
65501a74 | 323 | vdev->intx.pending = false; |
68919cac | 324 | pci_irq_deassert(&vdev->pdev); |
65501a74 AW |
325 | vfio_mmap_set_enabled(vdev, true); |
326 | ||
327 | fd = event_notifier_get_fd(&vdev->intx.interrupt); | |
328 | qemu_set_fd_handler(fd, NULL, NULL, vdev); | |
329 | event_notifier_cleanup(&vdev->intx.interrupt); | |
330 | ||
331 | vdev->interrupt = VFIO_INT_NONE; | |
332 | ||
870cb6f1 | 333 | trace_vfio_intx_disable(vdev->vbasedev.name); |
65501a74 AW |
334 | } |
335 | ||
336 | /* | |
337 | * MSI/X | |
338 | */ | |
339 | static void vfio_msi_interrupt(void *opaque) | |
340 | { | |
341 | VFIOMSIVector *vector = opaque; | |
9ee27d73 | 342 | VFIOPCIDevice *vdev = vector->vdev; |
0de70dc7 AW |
343 | MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector); |
344 | void (*notify)(PCIDevice *dev, unsigned vector); | |
345 | MSIMessage msg; | |
65501a74 AW |
346 | int nr = vector - vdev->msi_vectors; |
347 | ||
348 | if (!event_notifier_test_and_clear(&vector->interrupt)) { | |
349 | return; | |
350 | } | |
351 | ||
b3ebc10c | 352 | if (vdev->interrupt == VFIO_INT_MSIX) { |
0de70dc7 AW |
353 | get_msg = msix_get_message; |
354 | notify = msix_notify; | |
95239e16 AW |
355 | |
356 | /* A masked vector firing needs to use the PBA, enable it */ | |
357 | if (msix_is_masked(&vdev->pdev, nr)) { | |
358 | set_bit(nr, vdev->msix->pending); | |
359 | memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true); | |
360 | trace_vfio_msix_pba_enable(vdev->vbasedev.name); | |
361 | } | |
9035f8c0 | 362 | } else if (vdev->interrupt == VFIO_INT_MSI) { |
0de70dc7 AW |
363 | get_msg = msi_get_message; |
364 | notify = msi_notify; | |
b3ebc10c AW |
365 | } else { |
366 | abort(); | |
367 | } | |
368 | ||
0de70dc7 | 369 | msg = get_msg(&vdev->pdev, nr); |
bc5baffa | 370 | trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); |
0de70dc7 | 371 | notify(&vdev->pdev, nr); |
65501a74 AW |
372 | } |
373 | ||
9ee27d73 | 374 | static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) |
65501a74 AW |
375 | { |
376 | struct vfio_irq_set *irq_set; | |
377 | int ret = 0, i, argsz; | |
378 | int32_t *fds; | |
379 | ||
380 | argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); | |
381 | ||
382 | irq_set = g_malloc0(argsz); | |
383 | irq_set->argsz = argsz; | |
384 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; | |
385 | irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; | |
386 | irq_set->start = 0; | |
387 | irq_set->count = vdev->nr_vectors; | |
388 | fds = (int32_t *)&irq_set->data; | |
389 | ||
390 | for (i = 0; i < vdev->nr_vectors; i++) { | |
c048be5c AW |
391 | int fd = -1; |
392 | ||
393 | /* | |
394 | * MSI vs MSI-X - The guest has direct access to MSI mask and pending | |
395 | * bits, therefore we always use the KVM signaling path when setup. | |
396 | * MSI-X mask and pending bits are emulated, so we want to use the | |
397 | * KVM signaling path only when configured and unmasked. | |
398 | */ | |
399 | if (vdev->msi_vectors[i].use) { | |
400 | if (vdev->msi_vectors[i].virq < 0 || | |
401 | (msix && msix_is_masked(&vdev->pdev, i))) { | |
402 | fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); | |
403 | } else { | |
404 | fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); | |
405 | } | |
65501a74 | 406 | } |
c048be5c AW |
407 | |
408 | fds[i] = fd; | |
65501a74 AW |
409 | } |
410 | ||
5546a621 | 411 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
65501a74 AW |
412 | |
413 | g_free(irq_set); | |
414 | ||
65501a74 AW |
415 | return ret; |
416 | } | |
417 | ||
46746dba AW |
418 | static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, |
419 | MSIMessage *msg, bool msix) | |
f4d45d47 AW |
420 | { |
421 | int virq; | |
422 | ||
46746dba | 423 | if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi) || !msg) { |
f4d45d47 AW |
424 | return; |
425 | } | |
426 | ||
427 | if (event_notifier_init(&vector->kvm_interrupt, 0)) { | |
428 | return; | |
429 | } | |
430 | ||
dc9f06ca | 431 | virq = kvm_irqchip_add_msi_route(kvm_state, *msg, &vdev->pdev); |
f4d45d47 AW |
432 | if (virq < 0) { |
433 | event_notifier_cleanup(&vector->kvm_interrupt); | |
434 | return; | |
435 | } | |
436 | ||
1c9b71a7 | 437 | if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, |
f4d45d47 AW |
438 | NULL, virq) < 0) { |
439 | kvm_irqchip_release_virq(kvm_state, virq); | |
440 | event_notifier_cleanup(&vector->kvm_interrupt); | |
441 | return; | |
442 | } | |
443 | ||
f4d45d47 AW |
444 | vector->virq = virq; |
445 | } | |
446 | ||
447 | static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) | |
448 | { | |
1c9b71a7 EA |
449 | kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, |
450 | vector->virq); | |
f4d45d47 AW |
451 | kvm_irqchip_release_virq(kvm_state, vector->virq); |
452 | vector->virq = -1; | |
453 | event_notifier_cleanup(&vector->kvm_interrupt); | |
454 | } | |
455 | ||
dc9f06ca PF |
456 | static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg, |
457 | PCIDevice *pdev) | |
f4d45d47 | 458 | { |
dc9f06ca | 459 | kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev); |
f4d45d47 AW |
460 | } |
461 | ||
b0223e29 AW |
462 | static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, |
463 | MSIMessage *msg, IOHandler *handler) | |
65501a74 | 464 | { |
9ee27d73 | 465 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 AW |
466 | VFIOMSIVector *vector; |
467 | int ret; | |
468 | ||
df92ee44 | 469 | trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); |
65501a74 | 470 | |
65501a74 | 471 | vector = &vdev->msi_vectors[nr]; |
65501a74 | 472 | |
f4d45d47 AW |
473 | if (!vector->use) { |
474 | vector->vdev = vdev; | |
475 | vector->virq = -1; | |
476 | if (event_notifier_init(&vector->interrupt, 0)) { | |
477 | error_report("vfio: Error: event_notifier_init failed"); | |
478 | } | |
479 | vector->use = true; | |
480 | msix_vector_use(pdev, nr); | |
65501a74 AW |
481 | } |
482 | ||
f4d45d47 AW |
483 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
484 | handler, NULL, vector); | |
485 | ||
65501a74 AW |
486 | /* |
487 | * Attempt to enable route through KVM irqchip, | |
488 | * default to userspace handling if unavailable. | |
489 | */ | |
f4d45d47 AW |
490 | if (vector->virq >= 0) { |
491 | if (!msg) { | |
492 | vfio_remove_kvm_msi_virq(vector); | |
493 | } else { | |
dc9f06ca | 494 | vfio_update_kvm_msi_virq(vector, *msg, pdev); |
65501a74 | 495 | } |
f4d45d47 | 496 | } else { |
46746dba | 497 | vfio_add_kvm_msi_virq(vdev, vector, msg, true); |
65501a74 AW |
498 | } |
499 | ||
500 | /* | |
501 | * We don't want to have the host allocate all possible MSI vectors | |
502 | * for a device if they're not in use, so we shutdown and incrementally | |
503 | * increase them as needed. | |
504 | */ | |
505 | if (vdev->nr_vectors < nr + 1) { | |
5546a621 | 506 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); |
65501a74 AW |
507 | vdev->nr_vectors = nr + 1; |
508 | ret = vfio_enable_vectors(vdev, true); | |
509 | if (ret) { | |
312fd5f2 | 510 | error_report("vfio: failed to enable vectors, %d", ret); |
65501a74 | 511 | } |
65501a74 | 512 | } else { |
1a403133 AW |
513 | int argsz; |
514 | struct vfio_irq_set *irq_set; | |
515 | int32_t *pfd; | |
516 | ||
517 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
518 | ||
519 | irq_set = g_malloc0(argsz); | |
520 | irq_set->argsz = argsz; | |
521 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
522 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
523 | irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; | |
524 | irq_set->start = nr; | |
525 | irq_set->count = 1; | |
526 | pfd = (int32_t *)&irq_set->data; | |
527 | ||
f4d45d47 AW |
528 | if (vector->virq >= 0) { |
529 | *pfd = event_notifier_get_fd(&vector->kvm_interrupt); | |
530 | } else { | |
531 | *pfd = event_notifier_get_fd(&vector->interrupt); | |
532 | } | |
1a403133 | 533 | |
5546a621 | 534 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
1a403133 | 535 | g_free(irq_set); |
65501a74 | 536 | if (ret) { |
312fd5f2 | 537 | error_report("vfio: failed to modify vector, %d", ret); |
65501a74 | 538 | } |
65501a74 AW |
539 | } |
540 | ||
95239e16 AW |
541 | /* Disable PBA emulation when nothing more is pending. */ |
542 | clear_bit(nr, vdev->msix->pending); | |
543 | if (find_first_bit(vdev->msix->pending, | |
544 | vdev->nr_vectors) == vdev->nr_vectors) { | |
545 | memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); | |
546 | trace_vfio_msix_pba_disable(vdev->vbasedev.name); | |
547 | } | |
548 | ||
65501a74 AW |
549 | return 0; |
550 | } | |
551 | ||
b0223e29 AW |
552 | static int vfio_msix_vector_use(PCIDevice *pdev, |
553 | unsigned int nr, MSIMessage msg) | |
554 | { | |
555 | return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); | |
556 | } | |
557 | ||
65501a74 AW |
558 | static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) |
559 | { | |
9ee27d73 | 560 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 561 | VFIOMSIVector *vector = &vdev->msi_vectors[nr]; |
65501a74 | 562 | |
df92ee44 | 563 | trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); |
65501a74 AW |
564 | |
565 | /* | |
f4d45d47 AW |
566 | * There are still old guests that mask and unmask vectors on every |
567 | * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of | |
568 | * the KVM setup in place, simply switch VFIO to use the non-bypass | |
569 | * eventfd. We'll then fire the interrupt through QEMU and the MSI-X | |
570 | * core will mask the interrupt and set pending bits, allowing it to | |
571 | * be re-asserted on unmask. Nothing to do if already using QEMU mode. | |
65501a74 | 572 | */ |
f4d45d47 AW |
573 | if (vector->virq >= 0) { |
574 | int argsz; | |
575 | struct vfio_irq_set *irq_set; | |
576 | int32_t *pfd; | |
1a403133 | 577 | |
f4d45d47 | 578 | argsz = sizeof(*irq_set) + sizeof(*pfd); |
1a403133 | 579 | |
f4d45d47 AW |
580 | irq_set = g_malloc0(argsz); |
581 | irq_set->argsz = argsz; | |
582 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
583 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
584 | irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; | |
585 | irq_set->start = nr; | |
586 | irq_set->count = 1; | |
587 | pfd = (int32_t *)&irq_set->data; | |
1a403133 | 588 | |
f4d45d47 | 589 | *pfd = event_notifier_get_fd(&vector->interrupt); |
1a403133 | 590 | |
5546a621 | 591 | ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
65501a74 | 592 | |
f4d45d47 | 593 | g_free(irq_set); |
65501a74 | 594 | } |
65501a74 AW |
595 | } |
596 | ||
0de70dc7 | 597 | static void vfio_msix_enable(VFIOPCIDevice *vdev) |
fd704adc AW |
598 | { |
599 | vfio_disable_interrupts(vdev); | |
600 | ||
bdd81add | 601 | vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); |
fd704adc AW |
602 | |
603 | vdev->interrupt = VFIO_INT_MSIX; | |
604 | ||
b0223e29 AW |
605 | /* |
606 | * Some communication channels between VF & PF or PF & fw rely on the | |
607 | * physical state of the device and expect that enabling MSI-X from the | |
608 | * guest enables the same on the host. When our guest is Linux, the | |
609 | * guest driver call to pci_enable_msix() sets the enabling bit in the | |
610 | * MSI-X capability, but leaves the vector table masked. We therefore | |
611 | * can't rely on a vector_use callback (from request_irq() in the guest) | |
612 | * to switch the physical device into MSI-X mode because that may come a | |
613 | * long time after pci_enable_msix(). This code enables vector 0 with | |
614 | * triggering to userspace, then immediately release the vector, leaving | |
615 | * the physical device with no vectors enabled, but MSI-X enabled, just | |
616 | * like the guest view. | |
617 | */ | |
618 | vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); | |
619 | vfio_msix_vector_release(&vdev->pdev, 0); | |
620 | ||
fd704adc | 621 | if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, |
bbef882c | 622 | vfio_msix_vector_release, NULL)) { |
312fd5f2 | 623 | error_report("vfio: msix_set_vector_notifiers failed"); |
fd704adc AW |
624 | } |
625 | ||
0de70dc7 | 626 | trace_vfio_msix_enable(vdev->vbasedev.name); |
fd704adc AW |
627 | } |
628 | ||
0de70dc7 | 629 | static void vfio_msi_enable(VFIOPCIDevice *vdev) |
65501a74 AW |
630 | { |
631 | int ret, i; | |
632 | ||
633 | vfio_disable_interrupts(vdev); | |
634 | ||
635 | vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); | |
636 | retry: | |
bdd81add | 637 | vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors); |
65501a74 AW |
638 | |
639 | for (i = 0; i < vdev->nr_vectors; i++) { | |
65501a74 | 640 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; |
9b3af4c0 | 641 | MSIMessage msg = msi_get_message(&vdev->pdev, i); |
65501a74 AW |
642 | |
643 | vector->vdev = vdev; | |
f4d45d47 | 644 | vector->virq = -1; |
65501a74 AW |
645 | vector->use = true; |
646 | ||
647 | if (event_notifier_init(&vector->interrupt, 0)) { | |
312fd5f2 | 648 | error_report("vfio: Error: event_notifier_init failed"); |
65501a74 AW |
649 | } |
650 | ||
f4d45d47 AW |
651 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
652 | vfio_msi_interrupt, NULL, vector); | |
653 | ||
65501a74 AW |
654 | /* |
655 | * Attempt to enable route through KVM irqchip, | |
656 | * default to userspace handling if unavailable. | |
657 | */ | |
46746dba | 658 | vfio_add_kvm_msi_virq(vdev, vector, &msg, false); |
65501a74 AW |
659 | } |
660 | ||
f4d45d47 AW |
661 | /* Set interrupt type prior to possible interrupts */ |
662 | vdev->interrupt = VFIO_INT_MSI; | |
663 | ||
65501a74 AW |
664 | ret = vfio_enable_vectors(vdev, false); |
665 | if (ret) { | |
666 | if (ret < 0) { | |
312fd5f2 | 667 | error_report("vfio: Error: Failed to setup MSI fds: %m"); |
65501a74 AW |
668 | } else if (ret != vdev->nr_vectors) { |
669 | error_report("vfio: Error: Failed to enable %d " | |
312fd5f2 | 670 | "MSI vectors, retry with %d", vdev->nr_vectors, ret); |
65501a74 AW |
671 | } |
672 | ||
673 | for (i = 0; i < vdev->nr_vectors; i++) { | |
674 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
675 | if (vector->virq >= 0) { | |
f4d45d47 | 676 | vfio_remove_kvm_msi_virq(vector); |
65501a74 | 677 | } |
f4d45d47 AW |
678 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), |
679 | NULL, NULL, NULL); | |
65501a74 AW |
680 | event_notifier_cleanup(&vector->interrupt); |
681 | } | |
682 | ||
683 | g_free(vdev->msi_vectors); | |
684 | ||
685 | if (ret > 0 && ret != vdev->nr_vectors) { | |
686 | vdev->nr_vectors = ret; | |
687 | goto retry; | |
688 | } | |
689 | vdev->nr_vectors = 0; | |
690 | ||
f4d45d47 AW |
691 | /* |
692 | * Failing to setup MSI doesn't really fall within any specification. | |
693 | * Let's try leaving interrupts disabled and hope the guest figures | |
694 | * out to fall back to INTx for this device. | |
695 | */ | |
696 | error_report("vfio: Error: Failed to enable MSI"); | |
697 | vdev->interrupt = VFIO_INT_NONE; | |
698 | ||
65501a74 AW |
699 | return; |
700 | } | |
701 | ||
0de70dc7 | 702 | trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors); |
65501a74 AW |
703 | } |
704 | ||
0de70dc7 | 705 | static void vfio_msi_disable_common(VFIOPCIDevice *vdev) |
fd704adc | 706 | { |
f4d45d47 AW |
707 | int i; |
708 | ||
709 | for (i = 0; i < vdev->nr_vectors; i++) { | |
710 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
711 | if (vdev->msi_vectors[i].use) { | |
712 | if (vector->virq >= 0) { | |
713 | vfio_remove_kvm_msi_virq(vector); | |
714 | } | |
715 | qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), | |
716 | NULL, NULL, NULL); | |
717 | event_notifier_cleanup(&vector->interrupt); | |
718 | } | |
719 | } | |
720 | ||
fd704adc AW |
721 | g_free(vdev->msi_vectors); |
722 | vdev->msi_vectors = NULL; | |
723 | vdev->nr_vectors = 0; | |
724 | vdev->interrupt = VFIO_INT_NONE; | |
725 | ||
870cb6f1 | 726 | vfio_intx_enable(vdev); |
fd704adc AW |
727 | } |
728 | ||
0de70dc7 | 729 | static void vfio_msix_disable(VFIOPCIDevice *vdev) |
fd704adc | 730 | { |
3e40ba0f AW |
731 | int i; |
732 | ||
fd704adc AW |
733 | msix_unset_vector_notifiers(&vdev->pdev); |
734 | ||
3e40ba0f AW |
735 | /* |
736 | * MSI-X will only release vectors if MSI-X is still enabled on the | |
737 | * device, check through the rest and release it ourselves if necessary. | |
738 | */ | |
739 | for (i = 0; i < vdev->nr_vectors; i++) { | |
740 | if (vdev->msi_vectors[i].use) { | |
741 | vfio_msix_vector_release(&vdev->pdev, i); | |
f4d45d47 | 742 | msix_vector_unuse(&vdev->pdev, i); |
3e40ba0f AW |
743 | } |
744 | } | |
745 | ||
fd704adc | 746 | if (vdev->nr_vectors) { |
5546a621 | 747 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); |
fd704adc AW |
748 | } |
749 | ||
0de70dc7 | 750 | vfio_msi_disable_common(vdev); |
fd704adc | 751 | |
95239e16 AW |
752 | memset(vdev->msix->pending, 0, |
753 | BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); | |
754 | ||
0de70dc7 | 755 | trace_vfio_msix_disable(vdev->vbasedev.name); |
fd704adc AW |
756 | } |
757 | ||
0de70dc7 | 758 | static void vfio_msi_disable(VFIOPCIDevice *vdev) |
65501a74 | 759 | { |
5546a621 | 760 | vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); |
0de70dc7 | 761 | vfio_msi_disable_common(vdev); |
65501a74 | 762 | |
0de70dc7 | 763 | trace_vfio_msi_disable(vdev->vbasedev.name); |
65501a74 AW |
764 | } |
765 | ||
9ee27d73 | 766 | static void vfio_update_msi(VFIOPCIDevice *vdev) |
c7679d45 AW |
767 | { |
768 | int i; | |
769 | ||
770 | for (i = 0; i < vdev->nr_vectors; i++) { | |
771 | VFIOMSIVector *vector = &vdev->msi_vectors[i]; | |
772 | MSIMessage msg; | |
773 | ||
774 | if (!vector->use || vector->virq < 0) { | |
775 | continue; | |
776 | } | |
777 | ||
778 | msg = msi_get_message(&vdev->pdev, i); | |
dc9f06ca | 779 | vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev); |
c7679d45 AW |
780 | } |
781 | } | |
782 | ||
9ee27d73 | 783 | static void vfio_pci_load_rom(VFIOPCIDevice *vdev) |
6f864e6e | 784 | { |
46900226 | 785 | struct vfio_region_info *reg_info; |
6f864e6e AW |
786 | uint64_t size; |
787 | off_t off = 0; | |
7d489dcd | 788 | ssize_t bytes; |
6f864e6e | 789 | |
46900226 AW |
790 | if (vfio_get_region_info(&vdev->vbasedev, |
791 | VFIO_PCI_ROM_REGION_INDEX, ®_info)) { | |
6f864e6e AW |
792 | error_report("vfio: Error getting ROM info: %m"); |
793 | return; | |
794 | } | |
795 | ||
46900226 AW |
796 | trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size, |
797 | (unsigned long)reg_info->offset, | |
798 | (unsigned long)reg_info->flags); | |
799 | ||
800 | vdev->rom_size = size = reg_info->size; | |
801 | vdev->rom_offset = reg_info->offset; | |
6f864e6e | 802 | |
46900226 | 803 | g_free(reg_info); |
6f864e6e AW |
804 | |
805 | if (!vdev->rom_size) { | |
e638073c | 806 | vdev->rom_read_failed = true; |
d20b43df | 807 | error_report("vfio-pci: Cannot read device rom at " |
df92ee44 | 808 | "%s", vdev->vbasedev.name); |
d20b43df BD |
809 | error_printf("Device option ROM contents are probably invalid " |
810 | "(check dmesg).\nSkip option ROM probe with rombar=0, " | |
811 | "or load from file with romfile=\n"); | |
6f864e6e AW |
812 | return; |
813 | } | |
814 | ||
815 | vdev->rom = g_malloc(size); | |
816 | memset(vdev->rom, 0xff, size); | |
817 | ||
818 | while (size) { | |
5546a621 EA |
819 | bytes = pread(vdev->vbasedev.fd, vdev->rom + off, |
820 | size, vdev->rom_offset + off); | |
6f864e6e AW |
821 | if (bytes == 0) { |
822 | break; | |
823 | } else if (bytes > 0) { | |
824 | off += bytes; | |
825 | size -= bytes; | |
826 | } else { | |
827 | if (errno == EINTR || errno == EAGAIN) { | |
828 | continue; | |
829 | } | |
830 | error_report("vfio: Error reading device ROM: %m"); | |
831 | break; | |
832 | } | |
833 | } | |
e2e5ee9c AW |
834 | |
835 | /* | |
836 | * Test the ROM signature against our device, if the vendor is correct | |
837 | * but the device ID doesn't match, store the correct device ID and | |
838 | * recompute the checksum. Intel IGD devices need this and are known | |
839 | * to have bogus checksums so we can't simply adjust the checksum. | |
840 | */ | |
841 | if (pci_get_word(vdev->rom) == 0xaa55 && | |
842 | pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size && | |
843 | !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) { | |
844 | uint16_t vid, did; | |
845 | ||
846 | vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4); | |
847 | did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6); | |
848 | ||
849 | if (vid == vdev->vendor_id && did != vdev->device_id) { | |
850 | int i; | |
851 | uint8_t csum, *data = vdev->rom; | |
852 | ||
853 | pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6, | |
854 | vdev->device_id); | |
855 | data[6] = 0; | |
856 | ||
857 | for (csum = 0, i = 0; i < vdev->rom_size; i++) { | |
858 | csum += data[i]; | |
859 | } | |
860 | ||
861 | data[6] = -csum; | |
862 | } | |
863 | } | |
6f864e6e AW |
864 | } |
865 | ||
866 | static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) | |
867 | { | |
9ee27d73 | 868 | VFIOPCIDevice *vdev = opaque; |
75bd0c72 ND |
869 | union { |
870 | uint8_t byte; | |
871 | uint16_t word; | |
872 | uint32_t dword; | |
873 | uint64_t qword; | |
874 | } val; | |
875 | uint64_t data = 0; | |
6f864e6e AW |
876 | |
877 | /* Load the ROM lazily when the guest tries to read it */ | |
db01eedb | 878 | if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { |
6f864e6e AW |
879 | vfio_pci_load_rom(vdev); |
880 | } | |
881 | ||
6758008e | 882 | memcpy(&val, vdev->rom + addr, |
6f864e6e AW |
883 | (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); |
884 | ||
75bd0c72 ND |
885 | switch (size) { |
886 | case 1: | |
887 | data = val.byte; | |
888 | break; | |
889 | case 2: | |
890 | data = le16_to_cpu(val.word); | |
891 | break; | |
892 | case 4: | |
893 | data = le32_to_cpu(val.dword); | |
894 | break; | |
895 | default: | |
896 | hw_error("vfio: unsupported read size, %d bytes\n", size); | |
897 | break; | |
898 | } | |
899 | ||
df92ee44 | 900 | trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); |
6f864e6e | 901 | |
75bd0c72 | 902 | return data; |
6f864e6e AW |
903 | } |
904 | ||
64fa25a0 AW |
905 | static void vfio_rom_write(void *opaque, hwaddr addr, |
906 | uint64_t data, unsigned size) | |
907 | { | |
908 | } | |
909 | ||
6f864e6e AW |
910 | static const MemoryRegionOps vfio_rom_ops = { |
911 | .read = vfio_rom_read, | |
64fa25a0 | 912 | .write = vfio_rom_write, |
6758008e | 913 | .endianness = DEVICE_LITTLE_ENDIAN, |
6f864e6e AW |
914 | }; |
915 | ||
9ee27d73 | 916 | static void vfio_pci_size_rom(VFIOPCIDevice *vdev) |
6f864e6e | 917 | { |
b1c50c5f | 918 | uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); |
6f864e6e | 919 | off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; |
4b943029 | 920 | DeviceState *dev = DEVICE(vdev); |
062ed5d8 | 921 | char *name; |
5546a621 | 922 | int fd = vdev->vbasedev.fd; |
6f864e6e AW |
923 | |
924 | if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { | |
4b943029 BD |
925 | /* Since pci handles romfile, just print a message and return */ |
926 | if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { | |
7df9381b AW |
927 | error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified romfile\n", |
928 | vdev->vbasedev.name); | |
4b943029 | 929 | } |
6f864e6e AW |
930 | return; |
931 | } | |
932 | ||
933 | /* | |
934 | * Use the same size ROM BAR as the physical device. The contents | |
935 | * will get filled in later when the guest tries to read it. | |
936 | */ | |
5546a621 EA |
937 | if (pread(fd, &orig, 4, offset) != 4 || |
938 | pwrite(fd, &size, 4, offset) != 4 || | |
939 | pread(fd, &size, 4, offset) != 4 || | |
940 | pwrite(fd, &orig, 4, offset) != 4) { | |
7df9381b | 941 | error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name); |
6f864e6e AW |
942 | return; |
943 | } | |
944 | ||
b1c50c5f | 945 | size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; |
6f864e6e AW |
946 | |
947 | if (!size) { | |
948 | return; | |
949 | } | |
950 | ||
4b943029 BD |
951 | if (vfio_blacklist_opt_rom(vdev)) { |
952 | if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { | |
7df9381b AW |
953 | error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified non zero value for rombar\n", |
954 | vdev->vbasedev.name); | |
4b943029 | 955 | } else { |
7df9381b AW |
956 | error_printf("Warning : Rom loading for device at %s has been disabled due to system instability issues. Specify rombar=1 or romfile to force\n", |
957 | vdev->vbasedev.name); | |
4b943029 BD |
958 | return; |
959 | } | |
960 | } | |
961 | ||
df92ee44 | 962 | trace_vfio_pci_size_rom(vdev->vbasedev.name, size); |
6f864e6e | 963 | |
062ed5d8 | 964 | name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name); |
6f864e6e AW |
965 | |
966 | memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), | |
967 | &vfio_rom_ops, vdev, name, size); | |
062ed5d8 | 968 | g_free(name); |
6f864e6e AW |
969 | |
970 | pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, | |
971 | PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); | |
972 | ||
973 | vdev->pdev.has_rom = true; | |
e638073c | 974 | vdev->rom_read_failed = false; |
6f864e6e AW |
975 | } |
976 | ||
c00d61d8 | 977 | void vfio_vga_write(void *opaque, hwaddr addr, |
f15689c7 AW |
978 | uint64_t data, unsigned size) |
979 | { | |
980 | VFIOVGARegion *region = opaque; | |
981 | VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); | |
982 | union { | |
983 | uint8_t byte; | |
984 | uint16_t word; | |
985 | uint32_t dword; | |
986 | uint64_t qword; | |
987 | } buf; | |
988 | off_t offset = vga->fd_offset + region->offset + addr; | |
989 | ||
990 | switch (size) { | |
991 | case 1: | |
992 | buf.byte = data; | |
993 | break; | |
994 | case 2: | |
995 | buf.word = cpu_to_le16(data); | |
996 | break; | |
997 | case 4: | |
998 | buf.dword = cpu_to_le32(data); | |
999 | break; | |
1000 | default: | |
4e505ddd | 1001 | hw_error("vfio: unsupported write size, %d bytes", size); |
f15689c7 AW |
1002 | break; |
1003 | } | |
1004 | ||
1005 | if (pwrite(vga->fd, &buf, size, offset) != size) { | |
1006 | error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", | |
1007 | __func__, region->offset + addr, data, size); | |
1008 | } | |
1009 | ||
385f57cf | 1010 | trace_vfio_vga_write(region->offset + addr, data, size); |
f15689c7 AW |
1011 | } |
1012 | ||
c00d61d8 | 1013 | uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) |
f15689c7 AW |
1014 | { |
1015 | VFIOVGARegion *region = opaque; | |
1016 | VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); | |
1017 | union { | |
1018 | uint8_t byte; | |
1019 | uint16_t word; | |
1020 | uint32_t dword; | |
1021 | uint64_t qword; | |
1022 | } buf; | |
1023 | uint64_t data = 0; | |
1024 | off_t offset = vga->fd_offset + region->offset + addr; | |
1025 | ||
1026 | if (pread(vga->fd, &buf, size, offset) != size) { | |
1027 | error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", | |
1028 | __func__, region->offset + addr, size); | |
1029 | return (uint64_t)-1; | |
1030 | } | |
1031 | ||
1032 | switch (size) { | |
1033 | case 1: | |
1034 | data = buf.byte; | |
1035 | break; | |
1036 | case 2: | |
1037 | data = le16_to_cpu(buf.word); | |
1038 | break; | |
1039 | case 4: | |
1040 | data = le32_to_cpu(buf.dword); | |
1041 | break; | |
1042 | default: | |
4e505ddd | 1043 | hw_error("vfio: unsupported read size, %d bytes", size); |
f15689c7 AW |
1044 | break; |
1045 | } | |
1046 | ||
385f57cf | 1047 | trace_vfio_vga_read(region->offset + addr, size, data); |
f15689c7 AW |
1048 | |
1049 | return data; | |
1050 | } | |
1051 | ||
1052 | static const MemoryRegionOps vfio_vga_ops = { | |
1053 | .read = vfio_vga_read, | |
1054 | .write = vfio_vga_write, | |
1055 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1056 | }; | |
1057 | ||
65501a74 AW |
1058 | /* |
1059 | * PCI config space | |
1060 | */ | |
c00d61d8 | 1061 | uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) |
65501a74 | 1062 | { |
9ee27d73 | 1063 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
4b5d5e87 | 1064 | uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; |
65501a74 | 1065 | |
4b5d5e87 AW |
1066 | memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); |
1067 | emu_bits = le32_to_cpu(emu_bits); | |
65501a74 | 1068 | |
4b5d5e87 AW |
1069 | if (emu_bits) { |
1070 | emu_val = pci_default_read_config(pdev, addr, len); | |
1071 | } | |
1072 | ||
1073 | if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { | |
1074 | ssize_t ret; | |
1075 | ||
5546a621 EA |
1076 | ret = pread(vdev->vbasedev.fd, &phys_val, len, |
1077 | vdev->config_offset + addr); | |
4b5d5e87 | 1078 | if (ret != len) { |
7df9381b AW |
1079 | error_report("%s(%s, 0x%x, 0x%x) failed: %m", |
1080 | __func__, vdev->vbasedev.name, addr, len); | |
65501a74 AW |
1081 | return -errno; |
1082 | } | |
4b5d5e87 | 1083 | phys_val = le32_to_cpu(phys_val); |
65501a74 AW |
1084 | } |
1085 | ||
4b5d5e87 | 1086 | val = (emu_val & emu_bits) | (phys_val & ~emu_bits); |
65501a74 | 1087 | |
df92ee44 | 1088 | trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); |
65501a74 AW |
1089 | |
1090 | return val; | |
1091 | } | |
1092 | ||
c00d61d8 AW |
1093 | void vfio_pci_write_config(PCIDevice *pdev, |
1094 | uint32_t addr, uint32_t val, int len) | |
65501a74 | 1095 | { |
9ee27d73 | 1096 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 AW |
1097 | uint32_t val_le = cpu_to_le32(val); |
1098 | ||
df92ee44 | 1099 | trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); |
65501a74 AW |
1100 | |
1101 | /* Write everything to VFIO, let it filter out what we can't write */ | |
5546a621 EA |
1102 | if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) |
1103 | != len) { | |
7df9381b AW |
1104 | error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m", |
1105 | __func__, vdev->vbasedev.name, addr, val, len); | |
65501a74 AW |
1106 | } |
1107 | ||
65501a74 AW |
1108 | /* MSI/MSI-X Enabling/Disabling */ |
1109 | if (pdev->cap_present & QEMU_PCI_CAP_MSI && | |
1110 | ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { | |
1111 | int is_enabled, was_enabled = msi_enabled(pdev); | |
1112 | ||
1113 | pci_default_write_config(pdev, addr, val, len); | |
1114 | ||
1115 | is_enabled = msi_enabled(pdev); | |
1116 | ||
c7679d45 AW |
1117 | if (!was_enabled) { |
1118 | if (is_enabled) { | |
0de70dc7 | 1119 | vfio_msi_enable(vdev); |
c7679d45 AW |
1120 | } |
1121 | } else { | |
1122 | if (!is_enabled) { | |
0de70dc7 | 1123 | vfio_msi_disable(vdev); |
c7679d45 AW |
1124 | } else { |
1125 | vfio_update_msi(vdev); | |
1126 | } | |
65501a74 | 1127 | } |
4b5d5e87 | 1128 | } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && |
65501a74 AW |
1129 | ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { |
1130 | int is_enabled, was_enabled = msix_enabled(pdev); | |
1131 | ||
1132 | pci_default_write_config(pdev, addr, val, len); | |
1133 | ||
1134 | is_enabled = msix_enabled(pdev); | |
1135 | ||
1136 | if (!was_enabled && is_enabled) { | |
0de70dc7 | 1137 | vfio_msix_enable(vdev); |
65501a74 | 1138 | } else if (was_enabled && !is_enabled) { |
0de70dc7 | 1139 | vfio_msix_disable(vdev); |
65501a74 | 1140 | } |
4b5d5e87 AW |
1141 | } else { |
1142 | /* Write everything to QEMU to keep emulated bits correct */ | |
1143 | pci_default_write_config(pdev, addr, val, len); | |
65501a74 AW |
1144 | } |
1145 | } | |
1146 | ||
65501a74 AW |
1147 | /* |
1148 | * Interrupt setup | |
1149 | */ | |
9ee27d73 | 1150 | static void vfio_disable_interrupts(VFIOPCIDevice *vdev) |
65501a74 | 1151 | { |
b3e27c3a AW |
1152 | /* |
1153 | * More complicated than it looks. Disabling MSI/X transitions the | |
1154 | * device to INTx mode (if supported). Therefore we need to first | |
1155 | * disable MSI/X and then cleanup by disabling INTx. | |
1156 | */ | |
1157 | if (vdev->interrupt == VFIO_INT_MSIX) { | |
0de70dc7 | 1158 | vfio_msix_disable(vdev); |
b3e27c3a | 1159 | } else if (vdev->interrupt == VFIO_INT_MSI) { |
0de70dc7 | 1160 | vfio_msi_disable(vdev); |
b3e27c3a AW |
1161 | } |
1162 | ||
1163 | if (vdev->interrupt == VFIO_INT_INTx) { | |
870cb6f1 | 1164 | vfio_intx_disable(vdev); |
65501a74 AW |
1165 | } |
1166 | } | |
1167 | ||
0de70dc7 | 1168 | static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos) |
65501a74 AW |
1169 | { |
1170 | uint16_t ctrl; | |
1171 | bool msi_64bit, msi_maskbit; | |
1172 | int ret, entries; | |
1173 | ||
5546a621 | 1174 | if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), |
65501a74 AW |
1175 | vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { |
1176 | return -errno; | |
1177 | } | |
1178 | ctrl = le16_to_cpu(ctrl); | |
1179 | ||
1180 | msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); | |
1181 | msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); | |
1182 | entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); | |
1183 | ||
0de70dc7 | 1184 | trace_vfio_msi_setup(vdev->vbasedev.name, pos); |
65501a74 AW |
1185 | |
1186 | ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit); | |
1187 | if (ret < 0) { | |
e43b9a5a AW |
1188 | if (ret == -ENOTSUP) { |
1189 | return 0; | |
1190 | } | |
312fd5f2 | 1191 | error_report("vfio: msi_init failed"); |
65501a74 AW |
1192 | return ret; |
1193 | } | |
1194 | vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); | |
1195 | ||
1196 | return 0; | |
1197 | } | |
1198 | ||
db0da029 AW |
1199 | static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev) |
1200 | { | |
1201 | off_t start, end; | |
1202 | VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region; | |
1203 | ||
1204 | /* | |
1205 | * We expect to find a single mmap covering the whole BAR, anything else | |
1206 | * means it's either unsupported or already setup. | |
1207 | */ | |
1208 | if (region->nr_mmaps != 1 || region->mmaps[0].offset || | |
1209 | region->size != region->mmaps[0].size) { | |
1210 | return; | |
1211 | } | |
1212 | ||
1213 | /* MSI-X table start and end aligned to host page size */ | |
1214 | start = vdev->msix->table_offset & qemu_real_host_page_mask; | |
1215 | end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + | |
1216 | (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); | |
1217 | ||
1218 | /* | |
1219 | * Does the MSI-X table cover the beginning of the BAR? The whole BAR? | |
1220 | * NB - Host page size is necessarily a power of two and so is the PCI | |
1221 | * BAR (not counting EA yet), therefore if we have host page aligned | |
1222 | * @start and @end, then any remainder of the BAR before or after those | |
1223 | * must be at least host page sized and therefore mmap'able. | |
1224 | */ | |
1225 | if (!start) { | |
1226 | if (end >= region->size) { | |
1227 | region->nr_mmaps = 0; | |
1228 | g_free(region->mmaps); | |
1229 | region->mmaps = NULL; | |
1230 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1231 | vdev->msix->table_bar, 0, 0); | |
1232 | } else { | |
1233 | region->mmaps[0].offset = end; | |
1234 | region->mmaps[0].size = region->size - end; | |
1235 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1236 | vdev->msix->table_bar, region->mmaps[0].offset, | |
1237 | region->mmaps[0].offset + region->mmaps[0].size); | |
1238 | } | |
1239 | ||
1240 | /* Maybe it's aligned at the end of the BAR */ | |
1241 | } else if (end >= region->size) { | |
1242 | region->mmaps[0].size = start; | |
1243 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1244 | vdev->msix->table_bar, region->mmaps[0].offset, | |
1245 | region->mmaps[0].offset + region->mmaps[0].size); | |
1246 | ||
1247 | /* Otherwise it must split the BAR */ | |
1248 | } else { | |
1249 | region->nr_mmaps = 2; | |
1250 | region->mmaps = g_renew(VFIOMmap, region->mmaps, 2); | |
1251 | ||
1252 | memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap)); | |
1253 | ||
1254 | region->mmaps[0].size = start; | |
1255 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1256 | vdev->msix->table_bar, region->mmaps[0].offset, | |
1257 | region->mmaps[0].offset + region->mmaps[0].size); | |
1258 | ||
1259 | region->mmaps[1].offset = end; | |
1260 | region->mmaps[1].size = region->size - end; | |
1261 | trace_vfio_msix_fixup(vdev->vbasedev.name, | |
1262 | vdev->msix->table_bar, region->mmaps[1].offset, | |
1263 | region->mmaps[1].offset + region->mmaps[1].size); | |
1264 | } | |
1265 | } | |
1266 | ||
65501a74 AW |
1267 | /* |
1268 | * We don't have any control over how pci_add_capability() inserts | |
1269 | * capabilities into the chain. In order to setup MSI-X we need a | |
1270 | * MemoryRegion for the BAR. In order to setup the BAR and not | |
1271 | * attempt to mmap the MSI-X table area, which VFIO won't allow, we | |
1272 | * need to first look for where the MSI-X table lives. So we | |
1273 | * unfortunately split MSI-X setup across two functions. | |
1274 | */ | |
0de70dc7 | 1275 | static int vfio_msix_early_setup(VFIOPCIDevice *vdev) |
65501a74 AW |
1276 | { |
1277 | uint8_t pos; | |
1278 | uint16_t ctrl; | |
1279 | uint32_t table, pba; | |
5546a621 | 1280 | int fd = vdev->vbasedev.fd; |
b5bd049f | 1281 | VFIOMSIXInfo *msix; |
65501a74 AW |
1282 | |
1283 | pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); | |
1284 | if (!pos) { | |
1285 | return 0; | |
1286 | } | |
1287 | ||
5546a621 | 1288 | if (pread(fd, &ctrl, sizeof(ctrl), |
b58b17f7 | 1289 | vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) { |
65501a74 AW |
1290 | return -errno; |
1291 | } | |
1292 | ||
5546a621 | 1293 | if (pread(fd, &table, sizeof(table), |
65501a74 AW |
1294 | vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { |
1295 | return -errno; | |
1296 | } | |
1297 | ||
5546a621 | 1298 | if (pread(fd, &pba, sizeof(pba), |
65501a74 AW |
1299 | vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { |
1300 | return -errno; | |
1301 | } | |
1302 | ||
1303 | ctrl = le16_to_cpu(ctrl); | |
1304 | table = le32_to_cpu(table); | |
1305 | pba = le32_to_cpu(pba); | |
1306 | ||
b5bd049f AW |
1307 | msix = g_malloc0(sizeof(*msix)); |
1308 | msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; | |
1309 | msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; | |
1310 | msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; | |
1311 | msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; | |
1312 | msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; | |
65501a74 | 1313 | |
43302969 GL |
1314 | /* |
1315 | * Test the size of the pba_offset variable and catch if it extends outside | |
1316 | * of the specified BAR. If it is the case, we need to apply a hardware | |
1317 | * specific quirk if the device is known or we have a broken configuration. | |
1318 | */ | |
b5bd049f | 1319 | if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) { |
43302969 GL |
1320 | /* |
1321 | * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5 | |
1322 | * adapters. The T5 hardware returns an incorrect value of 0x8000 for | |
1323 | * the VF PBA offset while the BAR itself is only 8k. The correct value | |
1324 | * is 0x1000, so we hard code that here. | |
1325 | */ | |
ff635e37 AW |
1326 | if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO && |
1327 | (vdev->device_id & 0xff00) == 0x5800) { | |
b5bd049f | 1328 | msix->pba_offset = 0x1000; |
43302969 GL |
1329 | } else { |
1330 | error_report("vfio: Hardware reports invalid configuration, " | |
1331 | "MSIX PBA outside of specified BAR"); | |
b5bd049f | 1332 | g_free(msix); |
43302969 GL |
1333 | return -EINVAL; |
1334 | } | |
1335 | } | |
1336 | ||
0de70dc7 | 1337 | trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar, |
b5bd049f AW |
1338 | msix->table_offset, msix->entries); |
1339 | vdev->msix = msix; | |
65501a74 | 1340 | |
db0da029 AW |
1341 | vfio_pci_fixup_msix_region(vdev); |
1342 | ||
65501a74 AW |
1343 | return 0; |
1344 | } | |
1345 | ||
0de70dc7 | 1346 | static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos) |
65501a74 AW |
1347 | { |
1348 | int ret; | |
1349 | ||
95239e16 AW |
1350 | vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * |
1351 | sizeof(unsigned long)); | |
65501a74 | 1352 | ret = msix_init(&vdev->pdev, vdev->msix->entries, |
db0da029 | 1353 | vdev->bars[vdev->msix->table_bar].region.mem, |
65501a74 | 1354 | vdev->msix->table_bar, vdev->msix->table_offset, |
db0da029 | 1355 | vdev->bars[vdev->msix->pba_bar].region.mem, |
65501a74 AW |
1356 | vdev->msix->pba_bar, vdev->msix->pba_offset, pos); |
1357 | if (ret < 0) { | |
e43b9a5a AW |
1358 | if (ret == -ENOTSUP) { |
1359 | return 0; | |
1360 | } | |
312fd5f2 | 1361 | error_report("vfio: msix_init failed"); |
65501a74 AW |
1362 | return ret; |
1363 | } | |
1364 | ||
95239e16 AW |
1365 | /* |
1366 | * The PCI spec suggests that devices provide additional alignment for | |
1367 | * MSI-X structures and avoid overlapping non-MSI-X related registers. | |
1368 | * For an assigned device, this hopefully means that emulation of MSI-X | |
1369 | * structures does not affect the performance of the device. If devices | |
1370 | * fail to provide that alignment, a significant performance penalty may | |
1371 | * result, for instance Mellanox MT27500 VFs: | |
1372 | * http://www.spinics.net/lists/kvm/msg125881.html | |
1373 | * | |
1374 | * The PBA is simply not that important for such a serious regression and | |
1375 | * most drivers do not appear to look at it. The solution for this is to | |
1376 | * disable the PBA MemoryRegion unless it's being used. We disable it | |
1377 | * here and only enable it if a masked vector fires through QEMU. As the | |
1378 | * vector-use notifier is called, which occurs on unmask, we test whether | |
1379 | * PBA emulation is needed and again disable if not. | |
1380 | */ | |
1381 | memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); | |
1382 | ||
65501a74 AW |
1383 | return 0; |
1384 | } | |
1385 | ||
9ee27d73 | 1386 | static void vfio_teardown_msi(VFIOPCIDevice *vdev) |
65501a74 AW |
1387 | { |
1388 | msi_uninit(&vdev->pdev); | |
1389 | ||
1390 | if (vdev->msix) { | |
a664477d | 1391 | msix_uninit(&vdev->pdev, |
db0da029 AW |
1392 | vdev->bars[vdev->msix->table_bar].region.mem, |
1393 | vdev->bars[vdev->msix->pba_bar].region.mem); | |
95239e16 | 1394 | g_free(vdev->msix->pending); |
65501a74 AW |
1395 | } |
1396 | } | |
1397 | ||
1398 | /* | |
1399 | * Resource setup | |
1400 | */ | |
9ee27d73 | 1401 | static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) |
65501a74 AW |
1402 | { |
1403 | int i; | |
1404 | ||
1405 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
db0da029 | 1406 | vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled); |
65501a74 AW |
1407 | } |
1408 | } | |
1409 | ||
2d82f8a3 | 1410 | static void vfio_bar_setup(VFIOPCIDevice *vdev, int nr) |
65501a74 AW |
1411 | { |
1412 | VFIOBAR *bar = &vdev->bars[nr]; | |
1413 | ||
65501a74 AW |
1414 | uint32_t pci_bar; |
1415 | uint8_t type; | |
1416 | int ret; | |
1417 | ||
1418 | /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ | |
2d82f8a3 | 1419 | if (!bar->region.size) { |
65501a74 AW |
1420 | return; |
1421 | } | |
1422 | ||
65501a74 | 1423 | /* Determine what type of BAR this is for registration */ |
5546a621 | 1424 | ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), |
65501a74 AW |
1425 | vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); |
1426 | if (ret != sizeof(pci_bar)) { | |
312fd5f2 | 1427 | error_report("vfio: Failed to read BAR %d (%m)", nr); |
65501a74 AW |
1428 | return; |
1429 | } | |
1430 | ||
1431 | pci_bar = le32_to_cpu(pci_bar); | |
39360f0b AW |
1432 | bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); |
1433 | bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); | |
1434 | type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : | |
1435 | ~PCI_BASE_ADDRESS_MEM_MASK); | |
65501a74 | 1436 | |
db0da029 AW |
1437 | if (vfio_region_mmap(&bar->region)) { |
1438 | error_report("Failed to mmap %s BAR %d. Performance may be slow", | |
1439 | vdev->vbasedev.name, nr); | |
65501a74 | 1440 | } |
7076eabc | 1441 | |
2d82f8a3 | 1442 | pci_register_bar(&vdev->pdev, nr, type, bar->region.mem); |
65501a74 AW |
1443 | } |
1444 | ||
2d82f8a3 | 1445 | static void vfio_bars_setup(VFIOPCIDevice *vdev) |
65501a74 AW |
1446 | { |
1447 | int i; | |
1448 | ||
1449 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2d82f8a3 | 1450 | vfio_bar_setup(vdev, i); |
65501a74 AW |
1451 | } |
1452 | } | |
1453 | ||
2d82f8a3 | 1454 | static void vfio_bars_exit(VFIOPCIDevice *vdev) |
65501a74 AW |
1455 | { |
1456 | int i; | |
1457 | ||
1458 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2d82f8a3 AW |
1459 | vfio_bar_quirk_exit(vdev, i); |
1460 | vfio_region_exit(&vdev->bars[i].region); | |
65501a74 | 1461 | } |
f15689c7 | 1462 | |
2d82f8a3 | 1463 | if (vdev->vga) { |
f15689c7 | 1464 | pci_unregister_vga(&vdev->pdev); |
2d82f8a3 | 1465 | vfio_vga_quirk_exit(vdev); |
f15689c7 | 1466 | } |
65501a74 AW |
1467 | } |
1468 | ||
2d82f8a3 | 1469 | static void vfio_bars_finalize(VFIOPCIDevice *vdev) |
ba5e6bfa PB |
1470 | { |
1471 | int i; | |
1472 | ||
1473 | for (i = 0; i < PCI_ROM_SLOT; i++) { | |
2d82f8a3 AW |
1474 | vfio_bar_quirk_finalize(vdev, i); |
1475 | vfio_region_finalize(&vdev->bars[i].region); | |
ba5e6bfa PB |
1476 | } |
1477 | ||
2d82f8a3 AW |
1478 | if (vdev->vga) { |
1479 | vfio_vga_quirk_finalize(vdev); | |
1480 | for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { | |
1481 | object_unparent(OBJECT(&vdev->vga->region[i].mem)); | |
1482 | } | |
1483 | g_free(vdev->vga); | |
ba5e6bfa PB |
1484 | } |
1485 | } | |
1486 | ||
65501a74 AW |
1487 | /* |
1488 | * General setup | |
1489 | */ | |
1490 | static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) | |
1491 | { | |
88caf177 CF |
1492 | uint8_t tmp; |
1493 | uint16_t next = PCI_CONFIG_SPACE_SIZE; | |
65501a74 AW |
1494 | |
1495 | for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; | |
3fc1c182 | 1496 | tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) { |
65501a74 AW |
1497 | if (tmp > pos && tmp < next) { |
1498 | next = tmp; | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | return next - pos; | |
1503 | } | |
1504 | ||
325ae8d5 CF |
1505 | |
1506 | static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos) | |
1507 | { | |
1508 | uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE; | |
1509 | ||
1510 | for (tmp = PCI_CONFIG_SPACE_SIZE; tmp; | |
1511 | tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { | |
1512 | if (tmp > pos && tmp < next) { | |
1513 | next = tmp; | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | return next - pos; | |
1518 | } | |
1519 | ||
96adc5c7 AW |
1520 | static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) |
1521 | { | |
1522 | pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); | |
1523 | } | |
1524 | ||
9ee27d73 | 1525 | static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, |
96adc5c7 AW |
1526 | uint16_t val, uint16_t mask) |
1527 | { | |
1528 | vfio_set_word_bits(vdev->pdev.config + pos, val, mask); | |
1529 | vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); | |
1530 | vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); | |
1531 | } | |
1532 | ||
1533 | static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) | |
1534 | { | |
1535 | pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); | |
1536 | } | |
1537 | ||
9ee27d73 | 1538 | static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, |
96adc5c7 AW |
1539 | uint32_t val, uint32_t mask) |
1540 | { | |
1541 | vfio_set_long_bits(vdev->pdev.config + pos, val, mask); | |
1542 | vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); | |
1543 | vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); | |
1544 | } | |
1545 | ||
9ee27d73 | 1546 | static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size) |
96adc5c7 AW |
1547 | { |
1548 | uint16_t flags; | |
1549 | uint8_t type; | |
1550 | ||
1551 | flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); | |
1552 | type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; | |
1553 | ||
1554 | if (type != PCI_EXP_TYPE_ENDPOINT && | |
1555 | type != PCI_EXP_TYPE_LEG_END && | |
1556 | type != PCI_EXP_TYPE_RC_END) { | |
1557 | ||
1558 | error_report("vfio: Assignment of PCIe type 0x%x " | |
1559 | "devices is not currently supported", type); | |
1560 | return -EINVAL; | |
1561 | } | |
1562 | ||
1563 | if (!pci_bus_is_express(vdev->pdev.bus)) { | |
0282abf0 AW |
1564 | PCIBus *bus = vdev->pdev.bus; |
1565 | PCIDevice *bridge; | |
1566 | ||
96adc5c7 | 1567 | /* |
0282abf0 AW |
1568 | * Traditionally PCI device assignment exposes the PCIe capability |
1569 | * as-is on non-express buses. The reason being that some drivers | |
1570 | * simply assume that it's there, for example tg3. However when | |
1571 | * we're running on a native PCIe machine type, like Q35, we need | |
1572 | * to hide the PCIe capability. The reason for this is twofold; | |
1573 | * first Windows guests get a Code 10 error when the PCIe capability | |
1574 | * is exposed in this configuration. Therefore express devices won't | |
1575 | * work at all unless they're attached to express buses in the VM. | |
1576 | * Second, a native PCIe machine introduces the possibility of fine | |
1577 | * granularity IOMMUs supporting both translation and isolation. | |
1578 | * Guest code to discover the IOMMU visibility of a device, such as | |
1579 | * IOMMU grouping code on Linux, is very aware of device types and | |
1580 | * valid transitions between bus types. An express device on a non- | |
1581 | * express bus is not a valid combination on bare metal systems. | |
1582 | * | |
1583 | * Drivers that require a PCIe capability to make the device | |
1584 | * functional are simply going to need to have their devices placed | |
1585 | * on a PCIe bus in the VM. | |
96adc5c7 | 1586 | */ |
0282abf0 AW |
1587 | while (!pci_bus_is_root(bus)) { |
1588 | bridge = pci_bridge_get_device(bus); | |
1589 | bus = bridge->bus; | |
1590 | } | |
1591 | ||
1592 | if (pci_bus_is_express(bus)) { | |
1593 | return 0; | |
1594 | } | |
1595 | ||
96adc5c7 AW |
1596 | } else if (pci_bus_is_root(vdev->pdev.bus)) { |
1597 | /* | |
1598 | * On a Root Complex bus Endpoints become Root Complex Integrated | |
1599 | * Endpoints, which changes the type and clears the LNK & LNK2 fields. | |
1600 | */ | |
1601 | if (type == PCI_EXP_TYPE_ENDPOINT) { | |
1602 | vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, | |
1603 | PCI_EXP_TYPE_RC_END << 4, | |
1604 | PCI_EXP_FLAGS_TYPE); | |
1605 | ||
1606 | /* Link Capabilities, Status, and Control goes away */ | |
1607 | if (size > PCI_EXP_LNKCTL) { | |
1608 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); | |
1609 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); | |
1610 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); | |
1611 | ||
1612 | #ifndef PCI_EXP_LNKCAP2 | |
1613 | #define PCI_EXP_LNKCAP2 44 | |
1614 | #endif | |
1615 | #ifndef PCI_EXP_LNKSTA2 | |
1616 | #define PCI_EXP_LNKSTA2 50 | |
1617 | #endif | |
1618 | /* Link 2 Capabilities, Status, and Control goes away */ | |
1619 | if (size > PCI_EXP_LNKCAP2) { | |
1620 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); | |
1621 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); | |
1622 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); | |
1623 | } | |
1624 | } | |
1625 | ||
1626 | } else if (type == PCI_EXP_TYPE_LEG_END) { | |
1627 | /* | |
1628 | * Legacy endpoints don't belong on the root complex. Windows | |
1629 | * seems to be happier with devices if we skip the capability. | |
1630 | */ | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | } else { | |
1635 | /* | |
1636 | * Convert Root Complex Integrated Endpoints to regular endpoints. | |
1637 | * These devices don't support LNK/LNK2 capabilities, so make them up. | |
1638 | */ | |
1639 | if (type == PCI_EXP_TYPE_RC_END) { | |
1640 | vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, | |
1641 | PCI_EXP_TYPE_ENDPOINT << 4, | |
1642 | PCI_EXP_FLAGS_TYPE); | |
1643 | vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, | |
1644 | PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); | |
1645 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); | |
1646 | } | |
1647 | ||
1648 | /* Mark the Link Status bits as emulated to allow virtual negotiation */ | |
1649 | vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, | |
1650 | pci_get_word(vdev->pdev.config + pos + | |
1651 | PCI_EXP_LNKSTA), | |
1652 | PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); | |
1653 | } | |
1654 | ||
1655 | pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); | |
1656 | if (pos >= 0) { | |
1657 | vdev->pdev.exp.exp_cap = pos; | |
1658 | } | |
1659 | ||
1660 | return pos; | |
1661 | } | |
1662 | ||
9ee27d73 | 1663 | static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
1664 | { |
1665 | uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); | |
1666 | ||
1667 | if (cap & PCI_EXP_DEVCAP_FLR) { | |
df92ee44 | 1668 | trace_vfio_check_pcie_flr(vdev->vbasedev.name); |
befe5176 AW |
1669 | vdev->has_flr = true; |
1670 | } | |
1671 | } | |
1672 | ||
9ee27d73 | 1673 | static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
1674 | { |
1675 | uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); | |
1676 | ||
1677 | if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { | |
df92ee44 | 1678 | trace_vfio_check_pm_reset(vdev->vbasedev.name); |
befe5176 AW |
1679 | vdev->has_pm_reset = true; |
1680 | } | |
1681 | } | |
1682 | ||
9ee27d73 | 1683 | static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) |
befe5176 AW |
1684 | { |
1685 | uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); | |
1686 | ||
1687 | if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { | |
df92ee44 | 1688 | trace_vfio_check_af_flr(vdev->vbasedev.name); |
befe5176 AW |
1689 | vdev->has_flr = true; |
1690 | } | |
1691 | } | |
1692 | ||
9ee27d73 | 1693 | static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos) |
65501a74 AW |
1694 | { |
1695 | PCIDevice *pdev = &vdev->pdev; | |
1696 | uint8_t cap_id, next, size; | |
1697 | int ret; | |
1698 | ||
1699 | cap_id = pdev->config[pos]; | |
3fc1c182 | 1700 | next = pdev->config[pos + PCI_CAP_LIST_NEXT]; |
65501a74 AW |
1701 | |
1702 | /* | |
1703 | * If it becomes important to configure capabilities to their actual | |
1704 | * size, use this as the default when it's something we don't recognize. | |
1705 | * Since QEMU doesn't actually handle many of the config accesses, | |
1706 | * exact size doesn't seem worthwhile. | |
1707 | */ | |
1708 | size = vfio_std_cap_max_size(pdev, pos); | |
1709 | ||
1710 | /* | |
1711 | * pci_add_capability always inserts the new capability at the head | |
1712 | * of the chain. Therefore to end up with a chain that matches the | |
1713 | * physical device, we insert from the end by making this recursive. | |
3fc1c182 | 1714 | * This is also why we pre-calculate size above as cached config space |
65501a74 AW |
1715 | * will be changed as we unwind the stack. |
1716 | */ | |
1717 | if (next) { | |
1718 | ret = vfio_add_std_cap(vdev, next); | |
1719 | if (ret) { | |
1720 | return ret; | |
1721 | } | |
1722 | } else { | |
96adc5c7 AW |
1723 | /* Begin the rebuild, use QEMU emulated list bits */ |
1724 | pdev->config[PCI_CAPABILITY_LIST] = 0; | |
1725 | vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; | |
1726 | vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; | |
65501a74 AW |
1727 | } |
1728 | ||
96adc5c7 | 1729 | /* Use emulated next pointer to allow dropping caps */ |
3fc1c182 | 1730 | pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); |
96adc5c7 | 1731 | |
65501a74 AW |
1732 | switch (cap_id) { |
1733 | case PCI_CAP_ID_MSI: | |
0de70dc7 | 1734 | ret = vfio_msi_setup(vdev, pos); |
65501a74 | 1735 | break; |
96adc5c7 | 1736 | case PCI_CAP_ID_EXP: |
befe5176 | 1737 | vfio_check_pcie_flr(vdev, pos); |
96adc5c7 AW |
1738 | ret = vfio_setup_pcie_cap(vdev, pos, size); |
1739 | break; | |
65501a74 | 1740 | case PCI_CAP_ID_MSIX: |
0de70dc7 | 1741 | ret = vfio_msix_setup(vdev, pos); |
65501a74 | 1742 | break; |
ba661818 | 1743 | case PCI_CAP_ID_PM: |
befe5176 | 1744 | vfio_check_pm_reset(vdev, pos); |
ba661818 | 1745 | vdev->pm_cap = pos; |
befe5176 AW |
1746 | ret = pci_add_capability(pdev, cap_id, pos, size); |
1747 | break; | |
1748 | case PCI_CAP_ID_AF: | |
1749 | vfio_check_af_flr(vdev, pos); | |
1750 | ret = pci_add_capability(pdev, cap_id, pos, size); | |
1751 | break; | |
65501a74 AW |
1752 | default: |
1753 | ret = pci_add_capability(pdev, cap_id, pos, size); | |
1754 | break; | |
1755 | } | |
1756 | ||
1757 | if (ret < 0) { | |
7df9381b AW |
1758 | error_report("vfio: %s Error adding PCI capability " |
1759 | "0x%x[0x%x]@0x%x: %d", vdev->vbasedev.name, | |
65501a74 AW |
1760 | cap_id, size, pos, ret); |
1761 | return ret; | |
1762 | } | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
325ae8d5 CF |
1767 | static int vfio_add_ext_cap(VFIOPCIDevice *vdev) |
1768 | { | |
1769 | PCIDevice *pdev = &vdev->pdev; | |
1770 | uint32_t header; | |
1771 | uint16_t cap_id, next, size; | |
1772 | uint8_t cap_ver; | |
1773 | uint8_t *config; | |
1774 | ||
e37dac06 AW |
1775 | /* Only add extended caps if we have them and the guest can see them */ |
1776 | if (!pci_is_express(pdev) || !pci_bus_is_express(pdev->bus) || | |
1777 | !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { | |
1778 | return 0; | |
1779 | } | |
1780 | ||
325ae8d5 CF |
1781 | /* |
1782 | * pcie_add_capability always inserts the new capability at the tail | |
1783 | * of the chain. Therefore to end up with a chain that matches the | |
1784 | * physical device, we cache the config space to avoid overwriting | |
1785 | * the original config space when we parse the extended capabilities. | |
1786 | */ | |
1787 | config = g_memdup(pdev->config, vdev->config_size); | |
1788 | ||
e37dac06 AW |
1789 | /* |
1790 | * Extended capabilities are chained with each pointing to the next, so we | |
1791 | * can drop anything other than the head of the chain simply by modifying | |
1792 | * the previous next pointer. For the head of the chain, we can modify the | |
1793 | * capability ID to something that cannot match a valid capability. ID | |
1794 | * 0 is reserved for this since absence of capabilities is indicated by | |
1795 | * 0 for the ID, version, AND next pointer. However, pcie_add_capability() | |
1796 | * uses ID 0 as reserved for list management and will incorrectly match and | |
1797 | * assert if we attempt to pre-load the head of the chain with with this | |
1798 | * ID. Use ID 0xFFFF temporarily since it is also seems to be reserved in | |
1799 | * part for identifying absence of capabilities in a root complex register | |
1800 | * block. If the ID still exists after adding capabilities, switch back to | |
1801 | * zero. We'll mark this entire first dword as emulated for this purpose. | |
1802 | */ | |
1803 | pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE, | |
1804 | PCI_EXT_CAP(0xFFFF, 0, 0)); | |
1805 | pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); | |
1806 | pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); | |
1807 | ||
325ae8d5 CF |
1808 | for (next = PCI_CONFIG_SPACE_SIZE; next; |
1809 | next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { | |
1810 | header = pci_get_long(config + next); | |
1811 | cap_id = PCI_EXT_CAP_ID(header); | |
1812 | cap_ver = PCI_EXT_CAP_VER(header); | |
1813 | ||
1814 | /* | |
1815 | * If it becomes important to configure extended capabilities to their | |
1816 | * actual size, use this as the default when it's something we don't | |
1817 | * recognize. Since QEMU doesn't actually handle many of the config | |
1818 | * accesses, exact size doesn't seem worthwhile. | |
1819 | */ | |
1820 | size = vfio_ext_cap_max_size(config, next); | |
1821 | ||
325ae8d5 CF |
1822 | /* Use emulated next pointer to allow dropping extended caps */ |
1823 | pci_long_test_and_set_mask(vdev->emulated_config_bits + next, | |
1824 | PCI_EXT_CAP_NEXT_MASK); | |
e37dac06 AW |
1825 | |
1826 | switch (cap_id) { | |
1827 | case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */ | |
1828 | trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next); | |
1829 | break; | |
1830 | default: | |
1831 | pcie_add_capability(pdev, cap_id, cap_ver, next, size); | |
1832 | } | |
1833 | ||
1834 | } | |
1835 | ||
1836 | /* Cleanup chain head ID if necessary */ | |
1837 | if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { | |
1838 | pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); | |
325ae8d5 CF |
1839 | } |
1840 | ||
1841 | g_free(config); | |
1842 | return 0; | |
1843 | } | |
1844 | ||
9ee27d73 | 1845 | static int vfio_add_capabilities(VFIOPCIDevice *vdev) |
65501a74 AW |
1846 | { |
1847 | PCIDevice *pdev = &vdev->pdev; | |
325ae8d5 | 1848 | int ret; |
65501a74 AW |
1849 | |
1850 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || | |
1851 | !pdev->config[PCI_CAPABILITY_LIST]) { | |
1852 | return 0; /* Nothing to add */ | |
1853 | } | |
1854 | ||
325ae8d5 CF |
1855 | ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST]); |
1856 | if (ret) { | |
1857 | return ret; | |
1858 | } | |
1859 | ||
325ae8d5 | 1860 | return vfio_add_ext_cap(vdev); |
65501a74 AW |
1861 | } |
1862 | ||
9ee27d73 | 1863 | static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) |
f16f39c3 AW |
1864 | { |
1865 | PCIDevice *pdev = &vdev->pdev; | |
1866 | uint16_t cmd; | |
1867 | ||
1868 | vfio_disable_interrupts(vdev); | |
1869 | ||
1870 | /* Make sure the device is in D0 */ | |
1871 | if (vdev->pm_cap) { | |
1872 | uint16_t pmcsr; | |
1873 | uint8_t state; | |
1874 | ||
1875 | pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); | |
1876 | state = pmcsr & PCI_PM_CTRL_STATE_MASK; | |
1877 | if (state) { | |
1878 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
1879 | vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); | |
1880 | /* vfio handles the necessary delay here */ | |
1881 | pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); | |
1882 | state = pmcsr & PCI_PM_CTRL_STATE_MASK; | |
1883 | if (state) { | |
4e505ddd | 1884 | error_report("vfio: Unable to power on device, stuck in D%d", |
f16f39c3 AW |
1885 | state); |
1886 | } | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | /* | |
1891 | * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. | |
1892 | * Also put INTx Disable in known state. | |
1893 | */ | |
1894 | cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); | |
1895 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | | |
1896 | PCI_COMMAND_INTX_DISABLE); | |
1897 | vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); | |
1898 | } | |
1899 | ||
9ee27d73 | 1900 | static void vfio_pci_post_reset(VFIOPCIDevice *vdev) |
f16f39c3 | 1901 | { |
870cb6f1 | 1902 | vfio_intx_enable(vdev); |
f16f39c3 AW |
1903 | } |
1904 | ||
7df9381b | 1905 | static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name) |
f16f39c3 | 1906 | { |
7df9381b AW |
1907 | char tmp[13]; |
1908 | ||
1909 | sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain, | |
1910 | addr->bus, addr->slot, addr->function); | |
1911 | ||
1912 | return (strcmp(tmp, name) == 0); | |
f16f39c3 AW |
1913 | } |
1914 | ||
9ee27d73 | 1915 | static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) |
f16f39c3 AW |
1916 | { |
1917 | VFIOGroup *group; | |
1918 | struct vfio_pci_hot_reset_info *info; | |
1919 | struct vfio_pci_dependent_device *devices; | |
1920 | struct vfio_pci_hot_reset *reset; | |
1921 | int32_t *fds; | |
1922 | int ret, i, count; | |
1923 | bool multi = false; | |
1924 | ||
df92ee44 | 1925 | trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); |
f16f39c3 AW |
1926 | |
1927 | vfio_pci_pre_reset(vdev); | |
b47d8efa | 1928 | vdev->vbasedev.needs_reset = false; |
f16f39c3 AW |
1929 | |
1930 | info = g_malloc0(sizeof(*info)); | |
1931 | info->argsz = sizeof(*info); | |
1932 | ||
5546a621 | 1933 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); |
f16f39c3 AW |
1934 | if (ret && errno != ENOSPC) { |
1935 | ret = -errno; | |
1936 | if (!vdev->has_pm_reset) { | |
7df9381b AW |
1937 | error_report("vfio: Cannot reset device %s, " |
1938 | "no available reset mechanism.", vdev->vbasedev.name); | |
f16f39c3 AW |
1939 | } |
1940 | goto out_single; | |
1941 | } | |
1942 | ||
1943 | count = info->count; | |
1944 | info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); | |
1945 | info->argsz = sizeof(*info) + (count * sizeof(*devices)); | |
1946 | devices = &info->devices[0]; | |
1947 | ||
5546a621 | 1948 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); |
f16f39c3 AW |
1949 | if (ret) { |
1950 | ret = -errno; | |
1951 | error_report("vfio: hot reset info failed: %m"); | |
1952 | goto out_single; | |
1953 | } | |
1954 | ||
df92ee44 | 1955 | trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); |
f16f39c3 AW |
1956 | |
1957 | /* Verify that we have all the groups required */ | |
1958 | for (i = 0; i < info->count; i++) { | |
1959 | PCIHostDeviceAddress host; | |
9ee27d73 | 1960 | VFIOPCIDevice *tmp; |
b47d8efa | 1961 | VFIODevice *vbasedev_iter; |
f16f39c3 AW |
1962 | |
1963 | host.domain = devices[i].segment; | |
1964 | host.bus = devices[i].bus; | |
1965 | host.slot = PCI_SLOT(devices[i].devfn); | |
1966 | host.function = PCI_FUNC(devices[i].devfn); | |
1967 | ||
385f57cf | 1968 | trace_vfio_pci_hot_reset_dep_devices(host.domain, |
f16f39c3 AW |
1969 | host.bus, host.slot, host.function, devices[i].group_id); |
1970 | ||
7df9381b | 1971 | if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { |
f16f39c3 AW |
1972 | continue; |
1973 | } | |
1974 | ||
62356b72 | 1975 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
1976 | if (group->groupid == devices[i].group_id) { |
1977 | break; | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | if (!group) { | |
1982 | if (!vdev->has_pm_reset) { | |
df92ee44 | 1983 | error_report("vfio: Cannot reset device %s, " |
f16f39c3 | 1984 | "depends on group %d which is not owned.", |
df92ee44 | 1985 | vdev->vbasedev.name, devices[i].group_id); |
f16f39c3 AW |
1986 | } |
1987 | ret = -EPERM; | |
1988 | goto out; | |
1989 | } | |
1990 | ||
1991 | /* Prep dependent devices for reset and clear our marker. */ | |
b47d8efa EA |
1992 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
1993 | if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { | |
1994 | continue; | |
1995 | } | |
1996 | tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); | |
7df9381b | 1997 | if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { |
f16f39c3 | 1998 | if (single) { |
f16f39c3 AW |
1999 | ret = -EINVAL; |
2000 | goto out_single; | |
2001 | } | |
2002 | vfio_pci_pre_reset(tmp); | |
b47d8efa | 2003 | tmp->vbasedev.needs_reset = false; |
f16f39c3 AW |
2004 | multi = true; |
2005 | break; | |
2006 | } | |
2007 | } | |
2008 | } | |
2009 | ||
2010 | if (!single && !multi) { | |
f16f39c3 AW |
2011 | ret = -EINVAL; |
2012 | goto out_single; | |
2013 | } | |
2014 | ||
2015 | /* Determine how many group fds need to be passed */ | |
2016 | count = 0; | |
62356b72 | 2017 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2018 | for (i = 0; i < info->count; i++) { |
2019 | if (group->groupid == devices[i].group_id) { | |
2020 | count++; | |
2021 | break; | |
2022 | } | |
2023 | } | |
2024 | } | |
2025 | ||
2026 | reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); | |
2027 | reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); | |
2028 | fds = &reset->group_fds[0]; | |
2029 | ||
2030 | /* Fill in group fds */ | |
62356b72 | 2031 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2032 | for (i = 0; i < info->count; i++) { |
2033 | if (group->groupid == devices[i].group_id) { | |
2034 | fds[reset->count++] = group->fd; | |
2035 | break; | |
2036 | } | |
2037 | } | |
2038 | } | |
2039 | ||
2040 | /* Bus reset! */ | |
5546a621 | 2041 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); |
f16f39c3 AW |
2042 | g_free(reset); |
2043 | ||
df92ee44 | 2044 | trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, |
385f57cf | 2045 | ret ? "%m" : "Success"); |
f16f39c3 AW |
2046 | |
2047 | out: | |
2048 | /* Re-enable INTx on affected devices */ | |
2049 | for (i = 0; i < info->count; i++) { | |
2050 | PCIHostDeviceAddress host; | |
9ee27d73 | 2051 | VFIOPCIDevice *tmp; |
b47d8efa | 2052 | VFIODevice *vbasedev_iter; |
f16f39c3 AW |
2053 | |
2054 | host.domain = devices[i].segment; | |
2055 | host.bus = devices[i].bus; | |
2056 | host.slot = PCI_SLOT(devices[i].devfn); | |
2057 | host.function = PCI_FUNC(devices[i].devfn); | |
2058 | ||
7df9381b | 2059 | if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { |
f16f39c3 AW |
2060 | continue; |
2061 | } | |
2062 | ||
62356b72 | 2063 | QLIST_FOREACH(group, &vfio_group_list, next) { |
f16f39c3 AW |
2064 | if (group->groupid == devices[i].group_id) { |
2065 | break; | |
2066 | } | |
2067 | } | |
2068 | ||
2069 | if (!group) { | |
2070 | break; | |
2071 | } | |
2072 | ||
b47d8efa EA |
2073 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2074 | if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { | |
2075 | continue; | |
2076 | } | |
2077 | tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); | |
7df9381b | 2078 | if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { |
f16f39c3 AW |
2079 | vfio_pci_post_reset(tmp); |
2080 | break; | |
2081 | } | |
2082 | } | |
2083 | } | |
2084 | out_single: | |
2085 | vfio_pci_post_reset(vdev); | |
2086 | g_free(info); | |
2087 | ||
2088 | return ret; | |
2089 | } | |
2090 | ||
2091 | /* | |
2092 | * We want to differentiate hot reset of mulitple in-use devices vs hot reset | |
2093 | * of a single in-use device. VFIO_DEVICE_RESET will already handle the case | |
2094 | * of doing hot resets when there is only a single device per bus. The in-use | |
2095 | * here refers to how many VFIODevices are affected. A hot reset that affects | |
2096 | * multiple devices, but only a single in-use device, means that we can call | |
2097 | * it from our bus ->reset() callback since the extent is effectively a single | |
2098 | * device. This allows us to make use of it in the hotplug path. When there | |
2099 | * are multiple in-use devices, we can only trigger the hot reset during a | |
2100 | * system reset and thus from our reset handler. We separate _one vs _multi | |
2101 | * here so that we don't overlap and do a double reset on the system reset | |
2102 | * path where both our reset handler and ->reset() callback are used. Calling | |
2103 | * _one() will only do a hot reset for the one in-use devices case, calling | |
2104 | * _multi() will do nothing if a _one() would have been sufficient. | |
2105 | */ | |
9ee27d73 | 2106 | static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) |
f16f39c3 AW |
2107 | { |
2108 | return vfio_pci_hot_reset(vdev, true); | |
2109 | } | |
2110 | ||
b47d8efa | 2111 | static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) |
f16f39c3 | 2112 | { |
b47d8efa | 2113 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); |
f16f39c3 AW |
2114 | return vfio_pci_hot_reset(vdev, false); |
2115 | } | |
2116 | ||
b47d8efa EA |
2117 | static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) |
2118 | { | |
2119 | VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); | |
2120 | if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { | |
2121 | vbasedev->needs_reset = true; | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | static VFIODeviceOps vfio_pci_ops = { | |
2126 | .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, | |
2127 | .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, | |
870cb6f1 | 2128 | .vfio_eoi = vfio_intx_eoi, |
b47d8efa EA |
2129 | }; |
2130 | ||
e593c021 AW |
2131 | int vfio_populate_vga(VFIOPCIDevice *vdev) |
2132 | { | |
2133 | VFIODevice *vbasedev = &vdev->vbasedev; | |
2134 | struct vfio_region_info *reg_info; | |
2135 | int ret; | |
2136 | ||
4225f2b6 AW |
2137 | ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info); |
2138 | if (ret) { | |
2139 | return ret; | |
2140 | } | |
e593c021 | 2141 | |
4225f2b6 AW |
2142 | if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) || |
2143 | !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) || | |
2144 | reg_info->size < 0xbffff + 1) { | |
2145 | error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx", | |
2146 | (unsigned long)reg_info->flags, | |
2147 | (unsigned long)reg_info->size); | |
2148 | g_free(reg_info); | |
2149 | return -EINVAL; | |
2150 | } | |
e593c021 | 2151 | |
4225f2b6 | 2152 | vdev->vga = g_new0(VFIOVGA, 1); |
e593c021 | 2153 | |
4225f2b6 AW |
2154 | vdev->vga->fd_offset = reg_info->offset; |
2155 | vdev->vga->fd = vdev->vbasedev.fd; | |
e593c021 | 2156 | |
4225f2b6 | 2157 | g_free(reg_info); |
e593c021 | 2158 | |
4225f2b6 AW |
2159 | vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; |
2160 | vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; | |
2161 | QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks); | |
e593c021 | 2162 | |
182bca45 AW |
2163 | memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem, |
2164 | OBJECT(vdev), &vfio_vga_ops, | |
2165 | &vdev->vga->region[QEMU_PCI_VGA_MEM], | |
2166 | "vfio-vga-mmio@0xa0000", | |
2167 | QEMU_PCI_VGA_MEM_SIZE); | |
2168 | ||
4225f2b6 AW |
2169 | vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; |
2170 | vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; | |
2171 | QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks); | |
e593c021 | 2172 | |
182bca45 AW |
2173 | memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, |
2174 | OBJECT(vdev), &vfio_vga_ops, | |
2175 | &vdev->vga->region[QEMU_PCI_VGA_IO_LO], | |
2176 | "vfio-vga-io@0x3b0", | |
2177 | QEMU_PCI_VGA_IO_LO_SIZE); | |
2178 | ||
4225f2b6 AW |
2179 | vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; |
2180 | vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; | |
2181 | QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks); | |
e593c021 | 2182 | |
182bca45 AW |
2183 | memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, |
2184 | OBJECT(vdev), &vfio_vga_ops, | |
2185 | &vdev->vga->region[QEMU_PCI_VGA_IO_HI], | |
2186 | "vfio-vga-io@0x3c0", | |
2187 | QEMU_PCI_VGA_IO_HI_SIZE); | |
2188 | ||
2189 | pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem, | |
2190 | &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, | |
2191 | &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem); | |
2192 | ||
e593c021 AW |
2193 | return 0; |
2194 | } | |
2195 | ||
217e9fdc | 2196 | static int vfio_populate_device(VFIOPCIDevice *vdev) |
65501a74 | 2197 | { |
217e9fdc | 2198 | VFIODevice *vbasedev = &vdev->vbasedev; |
46900226 | 2199 | struct vfio_region_info *reg_info; |
7b4b0e9e | 2200 | struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; |
d13dd2d7 | 2201 | int i, ret = -1; |
65501a74 AW |
2202 | |
2203 | /* Sanity check device */ | |
d13dd2d7 | 2204 | if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { |
312fd5f2 | 2205 | error_report("vfio: Um, this isn't a PCI device"); |
65501a74 AW |
2206 | goto error; |
2207 | } | |
2208 | ||
d13dd2d7 | 2209 | if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { |
312fd5f2 | 2210 | error_report("vfio: unexpected number of io regions %u", |
d13dd2d7 | 2211 | vbasedev->num_regions); |
65501a74 AW |
2212 | goto error; |
2213 | } | |
2214 | ||
d13dd2d7 EA |
2215 | if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { |
2216 | error_report("vfio: unexpected number of irqs %u", vbasedev->num_irqs); | |
65501a74 AW |
2217 | goto error; |
2218 | } | |
2219 | ||
2220 | for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { | |
db0da029 AW |
2221 | char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i); |
2222 | ||
2223 | ret = vfio_region_setup(OBJECT(vdev), vbasedev, | |
2224 | &vdev->bars[i].region, i, name); | |
2225 | g_free(name); | |
2226 | ||
65501a74 | 2227 | if (ret) { |
312fd5f2 | 2228 | error_report("vfio: Error getting region %d info: %m", i); |
65501a74 AW |
2229 | goto error; |
2230 | } | |
2231 | ||
7076eabc | 2232 | QLIST_INIT(&vdev->bars[i].quirks); |
46900226 | 2233 | } |
65501a74 | 2234 | |
46900226 AW |
2235 | ret = vfio_get_region_info(vbasedev, |
2236 | VFIO_PCI_CONFIG_REGION_INDEX, ®_info); | |
65501a74 | 2237 | if (ret) { |
312fd5f2 | 2238 | error_report("vfio: Error getting config info: %m"); |
65501a74 AW |
2239 | goto error; |
2240 | } | |
2241 | ||
d13dd2d7 | 2242 | trace_vfio_populate_device_config(vdev->vbasedev.name, |
46900226 AW |
2243 | (unsigned long)reg_info->size, |
2244 | (unsigned long)reg_info->offset, | |
2245 | (unsigned long)reg_info->flags); | |
65501a74 | 2246 | |
46900226 | 2247 | vdev->config_size = reg_info->size; |
6a659bbf AW |
2248 | if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { |
2249 | vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; | |
2250 | } | |
46900226 AW |
2251 | vdev->config_offset = reg_info->offset; |
2252 | ||
2253 | g_free(reg_info); | |
65501a74 | 2254 | |
e593c021 AW |
2255 | if (vdev->features & VFIO_FEATURE_ENABLE_VGA) { |
2256 | ret = vfio_populate_vga(vdev); | |
f15689c7 AW |
2257 | if (ret) { |
2258 | error_report( | |
2259 | "vfio: Device does not support requested feature x-vga"); | |
2260 | goto error; | |
2261 | } | |
f15689c7 | 2262 | } |
47cbe50c | 2263 | |
7b4b0e9e VMP |
2264 | irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; |
2265 | ||
5546a621 | 2266 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); |
7b4b0e9e VMP |
2267 | if (ret) { |
2268 | /* This can fail for an old kernel or legacy PCI dev */ | |
d13dd2d7 | 2269 | trace_vfio_populate_device_get_irq_info_failure(); |
7b4b0e9e VMP |
2270 | ret = 0; |
2271 | } else if (irq_info.count == 1) { | |
2272 | vdev->pci_aer = true; | |
2273 | } else { | |
df92ee44 | 2274 | error_report("vfio: %s " |
8fbf47c3 | 2275 | "Could not enable error recovery for the device", |
df92ee44 | 2276 | vbasedev->name); |
7b4b0e9e | 2277 | } |
f15689c7 | 2278 | |
d13dd2d7 EA |
2279 | error: |
2280 | return ret; | |
2281 | } | |
2282 | ||
9ee27d73 | 2283 | static void vfio_put_device(VFIOPCIDevice *vdev) |
65501a74 | 2284 | { |
462037c9 | 2285 | g_free(vdev->vbasedev.name); |
db0da029 AW |
2286 | g_free(vdev->msix); |
2287 | ||
d13dd2d7 | 2288 | vfio_put_base_device(&vdev->vbasedev); |
65501a74 AW |
2289 | } |
2290 | ||
7b4b0e9e VMP |
2291 | static void vfio_err_notifier_handler(void *opaque) |
2292 | { | |
9ee27d73 | 2293 | VFIOPCIDevice *vdev = opaque; |
7b4b0e9e VMP |
2294 | |
2295 | if (!event_notifier_test_and_clear(&vdev->err_notifier)) { | |
2296 | return; | |
2297 | } | |
2298 | ||
2299 | /* | |
2300 | * TBD. Retrieve the error details and decide what action | |
2301 | * needs to be taken. One of the actions could be to pass | |
2302 | * the error to the guest and have the guest driver recover | |
2303 | * from the error. This requires that PCIe capabilities be | |
2304 | * exposed to the guest. For now, we just terminate the | |
2305 | * guest to contain the error. | |
2306 | */ | |
2307 | ||
7df9381b | 2308 | error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name); |
7b4b0e9e | 2309 | |
ba29776f | 2310 | vm_stop(RUN_STATE_INTERNAL_ERROR); |
7b4b0e9e VMP |
2311 | } |
2312 | ||
2313 | /* | |
2314 | * Registers error notifier for devices supporting error recovery. | |
2315 | * If we encounter a failure in this function, we report an error | |
2316 | * and continue after disabling error recovery support for the | |
2317 | * device. | |
2318 | */ | |
9ee27d73 | 2319 | static void vfio_register_err_notifier(VFIOPCIDevice *vdev) |
7b4b0e9e VMP |
2320 | { |
2321 | int ret; | |
2322 | int argsz; | |
2323 | struct vfio_irq_set *irq_set; | |
2324 | int32_t *pfd; | |
2325 | ||
2326 | if (!vdev->pci_aer) { | |
2327 | return; | |
2328 | } | |
2329 | ||
2330 | if (event_notifier_init(&vdev->err_notifier, 0)) { | |
8fbf47c3 | 2331 | error_report("vfio: Unable to init event notifier for error detection"); |
7b4b0e9e VMP |
2332 | vdev->pci_aer = false; |
2333 | return; | |
2334 | } | |
2335 | ||
2336 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2337 | ||
2338 | irq_set = g_malloc0(argsz); | |
2339 | irq_set->argsz = argsz; | |
2340 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2341 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2342 | irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; | |
2343 | irq_set->start = 0; | |
2344 | irq_set->count = 1; | |
2345 | pfd = (int32_t *)&irq_set->data; | |
2346 | ||
2347 | *pfd = event_notifier_get_fd(&vdev->err_notifier); | |
2348 | qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); | |
2349 | ||
5546a621 | 2350 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
7b4b0e9e | 2351 | if (ret) { |
8fbf47c3 | 2352 | error_report("vfio: Failed to set up error notification"); |
7b4b0e9e VMP |
2353 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); |
2354 | event_notifier_cleanup(&vdev->err_notifier); | |
2355 | vdev->pci_aer = false; | |
2356 | } | |
2357 | g_free(irq_set); | |
2358 | } | |
2359 | ||
9ee27d73 | 2360 | static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) |
7b4b0e9e VMP |
2361 | { |
2362 | int argsz; | |
2363 | struct vfio_irq_set *irq_set; | |
2364 | int32_t *pfd; | |
2365 | int ret; | |
2366 | ||
2367 | if (!vdev->pci_aer) { | |
2368 | return; | |
2369 | } | |
2370 | ||
2371 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2372 | ||
2373 | irq_set = g_malloc0(argsz); | |
2374 | irq_set->argsz = argsz; | |
2375 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2376 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2377 | irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; | |
2378 | irq_set->start = 0; | |
2379 | irq_set->count = 1; | |
2380 | pfd = (int32_t *)&irq_set->data; | |
2381 | *pfd = -1; | |
2382 | ||
5546a621 | 2383 | ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); |
7b4b0e9e | 2384 | if (ret) { |
8fbf47c3 | 2385 | error_report("vfio: Failed to de-assign error fd: %m"); |
7b4b0e9e VMP |
2386 | } |
2387 | g_free(irq_set); | |
2388 | qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), | |
2389 | NULL, NULL, vdev); | |
2390 | event_notifier_cleanup(&vdev->err_notifier); | |
2391 | } | |
2392 | ||
47cbe50c AW |
2393 | static void vfio_req_notifier_handler(void *opaque) |
2394 | { | |
2395 | VFIOPCIDevice *vdev = opaque; | |
2396 | ||
2397 | if (!event_notifier_test_and_clear(&vdev->req_notifier)) { | |
2398 | return; | |
2399 | } | |
2400 | ||
2401 | qdev_unplug(&vdev->pdev.qdev, NULL); | |
2402 | } | |
2403 | ||
2404 | static void vfio_register_req_notifier(VFIOPCIDevice *vdev) | |
2405 | { | |
2406 | struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), | |
2407 | .index = VFIO_PCI_REQ_IRQ_INDEX }; | |
2408 | int argsz; | |
2409 | struct vfio_irq_set *irq_set; | |
2410 | int32_t *pfd; | |
2411 | ||
2412 | if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { | |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | if (ioctl(vdev->vbasedev.fd, | |
2417 | VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { | |
2418 | return; | |
2419 | } | |
2420 | ||
2421 | if (event_notifier_init(&vdev->req_notifier, 0)) { | |
2422 | error_report("vfio: Unable to init event notifier for device request"); | |
2423 | return; | |
2424 | } | |
2425 | ||
2426 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2427 | ||
2428 | irq_set = g_malloc0(argsz); | |
2429 | irq_set->argsz = argsz; | |
2430 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2431 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2432 | irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; | |
2433 | irq_set->start = 0; | |
2434 | irq_set->count = 1; | |
2435 | pfd = (int32_t *)&irq_set->data; | |
2436 | ||
2437 | *pfd = event_notifier_get_fd(&vdev->req_notifier); | |
2438 | qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); | |
2439 | ||
2440 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { | |
2441 | error_report("vfio: Failed to set up device request notification"); | |
2442 | qemu_set_fd_handler(*pfd, NULL, NULL, vdev); | |
2443 | event_notifier_cleanup(&vdev->req_notifier); | |
2444 | } else { | |
2445 | vdev->req_enabled = true; | |
2446 | } | |
2447 | ||
2448 | g_free(irq_set); | |
2449 | } | |
2450 | ||
2451 | static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) | |
2452 | { | |
2453 | int argsz; | |
2454 | struct vfio_irq_set *irq_set; | |
2455 | int32_t *pfd; | |
2456 | ||
2457 | if (!vdev->req_enabled) { | |
2458 | return; | |
2459 | } | |
2460 | ||
2461 | argsz = sizeof(*irq_set) + sizeof(*pfd); | |
2462 | ||
2463 | irq_set = g_malloc0(argsz); | |
2464 | irq_set->argsz = argsz; | |
2465 | irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | | |
2466 | VFIO_IRQ_SET_ACTION_TRIGGER; | |
2467 | irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; | |
2468 | irq_set->start = 0; | |
2469 | irq_set->count = 1; | |
2470 | pfd = (int32_t *)&irq_set->data; | |
2471 | *pfd = -1; | |
2472 | ||
2473 | if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { | |
2474 | error_report("vfio: Failed to de-assign device request fd: %m"); | |
2475 | } | |
2476 | g_free(irq_set); | |
2477 | qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), | |
2478 | NULL, NULL, vdev); | |
2479 | event_notifier_cleanup(&vdev->req_notifier); | |
2480 | ||
2481 | vdev->req_enabled = false; | |
2482 | } | |
2483 | ||
65501a74 AW |
2484 | static int vfio_initfn(PCIDevice *pdev) |
2485 | { | |
b47d8efa EA |
2486 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
2487 | VFIODevice *vbasedev_iter; | |
65501a74 | 2488 | VFIOGroup *group; |
7df9381b | 2489 | char *tmp, group_path[PATH_MAX], *group_name; |
65501a74 AW |
2490 | ssize_t len; |
2491 | struct stat st; | |
2492 | int groupid; | |
581406e0 | 2493 | int i, ret; |
65501a74 | 2494 | |
7df9381b AW |
2495 | if (!vdev->vbasedev.sysfsdev) { |
2496 | vdev->vbasedev.sysfsdev = | |
2497 | g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x", | |
2498 | vdev->host.domain, vdev->host.bus, | |
2499 | vdev->host.slot, vdev->host.function); | |
2500 | } | |
2501 | ||
2502 | if (stat(vdev->vbasedev.sysfsdev, &st) < 0) { | |
2503 | error_report("vfio: error: no such host device: %s", | |
2504 | vdev->vbasedev.sysfsdev); | |
65501a74 AW |
2505 | return -errno; |
2506 | } | |
2507 | ||
7df9381b | 2508 | vdev->vbasedev.name = g_strdup(basename(vdev->vbasedev.sysfsdev)); |
b47d8efa | 2509 | vdev->vbasedev.ops = &vfio_pci_ops; |
462037c9 | 2510 | vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; |
462037c9 | 2511 | |
7df9381b AW |
2512 | tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev); |
2513 | len = readlink(tmp, group_path, sizeof(group_path)); | |
2514 | g_free(tmp); | |
65501a74 | 2515 | |
7df9381b | 2516 | if (len <= 0 || len >= sizeof(group_path)) { |
312fd5f2 | 2517 | error_report("vfio: error no iommu_group for device"); |
c6d231e2 | 2518 | return len < 0 ? -errno : -ENAMETOOLONG; |
65501a74 AW |
2519 | } |
2520 | ||
7df9381b | 2521 | group_path[len] = 0; |
65501a74 | 2522 | |
7df9381b | 2523 | group_name = basename(group_path); |
65501a74 | 2524 | if (sscanf(group_name, "%d", &groupid) != 1) { |
7df9381b | 2525 | error_report("vfio: error reading %s: %m", group_path); |
65501a74 AW |
2526 | return -errno; |
2527 | } | |
2528 | ||
df92ee44 | 2529 | trace_vfio_initfn(vdev->vbasedev.name, groupid); |
65501a74 | 2530 | |
0688448b | 2531 | group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev)); |
65501a74 | 2532 | if (!group) { |
312fd5f2 | 2533 | error_report("vfio: failed to get group %d", groupid); |
65501a74 AW |
2534 | return -ENOENT; |
2535 | } | |
2536 | ||
b47d8efa EA |
2537 | QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { |
2538 | if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { | |
7df9381b AW |
2539 | error_report("vfio: error: device %s is already attached", |
2540 | vdev->vbasedev.name); | |
65501a74 AW |
2541 | vfio_put_group(group); |
2542 | return -EBUSY; | |
2543 | } | |
2544 | } | |
2545 | ||
7df9381b | 2546 | ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev); |
65501a74 | 2547 | if (ret) { |
7df9381b | 2548 | error_report("vfio: failed to get device %s", vdev->vbasedev.name); |
65501a74 AW |
2549 | vfio_put_group(group); |
2550 | return ret; | |
2551 | } | |
2552 | ||
217e9fdc PB |
2553 | ret = vfio_populate_device(vdev); |
2554 | if (ret) { | |
77a10d04 | 2555 | return ret; |
217e9fdc PB |
2556 | } |
2557 | ||
65501a74 | 2558 | /* Get a copy of config space */ |
5546a621 | 2559 | ret = pread(vdev->vbasedev.fd, vdev->pdev.config, |
65501a74 AW |
2560 | MIN(pci_config_size(&vdev->pdev), vdev->config_size), |
2561 | vdev->config_offset); | |
2562 | if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { | |
2563 | ret = ret < 0 ? -errno : -EFAULT; | |
312fd5f2 | 2564 | error_report("vfio: Failed to read device config space"); |
77a10d04 | 2565 | return ret; |
65501a74 AW |
2566 | } |
2567 | ||
4b5d5e87 AW |
2568 | /* vfio emulates a lot for us, but some bits need extra love */ |
2569 | vdev->emulated_config_bits = g_malloc0(vdev->config_size); | |
2570 | ||
2571 | /* QEMU can choose to expose the ROM or not */ | |
2572 | memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); | |
2573 | ||
89dcccc5 AW |
2574 | /* |
2575 | * The PCI spec reserves vendor ID 0xffff as an invalid value. The | |
2576 | * device ID is managed by the vendor and need only be a 16-bit value. | |
2577 | * Allow any 16-bit value for subsystem so they can be hidden or changed. | |
2578 | */ | |
2579 | if (vdev->vendor_id != PCI_ANY_ID) { | |
2580 | if (vdev->vendor_id >= 0xffff) { | |
2581 | error_report("vfio: Invalid PCI vendor ID provided"); | |
2582 | return -EINVAL; | |
2583 | } | |
2584 | vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); | |
2585 | trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); | |
2586 | } else { | |
2587 | vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); | |
2588 | } | |
2589 | ||
2590 | if (vdev->device_id != PCI_ANY_ID) { | |
2591 | if (vdev->device_id > 0xffff) { | |
2592 | error_report("vfio: Invalid PCI device ID provided"); | |
2593 | return -EINVAL; | |
2594 | } | |
2595 | vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); | |
2596 | trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); | |
2597 | } else { | |
2598 | vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); | |
2599 | } | |
2600 | ||
2601 | if (vdev->sub_vendor_id != PCI_ANY_ID) { | |
2602 | if (vdev->sub_vendor_id > 0xffff) { | |
2603 | error_report("vfio: Invalid PCI subsystem vendor ID provided"); | |
2604 | return -EINVAL; | |
2605 | } | |
2606 | vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, | |
2607 | vdev->sub_vendor_id, ~0); | |
2608 | trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, | |
2609 | vdev->sub_vendor_id); | |
2610 | } | |
2611 | ||
2612 | if (vdev->sub_device_id != PCI_ANY_ID) { | |
2613 | if (vdev->sub_device_id > 0xffff) { | |
2614 | error_report("vfio: Invalid PCI subsystem device ID provided"); | |
2615 | return -EINVAL; | |
2616 | } | |
2617 | vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); | |
2618 | trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, | |
2619 | vdev->sub_device_id); | |
2620 | } | |
ff635e37 | 2621 | |
4b5d5e87 AW |
2622 | /* QEMU can change multi-function devices to single function, or reverse */ |
2623 | vdev->emulated_config_bits[PCI_HEADER_TYPE] = | |
2624 | PCI_HEADER_TYPE_MULTI_FUNCTION; | |
2625 | ||
187d6232 AW |
2626 | /* Restore or clear multifunction, this is always controlled by QEMU */ |
2627 | if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { | |
2628 | vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; | |
2629 | } else { | |
2630 | vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; | |
2631 | } | |
2632 | ||
65501a74 AW |
2633 | /* |
2634 | * Clear host resource mapping info. If we choose not to register a | |
2635 | * BAR, such as might be the case with the option ROM, we can get | |
2636 | * confusing, unwritable, residual addresses from the host here. | |
2637 | */ | |
2638 | memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); | |
2639 | memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); | |
2640 | ||
6f864e6e | 2641 | vfio_pci_size_rom(vdev); |
65501a74 | 2642 | |
0de70dc7 | 2643 | ret = vfio_msix_early_setup(vdev); |
65501a74 | 2644 | if (ret) { |
77a10d04 | 2645 | return ret; |
65501a74 AW |
2646 | } |
2647 | ||
2d82f8a3 | 2648 | vfio_bars_setup(vdev); |
65501a74 AW |
2649 | |
2650 | ret = vfio_add_capabilities(vdev); | |
2651 | if (ret) { | |
2652 | goto out_teardown; | |
2653 | } | |
2654 | ||
182bca45 AW |
2655 | if (vdev->vga) { |
2656 | vfio_vga_quirk_setup(vdev); | |
2657 | } | |
2658 | ||
581406e0 AW |
2659 | for (i = 0; i < PCI_ROM_SLOT; i++) { |
2660 | vfio_bar_quirk_setup(vdev, i); | |
2661 | } | |
2662 | ||
6ced0bba AW |
2663 | if (!vdev->igd_opregion && |
2664 | vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) { | |
2665 | struct vfio_region_info *opregion; | |
2666 | ||
2667 | if (vdev->pdev.qdev.hotplugged) { | |
2668 | error_report("Cannot support IGD OpRegion feature on hotplugged " | |
2669 | "device %s", vdev->vbasedev.name); | |
2670 | ret = -EINVAL; | |
2671 | goto out_teardown; | |
2672 | } | |
2673 | ||
2674 | ret = vfio_get_dev_region_info(&vdev->vbasedev, | |
2675 | VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, | |
2676 | VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); | |
2677 | if (ret) { | |
2678 | error_report("Device %s does not support requested IGD OpRegion " | |
2679 | "feature", vdev->vbasedev.name); | |
2680 | goto out_teardown; | |
2681 | } | |
2682 | ||
2683 | ret = vfio_pci_igd_opregion_init(vdev, opregion); | |
2684 | g_free(opregion); | |
2685 | if (ret) { | |
2686 | error_report("Device %s IGD OpRegion initialization failed", | |
2687 | vdev->vbasedev.name); | |
2688 | goto out_teardown; | |
2689 | } | |
2690 | } | |
2691 | ||
4b5d5e87 AW |
2692 | /* QEMU emulates all of MSI & MSIX */ |
2693 | if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { | |
2694 | memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, | |
2695 | MSIX_CAP_LENGTH); | |
2696 | } | |
2697 | ||
2698 | if (pdev->cap_present & QEMU_PCI_CAP_MSI) { | |
2699 | memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, | |
2700 | vdev->msi_cap_size); | |
2701 | } | |
2702 | ||
65501a74 | 2703 | if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { |
bc72ad67 | 2704 | vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, |
ea486926 | 2705 | vfio_intx_mmap_enable, vdev); |
870cb6f1 AW |
2706 | pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); |
2707 | ret = vfio_intx_enable(vdev); | |
65501a74 AW |
2708 | if (ret) { |
2709 | goto out_teardown; | |
2710 | } | |
2711 | } | |
2712 | ||
7b4b0e9e | 2713 | vfio_register_err_notifier(vdev); |
47cbe50c | 2714 | vfio_register_req_notifier(vdev); |
c9c50009 | 2715 | vfio_setup_resetfn_quirk(vdev); |
c29029dd | 2716 | |
65501a74 AW |
2717 | return 0; |
2718 | ||
2719 | out_teardown: | |
2720 | pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); | |
2721 | vfio_teardown_msi(vdev); | |
2d82f8a3 | 2722 | vfio_bars_exit(vdev); |
77a10d04 PB |
2723 | return ret; |
2724 | } | |
2725 | ||
2726 | static void vfio_instance_finalize(Object *obj) | |
2727 | { | |
2728 | PCIDevice *pci_dev = PCI_DEVICE(obj); | |
2729 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pci_dev); | |
2730 | VFIOGroup *group = vdev->vbasedev.group; | |
2731 | ||
2d82f8a3 | 2732 | vfio_bars_finalize(vdev); |
4b5d5e87 | 2733 | g_free(vdev->emulated_config_bits); |
77a10d04 | 2734 | g_free(vdev->rom); |
c4c45e94 AW |
2735 | /* |
2736 | * XXX Leaking igd_opregion is not an oversight, we can't remove the | |
2737 | * fw_cfg entry therefore leaking this allocation seems like the safest | |
2738 | * option. | |
2739 | * | |
2740 | * g_free(vdev->igd_opregion); | |
2741 | */ | |
65501a74 AW |
2742 | vfio_put_device(vdev); |
2743 | vfio_put_group(group); | |
65501a74 AW |
2744 | } |
2745 | ||
2746 | static void vfio_exitfn(PCIDevice *pdev) | |
2747 | { | |
9ee27d73 | 2748 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 2749 | |
47cbe50c | 2750 | vfio_unregister_req_notifier(vdev); |
7b4b0e9e | 2751 | vfio_unregister_err_notifier(vdev); |
65501a74 AW |
2752 | pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); |
2753 | vfio_disable_interrupts(vdev); | |
ea486926 | 2754 | if (vdev->intx.mmap_timer) { |
bc72ad67 | 2755 | timer_free(vdev->intx.mmap_timer); |
ea486926 | 2756 | } |
65501a74 | 2757 | vfio_teardown_msi(vdev); |
2d82f8a3 | 2758 | vfio_bars_exit(vdev); |
65501a74 AW |
2759 | } |
2760 | ||
2761 | static void vfio_pci_reset(DeviceState *dev) | |
2762 | { | |
2763 | PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev); | |
9ee27d73 | 2764 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); |
65501a74 | 2765 | |
df92ee44 | 2766 | trace_vfio_pci_reset(vdev->vbasedev.name); |
5834a83f | 2767 | |
f16f39c3 | 2768 | vfio_pci_pre_reset(vdev); |
ba661818 | 2769 | |
5655f931 AW |
2770 | if (vdev->resetfn && !vdev->resetfn(vdev)) { |
2771 | goto post_reset; | |
2772 | } | |
2773 | ||
b47d8efa EA |
2774 | if (vdev->vbasedev.reset_works && |
2775 | (vdev->has_flr || !vdev->has_pm_reset) && | |
5546a621 | 2776 | !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { |
df92ee44 | 2777 | trace_vfio_pci_reset_flr(vdev->vbasedev.name); |
f16f39c3 | 2778 | goto post_reset; |
ba661818 AW |
2779 | } |
2780 | ||
f16f39c3 AW |
2781 | /* See if we can do our own bus reset */ |
2782 | if (!vfio_pci_hot_reset_one(vdev)) { | |
2783 | goto post_reset; | |
2784 | } | |
5834a83f | 2785 | |
f16f39c3 | 2786 | /* If nothing else works and the device supports PM reset, use it */ |
b47d8efa | 2787 | if (vdev->vbasedev.reset_works && vdev->has_pm_reset && |
5546a621 | 2788 | !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { |
df92ee44 | 2789 | trace_vfio_pci_reset_pm(vdev->vbasedev.name); |
f16f39c3 | 2790 | goto post_reset; |
65501a74 | 2791 | } |
5834a83f | 2792 | |
f16f39c3 AW |
2793 | post_reset: |
2794 | vfio_pci_post_reset(vdev); | |
65501a74 AW |
2795 | } |
2796 | ||
abc5b3bf GA |
2797 | static void vfio_instance_init(Object *obj) |
2798 | { | |
2799 | PCIDevice *pci_dev = PCI_DEVICE(obj); | |
9ee27d73 | 2800 | VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, PCI_DEVICE(obj)); |
abc5b3bf GA |
2801 | |
2802 | device_add_bootindex_property(obj, &vdev->bootindex, | |
2803 | "bootindex", NULL, | |
2804 | &pci_dev->qdev, NULL); | |
2805 | } | |
2806 | ||
65501a74 | 2807 | static Property vfio_pci_dev_properties[] = { |
9ee27d73 | 2808 | DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), |
7df9381b | 2809 | DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev), |
9ee27d73 | 2810 | DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, |
ea486926 | 2811 | intx.mmap_timeout, 1100), |
9ee27d73 | 2812 | DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, |
f15689c7 | 2813 | VFIO_FEATURE_ENABLE_VGA_BIT, false), |
47cbe50c AW |
2814 | DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, |
2815 | VFIO_FEATURE_ENABLE_REQ_BIT, true), | |
6ced0bba AW |
2816 | DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features, |
2817 | VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false), | |
5e15d79b | 2818 | DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false), |
46746dba AW |
2819 | DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false), |
2820 | DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false), | |
2821 | DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false), | |
89dcccc5 AW |
2822 | DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID), |
2823 | DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID), | |
2824 | DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice, | |
2825 | sub_vendor_id, PCI_ANY_ID), | |
2826 | DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, | |
2827 | sub_device_id, PCI_ANY_ID), | |
c4c45e94 | 2828 | DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), |
65501a74 AW |
2829 | /* |
2830 | * TODO - support passed fds... is this necessary? | |
9ee27d73 EA |
2831 | * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), |
2832 | * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), | |
65501a74 AW |
2833 | */ |
2834 | DEFINE_PROP_END_OF_LIST(), | |
2835 | }; | |
2836 | ||
d9f0e638 AW |
2837 | static const VMStateDescription vfio_pci_vmstate = { |
2838 | .name = "vfio-pci", | |
2839 | .unmigratable = 1, | |
2840 | }; | |
65501a74 AW |
2841 | |
2842 | static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) | |
2843 | { | |
2844 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2845 | PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); | |
2846 | ||
2847 | dc->reset = vfio_pci_reset; | |
2848 | dc->props = vfio_pci_dev_properties; | |
d9f0e638 AW |
2849 | dc->vmsd = &vfio_pci_vmstate; |
2850 | dc->desc = "VFIO-based PCI device assignment"; | |
125ee0ed | 2851 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
65501a74 AW |
2852 | pdc->init = vfio_initfn; |
2853 | pdc->exit = vfio_exitfn; | |
2854 | pdc->config_read = vfio_pci_read_config; | |
2855 | pdc->config_write = vfio_pci_write_config; | |
6a659bbf | 2856 | pdc->is_express = 1; /* We might be */ |
65501a74 AW |
2857 | } |
2858 | ||
2859 | static const TypeInfo vfio_pci_dev_info = { | |
2860 | .name = "vfio-pci", | |
2861 | .parent = TYPE_PCI_DEVICE, | |
9ee27d73 | 2862 | .instance_size = sizeof(VFIOPCIDevice), |
65501a74 | 2863 | .class_init = vfio_pci_dev_class_init, |
abc5b3bf | 2864 | .instance_init = vfio_instance_init, |
77a10d04 | 2865 | .instance_finalize = vfio_instance_finalize, |
65501a74 AW |
2866 | }; |
2867 | ||
2868 | static void register_vfio_pci_dev_type(void) | |
2869 | { | |
2870 | type_register_static(&vfio_pci_dev_info); | |
2871 | } | |
2872 | ||
2873 | type_init(register_vfio_pci_dev_type) |