[mirror_qemu.git] / hw / vfio / pci.h

/*
 * vfio based device assignment support - PCI devices
 *
 * Copyright Red Hat, Inc. 2012-2015
 *
 * Authors:
 *  Alex Williamson <alex.williamson@redhat.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */
#ifndef HW_VFIO_VFIO_PCI_H
#define HW_VFIO_VFIO_PCI_H

#include "exec/memory.h"
#include "hw/pci/pci.h"
#include "hw/vfio/vfio-common.h"
#include "qemu/event_notifier.h"
#include "qemu/queue.h"
#include "qemu/timer.h"
#include "qom/object.h"

#define PCI_ANY_ID (~0)

struct VFIOPCIDevice;

typedef struct VFIOIOEventFD {
    QLIST_ENTRY(VFIOIOEventFD) next;
    MemoryRegion *mr;
    hwaddr addr;
    unsigned size;
    uint64_t data;
    EventNotifier e;
    VFIORegion *region;
    hwaddr region_addr;
    bool dynamic; /* Added runtime, removed on device reset */
    bool vfio;
} VFIOIOEventFD;

typedef struct VFIOQuirk {
    QLIST_ENTRY(VFIOQuirk) next;
    void *data;
    QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
    int nr_mem;
    MemoryRegion *mem;
    void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
} VFIOQuirk;

typedef struct VFIOBAR {
    VFIORegion region;
    MemoryRegion *mr;
    size_t size;
    uint8_t type;
    bool ioport;
    bool mem64;
    QLIST_HEAD(, VFIOQuirk) quirks;
} VFIOBAR;

typedef struct VFIOVGARegion {
    MemoryRegion mem;
    off_t offset;
    int nr;
    QLIST_HEAD(, VFIOQuirk) quirks;
} VFIOVGARegion;

typedef struct VFIOVGA {
    off_t fd_offset;
    int fd;
    VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
} VFIOVGA;

typedef struct VFIOINTx {
    bool pending; /* interrupt pending */
    bool kvm_accel; /* set when QEMU bypass through KVM enabled */
    uint8_t pin; /* which pin to pull for qemu_set_irq */
    EventNotifier interrupt; /* eventfd triggered on interrupt */
    EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
    PCIINTxRoute route; /* routing info for QEMU bypass */
    uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
    QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */
} VFIOINTx;

typedef struct VFIOMSIVector {
    /*
     * Two interrupt paths are configured per vector.  The first, is only used
     * for interrupts injected via QEMU.  This is typically the non-accel path,
     * but may also be used when we want QEMU to handle masking and pending
     * bits.  The KVM path bypasses QEMU and is therefore higher performance,
     * but requires masking at the device.  virq is used to track the MSI route
     * through KVM, thus kvm_interrupt is only available when virq is set to a
     * valid (>= 0) value.
     */
    EventNotifier interrupt;
    EventNotifier kvm_interrupt;
    struct VFIOPCIDevice *vdev; /* back pointer to device */
    int virq;
    bool use;
} VFIOMSIVector;

enum {
    VFIO_INT_NONE = 0,
    VFIO_INT_INTx = 1,
    VFIO_INT_MSI  = 2,
    VFIO_INT_MSIX = 3,
};

/* Cache of MSI-X setup */
typedef struct VFIOMSIXInfo {
    uint8_t table_bar;
    uint8_t pba_bar;
    uint16_t entries;
    uint32_t table_offset;
    uint32_t pba_offset;
    unsigned long *pending;
} VFIOMSIXInfo;

#define TYPE_VFIO_PCI "vfio-pci"
typedef struct VFIOPCIDevice VFIOPCIDevice;
#define PCI_VFIO(obj)    OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI)

struct VFIOPCIDevice {
    PCIDevice pdev;
    VFIODevice vbasedev;
    VFIOINTx intx;
    unsigned int config_size;
    uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */
    off_t config_offset; /* Offset of config space region within device fd */
    unsigned int rom_size;
    off_t rom_offset; /* Offset of ROM region within device fd */
    void *rom;
    int msi_cap_size;
    VFIOMSIVector *msi_vectors;
    VFIOMSIXInfo *msix;
    int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
    int interrupt; /* Current interrupt type */
    VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
    VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */
    void *igd_opregion;
    PCIHostDeviceAddress host;
    EventNotifier err_notifier;
    EventNotifier req_notifier;
    int (*resetfn)(struct VFIOPCIDevice *);
    uint32_t vendor_id;
    uint32_t device_id;
    uint32_t sub_vendor_id;
    uint32_t sub_device_id;
    uint32_t features;
#define VFIO_FEATURE_ENABLE_VGA_BIT 0
#define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
#define VFIO_FEATURE_ENABLE_REQ_BIT 1
#define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
#define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
#define VFIO_FEATURE_ENABLE_IGD_OPREGION \
                                (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
    OnOffAuto display;
    uint32_t display_xres;
    uint32_t display_yres;
    int32_t bootindex;
    uint32_t igd_gms;
    OffAutoPCIBAR msix_relo;
    uint8_t pm_cap;
    uint8_t nv_gpudirect_clique;
    bool pci_aer;
    bool req_enabled;
    bool has_flr;
    bool has_pm_reset;
    bool rom_read_failed;
    bool no_kvm_intx;
    bool no_kvm_msi;
    bool no_kvm_msix;
    bool no_geforce_quirks;
    bool no_kvm_ioeventfd;
    bool no_vfio_ioeventfd;
    bool enable_ramfb;
    VFIODisplay *dpy;
    Error *migration_blocker;
    Notifier irqchip_change_notifier;
};

/* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */
static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device)
{
    return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) &&
           (device == PCI_ANY_ID || device == vdev->device_id);
}

static inline bool vfio_is_vga(VFIOPCIDevice *vdev)
{
    PCIDevice *pdev = &vdev->pdev;
    uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);

    return class == PCI_CLASS_DISPLAY_VGA;
}

uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
void vfio_pci_write_config(PCIDevice *pdev,
                           uint32_t addr, uint32_t val, int len);

uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);

bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev);
void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
void vfio_quirk_reset(VFIOPCIDevice *vdev);
VFIOQuirk *vfio_quirk_alloc(int nr_mem);
void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr);

extern const PropertyInfo qdev_prop_nv_gpudirect_clique;

int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);

int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
                               struct vfio_region_info *info,
                               Error **errp);
int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp);
int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp);

void vfio_display_reset(VFIOPCIDevice *vdev);
int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
void vfio_display_finalize(VFIOPCIDevice *vdev);

#endif /* HW_VFIO_VFIO_PCI_H */
Commit	Line	Data
78f33d2b AW	1	/*
	2	* vfio based device assignment support - PCI devices
	3	*
	4	* Copyright Red Hat, Inc. 2012-2015
	5	*
	6	* Authors:
	7	* Alex Williamson <alex.williamson@redhat.com>
	8	*
	9	* This work is licensed under the terms of the GNU GPL, version 2. See
	10	* the COPYING file in the top-level directory.
	11	*/
	12	#ifndef HW_VFIO_VFIO_PCI_H
	13	#define HW_VFIO_VFIO_PCI_H
	14
78f33d2b AW	15	#include "exec/memory.h"
	16	#include "hw/pci/pci.h"
	17	#include "hw/vfio/vfio-common.h"
	18	#include "qemu/event_notifier.h"
	19	#include "qemu/queue.h"
	20	#include "qemu/timer.h"
db1015e9	21	#include "qom/object.h"
78f33d2b	22
89dcccc5 AW	23	#define PCI_ANY_ID (~0)
89dcccc5 AW	24
78f33d2b AW	25	struct VFIOPCIDevice;
78f33d2b AW	26
c958c51d AW	27	typedef struct VFIOIOEventFD {
	28	QLIST_ENTRY(VFIOIOEventFD) next;
	29	MemoryRegion *mr;
	30	hwaddr addr;
	31	unsigned size;
	32	uint64_t data;
	33	EventNotifier e;
	34	VFIORegion *region;
	35	hwaddr region_addr;
	36	bool dynamic; /* Added runtime, removed on device reset */
2b1dbd0d	37	bool vfio;
c958c51d AW	38	} VFIOIOEventFD;
c958c51d AW	39
8c4f2348 AW	40	typedef struct VFIOQuirk {
	41	QLIST_ENTRY(VFIOQuirk) next;
	42	void *data;
c958c51d	43	QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
8c4f2348 AW	44	int nr_mem;
8c4f2348 AW	45	MemoryRegion *mem;
469d02de	46	void (reset)(struct VFIOPCIDevice vdev, struct VFIOQuirk *quirk);
78f33d2b AW	47	} VFIOQuirk;
	48
	49	typedef struct VFIOBAR {
	50	VFIORegion region;
3a286732 AW	51	MemoryRegion *mr;
	52	size_t size;
	53	uint8_t type;
78f33d2b AW	54	bool ioport;
	55	bool mem64;
	56	QLIST_HEAD(, VFIOQuirk) quirks;
	57	} VFIOBAR;
	58
	59	typedef struct VFIOVGARegion {
	60	MemoryRegion mem;
	61	off_t offset;
	62	int nr;
	63	QLIST_HEAD(, VFIOQuirk) quirks;
	64	} VFIOVGARegion;
	65
	66	typedef struct VFIOVGA {
	67	off_t fd_offset;
	68	int fd;
	69	VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
	70	} VFIOVGA;
	71
	72	typedef struct VFIOINTx {
	73	bool pending; /* interrupt pending */
	74	bool kvm_accel; /* set when QEMU bypass through KVM enabled */
	75	uint8_t pin; /* which pin to pull for qemu_set_irq */
	76	EventNotifier interrupt; /* eventfd triggered on interrupt */
	77	EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
	78	PCIINTxRoute route; /* routing info for QEMU bypass */
	79	uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
	80	QEMUTimer mmap_timer; / enable mmaps after periods w/o interrupts */
	81	} VFIOINTx;
	82
	83	typedef struct VFIOMSIVector {
	84	/*
	85	* Two interrupt paths are configured per vector. The first, is only used
	86	* for interrupts injected via QEMU. This is typically the non-accel path,
	87	* but may also be used when we want QEMU to handle masking and pending
	88	* bits. The KVM path bypasses QEMU and is therefore higher performance,
	89	* but requires masking at the device. virq is used to track the MSI route
	90	* through KVM, thus kvm_interrupt is only available when virq is set to a
	91	* valid (>= 0) value.
	92	*/
	93	EventNotifier interrupt;
	94	EventNotifier kvm_interrupt;
	95	struct VFIOPCIDevice vdev; / back pointer to device */
	96	int virq;
	97	bool use;
	98	} VFIOMSIVector;
	99
	100	enum {
	101	VFIO_INT_NONE = 0,
	102	VFIO_INT_INTx = 1,
	103	VFIO_INT_MSI = 2,
	104	VFIO_INT_MSIX = 3,
	105	};
	106
edd09278	107	/* Cache of MSI-X setup */
78f33d2b AW	108	typedef struct VFIOMSIXInfo {
	109	uint8_t table_bar;
	110	uint8_t pba_bar;
	111	uint16_t entries;
	112	uint32_t table_offset;
	113	uint32_t pba_offset;
95239e16	114	unsigned long *pending;
78f33d2b AW	115	} VFIOMSIXInfo;
78f33d2b AW	116
42db0fb5	117	#define TYPE_VFIO_PCI "vfio-pci"
db1015e9	118	typedef struct VFIOPCIDevice VFIOPCIDevice;
42db0fb5 EH	119	#define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI)
42db0fb5 EH	120
db1015e9	121	struct VFIOPCIDevice {
78f33d2b AW	122	PCIDevice pdev;
	123	VFIODevice vbasedev;
	124	VFIOINTx intx;
	125	unsigned int config_size;
	126	uint8_t emulated_config_bits; / QEMU emulated bits, little-endian */
	127	off_t config_offset; /* Offset of config space region within device fd */
	128	unsigned int rom_size;
	129	off_t rom_offset; /* Offset of ROM region within device fd */
	130	void *rom;
	131	int msi_cap_size;
	132	VFIOMSIVector *msi_vectors;
	133	VFIOMSIXInfo *msix;
	134	int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
	135	int interrupt; /* Current interrupt type */
	136	VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
2d82f8a3	137	VFIOVGA vga; / 0xa0000, 0x3b0, 0x3c0 */
c4c45e94	138	void *igd_opregion;
78f33d2b AW	139	PCIHostDeviceAddress host;
	140	EventNotifier err_notifier;
	141	EventNotifier req_notifier;
	142	int (resetfn)(struct VFIOPCIDevice );
89dcccc5 AW	143	uint32_t vendor_id;
	144	uint32_t device_id;
	145	uint32_t sub_vendor_id;
	146	uint32_t sub_device_id;
78f33d2b AW	147	uint32_t features;
	148	#define VFIO_FEATURE_ENABLE_VGA_BIT 0
	149	#define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
	150	#define VFIO_FEATURE_ENABLE_REQ_BIT 1
	151	#define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
6ced0bba AW	152	#define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
	153	#define VFIO_FEATURE_ENABLE_IGD_OPREGION \
	154	(1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
a9994687	155	OnOffAuto display;
c62a0c7c GH	156	uint32_t display_xres;
c62a0c7c GH	157	uint32_t display_yres;
78f33d2b	158	int32_t bootindex;
c4c45e94	159	uint32_t igd_gms;
89d5202e	160	OffAutoPCIBAR msix_relo;
78f33d2b	161	uint8_t pm_cap;
dfbee78d	162	uint8_t nv_gpudirect_clique;
78f33d2b AW	163	bool pci_aer;
	164	bool req_enabled;
	165	bool has_flr;
	166	bool has_pm_reset;
	167	bool rom_read_failed;
	168	bool no_kvm_intx;
	169	bool no_kvm_msi;
	170	bool no_kvm_msix;
db32d0f4	171	bool no_geforce_quirks;
c958c51d	172	bool no_kvm_ioeventfd;
2b1dbd0d	173	bool no_vfio_ioeventfd;
b290659f	174	bool enable_ramfb;
00195ba7	175	VFIODisplay *dpy;
f045a010	176	Error *migration_blocker;
c5478fea	177	Notifier irqchip_change_notifier;
db1015e9	178	};
78f33d2b	179
29d62771 TH	180	/* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */
	181	static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device)
	182	{
	183	return (vendor == PCI_ANY_ID \|\| vendor == vdev->vendor_id) &&
	184	(device == PCI_ANY_ID \|\| device == vdev->device_id);
	185	}
	186
	187	static inline bool vfio_is_vga(VFIOPCIDevice *vdev)
	188	{
	189	PCIDevice *pdev = &vdev->pdev;
	190	uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
	191
	192	return class == PCI_CLASS_DISPLAY_VGA;
	193	}
	194
c00d61d8 AW	195	uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
	196	void vfio_pci_write_config(PCIDevice *pdev,
	197	uint32_t addr, uint32_t val, int len);
	198
	199	uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
	200	void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
	201
	202	bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev);
	203	void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
2d82f8a3 AW	204	void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
2d82f8a3 AW	205	void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
c00d61d8	206	void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
2d82f8a3 AW	207	void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
2d82f8a3 AW	208	void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
c9c50009	209	void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
e3f79f3b	210	int vfio_add_virt_caps(VFIOPCIDevice vdev, Error *errp);
469d02de	211	void vfio_quirk_reset(VFIOPCIDevice *vdev);
29d62771 TH	212	VFIOQuirk *vfio_quirk_alloc(int nr_mem);
29d62771 TH	213	void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr);
c00d61d8	214
dfbee78d AW	215	extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
dfbee78d AW	216
cde4279b	217	int vfio_populate_vga(VFIOPCIDevice vdev, Error *errp);
e593c021	218
6ced0bba	219	int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
7237011d EA	220	struct vfio_region_info *info,
7237011d EA	221	Error **errp);
ec132efa AK	222	int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice vdev, Error *errp);
ec132efa AK	223	int vfio_pci_nvlink2_init(VFIOPCIDevice vdev, Error *errp);
6ced0bba	224
8983e3e3	225	void vfio_display_reset(VFIOPCIDevice *vdev);
a9994687 GH	226	int vfio_display_probe(VFIOPCIDevice vdev, Error *errp);
	227	void vfio_display_finalize(VFIOPCIDevice *vdev);
	228
78f33d2b	229	#endif /* HW_VFIO_VFIO_PCI_H */