]> git.proxmox.com Git - mirror_qemu.git/blame - hw/vga-isa-mm.c
vga: raise xres+yres limits
[mirror_qemu.git] / hw / vga-isa-mm.c
CommitLineData
79b97bf2
JQ
1/*
2 * QEMU ISA MM VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "hw.h"
25#include "console.h"
26#include "pc.h"
27#include "vga_int.h"
28#include "pixel_ops.h"
29#include "qemu-timer.h"
30
31typedef struct ISAVGAMMState {
32 VGACommonState vga;
33 int it_shift;
34} ISAVGAMMState;
35
36/* Memory mapped interface */
c227f099 37static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
79b97bf2
JQ
38{
39 ISAVGAMMState *s = opaque;
40
41 return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
42}
43
44static void vga_mm_writeb (void *opaque,
c227f099 45 target_phys_addr_t addr, uint32_t value)
79b97bf2
JQ
46{
47 ISAVGAMMState *s = opaque;
48
49 vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
50}
51
c227f099 52static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
79b97bf2
JQ
53{
54 ISAVGAMMState *s = opaque;
55
56 return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
57}
58
59static void vga_mm_writew (void *opaque,
c227f099 60 target_phys_addr_t addr, uint32_t value)
79b97bf2
JQ
61{
62 ISAVGAMMState *s = opaque;
63
64 vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
65}
66
c227f099 67static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
79b97bf2
JQ
68{
69 ISAVGAMMState *s = opaque;
70
71 return vga_ioport_read(&s->vga, addr >> s->it_shift);
72}
73
74static void vga_mm_writel (void *opaque,
c227f099 75 target_phys_addr_t addr, uint32_t value)
79b97bf2
JQ
76{
77 ISAVGAMMState *s = opaque;
78
79 vga_ioport_write(&s->vga, addr >> s->it_shift, value);
80}
81
b1950430
AK
82static const MemoryRegionOps vga_mm_ctrl_ops = {
83 .old_mmio = {
84 .read = {
85 vga_mm_readb,
86 vga_mm_readw,
87 vga_mm_readl,
88 },
89 .write = {
90 vga_mm_writeb,
91 vga_mm_writew,
92 vga_mm_writel,
93 },
94 },
95 .endianness = DEVICE_NATIVE_ENDIAN,
79b97bf2
JQ
96};
97
c227f099 98static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
be20f9e9
AK
99 target_phys_addr_t ctrl_base, int it_shift,
100 MemoryRegion *address_space)
79b97bf2 101{
b1950430 102 MemoryRegion *s_ioport_ctrl, *vga_io_memory;
79b97bf2
JQ
103
104 s->it_shift = it_shift;
7267c094 105 s_ioport_ctrl = g_malloc(sizeof(*s_ioport_ctrl));
b1950430
AK
106 memory_region_init_io(s_ioport_ctrl, &vga_mm_ctrl_ops, s,
107 "vga-mm-ctrl", 0x100000);
108
7267c094 109 vga_io_memory = g_malloc(sizeof(*vga_io_memory));
b1950430
AK
110 /* XXX: endianness? */
111 memory_region_init_io(vga_io_memory, &vga_mem_ops, &s->vga,
112 "vga-mem", 0x20000);
79b97bf2 113
0be71e32 114 vmstate_register(NULL, 0, &vmstate_vga_common, s);
79b97bf2 115
be20f9e9 116 memory_region_add_subregion(address_space, ctrl_base, s_ioport_ctrl);
79b97bf2 117 s->vga.bank_offset = 0;
be20f9e9 118 memory_region_add_subregion(address_space,
b1950430
AK
119 vram_base + 0x000a0000, vga_io_memory);
120 memory_region_set_coalescing(vga_io_memory);
79b97bf2
JQ
121}
122
c227f099 123int isa_vga_mm_init(target_phys_addr_t vram_base,
be20f9e9
AK
124 target_phys_addr_t ctrl_base, int it_shift,
125 MemoryRegion *address_space)
79b97bf2
JQ
126{
127 ISAVGAMMState *s;
128
7267c094 129 s = g_malloc0(sizeof(*s));
79b97bf2
JQ
130
131 vga_common_init(&s->vga, VGA_RAM_SIZE);
be20f9e9 132 vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
79b97bf2
JQ
133
134 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
135 s->vga.screen_dump, s->vga.text_update, s);
136
be20f9e9 137 vga_init_vbe(&s->vga, address_space);
79b97bf2
JQ
138 return 0;
139}