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Commit | Line | Data |
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e89f66ec | 1 | /* |
4fa0f5d2 | 2 | * QEMU VGA Emulator. |
5fafdf24 | 3 | * |
e89f66ec | 4 | * Copyright (c) 2003 Fabrice Bellard |
5fafdf24 | 5 | * |
e89f66ec FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b | 24 | #include "hw.h" |
5e55efc9 | 25 | #include "vga.h" |
87ecb68b PB |
26 | #include "console.h" |
27 | #include "pc.h" | |
28 | #include "pci.h" | |
798b0c25 | 29 | #include "vga_int.h" |
94470844 | 30 | #include "pixel_ops.h" |
cb5a7aa8 | 31 | #include "qemu-timer.h" |
c65adf9b | 32 | #include "xen.h" |
e89f66ec | 33 | |
e89f66ec | 34 | //#define DEBUG_VGA |
17b0018b | 35 | //#define DEBUG_VGA_MEM |
a41bc9af FB |
36 | //#define DEBUG_VGA_REG |
37 | ||
4fa0f5d2 FB |
38 | //#define DEBUG_BOCHS_VBE |
39 | ||
e89f66ec | 40 | /* force some bits to zero */ |
798b0c25 | 41 | const uint8_t sr_mask[8] = { |
9e622b15 BS |
42 | 0x03, |
43 | 0x3d, | |
44 | 0x0f, | |
45 | 0x3f, | |
46 | 0x0e, | |
47 | 0x00, | |
48 | 0x00, | |
49 | 0xff, | |
e89f66ec FB |
50 | }; |
51 | ||
798b0c25 | 52 | const uint8_t gr_mask[16] = { |
9e622b15 BS |
53 | 0x0f, /* 0x00 */ |
54 | 0x0f, /* 0x01 */ | |
55 | 0x0f, /* 0x02 */ | |
56 | 0x1f, /* 0x03 */ | |
57 | 0x03, /* 0x04 */ | |
58 | 0x7b, /* 0x05 */ | |
59 | 0x0f, /* 0x06 */ | |
60 | 0x0f, /* 0x07 */ | |
61 | 0xff, /* 0x08 */ | |
62 | 0x00, /* 0x09 */ | |
63 | 0x00, /* 0x0a */ | |
64 | 0x00, /* 0x0b */ | |
65 | 0x00, /* 0x0c */ | |
66 | 0x00, /* 0x0d */ | |
67 | 0x00, /* 0x0e */ | |
68 | 0x00, /* 0x0f */ | |
e89f66ec FB |
69 | }; |
70 | ||
71 | #define cbswap_32(__x) \ | |
72 | ((uint32_t)( \ | |
73 | (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \ | |
74 | (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \ | |
75 | (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \ | |
76 | (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) )) | |
77 | ||
e2542fe2 | 78 | #ifdef HOST_WORDS_BIGENDIAN |
e89f66ec FB |
79 | #define PAT(x) cbswap_32(x) |
80 | #else | |
81 | #define PAT(x) (x) | |
82 | #endif | |
83 | ||
e2542fe2 | 84 | #ifdef HOST_WORDS_BIGENDIAN |
b8ed223b FB |
85 | #define BIG 1 |
86 | #else | |
87 | #define BIG 0 | |
88 | #endif | |
89 | ||
e2542fe2 | 90 | #ifdef HOST_WORDS_BIGENDIAN |
b8ed223b FB |
91 | #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff) |
92 | #else | |
93 | #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff) | |
94 | #endif | |
95 | ||
e89f66ec FB |
96 | static const uint32_t mask16[16] = { |
97 | PAT(0x00000000), | |
98 | PAT(0x000000ff), | |
99 | PAT(0x0000ff00), | |
100 | PAT(0x0000ffff), | |
101 | PAT(0x00ff0000), | |
102 | PAT(0x00ff00ff), | |
103 | PAT(0x00ffff00), | |
104 | PAT(0x00ffffff), | |
105 | PAT(0xff000000), | |
106 | PAT(0xff0000ff), | |
107 | PAT(0xff00ff00), | |
108 | PAT(0xff00ffff), | |
109 | PAT(0xffff0000), | |
110 | PAT(0xffff00ff), | |
111 | PAT(0xffffff00), | |
112 | PAT(0xffffffff), | |
113 | }; | |
114 | ||
115 | #undef PAT | |
116 | ||
e2542fe2 | 117 | #ifdef HOST_WORDS_BIGENDIAN |
e89f66ec FB |
118 | #define PAT(x) (x) |
119 | #else | |
120 | #define PAT(x) cbswap_32(x) | |
121 | #endif | |
122 | ||
123 | static const uint32_t dmask16[16] = { | |
124 | PAT(0x00000000), | |
125 | PAT(0x000000ff), | |
126 | PAT(0x0000ff00), | |
127 | PAT(0x0000ffff), | |
128 | PAT(0x00ff0000), | |
129 | PAT(0x00ff00ff), | |
130 | PAT(0x00ffff00), | |
131 | PAT(0x00ffffff), | |
132 | PAT(0xff000000), | |
133 | PAT(0xff0000ff), | |
134 | PAT(0xff00ff00), | |
135 | PAT(0xff00ffff), | |
136 | PAT(0xffff0000), | |
137 | PAT(0xffff00ff), | |
138 | PAT(0xffffff00), | |
139 | PAT(0xffffffff), | |
140 | }; | |
141 | ||
142 | static const uint32_t dmask4[4] = { | |
143 | PAT(0x00000000), | |
144 | PAT(0x0000ffff), | |
145 | PAT(0xffff0000), | |
146 | PAT(0xffffffff), | |
147 | }; | |
148 | ||
149 | static uint32_t expand4[256]; | |
150 | static uint16_t expand2[256]; | |
17b0018b | 151 | static uint8_t expand4to8[16]; |
e89f66ec | 152 | |
95219897 | 153 | static void vga_screen_dump(void *opaque, const char *filename); |
2313e998 | 154 | static const char *screen_dump_filename; |
04a52b41 | 155 | static DisplayChangeListener *screen_dump_dcl; |
95219897 | 156 | |
80763888 JK |
157 | static void vga_update_memory_access(VGACommonState *s) |
158 | { | |
159 | MemoryRegion *region, *old_region = s->chain4_alias; | |
160 | target_phys_addr_t base, offset, size; | |
161 | ||
162 | s->chain4_alias = NULL; | |
163 | ||
5e55efc9 BS |
164 | if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) == |
165 | VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { | |
80763888 | 166 | offset = 0; |
5e55efc9 | 167 | switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) { |
80763888 JK |
168 | case 0: |
169 | base = 0xa0000; | |
170 | size = 0x20000; | |
171 | break; | |
172 | case 1: | |
173 | base = 0xa0000; | |
174 | size = 0x10000; | |
175 | offset = s->bank_offset; | |
176 | break; | |
177 | case 2: | |
178 | base = 0xb0000; | |
179 | size = 0x8000; | |
180 | break; | |
181 | case 3: | |
f065aa0a | 182 | default: |
80763888 JK |
183 | base = 0xb8000; |
184 | size = 0x8000; | |
185 | break; | |
186 | } | |
71579cae | 187 | base += isa_mem_base; |
80763888 JK |
188 | region = g_malloc(sizeof(*region)); |
189 | memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size); | |
190 | memory_region_add_subregion_overlap(s->legacy_address_space, base, | |
191 | region, 2); | |
192 | s->chain4_alias = region; | |
193 | } | |
194 | if (old_region) { | |
195 | memory_region_del_subregion(s->legacy_address_space, old_region); | |
196 | memory_region_destroy(old_region); | |
197 | g_free(old_region); | |
198 | s->plane_updated = 0xf; | |
199 | } | |
200 | } | |
201 | ||
cedd91d2 | 202 | static void vga_dumb_update_retrace_info(VGACommonState *s) |
cb5a7aa8 | 203 | { |
204 | (void) s; | |
205 | } | |
206 | ||
cedd91d2 | 207 | static void vga_precise_update_retrace_info(VGACommonState *s) |
cb5a7aa8 | 208 | { |
209 | int htotal_chars; | |
210 | int hretr_start_char; | |
211 | int hretr_skew_chars; | |
212 | int hretr_end_char; | |
213 | ||
214 | int vtotal_lines; | |
215 | int vretr_start_line; | |
216 | int vretr_end_line; | |
217 | ||
7f5b7d3e BS |
218 | int dots; |
219 | #if 0 | |
220 | int div2, sldiv2; | |
221 | #endif | |
cb5a7aa8 | 222 | int clocking_mode; |
223 | int clock_sel; | |
b0f74c87 | 224 | const int clk_hz[] = {25175000, 28322000, 25175000, 25175000}; |
cb5a7aa8 | 225 | int64_t chars_per_sec; |
226 | struct vga_precise_retrace *r = &s->retrace_info.precise; | |
227 | ||
5e55efc9 BS |
228 | htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5; |
229 | hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START]; | |
230 | hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3; | |
231 | hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f; | |
cb5a7aa8 | 232 | |
5e55efc9 BS |
233 | vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] | |
234 | (((s->cr[VGA_CRTC_OVERFLOW] & 1) | | |
235 | ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2; | |
236 | vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] | | |
237 | ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) | | |
238 | ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8); | |
239 | vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf; | |
cb5a7aa8 | 240 | |
5e55efc9 | 241 | clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1; |
cb5a7aa8 | 242 | clock_sel = (s->msr >> 2) & 3; |
f87fc09b | 243 | dots = (s->msr & 1) ? 8 : 9; |
cb5a7aa8 | 244 | |
b0f74c87 | 245 | chars_per_sec = clk_hz[clock_sel] / dots; |
cb5a7aa8 | 246 | |
247 | htotal_chars <<= clocking_mode; | |
248 | ||
249 | r->total_chars = vtotal_lines * htotal_chars; | |
cb5a7aa8 | 250 | if (r->freq) { |
6ee093c9 | 251 | r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq); |
cb5a7aa8 | 252 | } else { |
6ee093c9 | 253 | r->ticks_per_char = get_ticks_per_sec() / chars_per_sec; |
cb5a7aa8 | 254 | } |
255 | ||
256 | r->vstart = vretr_start_line; | |
257 | r->vend = r->vstart + vretr_end_line + 1; | |
258 | ||
259 | r->hstart = hretr_start_char + hretr_skew_chars; | |
260 | r->hend = r->hstart + hretr_end_char + 1; | |
261 | r->htotal = htotal_chars; | |
262 | ||
f87fc09b | 263 | #if 0 |
5e55efc9 BS |
264 | div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1; |
265 | sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1; | |
cb5a7aa8 | 266 | printf ( |
f87fc09b | 267 | "hz=%f\n" |
cb5a7aa8 | 268 | "htotal = %d\n" |
269 | "hretr_start = %d\n" | |
270 | "hretr_skew = %d\n" | |
271 | "hretr_end = %d\n" | |
272 | "vtotal = %d\n" | |
273 | "vretr_start = %d\n" | |
274 | "vretr_end = %d\n" | |
275 | "div2 = %d sldiv2 = %d\n" | |
276 | "clocking_mode = %d\n" | |
277 | "clock_sel = %d %d\n" | |
278 | "dots = %d\n" | |
0bfcd599 | 279 | "ticks/char = %" PRId64 "\n" |
cb5a7aa8 | 280 | "\n", |
6ee093c9 | 281 | (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars), |
cb5a7aa8 | 282 | htotal_chars, |
283 | hretr_start_char, | |
284 | hretr_skew_chars, | |
285 | hretr_end_char, | |
286 | vtotal_lines, | |
287 | vretr_start_line, | |
288 | vretr_end_line, | |
289 | div2, sldiv2, | |
290 | clocking_mode, | |
291 | clock_sel, | |
b0f74c87 | 292 | clk_hz[clock_sel], |
cb5a7aa8 | 293 | dots, |
294 | r->ticks_per_char | |
295 | ); | |
296 | #endif | |
297 | } | |
298 | ||
cedd91d2 | 299 | static uint8_t vga_precise_retrace(VGACommonState *s) |
cb5a7aa8 | 300 | { |
301 | struct vga_precise_retrace *r = &s->retrace_info.precise; | |
302 | uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE); | |
303 | ||
304 | if (r->total_chars) { | |
305 | int cur_line, cur_line_char, cur_char; | |
306 | int64_t cur_tick; | |
307 | ||
74475455 | 308 | cur_tick = qemu_get_clock_ns(vm_clock); |
cb5a7aa8 | 309 | |
310 | cur_char = (cur_tick / r->ticks_per_char) % r->total_chars; | |
311 | cur_line = cur_char / r->htotal; | |
312 | ||
313 | if (cur_line >= r->vstart && cur_line <= r->vend) { | |
314 | val |= ST01_V_RETRACE | ST01_DISP_ENABLE; | |
f87fc09b | 315 | } else { |
316 | cur_line_char = cur_char % r->htotal; | |
317 | if (cur_line_char >= r->hstart && cur_line_char <= r->hend) { | |
318 | val |= ST01_DISP_ENABLE; | |
319 | } | |
cb5a7aa8 | 320 | } |
321 | ||
322 | return val; | |
323 | } else { | |
324 | return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE); | |
325 | } | |
326 | } | |
327 | ||
cedd91d2 | 328 | static uint8_t vga_dumb_retrace(VGACommonState *s) |
cb5a7aa8 | 329 | { |
330 | return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE); | |
331 | } | |
332 | ||
25a18cbd JQ |
333 | int vga_ioport_invalid(VGACommonState *s, uint32_t addr) |
334 | { | |
5e55efc9 | 335 | if (s->msr & VGA_MIS_COLOR) { |
25a18cbd JQ |
336 | /* Color */ |
337 | return (addr >= 0x3b0 && addr <= 0x3bf); | |
338 | } else { | |
339 | /* Monochrome */ | |
340 | return (addr >= 0x3d0 && addr <= 0x3df); | |
341 | } | |
342 | } | |
343 | ||
43bf782b | 344 | uint32_t vga_ioport_read(void *opaque, uint32_t addr) |
e89f66ec | 345 | { |
43bf782b | 346 | VGACommonState *s = opaque; |
e89f66ec FB |
347 | int val, index; |
348 | ||
25a18cbd | 349 | if (vga_ioport_invalid(s, addr)) { |
e89f66ec FB |
350 | val = 0xff; |
351 | } else { | |
352 | switch(addr) { | |
5e55efc9 | 353 | case VGA_ATT_W: |
e89f66ec FB |
354 | if (s->ar_flip_flop == 0) { |
355 | val = s->ar_index; | |
356 | } else { | |
357 | val = 0; | |
358 | } | |
359 | break; | |
5e55efc9 | 360 | case VGA_ATT_R: |
e89f66ec | 361 | index = s->ar_index & 0x1f; |
5e55efc9 | 362 | if (index < VGA_ATT_C) { |
e89f66ec | 363 | val = s->ar[index]; |
5e55efc9 | 364 | } else { |
e89f66ec | 365 | val = 0; |
5e55efc9 | 366 | } |
e89f66ec | 367 | break; |
5e55efc9 | 368 | case VGA_MIS_W: |
e89f66ec FB |
369 | val = s->st00; |
370 | break; | |
5e55efc9 | 371 | case VGA_SEQ_I: |
e89f66ec FB |
372 | val = s->sr_index; |
373 | break; | |
5e55efc9 | 374 | case VGA_SEQ_D: |
e89f66ec | 375 | val = s->sr[s->sr_index]; |
a41bc9af FB |
376 | #ifdef DEBUG_VGA_REG |
377 | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); | |
378 | #endif | |
e89f66ec | 379 | break; |
5e55efc9 | 380 | case VGA_PEL_IR: |
e89f66ec FB |
381 | val = s->dac_state; |
382 | break; | |
5e55efc9 | 383 | case VGA_PEL_IW: |
e9b43ea3 JQ |
384 | val = s->dac_write_index; |
385 | break; | |
5e55efc9 | 386 | case VGA_PEL_D: |
e89f66ec FB |
387 | val = s->palette[s->dac_read_index * 3 + s->dac_sub_index]; |
388 | if (++s->dac_sub_index == 3) { | |
389 | s->dac_sub_index = 0; | |
390 | s->dac_read_index++; | |
391 | } | |
392 | break; | |
5e55efc9 | 393 | case VGA_FTC_R: |
e89f66ec FB |
394 | val = s->fcr; |
395 | break; | |
5e55efc9 | 396 | case VGA_MIS_R: |
e89f66ec FB |
397 | val = s->msr; |
398 | break; | |
5e55efc9 | 399 | case VGA_GFX_I: |
e89f66ec FB |
400 | val = s->gr_index; |
401 | break; | |
5e55efc9 | 402 | case VGA_GFX_D: |
e89f66ec | 403 | val = s->gr[s->gr_index]; |
a41bc9af FB |
404 | #ifdef DEBUG_VGA_REG |
405 | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); | |
406 | #endif | |
e89f66ec | 407 | break; |
5e55efc9 BS |
408 | case VGA_CRT_IM: |
409 | case VGA_CRT_IC: | |
e89f66ec FB |
410 | val = s->cr_index; |
411 | break; | |
5e55efc9 BS |
412 | case VGA_CRT_DM: |
413 | case VGA_CRT_DC: | |
e89f66ec | 414 | val = s->cr[s->cr_index]; |
a41bc9af FB |
415 | #ifdef DEBUG_VGA_REG |
416 | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); | |
a41bc9af | 417 | #endif |
e89f66ec | 418 | break; |
5e55efc9 BS |
419 | case VGA_IS1_RM: |
420 | case VGA_IS1_RC: | |
e89f66ec | 421 | /* just toggle to fool polling */ |
cb5a7aa8 | 422 | val = s->st01 = s->retrace(s); |
e89f66ec FB |
423 | s->ar_flip_flop = 0; |
424 | break; | |
425 | default: | |
426 | val = 0x00; | |
427 | break; | |
428 | } | |
429 | } | |
4fa0f5d2 | 430 | #if defined(DEBUG_VGA) |
e89f66ec FB |
431 | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val); |
432 | #endif | |
433 | return val; | |
434 | } | |
435 | ||
43bf782b | 436 | void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
e89f66ec | 437 | { |
43bf782b | 438 | VGACommonState *s = opaque; |
5467a722 | 439 | int index; |
e89f66ec FB |
440 | |
441 | /* check port range access depending on color/monochrome mode */ | |
25a18cbd | 442 | if (vga_ioport_invalid(s, addr)) { |
e89f66ec | 443 | return; |
25a18cbd | 444 | } |
e89f66ec FB |
445 | #ifdef DEBUG_VGA |
446 | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val); | |
447 | #endif | |
448 | ||
449 | switch(addr) { | |
5e55efc9 | 450 | case VGA_ATT_W: |
e89f66ec FB |
451 | if (s->ar_flip_flop == 0) { |
452 | val &= 0x3f; | |
453 | s->ar_index = val; | |
454 | } else { | |
455 | index = s->ar_index & 0x1f; | |
456 | switch(index) { | |
5e55efc9 | 457 | case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF: |
e89f66ec FB |
458 | s->ar[index] = val & 0x3f; |
459 | break; | |
5e55efc9 | 460 | case VGA_ATC_MODE: |
e89f66ec FB |
461 | s->ar[index] = val & ~0x10; |
462 | break; | |
5e55efc9 | 463 | case VGA_ATC_OVERSCAN: |
e89f66ec FB |
464 | s->ar[index] = val; |
465 | break; | |
5e55efc9 | 466 | case VGA_ATC_PLANE_ENABLE: |
e89f66ec FB |
467 | s->ar[index] = val & ~0xc0; |
468 | break; | |
5e55efc9 | 469 | case VGA_ATC_PEL: |
e89f66ec FB |
470 | s->ar[index] = val & ~0xf0; |
471 | break; | |
5e55efc9 | 472 | case VGA_ATC_COLOR_PAGE: |
e89f66ec FB |
473 | s->ar[index] = val & ~0xf0; |
474 | break; | |
475 | default: | |
476 | break; | |
477 | } | |
478 | } | |
479 | s->ar_flip_flop ^= 1; | |
480 | break; | |
5e55efc9 | 481 | case VGA_MIS_W: |
e89f66ec | 482 | s->msr = val & ~0x10; |
cb5a7aa8 | 483 | s->update_retrace_info(s); |
e89f66ec | 484 | break; |
5e55efc9 | 485 | case VGA_SEQ_I: |
e89f66ec FB |
486 | s->sr_index = val & 7; |
487 | break; | |
5e55efc9 | 488 | case VGA_SEQ_D: |
a41bc9af FB |
489 | #ifdef DEBUG_VGA_REG |
490 | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val); | |
491 | #endif | |
e89f66ec | 492 | s->sr[s->sr_index] = val & sr_mask[s->sr_index]; |
5e55efc9 BS |
493 | if (s->sr_index == VGA_SEQ_CLOCK_MODE) { |
494 | s->update_retrace_info(s); | |
495 | } | |
80763888 | 496 | vga_update_memory_access(s); |
e89f66ec | 497 | break; |
5e55efc9 | 498 | case VGA_PEL_IR: |
e89f66ec FB |
499 | s->dac_read_index = val; |
500 | s->dac_sub_index = 0; | |
501 | s->dac_state = 3; | |
502 | break; | |
5e55efc9 | 503 | case VGA_PEL_IW: |
e89f66ec FB |
504 | s->dac_write_index = val; |
505 | s->dac_sub_index = 0; | |
506 | s->dac_state = 0; | |
507 | break; | |
5e55efc9 | 508 | case VGA_PEL_D: |
e89f66ec FB |
509 | s->dac_cache[s->dac_sub_index] = val; |
510 | if (++s->dac_sub_index == 3) { | |
511 | memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); | |
512 | s->dac_sub_index = 0; | |
513 | s->dac_write_index++; | |
514 | } | |
515 | break; | |
5e55efc9 | 516 | case VGA_GFX_I: |
e89f66ec FB |
517 | s->gr_index = val & 0x0f; |
518 | break; | |
5e55efc9 | 519 | case VGA_GFX_D: |
a41bc9af FB |
520 | #ifdef DEBUG_VGA_REG |
521 | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); | |
522 | #endif | |
e89f66ec | 523 | s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
80763888 | 524 | vga_update_memory_access(s); |
e89f66ec | 525 | break; |
5e55efc9 BS |
526 | case VGA_CRT_IM: |
527 | case VGA_CRT_IC: | |
e89f66ec FB |
528 | s->cr_index = val; |
529 | break; | |
5e55efc9 BS |
530 | case VGA_CRT_DM: |
531 | case VGA_CRT_DC: | |
a41bc9af FB |
532 | #ifdef DEBUG_VGA_REG |
533 | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val); | |
534 | #endif | |
e89f66ec | 535 | /* handle CR0-7 protection */ |
5e55efc9 BS |
536 | if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) && |
537 | s->cr_index <= VGA_CRTC_OVERFLOW) { | |
e89f66ec | 538 | /* can always write bit 4 of CR7 */ |
5e55efc9 BS |
539 | if (s->cr_index == VGA_CRTC_OVERFLOW) { |
540 | s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) | | |
541 | (val & 0x10); | |
542 | } | |
e89f66ec FB |
543 | return; |
544 | } | |
a46007a0 | 545 | s->cr[s->cr_index] = val; |
cb5a7aa8 | 546 | |
547 | switch(s->cr_index) { | |
5e55efc9 BS |
548 | case VGA_CRTC_H_TOTAL: |
549 | case VGA_CRTC_H_SYNC_START: | |
550 | case VGA_CRTC_H_SYNC_END: | |
551 | case VGA_CRTC_V_TOTAL: | |
552 | case VGA_CRTC_OVERFLOW: | |
553 | case VGA_CRTC_V_SYNC_END: | |
554 | case VGA_CRTC_MODE: | |
cb5a7aa8 | 555 | s->update_retrace_info(s); |
556 | break; | |
557 | } | |
e89f66ec | 558 | break; |
5e55efc9 BS |
559 | case VGA_IS1_RM: |
560 | case VGA_IS1_RC: | |
e89f66ec FB |
561 | s->fcr = val & 0x10; |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
4fa0f5d2 | 566 | #ifdef CONFIG_BOCHS_VBE |
09a79b49 | 567 | static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr) |
4fa0f5d2 | 568 | { |
cedd91d2 | 569 | VGACommonState *s = opaque; |
4fa0f5d2 | 570 | uint32_t val; |
09a79b49 FB |
571 | val = s->vbe_index; |
572 | return val; | |
573 | } | |
4fa0f5d2 | 574 | |
09a79b49 FB |
575 | static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr) |
576 | { | |
cedd91d2 | 577 | VGACommonState *s = opaque; |
09a79b49 FB |
578 | uint32_t val; |
579 | ||
af92284b | 580 | if (s->vbe_index < VBE_DISPI_INDEX_NB) { |
8454df8b FB |
581 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) { |
582 | switch(s->vbe_index) { | |
583 | /* XXX: do not hardcode ? */ | |
584 | case VBE_DISPI_INDEX_XRES: | |
585 | val = VBE_DISPI_MAX_XRES; | |
586 | break; | |
587 | case VBE_DISPI_INDEX_YRES: | |
588 | val = VBE_DISPI_MAX_YRES; | |
589 | break; | |
590 | case VBE_DISPI_INDEX_BPP: | |
591 | val = VBE_DISPI_MAX_BPP; | |
592 | break; | |
593 | default: | |
5fafdf24 | 594 | val = s->vbe_regs[s->vbe_index]; |
8454df8b FB |
595 | break; |
596 | } | |
597 | } else { | |
5fafdf24 | 598 | val = s->vbe_regs[s->vbe_index]; |
8454df8b | 599 | } |
af92284b GH |
600 | } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) { |
601 | val = s->vram_size / (64 * 1024); | |
8454df8b | 602 | } else { |
09a79b49 | 603 | val = 0; |
8454df8b | 604 | } |
4fa0f5d2 | 605 | #ifdef DEBUG_BOCHS_VBE |
09a79b49 | 606 | printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val); |
4fa0f5d2 | 607 | #endif |
4fa0f5d2 FB |
608 | return val; |
609 | } | |
610 | ||
09a79b49 FB |
611 | static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val) |
612 | { | |
cedd91d2 | 613 | VGACommonState *s = opaque; |
09a79b49 FB |
614 | s->vbe_index = val; |
615 | } | |
616 | ||
617 | static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val) | |
4fa0f5d2 | 618 | { |
cedd91d2 | 619 | VGACommonState *s = opaque; |
4fa0f5d2 | 620 | |
09a79b49 | 621 | if (s->vbe_index <= VBE_DISPI_INDEX_NB) { |
4fa0f5d2 FB |
622 | #ifdef DEBUG_BOCHS_VBE |
623 | printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val); | |
624 | #endif | |
625 | switch(s->vbe_index) { | |
626 | case VBE_DISPI_INDEX_ID: | |
cae61cef FB |
627 | if (val == VBE_DISPI_ID0 || |
628 | val == VBE_DISPI_ID1 || | |
37dd208d FB |
629 | val == VBE_DISPI_ID2 || |
630 | val == VBE_DISPI_ID3 || | |
631 | val == VBE_DISPI_ID4) { | |
cae61cef FB |
632 | s->vbe_regs[s->vbe_index] = val; |
633 | } | |
4fa0f5d2 FB |
634 | break; |
635 | case VBE_DISPI_INDEX_XRES: | |
cae61cef FB |
636 | if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) { |
637 | s->vbe_regs[s->vbe_index] = val; | |
638 | } | |
4fa0f5d2 FB |
639 | break; |
640 | case VBE_DISPI_INDEX_YRES: | |
cae61cef FB |
641 | if (val <= VBE_DISPI_MAX_YRES) { |
642 | s->vbe_regs[s->vbe_index] = val; | |
643 | } | |
4fa0f5d2 FB |
644 | break; |
645 | case VBE_DISPI_INDEX_BPP: | |
646 | if (val == 0) | |
647 | val = 8; | |
5fafdf24 | 648 | if (val == 4 || val == 8 || val == 15 || |
cae61cef FB |
649 | val == 16 || val == 24 || val == 32) { |
650 | s->vbe_regs[s->vbe_index] = val; | |
651 | } | |
4fa0f5d2 FB |
652 | break; |
653 | case VBE_DISPI_INDEX_BANK: | |
42fc925e FB |
654 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
655 | val &= (s->vbe_bank_mask >> 2); | |
656 | } else { | |
657 | val &= s->vbe_bank_mask; | |
658 | } | |
cae61cef | 659 | s->vbe_regs[s->vbe_index] = val; |
26aa7d72 | 660 | s->bank_offset = (val << 16); |
80763888 | 661 | vga_update_memory_access(s); |
4fa0f5d2 FB |
662 | break; |
663 | case VBE_DISPI_INDEX_ENABLE: | |
8454df8b FB |
664 | if ((val & VBE_DISPI_ENABLED) && |
665 | !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) { | |
4fa0f5d2 FB |
666 | int h, shift_control; |
667 | ||
5fafdf24 | 668 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = |
4fa0f5d2 | 669 | s->vbe_regs[VBE_DISPI_INDEX_XRES]; |
5fafdf24 | 670 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = |
4fa0f5d2 FB |
671 | s->vbe_regs[VBE_DISPI_INDEX_YRES]; |
672 | s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0; | |
673 | s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0; | |
3b46e624 | 674 | |
4fa0f5d2 FB |
675 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) |
676 | s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1; | |
677 | else | |
5fafdf24 | 678 | s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * |
4fa0f5d2 FB |
679 | ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); |
680 | s->vbe_start_addr = 0; | |
8454df8b | 681 | |
4fa0f5d2 FB |
682 | /* clear the screen (should be done in BIOS) */ |
683 | if (!(val & VBE_DISPI_NOCLEARMEM)) { | |
5fafdf24 | 684 | memset(s->vram_ptr, 0, |
4fa0f5d2 FB |
685 | s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset); |
686 | } | |
3b46e624 | 687 | |
cae61cef FB |
688 | /* we initialize the VGA graphic mode (should be done |
689 | in BIOS) */ | |
5e55efc9 BS |
690 | /* graphic mode + memory map 1 */ |
691 | s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 | | |
692 | VGA_GR06_GRAPHICS_MODE; | |
693 | s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */ | |
694 | s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3; | |
4fa0f5d2 | 695 | /* width */ |
5e55efc9 BS |
696 | s->cr[VGA_CRTC_H_DISP] = |
697 | (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1; | |
8454df8b | 698 | /* height (only meaningful if < 1024) */ |
4fa0f5d2 | 699 | h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1; |
5e55efc9 BS |
700 | s->cr[VGA_CRTC_V_DISP_END] = h; |
701 | s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) | | |
4fa0f5d2 FB |
702 | ((h >> 7) & 0x02) | ((h >> 3) & 0x40); |
703 | /* line compare to 1023 */ | |
5e55efc9 BS |
704 | s->cr[VGA_CRTC_LINE_COMPARE] = 0xff; |
705 | s->cr[VGA_CRTC_OVERFLOW] |= 0x10; | |
706 | s->cr[VGA_CRTC_MAX_SCAN] |= 0x40; | |
3b46e624 | 707 | |
4fa0f5d2 FB |
708 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { |
709 | shift_control = 0; | |
5e55efc9 | 710 | s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */ |
4fa0f5d2 FB |
711 | } else { |
712 | shift_control = 2; | |
5e55efc9 BS |
713 | /* set chain 4 mode */ |
714 | s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M; | |
715 | /* activate all planes */ | |
716 | s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES; | |
4fa0f5d2 | 717 | } |
5e55efc9 BS |
718 | s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) | |
719 | (shift_control << 5); | |
720 | s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */ | |
cae61cef FB |
721 | } else { |
722 | /* XXX: the bios should do that */ | |
26aa7d72 | 723 | s->bank_offset = 0; |
cae61cef | 724 | } |
37dd208d | 725 | s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0; |
141253b2 | 726 | s->vbe_regs[s->vbe_index] = val; |
80763888 | 727 | vga_update_memory_access(s); |
cae61cef FB |
728 | break; |
729 | case VBE_DISPI_INDEX_VIRT_WIDTH: | |
730 | { | |
731 | int w, h, line_offset; | |
732 | ||
733 | if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES]) | |
734 | return; | |
735 | w = val; | |
736 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) | |
737 | line_offset = w >> 1; | |
738 | else | |
739 | line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); | |
740 | h = s->vram_size / line_offset; | |
741 | /* XXX: support weird bochs semantics ? */ | |
742 | if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES]) | |
743 | return; | |
744 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w; | |
745 | s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h; | |
746 | s->vbe_line_offset = line_offset; | |
747 | } | |
748 | break; | |
749 | case VBE_DISPI_INDEX_X_OFFSET: | |
750 | case VBE_DISPI_INDEX_Y_OFFSET: | |
751 | { | |
752 | int x; | |
753 | s->vbe_regs[s->vbe_index] = val; | |
754 | s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET]; | |
755 | x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET]; | |
756 | if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) | |
757 | s->vbe_start_addr += x >> 1; | |
758 | else | |
759 | s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3); | |
760 | s->vbe_start_addr >>= 2; | |
4fa0f5d2 FB |
761 | } |
762 | break; | |
763 | default: | |
764 | break; | |
765 | } | |
4fa0f5d2 FB |
766 | } |
767 | } | |
768 | #endif | |
769 | ||
e89f66ec | 770 | /* called for accesses between 0xa0000 and 0xc0000 */ |
b2a5e761 | 771 | uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr) |
e89f66ec | 772 | { |
e89f66ec FB |
773 | int memory_map_mode, plane; |
774 | uint32_t ret; | |
3b46e624 | 775 | |
e89f66ec | 776 | /* convert to VGA memory offset */ |
5e55efc9 | 777 | memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; |
26aa7d72 | 778 | addr &= 0x1ffff; |
e89f66ec FB |
779 | switch(memory_map_mode) { |
780 | case 0: | |
e89f66ec FB |
781 | break; |
782 | case 1: | |
26aa7d72 | 783 | if (addr >= 0x10000) |
e89f66ec | 784 | return 0xff; |
cae61cef | 785 | addr += s->bank_offset; |
e89f66ec FB |
786 | break; |
787 | case 2: | |
26aa7d72 | 788 | addr -= 0x10000; |
e89f66ec FB |
789 | if (addr >= 0x8000) |
790 | return 0xff; | |
791 | break; | |
792 | default: | |
793 | case 3: | |
26aa7d72 | 794 | addr -= 0x18000; |
c92b2e84 FB |
795 | if (addr >= 0x8000) |
796 | return 0xff; | |
e89f66ec FB |
797 | break; |
798 | } | |
3b46e624 | 799 | |
5e55efc9 | 800 | if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { |
e89f66ec FB |
801 | /* chain 4 mode : simplest access */ |
802 | ret = s->vram_ptr[addr]; | |
5e55efc9 | 803 | } else if (s->gr[VGA_GFX_MODE] & 0x10) { |
e89f66ec | 804 | /* odd/even mode (aka text mode mapping) */ |
5e55efc9 | 805 | plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); |
e89f66ec FB |
806 | ret = s->vram_ptr[((addr & ~1) << 1) | plane]; |
807 | } else { | |
808 | /* standard VGA latched access */ | |
809 | s->latch = ((uint32_t *)s->vram_ptr)[addr]; | |
810 | ||
5e55efc9 | 811 | if (!(s->gr[VGA_GFX_MODE] & 0x08)) { |
e89f66ec | 812 | /* read mode 0 */ |
5e55efc9 | 813 | plane = s->gr[VGA_GFX_PLANE_READ]; |
b8ed223b | 814 | ret = GET_PLANE(s->latch, plane); |
e89f66ec FB |
815 | } else { |
816 | /* read mode 1 */ | |
5e55efc9 BS |
817 | ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) & |
818 | mask16[s->gr[VGA_GFX_COMPARE_MASK]]; | |
e89f66ec FB |
819 | ret |= ret >> 16; |
820 | ret |= ret >> 8; | |
821 | ret = (~ret) & 0xff; | |
822 | } | |
823 | } | |
824 | return ret; | |
825 | } | |
826 | ||
e89f66ec | 827 | /* called for accesses between 0xa0000 and 0xc0000 */ |
b2a5e761 | 828 | void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val) |
e89f66ec | 829 | { |
546fa6ab | 830 | int memory_map_mode, plane, write_mode, b, func_select, mask; |
e89f66ec FB |
831 | uint32_t write_mask, bit_mask, set_mask; |
832 | ||
17b0018b | 833 | #ifdef DEBUG_VGA_MEM |
0bf9e31a | 834 | printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val); |
e89f66ec FB |
835 | #endif |
836 | /* convert to VGA memory offset */ | |
5e55efc9 | 837 | memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; |
26aa7d72 | 838 | addr &= 0x1ffff; |
e89f66ec FB |
839 | switch(memory_map_mode) { |
840 | case 0: | |
e89f66ec FB |
841 | break; |
842 | case 1: | |
26aa7d72 | 843 | if (addr >= 0x10000) |
e89f66ec | 844 | return; |
cae61cef | 845 | addr += s->bank_offset; |
e89f66ec FB |
846 | break; |
847 | case 2: | |
26aa7d72 | 848 | addr -= 0x10000; |
e89f66ec FB |
849 | if (addr >= 0x8000) |
850 | return; | |
851 | break; | |
852 | default: | |
853 | case 3: | |
26aa7d72 | 854 | addr -= 0x18000; |
c92b2e84 FB |
855 | if (addr >= 0x8000) |
856 | return; | |
e89f66ec FB |
857 | break; |
858 | } | |
3b46e624 | 859 | |
5e55efc9 | 860 | if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { |
e89f66ec FB |
861 | /* chain 4 mode : simplest access */ |
862 | plane = addr & 3; | |
546fa6ab | 863 | mask = (1 << plane); |
5e55efc9 | 864 | if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) { |
e89f66ec | 865 | s->vram_ptr[addr] = val; |
17b0018b | 866 | #ifdef DEBUG_VGA_MEM |
0bf9e31a | 867 | printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr); |
e89f66ec | 868 | #endif |
546fa6ab | 869 | s->plane_updated |= mask; /* only used to detect font change */ |
fd4aa979 | 870 | memory_region_set_dirty(&s->vram, addr, 1); |
e89f66ec | 871 | } |
5e55efc9 | 872 | } else if (s->gr[VGA_GFX_MODE] & 0x10) { |
e89f66ec | 873 | /* odd/even mode (aka text mode mapping) */ |
5e55efc9 | 874 | plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); |
546fa6ab | 875 | mask = (1 << plane); |
5e55efc9 | 876 | if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) { |
e89f66ec FB |
877 | addr = ((addr & ~1) << 1) | plane; |
878 | s->vram_ptr[addr] = val; | |
17b0018b | 879 | #ifdef DEBUG_VGA_MEM |
0bf9e31a | 880 | printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr); |
e89f66ec | 881 | #endif |
546fa6ab | 882 | s->plane_updated |= mask; /* only used to detect font change */ |
fd4aa979 | 883 | memory_region_set_dirty(&s->vram, addr, 1); |
e89f66ec FB |
884 | } |
885 | } else { | |
886 | /* standard VGA latched access */ | |
5e55efc9 | 887 | write_mode = s->gr[VGA_GFX_MODE] & 3; |
e89f66ec FB |
888 | switch(write_mode) { |
889 | default: | |
890 | case 0: | |
891 | /* rotate */ | |
5e55efc9 | 892 | b = s->gr[VGA_GFX_DATA_ROTATE] & 7; |
e89f66ec FB |
893 | val = ((val >> b) | (val << (8 - b))) & 0xff; |
894 | val |= val << 8; | |
895 | val |= val << 16; | |
896 | ||
897 | /* apply set/reset mask */ | |
5e55efc9 BS |
898 | set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]]; |
899 | val = (val & ~set_mask) | | |
900 | (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask); | |
901 | bit_mask = s->gr[VGA_GFX_BIT_MASK]; | |
e89f66ec FB |
902 | break; |
903 | case 1: | |
904 | val = s->latch; | |
905 | goto do_write; | |
906 | case 2: | |
907 | val = mask16[val & 0x0f]; | |
5e55efc9 | 908 | bit_mask = s->gr[VGA_GFX_BIT_MASK]; |
e89f66ec FB |
909 | break; |
910 | case 3: | |
911 | /* rotate */ | |
5e55efc9 | 912 | b = s->gr[VGA_GFX_DATA_ROTATE] & 7; |
a41bc9af | 913 | val = (val >> b) | (val << (8 - b)); |
e89f66ec | 914 | |
5e55efc9 BS |
915 | bit_mask = s->gr[VGA_GFX_BIT_MASK] & val; |
916 | val = mask16[s->gr[VGA_GFX_SR_VALUE]]; | |
e89f66ec FB |
917 | break; |
918 | } | |
919 | ||
920 | /* apply logical operation */ | |
5e55efc9 | 921 | func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3; |
e89f66ec FB |
922 | switch(func_select) { |
923 | case 0: | |
924 | default: | |
925 | /* nothing to do */ | |
926 | break; | |
927 | case 1: | |
928 | /* and */ | |
929 | val &= s->latch; | |
930 | break; | |
931 | case 2: | |
932 | /* or */ | |
933 | val |= s->latch; | |
934 | break; | |
935 | case 3: | |
936 | /* xor */ | |
937 | val ^= s->latch; | |
938 | break; | |
939 | } | |
940 | ||
941 | /* apply bit mask */ | |
942 | bit_mask |= bit_mask << 8; | |
943 | bit_mask |= bit_mask << 16; | |
944 | val = (val & bit_mask) | (s->latch & ~bit_mask); | |
945 | ||
946 | do_write: | |
947 | /* mask data according to sr[2] */ | |
5e55efc9 | 948 | mask = s->sr[VGA_SEQ_PLANE_WRITE]; |
546fa6ab FB |
949 | s->plane_updated |= mask; /* only used to detect font change */ |
950 | write_mask = mask16[mask]; | |
5fafdf24 TS |
951 | ((uint32_t *)s->vram_ptr)[addr] = |
952 | (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | | |
e89f66ec | 953 | (val & write_mask); |
17b0018b | 954 | #ifdef DEBUG_VGA_MEM |
0bf9e31a BS |
955 | printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n", |
956 | addr * 4, write_mask, val); | |
e89f66ec | 957 | #endif |
fd4aa979 | 958 | memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); |
e89f66ec FB |
959 | } |
960 | } | |
961 | ||
e89f66ec FB |
962 | typedef void vga_draw_glyph8_func(uint8_t *d, int linesize, |
963 | const uint8_t *font_ptr, int h, | |
964 | uint32_t fgcol, uint32_t bgcol); | |
965 | typedef void vga_draw_glyph9_func(uint8_t *d, int linesize, | |
5fafdf24 | 966 | const uint8_t *font_ptr, int h, |
e89f66ec | 967 | uint32_t fgcol, uint32_t bgcol, int dup9); |
cedd91d2 | 968 | typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d, |
e89f66ec FB |
969 | const uint8_t *s, int width); |
970 | ||
e89f66ec FB |
971 | #define DEPTH 8 |
972 | #include "vga_template.h" | |
973 | ||
974 | #define DEPTH 15 | |
975 | #include "vga_template.h" | |
976 | ||
a2502b58 BS |
977 | #define BGR_FORMAT |
978 | #define DEPTH 15 | |
979 | #include "vga_template.h" | |
980 | ||
981 | #define DEPTH 16 | |
982 | #include "vga_template.h" | |
983 | ||
984 | #define BGR_FORMAT | |
e89f66ec FB |
985 | #define DEPTH 16 |
986 | #include "vga_template.h" | |
987 | ||
988 | #define DEPTH 32 | |
989 | #include "vga_template.h" | |
990 | ||
d3079cd2 FB |
991 | #define BGR_FORMAT |
992 | #define DEPTH 32 | |
993 | #include "vga_template.h" | |
994 | ||
17b0018b FB |
995 | static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b) |
996 | { | |
997 | unsigned int col; | |
998 | col = rgb_to_pixel8(r, g, b); | |
999 | col |= col << 8; | |
1000 | col |= col << 16; | |
1001 | return col; | |
1002 | } | |
1003 | ||
1004 | static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b) | |
1005 | { | |
1006 | unsigned int col; | |
1007 | col = rgb_to_pixel15(r, g, b); | |
1008 | col |= col << 16; | |
1009 | return col; | |
1010 | } | |
1011 | ||
b29169d2 BS |
1012 | static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g, |
1013 | unsigned int b) | |
1014 | { | |
1015 | unsigned int col; | |
1016 | col = rgb_to_pixel15bgr(r, g, b); | |
1017 | col |= col << 16; | |
1018 | return col; | |
1019 | } | |
1020 | ||
17b0018b FB |
1021 | static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b) |
1022 | { | |
1023 | unsigned int col; | |
1024 | col = rgb_to_pixel16(r, g, b); | |
1025 | col |= col << 16; | |
1026 | return col; | |
1027 | } | |
1028 | ||
b29169d2 BS |
1029 | static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g, |
1030 | unsigned int b) | |
1031 | { | |
1032 | unsigned int col; | |
1033 | col = rgb_to_pixel16bgr(r, g, b); | |
1034 | col |= col << 16; | |
1035 | return col; | |
1036 | } | |
1037 | ||
17b0018b FB |
1038 | static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b) |
1039 | { | |
1040 | unsigned int col; | |
1041 | col = rgb_to_pixel32(r, g, b); | |
1042 | return col; | |
1043 | } | |
1044 | ||
d3079cd2 FB |
1045 | static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b) |
1046 | { | |
1047 | unsigned int col; | |
1048 | col = rgb_to_pixel32bgr(r, g, b); | |
1049 | return col; | |
1050 | } | |
1051 | ||
e89f66ec | 1052 | /* return true if the palette was modified */ |
cedd91d2 | 1053 | static int update_palette16(VGACommonState *s) |
e89f66ec | 1054 | { |
17b0018b | 1055 | int full_update, i; |
e89f66ec | 1056 | uint32_t v, col, *palette; |
e89f66ec FB |
1057 | |
1058 | full_update = 0; | |
1059 | palette = s->last_palette; | |
1060 | for(i = 0; i < 16; i++) { | |
1061 | v = s->ar[i]; | |
5e55efc9 BS |
1062 | if (s->ar[VGA_ATC_MODE] & 0x80) { |
1063 | v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf); | |
1064 | } else { | |
1065 | v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f); | |
1066 | } | |
e89f66ec | 1067 | v = v * 3; |
5fafdf24 TS |
1068 | col = s->rgb_to_pixel(c6_to_8(s->palette[v]), |
1069 | c6_to_8(s->palette[v + 1]), | |
17b0018b FB |
1070 | c6_to_8(s->palette[v + 2])); |
1071 | if (col != palette[i]) { | |
1072 | full_update = 1; | |
1073 | palette[i] = col; | |
e89f66ec | 1074 | } |
17b0018b FB |
1075 | } |
1076 | return full_update; | |
1077 | } | |
1078 | ||
1079 | /* return true if the palette was modified */ | |
cedd91d2 | 1080 | static int update_palette256(VGACommonState *s) |
17b0018b FB |
1081 | { |
1082 | int full_update, i; | |
1083 | uint32_t v, col, *palette; | |
1084 | ||
1085 | full_update = 0; | |
1086 | palette = s->last_palette; | |
1087 | v = 0; | |
1088 | for(i = 0; i < 256; i++) { | |
37dd208d | 1089 | if (s->dac_8bit) { |
5fafdf24 TS |
1090 | col = s->rgb_to_pixel(s->palette[v], |
1091 | s->palette[v + 1], | |
37dd208d FB |
1092 | s->palette[v + 2]); |
1093 | } else { | |
5fafdf24 TS |
1094 | col = s->rgb_to_pixel(c6_to_8(s->palette[v]), |
1095 | c6_to_8(s->palette[v + 1]), | |
37dd208d FB |
1096 | c6_to_8(s->palette[v + 2])); |
1097 | } | |
e89f66ec FB |
1098 | if (col != palette[i]) { |
1099 | full_update = 1; | |
1100 | palette[i] = col; | |
1101 | } | |
17b0018b | 1102 | v += 3; |
e89f66ec FB |
1103 | } |
1104 | return full_update; | |
1105 | } | |
1106 | ||
cedd91d2 | 1107 | static void vga_get_offsets(VGACommonState *s, |
5fafdf24 | 1108 | uint32_t *pline_offset, |
83acc96b FB |
1109 | uint32_t *pstart_addr, |
1110 | uint32_t *pline_compare) | |
e89f66ec | 1111 | { |
83acc96b | 1112 | uint32_t start_addr, line_offset, line_compare; |
4fa0f5d2 FB |
1113 | #ifdef CONFIG_BOCHS_VBE |
1114 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) { | |
1115 | line_offset = s->vbe_line_offset; | |
1116 | start_addr = s->vbe_start_addr; | |
83acc96b | 1117 | line_compare = 65535; |
4fa0f5d2 FB |
1118 | } else |
1119 | #endif | |
3b46e624 | 1120 | { |
4fa0f5d2 | 1121 | /* compute line_offset in bytes */ |
5e55efc9 | 1122 | line_offset = s->cr[VGA_CRTC_OFFSET]; |
4fa0f5d2 | 1123 | line_offset <<= 3; |
08e48902 | 1124 | |
4fa0f5d2 | 1125 | /* starting address */ |
5e55efc9 BS |
1126 | start_addr = s->cr[VGA_CRTC_START_LO] | |
1127 | (s->cr[VGA_CRTC_START_HI] << 8); | |
83acc96b FB |
1128 | |
1129 | /* line compare */ | |
5e55efc9 BS |
1130 | line_compare = s->cr[VGA_CRTC_LINE_COMPARE] | |
1131 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) | | |
1132 | ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3); | |
4fa0f5d2 | 1133 | } |
798b0c25 FB |
1134 | *pline_offset = line_offset; |
1135 | *pstart_addr = start_addr; | |
83acc96b | 1136 | *pline_compare = line_compare; |
798b0c25 FB |
1137 | } |
1138 | ||
1139 | /* update start_addr and line_offset. Return TRUE if modified */ | |
cedd91d2 | 1140 | static int update_basic_params(VGACommonState *s) |
798b0c25 FB |
1141 | { |
1142 | int full_update; | |
1143 | uint32_t start_addr, line_offset, line_compare; | |
3b46e624 | 1144 | |
798b0c25 FB |
1145 | full_update = 0; |
1146 | ||
83acc96b | 1147 | s->get_offsets(s, &line_offset, &start_addr, &line_compare); |
e89f66ec FB |
1148 | |
1149 | if (line_offset != s->line_offset || | |
1150 | start_addr != s->start_addr || | |
1151 | line_compare != s->line_compare) { | |
1152 | s->line_offset = line_offset; | |
1153 | s->start_addr = start_addr; | |
1154 | s->line_compare = line_compare; | |
1155 | full_update = 1; | |
1156 | } | |
1157 | return full_update; | |
1158 | } | |
1159 | ||
b29169d2 | 1160 | #define NB_DEPTHS 7 |
d3079cd2 FB |
1161 | |
1162 | static inline int get_depth_index(DisplayState *s) | |
e89f66ec | 1163 | { |
0e1f5a0c | 1164 | switch(ds_get_bits_per_pixel(s)) { |
e89f66ec FB |
1165 | default: |
1166 | case 8: | |
1167 | return 0; | |
1168 | case 15: | |
8927bcfd | 1169 | return 1; |
e89f66ec | 1170 | case 16: |
8927bcfd | 1171 | return 2; |
e89f66ec | 1172 | case 32: |
7b5d76da AL |
1173 | if (is_surface_bgr(s->surface)) |
1174 | return 4; | |
1175 | else | |
1176 | return 3; | |
e89f66ec FB |
1177 | } |
1178 | } | |
1179 | ||
68f04a3c | 1180 | static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = { |
e89f66ec FB |
1181 | vga_draw_glyph8_8, |
1182 | vga_draw_glyph8_16, | |
1183 | vga_draw_glyph8_16, | |
1184 | vga_draw_glyph8_32, | |
d3079cd2 | 1185 | vga_draw_glyph8_32, |
b29169d2 BS |
1186 | vga_draw_glyph8_16, |
1187 | vga_draw_glyph8_16, | |
e89f66ec FB |
1188 | }; |
1189 | ||
68f04a3c | 1190 | static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = { |
17b0018b FB |
1191 | vga_draw_glyph16_8, |
1192 | vga_draw_glyph16_16, | |
1193 | vga_draw_glyph16_16, | |
1194 | vga_draw_glyph16_32, | |
d3079cd2 | 1195 | vga_draw_glyph16_32, |
b29169d2 BS |
1196 | vga_draw_glyph16_16, |
1197 | vga_draw_glyph16_16, | |
17b0018b FB |
1198 | }; |
1199 | ||
68f04a3c | 1200 | static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = { |
e89f66ec FB |
1201 | vga_draw_glyph9_8, |
1202 | vga_draw_glyph9_16, | |
1203 | vga_draw_glyph9_16, | |
1204 | vga_draw_glyph9_32, | |
d3079cd2 | 1205 | vga_draw_glyph9_32, |
b29169d2 BS |
1206 | vga_draw_glyph9_16, |
1207 | vga_draw_glyph9_16, | |
e89f66ec | 1208 | }; |
3b46e624 | 1209 | |
e89f66ec FB |
1210 | static const uint8_t cursor_glyph[32 * 4] = { |
1211 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1212 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1213 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1214 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1215 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1216 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1217 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1218 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1219 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1220 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1221 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1222 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1223 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1224 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1225 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
1226 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
3b46e624 | 1227 | }; |
e89f66ec | 1228 | |
cedd91d2 | 1229 | static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight, |
4c5e8c5c BS |
1230 | int *pcwidth, int *pcheight) |
1231 | { | |
1232 | int width, cwidth, height, cheight; | |
1233 | ||
1234 | /* total width & height */ | |
5e55efc9 | 1235 | cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1; |
4c5e8c5c | 1236 | cwidth = 8; |
5e55efc9 | 1237 | if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) { |
4c5e8c5c | 1238 | cwidth = 9; |
5e55efc9 BS |
1239 | } |
1240 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) { | |
4c5e8c5c | 1241 | cwidth = 16; /* NOTE: no 18 pixel wide */ |
5e55efc9 BS |
1242 | } |
1243 | width = (s->cr[VGA_CRTC_H_DISP] + 1); | |
1244 | if (s->cr[VGA_CRTC_V_TOTAL] == 100) { | |
4c5e8c5c BS |
1245 | /* ugly hack for CGA 160x100x16 - explain me the logic */ |
1246 | height = 100; | |
1247 | } else { | |
5e55efc9 BS |
1248 | height = s->cr[VGA_CRTC_V_DISP_END] | |
1249 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | | |
1250 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); | |
4c5e8c5c BS |
1251 | height = (height + 1) / cheight; |
1252 | } | |
1253 | ||
1254 | *pwidth = width; | |
1255 | *pheight = height; | |
1256 | *pcwidth = cwidth; | |
1257 | *pcheight = cheight; | |
1258 | } | |
1259 | ||
7d957bd8 AL |
1260 | typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b); |
1261 | ||
68f04a3c | 1262 | static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = { |
bdb19571 AL |
1263 | rgb_to_pixel8_dup, |
1264 | rgb_to_pixel15_dup, | |
1265 | rgb_to_pixel16_dup, | |
1266 | rgb_to_pixel32_dup, | |
1267 | rgb_to_pixel32bgr_dup, | |
1268 | rgb_to_pixel15bgr_dup, | |
1269 | rgb_to_pixel16bgr_dup, | |
1270 | }; | |
7d957bd8 | 1271 | |
5fafdf24 TS |
1272 | /* |
1273 | * Text mode update | |
e89f66ec FB |
1274 | * Missing: |
1275 | * - double scan | |
5fafdf24 | 1276 | * - double width |
e89f66ec FB |
1277 | * - underline |
1278 | * - flashing | |
1279 | */ | |
cedd91d2 | 1280 | static void vga_draw_text(VGACommonState *s, int full_update) |
e89f66ec FB |
1281 | { |
1282 | int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr; | |
cae334cd | 1283 | int cx_min, cx_max, linesize, x_incr, line, line1; |
e89f66ec | 1284 | uint32_t offset, fgcol, bgcol, v, cursor_offset; |
d1984194 | 1285 | uint8_t *d1, *d, *src, *dest, *cursor_ptr; |
e89f66ec FB |
1286 | const uint8_t *font_ptr, *font_base[2]; |
1287 | int dup9, line_offset, depth_index; | |
1288 | uint32_t *palette; | |
1289 | uint32_t *ch_attr_ptr; | |
1290 | vga_draw_glyph8_func *vga_draw_glyph8; | |
1291 | vga_draw_glyph9_func *vga_draw_glyph9; | |
1292 | ||
e89f66ec | 1293 | /* compute font data address (in plane 2) */ |
5e55efc9 | 1294 | v = s->sr[VGA_SEQ_CHARACTER_MAP]; |
1078f663 | 1295 | offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2; |
e89f66ec FB |
1296 | if (offset != s->font_offsets[0]) { |
1297 | s->font_offsets[0] = offset; | |
1298 | full_update = 1; | |
1299 | } | |
1300 | font_base[0] = s->vram_ptr + offset; | |
1301 | ||
1078f663 | 1302 | offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2; |
e89f66ec FB |
1303 | font_base[1] = s->vram_ptr + offset; |
1304 | if (offset != s->font_offsets[1]) { | |
1305 | s->font_offsets[1] = offset; | |
1306 | full_update = 1; | |
1307 | } | |
80763888 | 1308 | if (s->plane_updated & (1 << 2) || s->chain4_alias) { |
546fa6ab FB |
1309 | /* if the plane 2 was modified since the last display, it |
1310 | indicates the font may have been modified */ | |
1311 | s->plane_updated = 0; | |
1312 | full_update = 1; | |
1313 | } | |
799e709b | 1314 | full_update |= update_basic_params(s); |
e89f66ec FB |
1315 | |
1316 | line_offset = s->line_offset; | |
e89f66ec | 1317 | |
4c5e8c5c | 1318 | vga_get_text_resolution(s, &width, &height, &cw, &cheight); |
3294b949 FB |
1319 | if ((height * width) > CH_ATTR_SIZE) { |
1320 | /* better than nothing: exit if transient size is too big */ | |
1321 | return; | |
1322 | } | |
1323 | ||
799e709b AL |
1324 | if (width != s->last_width || height != s->last_height || |
1325 | cw != s->last_cw || cheight != s->last_ch || s->last_depth) { | |
1326 | s->last_scr_width = width * cw; | |
1327 | s->last_scr_height = height * cheight; | |
1328 | qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height); | |
1329 | s->last_depth = 0; | |
1330 | s->last_width = width; | |
1331 | s->last_height = height; | |
1332 | s->last_ch = cheight; | |
1333 | s->last_cw = cw; | |
1334 | full_update = 1; | |
1335 | } | |
7d957bd8 AL |
1336 | s->rgb_to_pixel = |
1337 | rgb_to_pixel_dup_table[get_depth_index(s->ds)]; | |
1338 | full_update |= update_palette16(s); | |
1339 | palette = s->last_palette; | |
1340 | x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); | |
1341 | ||
5e55efc9 BS |
1342 | cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | |
1343 | s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr; | |
e89f66ec | 1344 | if (cursor_offset != s->cursor_offset || |
5e55efc9 BS |
1345 | s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start || |
1346 | s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) { | |
e89f66ec FB |
1347 | /* if the cursor position changed, we update the old and new |
1348 | chars */ | |
1349 | if (s->cursor_offset < CH_ATTR_SIZE) | |
1350 | s->last_ch_attr[s->cursor_offset] = -1; | |
1351 | if (cursor_offset < CH_ATTR_SIZE) | |
1352 | s->last_ch_attr[cursor_offset] = -1; | |
1353 | s->cursor_offset = cursor_offset; | |
5e55efc9 BS |
1354 | s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; |
1355 | s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; | |
e89f66ec | 1356 | } |
39cf7803 | 1357 | cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4; |
3b46e624 | 1358 | |
d3079cd2 | 1359 | depth_index = get_depth_index(s->ds); |
17b0018b FB |
1360 | if (cw == 16) |
1361 | vga_draw_glyph8 = vga_draw_glyph16_table[depth_index]; | |
1362 | else | |
1363 | vga_draw_glyph8 = vga_draw_glyph8_table[depth_index]; | |
e89f66ec | 1364 | vga_draw_glyph9 = vga_draw_glyph9_table[depth_index]; |
3b46e624 | 1365 | |
0e1f5a0c AL |
1366 | dest = ds_get_data(s->ds); |
1367 | linesize = ds_get_linesize(s->ds); | |
e89f66ec | 1368 | ch_attr_ptr = s->last_ch_attr; |
d1984194 | 1369 | line = 0; |
1370 | offset = s->start_addr * 4; | |
e89f66ec FB |
1371 | for(cy = 0; cy < height; cy++) { |
1372 | d1 = dest; | |
d1984194 | 1373 | src = s->vram_ptr + offset; |
e89f66ec FB |
1374 | cx_min = width; |
1375 | cx_max = -1; | |
1376 | for(cx = 0; cx < width; cx++) { | |
1377 | ch_attr = *(uint16_t *)src; | |
1378 | if (full_update || ch_attr != *ch_attr_ptr) { | |
1379 | if (cx < cx_min) | |
1380 | cx_min = cx; | |
1381 | if (cx > cx_max) | |
1382 | cx_max = cx; | |
1383 | *ch_attr_ptr = ch_attr; | |
e2542fe2 | 1384 | #ifdef HOST_WORDS_BIGENDIAN |
e89f66ec FB |
1385 | ch = ch_attr >> 8; |
1386 | cattr = ch_attr & 0xff; | |
1387 | #else | |
1388 | ch = ch_attr & 0xff; | |
1389 | cattr = ch_attr >> 8; | |
1390 | #endif | |
1391 | font_ptr = font_base[(cattr >> 3) & 1]; | |
1392 | font_ptr += 32 * 4 * ch; | |
1393 | bgcol = palette[cattr >> 4]; | |
1394 | fgcol = palette[cattr & 0x0f]; | |
17b0018b | 1395 | if (cw != 9) { |
5fafdf24 | 1396 | vga_draw_glyph8(d1, linesize, |
e89f66ec FB |
1397 | font_ptr, cheight, fgcol, bgcol); |
1398 | } else { | |
1399 | dup9 = 0; | |
5e55efc9 BS |
1400 | if (ch >= 0xb0 && ch <= 0xdf && |
1401 | (s->ar[VGA_ATC_MODE] & 0x04)) { | |
e89f66ec | 1402 | dup9 = 1; |
5e55efc9 | 1403 | } |
5fafdf24 | 1404 | vga_draw_glyph9(d1, linesize, |
e89f66ec FB |
1405 | font_ptr, cheight, fgcol, bgcol, dup9); |
1406 | } | |
1407 | if (src == cursor_ptr && | |
5e55efc9 | 1408 | !(s->cr[VGA_CRTC_CURSOR_START] & 0x20)) { |
e89f66ec FB |
1409 | int line_start, line_last, h; |
1410 | /* draw the cursor */ | |
5e55efc9 BS |
1411 | line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f; |
1412 | line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f; | |
e89f66ec FB |
1413 | /* XXX: check that */ |
1414 | if (line_last > cheight - 1) | |
1415 | line_last = cheight - 1; | |
1416 | if (line_last >= line_start && line_start < cheight) { | |
1417 | h = line_last - line_start + 1; | |
1418 | d = d1 + linesize * line_start; | |
17b0018b | 1419 | if (cw != 9) { |
5fafdf24 | 1420 | vga_draw_glyph8(d, linesize, |
e89f66ec FB |
1421 | cursor_glyph, h, fgcol, bgcol); |
1422 | } else { | |
5fafdf24 | 1423 | vga_draw_glyph9(d, linesize, |
e89f66ec FB |
1424 | cursor_glyph, h, fgcol, bgcol, 1); |
1425 | } | |
1426 | } | |
1427 | } | |
1428 | } | |
1429 | d1 += x_incr; | |
1430 | src += 4; | |
1431 | ch_attr_ptr++; | |
1432 | } | |
1433 | if (cx_max != -1) { | |
5fafdf24 | 1434 | dpy_update(s->ds, cx_min * cw, cy * cheight, |
e89f66ec FB |
1435 | (cx_max - cx_min + 1) * cw, cheight); |
1436 | } | |
1437 | dest += linesize * cheight; | |
cae334cd | 1438 | line1 = line + cheight; |
1439 | offset += line_offset; | |
1440 | if (line < s->line_compare && line1 >= s->line_compare) { | |
d1984194 | 1441 | offset = 0; |
1442 | } | |
cae334cd | 1443 | line = line1; |
e89f66ec FB |
1444 | } |
1445 | } | |
1446 | ||
17b0018b FB |
1447 | enum { |
1448 | VGA_DRAW_LINE2, | |
1449 | VGA_DRAW_LINE2D2, | |
1450 | VGA_DRAW_LINE4, | |
1451 | VGA_DRAW_LINE4D2, | |
1452 | VGA_DRAW_LINE8D2, | |
1453 | VGA_DRAW_LINE8, | |
1454 | VGA_DRAW_LINE15, | |
1455 | VGA_DRAW_LINE16, | |
4fa0f5d2 | 1456 | VGA_DRAW_LINE24, |
17b0018b FB |
1457 | VGA_DRAW_LINE32, |
1458 | VGA_DRAW_LINE_NB, | |
1459 | }; | |
1460 | ||
68f04a3c | 1461 | static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = { |
e89f66ec FB |
1462 | vga_draw_line2_8, |
1463 | vga_draw_line2_16, | |
1464 | vga_draw_line2_16, | |
1465 | vga_draw_line2_32, | |
d3079cd2 | 1466 | vga_draw_line2_32, |
b29169d2 BS |
1467 | vga_draw_line2_16, |
1468 | vga_draw_line2_16, | |
e89f66ec | 1469 | |
17b0018b FB |
1470 | vga_draw_line2d2_8, |
1471 | vga_draw_line2d2_16, | |
1472 | vga_draw_line2d2_16, | |
1473 | vga_draw_line2d2_32, | |
d3079cd2 | 1474 | vga_draw_line2d2_32, |
b29169d2 BS |
1475 | vga_draw_line2d2_16, |
1476 | vga_draw_line2d2_16, | |
17b0018b | 1477 | |
e89f66ec FB |
1478 | vga_draw_line4_8, |
1479 | vga_draw_line4_16, | |
1480 | vga_draw_line4_16, | |
1481 | vga_draw_line4_32, | |
d3079cd2 | 1482 | vga_draw_line4_32, |
b29169d2 BS |
1483 | vga_draw_line4_16, |
1484 | vga_draw_line4_16, | |
e89f66ec | 1485 | |
17b0018b FB |
1486 | vga_draw_line4d2_8, |
1487 | vga_draw_line4d2_16, | |
1488 | vga_draw_line4d2_16, | |
1489 | vga_draw_line4d2_32, | |
d3079cd2 | 1490 | vga_draw_line4d2_32, |
b29169d2 BS |
1491 | vga_draw_line4d2_16, |
1492 | vga_draw_line4d2_16, | |
17b0018b FB |
1493 | |
1494 | vga_draw_line8d2_8, | |
1495 | vga_draw_line8d2_16, | |
1496 | vga_draw_line8d2_16, | |
1497 | vga_draw_line8d2_32, | |
d3079cd2 | 1498 | vga_draw_line8d2_32, |
b29169d2 BS |
1499 | vga_draw_line8d2_16, |
1500 | vga_draw_line8d2_16, | |
17b0018b | 1501 | |
e89f66ec FB |
1502 | vga_draw_line8_8, |
1503 | vga_draw_line8_16, | |
1504 | vga_draw_line8_16, | |
1505 | vga_draw_line8_32, | |
d3079cd2 | 1506 | vga_draw_line8_32, |
b29169d2 BS |
1507 | vga_draw_line8_16, |
1508 | vga_draw_line8_16, | |
e89f66ec FB |
1509 | |
1510 | vga_draw_line15_8, | |
1511 | vga_draw_line15_15, | |
1512 | vga_draw_line15_16, | |
1513 | vga_draw_line15_32, | |
d3079cd2 | 1514 | vga_draw_line15_32bgr, |
b29169d2 BS |
1515 | vga_draw_line15_15bgr, |
1516 | vga_draw_line15_16bgr, | |
e89f66ec FB |
1517 | |
1518 | vga_draw_line16_8, | |
1519 | vga_draw_line16_15, | |
1520 | vga_draw_line16_16, | |
1521 | vga_draw_line16_32, | |
d3079cd2 | 1522 | vga_draw_line16_32bgr, |
b29169d2 BS |
1523 | vga_draw_line16_15bgr, |
1524 | vga_draw_line16_16bgr, | |
e89f66ec | 1525 | |
4fa0f5d2 FB |
1526 | vga_draw_line24_8, |
1527 | vga_draw_line24_15, | |
1528 | vga_draw_line24_16, | |
1529 | vga_draw_line24_32, | |
d3079cd2 | 1530 | vga_draw_line24_32bgr, |
b29169d2 BS |
1531 | vga_draw_line24_15bgr, |
1532 | vga_draw_line24_16bgr, | |
4fa0f5d2 | 1533 | |
e89f66ec FB |
1534 | vga_draw_line32_8, |
1535 | vga_draw_line32_15, | |
1536 | vga_draw_line32_16, | |
1537 | vga_draw_line32_32, | |
d3079cd2 | 1538 | vga_draw_line32_32bgr, |
b29169d2 BS |
1539 | vga_draw_line32_15bgr, |
1540 | vga_draw_line32_16bgr, | |
d3079cd2 FB |
1541 | }; |
1542 | ||
cedd91d2 | 1543 | static int vga_get_bpp(VGACommonState *s) |
798b0c25 FB |
1544 | { |
1545 | int ret; | |
1546 | #ifdef CONFIG_BOCHS_VBE | |
1547 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) { | |
1548 | ret = s->vbe_regs[VBE_DISPI_INDEX_BPP]; | |
5fafdf24 | 1549 | } else |
798b0c25 FB |
1550 | #endif |
1551 | { | |
1552 | ret = 0; | |
1553 | } | |
1554 | return ret; | |
1555 | } | |
1556 | ||
cedd91d2 | 1557 | static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
a130a41e FB |
1558 | { |
1559 | int width, height; | |
3b46e624 | 1560 | |
8454df8b FB |
1561 | #ifdef CONFIG_BOCHS_VBE |
1562 | if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) { | |
1563 | width = s->vbe_regs[VBE_DISPI_INDEX_XRES]; | |
1564 | height = s->vbe_regs[VBE_DISPI_INDEX_YRES]; | |
5fafdf24 | 1565 | } else |
8454df8b FB |
1566 | #endif |
1567 | { | |
5e55efc9 BS |
1568 | width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8; |
1569 | height = s->cr[VGA_CRTC_V_DISP_END] | | |
1570 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | | |
1571 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); | |
8454df8b FB |
1572 | height = (height + 1); |
1573 | } | |
a130a41e FB |
1574 | *pwidth = width; |
1575 | *pheight = height; | |
1576 | } | |
1577 | ||
cedd91d2 | 1578 | void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2) |
a8aa669b FB |
1579 | { |
1580 | int y; | |
1581 | if (y1 >= VGA_MAX_HEIGHT) | |
1582 | return; | |
1583 | if (y2 >= VGA_MAX_HEIGHT) | |
1584 | y2 = VGA_MAX_HEIGHT; | |
1585 | for(y = y1; y < y2; y++) { | |
1586 | s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f); | |
1587 | } | |
1588 | } | |
1589 | ||
cedd91d2 | 1590 | static void vga_sync_dirty_bitmap(VGACommonState *s) |
2bec46dc | 1591 | { |
b1950430 | 1592 | memory_region_sync_dirty_bitmap(&s->vram); |
2bec46dc AL |
1593 | } |
1594 | ||
50af3246 JQ |
1595 | void vga_dirty_log_start(VGACommonState *s) |
1596 | { | |
b1950430 | 1597 | memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA); |
b5cc6e32 AL |
1598 | } |
1599 | ||
1600 | void vga_dirty_log_stop(VGACommonState *s) | |
1601 | { | |
b1950430 | 1602 | memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA); |
b5cc6e32 AL |
1603 | } |
1604 | ||
799e709b AL |
1605 | /* |
1606 | * graphic modes | |
1607 | */ | |
cedd91d2 | 1608 | static void vga_draw_graphic(VGACommonState *s, int full_update) |
e89f66ec | 1609 | { |
12c7e75a AK |
1610 | int y1, y, update, linesize, y_start, double_scan, mask, depth; |
1611 | int width, height, shift_control, line_offset, bwidth, bits; | |
c227f099 | 1612 | ram_addr_t page0, page1, page_min, page_max; |
a07cf92a | 1613 | int disp_width, multi_scan, multi_run; |
799e709b AL |
1614 | uint8_t *d; |
1615 | uint32_t v, addr1, addr; | |
1616 | vga_draw_line_func *vga_draw_line; | |
1617 | ||
1618 | full_update |= update_basic_params(s); | |
1619 | ||
1620 | if (!full_update) | |
1621 | vga_sync_dirty_bitmap(s); | |
2bec46dc | 1622 | |
a130a41e | 1623 | s->get_resolution(s, &width, &height); |
17b0018b | 1624 | disp_width = width; |
09a79b49 | 1625 | |
5e55efc9 BS |
1626 | shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3; |
1627 | double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7); | |
799e709b | 1628 | if (shift_control != 1) { |
5e55efc9 BS |
1629 | multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan) |
1630 | - 1; | |
799e709b AL |
1631 | } else { |
1632 | /* in CGA modes, multi_scan is ignored */ | |
1633 | /* XXX: is it correct ? */ | |
1634 | multi_scan = double_scan; | |
1635 | } | |
1636 | multi_run = multi_scan; | |
17b0018b FB |
1637 | if (shift_control != s->shift_control || |
1638 | double_scan != s->double_scan) { | |
799e709b | 1639 | full_update = 1; |
e89f66ec | 1640 | s->shift_control = shift_control; |
17b0018b | 1641 | s->double_scan = double_scan; |
e89f66ec | 1642 | } |
3b46e624 | 1643 | |
aba35a6c | 1644 | if (shift_control == 0) { |
5e55efc9 | 1645 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
aba35a6c | 1646 | disp_width <<= 1; |
1647 | } | |
1648 | } else if (shift_control == 1) { | |
5e55efc9 | 1649 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
aba35a6c | 1650 | disp_width <<= 1; |
1651 | } | |
1652 | } | |
1653 | ||
799e709b | 1654 | depth = s->get_bpp(s); |
e3697092 AJ |
1655 | if (s->line_offset != s->last_line_offset || |
1656 | disp_width != s->last_width || | |
1657 | height != s->last_height || | |
799e709b | 1658 | s->last_depth != depth) { |
e2542fe2 | 1659 | #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) |
e3697092 | 1660 | if (depth == 16 || depth == 32) { |
0da2ea1b | 1661 | #else |
1662 | if (depth == 32) { | |
1663 | #endif | |
b8c18e4c AL |
1664 | qemu_free_displaysurface(s->ds); |
1665 | s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth, | |
1666 | s->line_offset, | |
1667 | s->vram_ptr + (s->start_addr * 4)); | |
e2542fe2 | 1668 | #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
b8c18e4c | 1669 | s->ds->surface->pf = qemu_different_endianness_pixelformat(depth); |
0da2ea1b | 1670 | #endif |
b8c18e4c | 1671 | dpy_resize(s->ds); |
e3697092 AJ |
1672 | } else { |
1673 | qemu_console_resize(s->ds, disp_width, height); | |
1674 | } | |
1675 | s->last_scr_width = disp_width; | |
1676 | s->last_scr_height = height; | |
1677 | s->last_width = disp_width; | |
1678 | s->last_height = height; | |
1679 | s->last_line_offset = s->line_offset; | |
1680 | s->last_depth = depth; | |
799e709b AL |
1681 | full_update = 1; |
1682 | } else if (is_buffer_shared(s->ds->surface) && | |
e3697092 AJ |
1683 | (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) { |
1684 | s->ds->surface->data = s->vram_ptr + (s->start_addr * 4); | |
1685 | dpy_setdata(s->ds); | |
1686 | } | |
1687 | ||
1688 | s->rgb_to_pixel = | |
1689 | rgb_to_pixel_dup_table[get_depth_index(s->ds)]; | |
1690 | ||
799e709b | 1691 | if (shift_control == 0) { |
17b0018b | 1692 | full_update |= update_palette16(s); |
5e55efc9 | 1693 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
17b0018b | 1694 | v = VGA_DRAW_LINE4D2; |
17b0018b FB |
1695 | } else { |
1696 | v = VGA_DRAW_LINE4; | |
1697 | } | |
15342721 | 1698 | bits = 4; |
799e709b | 1699 | } else if (shift_control == 1) { |
17b0018b | 1700 | full_update |= update_palette16(s); |
5e55efc9 | 1701 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) { |
17b0018b | 1702 | v = VGA_DRAW_LINE2D2; |
17b0018b FB |
1703 | } else { |
1704 | v = VGA_DRAW_LINE2; | |
1705 | } | |
15342721 | 1706 | bits = 4; |
17b0018b | 1707 | } else { |
798b0c25 FB |
1708 | switch(s->get_bpp(s)) { |
1709 | default: | |
1710 | case 0: | |
4fa0f5d2 FB |
1711 | full_update |= update_palette256(s); |
1712 | v = VGA_DRAW_LINE8D2; | |
15342721 | 1713 | bits = 4; |
798b0c25 FB |
1714 | break; |
1715 | case 8: | |
1716 | full_update |= update_palette256(s); | |
1717 | v = VGA_DRAW_LINE8; | |
15342721 | 1718 | bits = 8; |
798b0c25 FB |
1719 | break; |
1720 | case 15: | |
1721 | v = VGA_DRAW_LINE15; | |
15342721 | 1722 | bits = 16; |
798b0c25 FB |
1723 | break; |
1724 | case 16: | |
1725 | v = VGA_DRAW_LINE16; | |
15342721 | 1726 | bits = 16; |
798b0c25 FB |
1727 | break; |
1728 | case 24: | |
1729 | v = VGA_DRAW_LINE24; | |
15342721 | 1730 | bits = 24; |
798b0c25 FB |
1731 | break; |
1732 | case 32: | |
1733 | v = VGA_DRAW_LINE32; | |
15342721 | 1734 | bits = 32; |
798b0c25 | 1735 | break; |
4fa0f5d2 | 1736 | } |
17b0018b | 1737 | } |
d3079cd2 | 1738 | vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)]; |
17b0018b | 1739 | |
7d957bd8 | 1740 | if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate) |
a8aa669b | 1741 | s->cursor_invalidate(s); |
3b46e624 | 1742 | |
e89f66ec | 1743 | line_offset = s->line_offset; |
17b0018b | 1744 | #if 0 |
f6c958c8 | 1745 | printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n", |
5e55efc9 BS |
1746 | width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE], |
1747 | s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]); | |
17b0018b | 1748 | #endif |
e89f66ec | 1749 | addr1 = (s->start_addr * 4); |
15342721 | 1750 | bwidth = (width * bits + 7) / 8; |
39cf7803 | 1751 | y_start = -1; |
12c7e75a AK |
1752 | page_min = -1; |
1753 | page_max = 0; | |
0e1f5a0c AL |
1754 | d = ds_get_data(s->ds); |
1755 | linesize = ds_get_linesize(s->ds); | |
17b0018b | 1756 | y1 = 0; |
e89f66ec FB |
1757 | for(y = 0; y < height; y++) { |
1758 | addr = addr1; | |
5e55efc9 | 1759 | if (!(s->cr[VGA_CRTC_MODE] & 1)) { |
17b0018b | 1760 | int shift; |
e89f66ec | 1761 | /* CGA compatibility handling */ |
5e55efc9 | 1762 | shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1); |
17b0018b | 1763 | addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift); |
e89f66ec | 1764 | } |
5e55efc9 | 1765 | if (!(s->cr[VGA_CRTC_MODE] & 2)) { |
17b0018b | 1766 | addr = (addr & ~0x8000) | ((y1 & 2) << 14); |
e89f66ec | 1767 | } |
cd7a45c9 BS |
1768 | page0 = addr; |
1769 | page1 = addr + bwidth - 1; | |
1770 | update = memory_region_get_dirty(&s->vram, page0, page1, | |
1771 | DIRTY_MEMORY_VGA); | |
a8aa669b FB |
1772 | /* explicit invalidation for the hardware cursor */ |
1773 | update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1; | |
e89f66ec | 1774 | if (update) { |
39cf7803 FB |
1775 | if (y_start < 0) |
1776 | y_start = y; | |
e89f66ec FB |
1777 | if (page0 < page_min) |
1778 | page_min = page0; | |
1779 | if (page1 > page_max) | |
1780 | page_max = page1; | |
7d957bd8 AL |
1781 | if (!(is_buffer_shared(s->ds->surface))) { |
1782 | vga_draw_line(s, d, s->vram_ptr + addr, width); | |
1783 | if (s->cursor_draw_line) | |
1784 | s->cursor_draw_line(s, d, y); | |
1785 | } | |
39cf7803 FB |
1786 | } else { |
1787 | if (y_start >= 0) { | |
1788 | /* flush to display */ | |
5fafdf24 | 1789 | dpy_update(s->ds, 0, y_start, |
799e709b | 1790 | disp_width, y - y_start); |
39cf7803 FB |
1791 | y_start = -1; |
1792 | } | |
e89f66ec | 1793 | } |
a07cf92a | 1794 | if (!multi_run) { |
5e55efc9 | 1795 | mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3; |
f6c958c8 FB |
1796 | if ((y1 & mask) == mask) |
1797 | addr1 += line_offset; | |
1798 | y1++; | |
799e709b | 1799 | multi_run = multi_scan; |
a07cf92a FB |
1800 | } else { |
1801 | multi_run--; | |
e89f66ec | 1802 | } |
f6c958c8 FB |
1803 | /* line compare acts on the displayed lines */ |
1804 | if (y == s->line_compare) | |
1805 | addr1 = 0; | |
e89f66ec FB |
1806 | d += linesize; |
1807 | } | |
39cf7803 FB |
1808 | if (y_start >= 0) { |
1809 | /* flush to display */ | |
5fafdf24 | 1810 | dpy_update(s->ds, 0, y_start, |
799e709b | 1811 | disp_width, y - y_start); |
39cf7803 | 1812 | } |
e89f66ec | 1813 | /* reset modified pages */ |
12c7e75a | 1814 | if (page_max >= page_min) { |
b1950430 AK |
1815 | memory_region_reset_dirty(&s->vram, |
1816 | page_min, | |
cd7a45c9 | 1817 | page_max - page_min, |
b1950430 | 1818 | DIRTY_MEMORY_VGA); |
e89f66ec | 1819 | } |
a8aa669b | 1820 | memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4); |
e89f66ec FB |
1821 | } |
1822 | ||
cedd91d2 | 1823 | static void vga_draw_blank(VGACommonState *s, int full_update) |
2aebb3eb FB |
1824 | { |
1825 | int i, w, val; | |
1826 | uint8_t *d; | |
1827 | ||
1828 | if (!full_update) | |
1829 | return; | |
1830 | if (s->last_scr_width <= 0 || s->last_scr_height <= 0) | |
1831 | return; | |
2bec46dc | 1832 | |
7d957bd8 AL |
1833 | s->rgb_to_pixel = |
1834 | rgb_to_pixel_dup_table[get_depth_index(s->ds)]; | |
0e1f5a0c | 1835 | if (ds_get_bits_per_pixel(s->ds) == 8) |
2aebb3eb FB |
1836 | val = s->rgb_to_pixel(0, 0, 0); |
1837 | else | |
1838 | val = 0; | |
0e1f5a0c AL |
1839 | w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); |
1840 | d = ds_get_data(s->ds); | |
2aebb3eb FB |
1841 | for(i = 0; i < s->last_scr_height; i++) { |
1842 | memset(d, val, w); | |
0e1f5a0c | 1843 | d += ds_get_linesize(s->ds); |
2aebb3eb | 1844 | } |
5fafdf24 | 1845 | dpy_update(s->ds, 0, 0, |
2aebb3eb FB |
1846 | s->last_scr_width, s->last_scr_height); |
1847 | } | |
1848 | ||
799e709b AL |
1849 | #define GMODE_TEXT 0 |
1850 | #define GMODE_GRAPH 1 | |
1851 | #define GMODE_BLANK 2 | |
1852 | ||
95219897 | 1853 | static void vga_update_display(void *opaque) |
e89f66ec | 1854 | { |
cedd91d2 | 1855 | VGACommonState *s = opaque; |
799e709b | 1856 | int full_update, graphic_mode; |
e89f66ec | 1857 | |
e9a07334 JK |
1858 | qemu_flush_coalesced_mmio_buffer(); |
1859 | ||
0e1f5a0c | 1860 | if (ds_get_bits_per_pixel(s->ds) == 0) { |
0f35920c | 1861 | /* nothing to do */ |
59a983b9 | 1862 | } else { |
3098b9fd | 1863 | full_update = 0; |
799e709b AL |
1864 | if (!(s->ar_index & 0x20)) { |
1865 | graphic_mode = GMODE_BLANK; | |
1866 | } else { | |
5e55efc9 | 1867 | graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE; |
799e709b AL |
1868 | } |
1869 | if (graphic_mode != s->graphic_mode) { | |
1870 | s->graphic_mode = graphic_mode; | |
1871 | full_update = 1; | |
1872 | } | |
1873 | switch(graphic_mode) { | |
2aebb3eb | 1874 | case GMODE_TEXT: |
e89f66ec | 1875 | vga_draw_text(s, full_update); |
2aebb3eb FB |
1876 | break; |
1877 | case GMODE_GRAPH: | |
1878 | vga_draw_graphic(s, full_update); | |
1879 | break; | |
1880 | case GMODE_BLANK: | |
1881 | default: | |
1882 | vga_draw_blank(s, full_update); | |
1883 | break; | |
1884 | } | |
e89f66ec FB |
1885 | } |
1886 | } | |
1887 | ||
a130a41e | 1888 | /* force a full display refresh */ |
95219897 | 1889 | static void vga_invalidate_display(void *opaque) |
a130a41e | 1890 | { |
cedd91d2 | 1891 | VGACommonState *s = opaque; |
3b46e624 | 1892 | |
3098b9fd AJ |
1893 | s->last_width = -1; |
1894 | s->last_height = -1; | |
a130a41e FB |
1895 | } |
1896 | ||
03a3e7ba | 1897 | void vga_common_reset(VGACommonState *s) |
e89f66ec | 1898 | { |
6e6b7363 BS |
1899 | s->sr_index = 0; |
1900 | memset(s->sr, '\0', sizeof(s->sr)); | |
1901 | s->gr_index = 0; | |
1902 | memset(s->gr, '\0', sizeof(s->gr)); | |
1903 | s->ar_index = 0; | |
1904 | memset(s->ar, '\0', sizeof(s->ar)); | |
1905 | s->ar_flip_flop = 0; | |
1906 | s->cr_index = 0; | |
1907 | memset(s->cr, '\0', sizeof(s->cr)); | |
1908 | s->msr = 0; | |
1909 | s->fcr = 0; | |
1910 | s->st00 = 0; | |
1911 | s->st01 = 0; | |
1912 | s->dac_state = 0; | |
1913 | s->dac_sub_index = 0; | |
1914 | s->dac_read_index = 0; | |
1915 | s->dac_write_index = 0; | |
1916 | memset(s->dac_cache, '\0', sizeof(s->dac_cache)); | |
1917 | s->dac_8bit = 0; | |
1918 | memset(s->palette, '\0', sizeof(s->palette)); | |
1919 | s->bank_offset = 0; | |
1920 | #ifdef CONFIG_BOCHS_VBE | |
1921 | s->vbe_index = 0; | |
1922 | memset(s->vbe_regs, '\0', sizeof(s->vbe_regs)); | |
af92284b | 1923 | s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5; |
6e6b7363 BS |
1924 | s->vbe_start_addr = 0; |
1925 | s->vbe_line_offset = 0; | |
1926 | s->vbe_bank_mask = (s->vram_size >> 16) - 1; | |
1927 | #endif | |
1928 | memset(s->font_offsets, '\0', sizeof(s->font_offsets)); | |
799e709b | 1929 | s->graphic_mode = -1; /* force full update */ |
6e6b7363 BS |
1930 | s->shift_control = 0; |
1931 | s->double_scan = 0; | |
1932 | s->line_offset = 0; | |
1933 | s->line_compare = 0; | |
1934 | s->start_addr = 0; | |
1935 | s->plane_updated = 0; | |
1936 | s->last_cw = 0; | |
1937 | s->last_ch = 0; | |
1938 | s->last_width = 0; | |
1939 | s->last_height = 0; | |
1940 | s->last_scr_width = 0; | |
1941 | s->last_scr_height = 0; | |
1942 | s->cursor_start = 0; | |
1943 | s->cursor_end = 0; | |
1944 | s->cursor_offset = 0; | |
1945 | memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table)); | |
1946 | memset(s->last_palette, '\0', sizeof(s->last_palette)); | |
1947 | memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr)); | |
1948 | switch (vga_retrace_method) { | |
1949 | case VGA_RETRACE_DUMB: | |
1950 | break; | |
1951 | case VGA_RETRACE_PRECISE: | |
1952 | memset(&s->retrace_info, 0, sizeof (s->retrace_info)); | |
1953 | break; | |
1954 | } | |
80763888 | 1955 | vga_update_memory_access(s); |
e89f66ec FB |
1956 | } |
1957 | ||
03a3e7ba JQ |
1958 | static void vga_reset(void *opaque) |
1959 | { | |
cedd91d2 | 1960 | VGACommonState *s = opaque; |
03a3e7ba JQ |
1961 | vga_common_reset(s); |
1962 | } | |
1963 | ||
4d3b6f6e AZ |
1964 | #define TEXTMODE_X(x) ((x) % width) |
1965 | #define TEXTMODE_Y(x) ((x) / width) | |
1966 | #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \ | |
1967 | ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1)) | |
1968 | /* relay text rendering to the display driver | |
1969 | * instead of doing a full vga_update_display() */ | |
c227f099 | 1970 | static void vga_update_text(void *opaque, console_ch_t *chardata) |
4d3b6f6e | 1971 | { |
cedd91d2 | 1972 | VGACommonState *s = opaque; |
799e709b | 1973 | int graphic_mode, i, cursor_offset, cursor_visible; |
4d3b6f6e AZ |
1974 | int cw, cheight, width, height, size, c_min, c_max; |
1975 | uint32_t *src; | |
c227f099 | 1976 | console_ch_t *dst, val; |
4d3b6f6e | 1977 | char msg_buffer[80]; |
799e709b AL |
1978 | int full_update = 0; |
1979 | ||
e9a07334 JK |
1980 | qemu_flush_coalesced_mmio_buffer(); |
1981 | ||
799e709b AL |
1982 | if (!(s->ar_index & 0x20)) { |
1983 | graphic_mode = GMODE_BLANK; | |
1984 | } else { | |
5e55efc9 | 1985 | graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE; |
799e709b AL |
1986 | } |
1987 | if (graphic_mode != s->graphic_mode) { | |
1988 | s->graphic_mode = graphic_mode; | |
1989 | full_update = 1; | |
1990 | } | |
1991 | if (s->last_width == -1) { | |
1992 | s->last_width = 0; | |
1993 | full_update = 1; | |
1994 | } | |
4d3b6f6e | 1995 | |
799e709b | 1996 | switch (graphic_mode) { |
4d3b6f6e AZ |
1997 | case GMODE_TEXT: |
1998 | /* TODO: update palette */ | |
799e709b | 1999 | full_update |= update_basic_params(s); |
4d3b6f6e | 2000 | |
799e709b | 2001 | /* total width & height */ |
5e55efc9 | 2002 | cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1; |
799e709b | 2003 | cw = 8; |
5e55efc9 | 2004 | if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) { |
799e709b | 2005 | cw = 9; |
5e55efc9 BS |
2006 | } |
2007 | if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) { | |
799e709b | 2008 | cw = 16; /* NOTE: no 18 pixel wide */ |
5e55efc9 BS |
2009 | } |
2010 | width = (s->cr[VGA_CRTC_H_DISP] + 1); | |
2011 | if (s->cr[VGA_CRTC_V_TOTAL] == 100) { | |
799e709b AL |
2012 | /* ugly hack for CGA 160x100x16 - explain me the logic */ |
2013 | height = 100; | |
2014 | } else { | |
5e55efc9 BS |
2015 | height = s->cr[VGA_CRTC_V_DISP_END] | |
2016 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | | |
2017 | ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); | |
799e709b | 2018 | height = (height + 1) / cheight; |
4d3b6f6e AZ |
2019 | } |
2020 | ||
2021 | size = (height * width); | |
2022 | if (size > CH_ATTR_SIZE) { | |
2023 | if (!full_update) | |
2024 | return; | |
2025 | ||
363a37d5 BS |
2026 | snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode", |
2027 | width, height); | |
4d3b6f6e AZ |
2028 | break; |
2029 | } | |
2030 | ||
799e709b AL |
2031 | if (width != s->last_width || height != s->last_height || |
2032 | cw != s->last_cw || cheight != s->last_ch) { | |
2033 | s->last_scr_width = width * cw; | |
2034 | s->last_scr_height = height * cheight; | |
2035 | s->ds->surface->width = width; | |
2036 | s->ds->surface->height = height; | |
2037 | dpy_resize(s->ds); | |
2038 | s->last_width = width; | |
2039 | s->last_height = height; | |
2040 | s->last_ch = cheight; | |
2041 | s->last_cw = cw; | |
2042 | full_update = 1; | |
2043 | } | |
2044 | ||
4d3b6f6e | 2045 | /* Update "hardware" cursor */ |
5e55efc9 BS |
2046 | cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | |
2047 | s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr; | |
4d3b6f6e | 2048 | if (cursor_offset != s->cursor_offset || |
5e55efc9 BS |
2049 | s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start || |
2050 | s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) { | |
2051 | cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20); | |
4d3b6f6e AZ |
2052 | if (cursor_visible && cursor_offset < size && cursor_offset >= 0) |
2053 | dpy_cursor(s->ds, | |
2054 | TEXTMODE_X(cursor_offset), | |
2055 | TEXTMODE_Y(cursor_offset)); | |
2056 | else | |
2057 | dpy_cursor(s->ds, -1, -1); | |
2058 | s->cursor_offset = cursor_offset; | |
5e55efc9 BS |
2059 | s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; |
2060 | s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; | |
4d3b6f6e AZ |
2061 | } |
2062 | ||
2063 | src = (uint32_t *) s->vram_ptr + s->start_addr; | |
2064 | dst = chardata; | |
2065 | ||
2066 | if (full_update) { | |
2067 | for (i = 0; i < size; src ++, dst ++, i ++) | |
9ae19b65 | 2068 | console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src))); |
4d3b6f6e AZ |
2069 | |
2070 | dpy_update(s->ds, 0, 0, width, height); | |
2071 | } else { | |
2072 | c_max = 0; | |
2073 | ||
2074 | for (i = 0; i < size; src ++, dst ++, i ++) { | |
9ae19b65 | 2075 | console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src))); |
4d3b6f6e AZ |
2076 | if (*dst != val) { |
2077 | *dst = val; | |
2078 | c_max = i; | |
2079 | break; | |
2080 | } | |
2081 | } | |
2082 | c_min = i; | |
2083 | for (; i < size; src ++, dst ++, i ++) { | |
9ae19b65 | 2084 | console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src))); |
4d3b6f6e AZ |
2085 | if (*dst != val) { |
2086 | *dst = val; | |
2087 | c_max = i; | |
2088 | } | |
2089 | } | |
2090 | ||
2091 | if (c_min <= c_max) { | |
2092 | i = TEXTMODE_Y(c_min); | |
2093 | dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1); | |
2094 | } | |
2095 | } | |
2096 | ||
2097 | return; | |
2098 | case GMODE_GRAPH: | |
2099 | if (!full_update) | |
2100 | return; | |
2101 | ||
2102 | s->get_resolution(s, &width, &height); | |
363a37d5 BS |
2103 | snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode", |
2104 | width, height); | |
4d3b6f6e AZ |
2105 | break; |
2106 | case GMODE_BLANK: | |
2107 | default: | |
2108 | if (!full_update) | |
2109 | return; | |
2110 | ||
363a37d5 | 2111 | snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode"); |
4d3b6f6e AZ |
2112 | break; |
2113 | } | |
2114 | ||
2115 | /* Display a message */ | |
5228c2d3 AZ |
2116 | s->last_width = 60; |
2117 | s->last_height = height = 3; | |
4d3b6f6e | 2118 | dpy_cursor(s->ds, -1, -1); |
7d957bd8 AL |
2119 | s->ds->surface->width = s->last_width; |
2120 | s->ds->surface->height = height; | |
2121 | dpy_resize(s->ds); | |
4d3b6f6e | 2122 | |
5228c2d3 | 2123 | for (dst = chardata, i = 0; i < s->last_width * height; i ++) |
4d3b6f6e AZ |
2124 | console_write_ch(dst ++, ' '); |
2125 | ||
2126 | size = strlen(msg_buffer); | |
5228c2d3 AZ |
2127 | width = (s->last_width - size) / 2; |
2128 | dst = chardata + s->last_width + width; | |
4d3b6f6e AZ |
2129 | for (i = 0; i < size; i ++) |
2130 | console_write_ch(dst ++, 0x00200100 | msg_buffer[i]); | |
2131 | ||
5228c2d3 | 2132 | dpy_update(s->ds, 0, 0, s->last_width, height); |
4d3b6f6e AZ |
2133 | } |
2134 | ||
b1950430 AK |
2135 | static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr, |
2136 | unsigned size) | |
2137 | { | |
2138 | VGACommonState *s = opaque; | |
2139 | ||
b2a5e761 | 2140 | return vga_mem_readb(s, addr); |
b1950430 | 2141 | } |
e89f66ec | 2142 | |
b1950430 AK |
2143 | static void vga_mem_write(void *opaque, target_phys_addr_t addr, |
2144 | uint64_t data, unsigned size) | |
2145 | { | |
2146 | VGACommonState *s = opaque; | |
2147 | ||
b2a5e761 | 2148 | return vga_mem_writeb(s, addr, data); |
b1950430 AK |
2149 | } |
2150 | ||
2151 | const MemoryRegionOps vga_mem_ops = { | |
2152 | .read = vga_mem_read, | |
2153 | .write = vga_mem_write, | |
2154 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b2a5e761 AK |
2155 | .impl = { |
2156 | .min_access_size = 1, | |
2157 | .max_access_size = 1, | |
2158 | }, | |
e89f66ec FB |
2159 | }; |
2160 | ||
11b6b345 | 2161 | static int vga_common_post_load(void *opaque, int version_id) |
b0a21b53 | 2162 | { |
0d65ddc3 | 2163 | VGACommonState *s = opaque; |
11b6b345 JQ |
2164 | |
2165 | /* force refresh */ | |
2166 | s->graphic_mode = -1; | |
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | const VMStateDescription vmstate_vga_common = { | |
2171 | .name = "vga", | |
2172 | .version_id = 2, | |
2173 | .minimum_version_id = 2, | |
2174 | .minimum_version_id_old = 2, | |
2175 | .post_load = vga_common_post_load, | |
2176 | .fields = (VMStateField []) { | |
2177 | VMSTATE_UINT32(latch, VGACommonState), | |
2178 | VMSTATE_UINT8(sr_index, VGACommonState), | |
2179 | VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8), | |
2180 | VMSTATE_UINT8(gr_index, VGACommonState), | |
2181 | VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16), | |
2182 | VMSTATE_UINT8(ar_index, VGACommonState), | |
2183 | VMSTATE_BUFFER(ar, VGACommonState), | |
2184 | VMSTATE_INT32(ar_flip_flop, VGACommonState), | |
2185 | VMSTATE_UINT8(cr_index, VGACommonState), | |
2186 | VMSTATE_BUFFER(cr, VGACommonState), | |
2187 | VMSTATE_UINT8(msr, VGACommonState), | |
2188 | VMSTATE_UINT8(fcr, VGACommonState), | |
2189 | VMSTATE_UINT8(st00, VGACommonState), | |
2190 | VMSTATE_UINT8(st01, VGACommonState), | |
2191 | ||
2192 | VMSTATE_UINT8(dac_state, VGACommonState), | |
2193 | VMSTATE_UINT8(dac_sub_index, VGACommonState), | |
2194 | VMSTATE_UINT8(dac_read_index, VGACommonState), | |
2195 | VMSTATE_UINT8(dac_write_index, VGACommonState), | |
2196 | VMSTATE_BUFFER(dac_cache, VGACommonState), | |
2197 | VMSTATE_BUFFER(palette, VGACommonState), | |
2198 | ||
2199 | VMSTATE_INT32(bank_offset, VGACommonState), | |
2200 | VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState), | |
b0a21b53 | 2201 | #ifdef CONFIG_BOCHS_VBE |
11b6b345 JQ |
2202 | VMSTATE_UINT16(vbe_index, VGACommonState), |
2203 | VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB), | |
2204 | VMSTATE_UINT32(vbe_start_addr, VGACommonState), | |
2205 | VMSTATE_UINT32(vbe_line_offset, VGACommonState), | |
2206 | VMSTATE_UINT32(vbe_bank_mask, VGACommonState), | |
b0a21b53 | 2207 | #endif |
11b6b345 JQ |
2208 | VMSTATE_END_OF_LIST() |
2209 | } | |
2210 | }; | |
2211 | ||
a4a2f59c | 2212 | void vga_common_init(VGACommonState *s, int vga_ram_size) |
e89f66ec | 2213 | { |
17b0018b | 2214 | int i, j, v, b; |
e89f66ec FB |
2215 | |
2216 | for(i = 0;i < 256; i++) { | |
2217 | v = 0; | |
2218 | for(j = 0; j < 8; j++) { | |
2219 | v |= ((i >> j) & 1) << (j * 4); | |
2220 | } | |
2221 | expand4[i] = v; | |
2222 | ||
2223 | v = 0; | |
2224 | for(j = 0; j < 4; j++) { | |
2225 | v |= ((i >> (2 * j)) & 3) << (j * 4); | |
2226 | } | |
2227 | expand2[i] = v; | |
2228 | } | |
17b0018b FB |
2229 | for(i = 0; i < 16; i++) { |
2230 | v = 0; | |
2231 | for(j = 0; j < 4; j++) { | |
2232 | b = ((i >> j) & 1); | |
2233 | v |= b << (2 * j); | |
2234 | v |= b << (2 * j + 1); | |
2235 | } | |
2236 | expand4to8[i] = v; | |
2237 | } | |
e89f66ec | 2238 | |
2a3138ab JQ |
2239 | #ifdef CONFIG_BOCHS_VBE |
2240 | s->is_vbe_vmstate = 1; | |
2241 | #else | |
2242 | s->is_vbe_vmstate = 0; | |
2243 | #endif | |
c5705a77 AK |
2244 | memory_region_init_ram(&s->vram, "vga.vram", vga_ram_size); |
2245 | vmstate_register_ram_global(&s->vram); | |
c65adf9b | 2246 | xen_register_framebuffer(&s->vram); |
b1950430 | 2247 | s->vram_ptr = memory_region_get_ram_ptr(&s->vram); |
e89f66ec | 2248 | s->vram_size = vga_ram_size; |
798b0c25 FB |
2249 | s->get_bpp = vga_get_bpp; |
2250 | s->get_offsets = vga_get_offsets; | |
a130a41e | 2251 | s->get_resolution = vga_get_resolution; |
d34cab9f TS |
2252 | s->update = vga_update_display; |
2253 | s->invalidate = vga_invalidate_display; | |
2254 | s->screen_dump = vga_screen_dump; | |
4d3b6f6e | 2255 | s->text_update = vga_update_text; |
cb5a7aa8 | 2256 | switch (vga_retrace_method) { |
2257 | case VGA_RETRACE_DUMB: | |
2258 | s->retrace = vga_dumb_retrace; | |
2259 | s->update_retrace_info = vga_dumb_update_retrace_info; | |
2260 | break; | |
2261 | ||
2262 | case VGA_RETRACE_PRECISE: | |
2263 | s->retrace = vga_precise_retrace; | |
2264 | s->update_retrace_info = vga_precise_update_retrace_info; | |
cb5a7aa8 | 2265 | break; |
2266 | } | |
b1950430 | 2267 | vga_dirty_log_start(s); |
798b0c25 FB |
2268 | } |
2269 | ||
0a039dc7 RH |
2270 | static const MemoryRegionPortio vga_portio_list[] = { |
2271 | { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */ | |
2272 | { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */ | |
2273 | { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */ | |
2274 | { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */ | |
2275 | { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */ | |
2276 | PORTIO_END_OF_LIST(), | |
2277 | }; | |
e89f66ec | 2278 | |
4fa0f5d2 | 2279 | #ifdef CONFIG_BOCHS_VBE |
0a039dc7 RH |
2280 | static const MemoryRegionPortio vbe_portio_list[] = { |
2281 | { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index }, | |
2282 | # ifdef TARGET_I386 | |
2283 | { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data }, | |
2284 | # else | |
2285 | { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data }, | |
2286 | # endif | |
2287 | PORTIO_END_OF_LIST(), | |
2288 | }; | |
2289 | #endif /* CONFIG_BOCHS_VBE */ | |
4fa0f5d2 | 2290 | |
0a039dc7 RH |
2291 | /* Used by both ISA and PCI */ |
2292 | MemoryRegion *vga_init_io(VGACommonState *s, | |
2293 | const MemoryRegionPortio **vga_ports, | |
2294 | const MemoryRegionPortio **vbe_ports) | |
2295 | { | |
2296 | MemoryRegion *vga_mem; | |
09a79b49 | 2297 | |
0a039dc7 RH |
2298 | *vga_ports = vga_portio_list; |
2299 | *vbe_ports = NULL; | |
2300 | #ifdef CONFIG_BOCHS_VBE | |
2301 | *vbe_ports = vbe_portio_list; | |
4fa0f5d2 FB |
2302 | #endif |
2303 | ||
7267c094 | 2304 | vga_mem = g_malloc(sizeof(*vga_mem)); |
b1950430 AK |
2305 | memory_region_init_io(vga_mem, &vga_mem_ops, s, |
2306 | "vga-lowmem", 0x20000); | |
2307 | ||
2308 | return vga_mem; | |
7435b791 BS |
2309 | } |
2310 | ||
0a039dc7 RH |
2311 | void vga_init(VGACommonState *s, MemoryRegion *address_space, |
2312 | MemoryRegion *address_space_io, bool init_vga_ports) | |
7435b791 | 2313 | { |
b1950430 | 2314 | MemoryRegion *vga_io_memory; |
0a039dc7 RH |
2315 | const MemoryRegionPortio *vga_ports, *vbe_ports; |
2316 | PortioList *vga_port_list = g_new(PortioList, 1); | |
2317 | PortioList *vbe_port_list = g_new(PortioList, 1); | |
7435b791 BS |
2318 | |
2319 | qemu_register_reset(vga_reset, s); | |
2320 | ||
2321 | s->bank_offset = 0; | |
2322 | ||
80763888 JK |
2323 | s->legacy_address_space = address_space; |
2324 | ||
0a039dc7 | 2325 | vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports); |
be20f9e9 | 2326 | memory_region_add_subregion_overlap(address_space, |
b1950430 AK |
2327 | isa_mem_base + 0x000a0000, |
2328 | vga_io_memory, | |
2329 | 1); | |
2330 | memory_region_set_coalescing(vga_io_memory); | |
0a039dc7 RH |
2331 | if (init_vga_ports) { |
2332 | portio_list_init(vga_port_list, vga_ports, s, "vga"); | |
2333 | portio_list_add(vga_port_list, address_space_io, 0x3b0); | |
2334 | } | |
2335 | if (vbe_ports) { | |
2336 | portio_list_init(vbe_port_list, vbe_ports, s, "vbe"); | |
2337 | portio_list_add(vbe_port_list, address_space_io, 0x1ce); | |
2338 | } | |
d2269f6f FB |
2339 | } |
2340 | ||
be20f9e9 | 2341 | void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory) |
f0138a63 AL |
2342 | { |
2343 | #ifdef CONFIG_BOCHS_VBE | |
2344 | /* XXX: use optimized standard vga accesses */ | |
be20f9e9 | 2345 | memory_region_add_subregion(system_memory, |
b1950430 AK |
2346 | VBE_DISPI_LFB_PHYSICAL_ADDRESS, |
2347 | &s->vram); | |
f0138a63 AL |
2348 | s->vbe_mapped = 1; |
2349 | #endif | |
2350 | } | |
59a983b9 FB |
2351 | /********************************************************/ |
2352 | /* vga screen dump */ | |
2353 | ||
04a52b41 | 2354 | static void vga_save_dpy_update(DisplayState *ds, |
59a983b9 FB |
2355 | int x, int y, int w, int h) |
2356 | { | |
04a52b41 SS |
2357 | if (screen_dump_filename) { |
2358 | ppm_save(screen_dump_filename, ds->surface); | |
04a52b41 | 2359 | } |
59a983b9 FB |
2360 | } |
2361 | ||
7d957bd8 | 2362 | static void vga_save_dpy_resize(DisplayState *s) |
59a983b9 | 2363 | { |
59a983b9 FB |
2364 | } |
2365 | ||
2366 | static void vga_save_dpy_refresh(DisplayState *s) | |
2367 | { | |
2368 | } | |
2369 | ||
e07d630a | 2370 | int ppm_save(const char *filename, struct DisplaySurface *ds) |
59a983b9 FB |
2371 | { |
2372 | FILE *f; | |
2373 | uint8_t *d, *d1; | |
e07d630a | 2374 | uint32_t v; |
59a983b9 | 2375 | int y, x; |
e07d630a | 2376 | uint8_t r, g, b; |
f8e378f2 AK |
2377 | int ret; |
2378 | char *linebuf, *pbuf; | |
59a983b9 FB |
2379 | |
2380 | f = fopen(filename, "wb"); | |
2381 | if (!f) | |
2382 | return -1; | |
2383 | fprintf(f, "P6\n%d %d\n%d\n", | |
e07d630a | 2384 | ds->width, ds->height, 255); |
7267c094 | 2385 | linebuf = g_malloc(ds->width * 3); |
e07d630a AL |
2386 | d1 = ds->data; |
2387 | for(y = 0; y < ds->height; y++) { | |
59a983b9 | 2388 | d = d1; |
f8e378f2 | 2389 | pbuf = linebuf; |
e07d630a AL |
2390 | for(x = 0; x < ds->width; x++) { |
2391 | if (ds->pf.bits_per_pixel == 32) | |
2392 | v = *(uint32_t *)d; | |
2393 | else | |
2394 | v = (uint32_t) (*(uint16_t *)d); | |
a0f42610 AK |
2395 | /* Limited to 8 or fewer bits per channel: */ |
2396 | r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits); | |
2397 | g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits); | |
2398 | b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits); | |
f8e378f2 AK |
2399 | *pbuf++ = r; |
2400 | *pbuf++ = g; | |
2401 | *pbuf++ = b; | |
e07d630a | 2402 | d += ds->pf.bytes_per_pixel; |
59a983b9 | 2403 | } |
e07d630a | 2404 | d1 += ds->linesize; |
f8e378f2 AK |
2405 | ret = fwrite(linebuf, 1, pbuf - linebuf, f); |
2406 | (void)ret; | |
59a983b9 | 2407 | } |
7267c094 | 2408 | g_free(linebuf); |
59a983b9 FB |
2409 | fclose(f); |
2410 | return 0; | |
2411 | } | |
2412 | ||
04a52b41 | 2413 | static DisplayChangeListener* vga_screen_dump_init(DisplayState *ds) |
4c5e8c5c | 2414 | { |
04a52b41 | 2415 | DisplayChangeListener *dcl; |
4c5e8c5c | 2416 | |
7267c094 | 2417 | dcl = g_malloc0(sizeof(DisplayChangeListener)); |
04a52b41 SS |
2418 | dcl->dpy_update = vga_save_dpy_update; |
2419 | dcl->dpy_resize = vga_save_dpy_resize; | |
2420 | dcl->dpy_refresh = vga_save_dpy_refresh; | |
2421 | register_displaychangelistener(ds, dcl); | |
2422 | return dcl; | |
4c5e8c5c BS |
2423 | } |
2424 | ||
2425 | /* save the vga display in a PPM image even if no display is | |
2426 | available */ | |
2427 | static void vga_screen_dump(void *opaque, const char *filename) | |
2428 | { | |
cedd91d2 | 2429 | VGACommonState *s = opaque; |
4c5e8c5c | 2430 | |
04a52b41 SS |
2431 | if (!screen_dump_dcl) |
2432 | screen_dump_dcl = vga_screen_dump_init(s->ds); | |
2433 | ||
2313e998 | 2434 | screen_dump_filename = filename; |
9d1b494a | 2435 | vga_invalidate_display(s); |
04a52b41 | 2436 | vga_hw_update(); |
2313e998 | 2437 | screen_dump_filename = NULL; |
4c5e8c5c | 2438 | } |