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vga: fix text mode updating
[mirror_qemu.git] / hw / vga.c
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e89f66ec 1/*
4fa0f5d2 2 * QEMU VGA Emulator.
5fafdf24 3 *
e89f66ec 4 * Copyright (c) 2003 Fabrice Bellard
5fafdf24 5 *
e89f66ec
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b 24#include "hw.h"
5e55efc9 25#include "vga.h"
87ecb68b
PB		 26#include "console.h"
27#include "pc.h"
28#include "pci.h"
798b0c25 29#include "vga_int.h"
94470844 30#include "pixel_ops.h"
cb5a7aa8 31#include "qemu-timer.h"
c65adf9b 32#include "xen.h"
72750018 33#include "trace.h"
e89f66ec 34
e89f66ec 35//#define DEBUG_VGA
17b0018b 36//#define DEBUG_VGA_MEM
a41bc9af
FB		 37//#define DEBUG_VGA_REG
38
4fa0f5d2
FB		 39//#define DEBUG_BOCHS_VBE
40
9aa0ff0b
JK		 41/* 16 state changes per vertical frame @60 Hz */
42#define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
43
47c012e2
BS		 44/*
45 * Video Graphics Array (VGA)
46 *
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
49 *
50 * FreeVGA site:
51 * http://www.osdever.net/FreeVGA/home.htm
52 *
53 * Standard VGA features and Bochs VBE extensions are implemented.
54 */
55
e89f66ec 56/* force some bits to zero */
798b0c25 57const uint8_t sr_mask[8] = {
9e622b15
BS		 58 0x03,
59 0x3d,
60 0x0f,
61 0x3f,
62 0x0e,
63 0x00,
64 0x00,
65 0xff,
e89f66ec
FB		 66};
67
798b0c25 68const uint8_t gr_mask[16] = {
9e622b15
BS		 69 0x0f, /* 0x00 */
70 0x0f, /* 0x01 */
71 0x0f, /* 0x02 */
72 0x1f, /* 0x03 */
73 0x03, /* 0x04 */
74 0x7b, /* 0x05 */
75 0x0f, /* 0x06 */
76 0x0f, /* 0x07 */
77 0xff, /* 0x08 */
78 0x00, /* 0x09 */
79 0x00, /* 0x0a */
80 0x00, /* 0x0b */
81 0x00, /* 0x0c */
82 0x00, /* 0x0d */
83 0x00, /* 0x0e */
84 0x00, /* 0x0f */
e89f66ec
FB		 85};
86
87#define cbswap_32(__x) \
88((uint32_t)( \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
93
e2542fe2 94#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 95#define PAT(x) cbswap_32(x)
96#else
97#define PAT(x) (x)
98#endif
99
e2542fe2 100#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 101#define BIG 1
102#else
103#define BIG 0
104#endif
105
e2542fe2 106#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 107#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108#else
109#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110#endif
111
e89f66ec
FB		 112static const uint32_t mask16[16] = {
113 PAT(0x00000000),
114 PAT(0x000000ff),
115 PAT(0x0000ff00),
116 PAT(0x0000ffff),
117 PAT(0x00ff0000),
118 PAT(0x00ff00ff),
119 PAT(0x00ffff00),
120 PAT(0x00ffffff),
121 PAT(0xff000000),
122 PAT(0xff0000ff),
123 PAT(0xff00ff00),
124 PAT(0xff00ffff),
125 PAT(0xffff0000),
126 PAT(0xffff00ff),
127 PAT(0xffffff00),
128 PAT(0xffffffff),
129};
130
131#undef PAT
132
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 134#define PAT(x) (x)
135#else
136#define PAT(x) cbswap_32(x)
137#endif
138
139static const uint32_t dmask16[16] = {
140 PAT(0x00000000),
141 PAT(0x000000ff),
142 PAT(0x0000ff00),
143 PAT(0x0000ffff),
144 PAT(0x00ff0000),
145 PAT(0x00ff00ff),
146 PAT(0x00ffff00),
147 PAT(0x00ffffff),
148 PAT(0xff000000),
149 PAT(0xff0000ff),
150 PAT(0xff00ff00),
151 PAT(0xff00ffff),
152 PAT(0xffff0000),
153 PAT(0xffff00ff),
154 PAT(0xffffff00),
155 PAT(0xffffffff),
156};
157
158static const uint32_t dmask4[4] = {
159 PAT(0x00000000),
160 PAT(0x0000ffff),
161 PAT(0xffff0000),
162 PAT(0xffffffff),
163};
164
165static uint32_t expand4[256];
166static uint16_t expand2[256];
17b0018b 167static uint8_t expand4to8[16];
e89f66ec 168
d7098135
LC		 169static void vga_screen_dump(void *opaque, const char *filename, bool cswitch,
170 Error **errp);
95219897 171
80763888
JK		 172static void vga_update_memory_access(VGACommonState *s)
173{
174 MemoryRegion *region, *old_region = s->chain4_alias;
a8170e5e 175 hwaddr base, offset, size;
80763888
JK		 176
177 s->chain4_alias = NULL;
178
5e55efc9
BS		 179 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
180 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
80763888 181 offset = 0;
5e55efc9 182 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
80763888
JK		 183 case 0:
184 base = 0xa0000;
185 size = 0x20000;
186 break;
187 case 1:
188 base = 0xa0000;
189 size = 0x10000;
190 offset = s->bank_offset;
191 break;
192 case 2:
193 base = 0xb0000;
194 size = 0x8000;
195 break;
196 case 3:
f065aa0a 197 default:
80763888
JK		 198 base = 0xb8000;
199 size = 0x8000;
200 break;
201 }
71579cae 202 base += isa_mem_base;
80763888
JK		 203 region = g_malloc(sizeof(*region));
204 memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
205 memory_region_add_subregion_overlap(s->legacy_address_space, base,
206 region, 2);
207 s->chain4_alias = region;
208 }
209 if (old_region) {
210 memory_region_del_subregion(s->legacy_address_space, old_region);
211 memory_region_destroy(old_region);
212 g_free(old_region);
213 s->plane_updated = 0xf;
214 }
215}
216
cedd91d2 217static void vga_dumb_update_retrace_info(VGACommonState *s)
cb5a7aa8 218{
219 (void) s;
220}
221
cedd91d2 222static void vga_precise_update_retrace_info(VGACommonState *s)
cb5a7aa8 223{
224 int htotal_chars;
225 int hretr_start_char;
226 int hretr_skew_chars;
227 int hretr_end_char;
228
229 int vtotal_lines;
230 int vretr_start_line;
231 int vretr_end_line;
232
7f5b7d3e
BS		 233 int dots;
234#if 0
235 int div2, sldiv2;
236#endif
cb5a7aa8 237 int clocking_mode;
238 int clock_sel;
b0f74c87 239 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
cb5a7aa8 240 int64_t chars_per_sec;
241 struct vga_precise_retrace *r = &s->retrace_info.precise;
242
5e55efc9
BS		 243 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
244 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
245 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
246 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
cb5a7aa8 247
5e55efc9
BS		 248 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
249 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
250 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
251 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
252 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
253 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
254 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
cb5a7aa8 255
5e55efc9 256 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
cb5a7aa8 257 clock_sel = (s->msr >> 2) & 3;
f87fc09b 258 dots = (s->msr & 1) ? 8 : 9;
cb5a7aa8 259
b0f74c87 260 chars_per_sec = clk_hz[clock_sel] / dots;
cb5a7aa8 261
262 htotal_chars <<= clocking_mode;
263
264 r->total_chars = vtotal_lines * htotal_chars;
cb5a7aa8 265 if (r->freq) {
6ee093c9 266 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
cb5a7aa8 267 } else {
6ee093c9 268 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
cb5a7aa8 269 }
270
271 r->vstart = vretr_start_line;
272 r->vend = r->vstart + vretr_end_line + 1;
273
274 r->hstart = hretr_start_char + hretr_skew_chars;
275 r->hend = r->hstart + hretr_end_char + 1;
276 r->htotal = htotal_chars;
277
f87fc09b 278#if 0
5e55efc9
BS		 279 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
280 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
cb5a7aa8 281 printf (
f87fc09b 282 "hz=%f\n"
cb5a7aa8 283 "htotal = %d\n"
284 "hretr_start = %d\n"
285 "hretr_skew = %d\n"
286 "hretr_end = %d\n"
287 "vtotal = %d\n"
288 "vretr_start = %d\n"
289 "vretr_end = %d\n"
290 "div2 = %d sldiv2 = %d\n"
291 "clocking_mode = %d\n"
292 "clock_sel = %d %d\n"
293 "dots = %d\n"
0bfcd599 294 "ticks/char = %" PRId64 "\n"
cb5a7aa8 295 "\n",
6ee093c9 296 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
cb5a7aa8 297 htotal_chars,
298 hretr_start_char,
299 hretr_skew_chars,
300 hretr_end_char,
301 vtotal_lines,
302 vretr_start_line,
303 vretr_end_line,
304 div2, sldiv2,
305 clocking_mode,
306 clock_sel,
b0f74c87 307 clk_hz[clock_sel],
cb5a7aa8 308 dots,
309 r->ticks_per_char
310 );
311#endif
312}
313
cedd91d2 314static uint8_t vga_precise_retrace(VGACommonState *s)
cb5a7aa8 315{
316 struct vga_precise_retrace *r = &s->retrace_info.precise;
317 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
318
319 if (r->total_chars) {
320 int cur_line, cur_line_char, cur_char;
321 int64_t cur_tick;
322
74475455 323 cur_tick = qemu_get_clock_ns(vm_clock);
cb5a7aa8 324
325 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
326 cur_line = cur_char / r->htotal;
327
328 if (cur_line >= r->vstart && cur_line <= r->vend) {
329 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
f87fc09b 330 } else {
331 cur_line_char = cur_char % r->htotal;
332 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
333 val |= ST01_DISP_ENABLE;
334 }
cb5a7aa8 335 }
336
337 return val;
338 } else {
339 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
340 }
341}
342
cedd91d2 343static uint8_t vga_dumb_retrace(VGACommonState *s)
cb5a7aa8 344{
345 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
346}
347
25a18cbd
JQ		 348int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
349{
5e55efc9 350 if (s->msr & VGA_MIS_COLOR) {
25a18cbd
JQ		 351 /* Color */
352 return (addr >= 0x3b0 && addr <= 0x3bf);
353 } else {
354 /* Monochrome */
355 return (addr >= 0x3d0 && addr <= 0x3df);
356 }
357}
358
43bf782b 359uint32_t vga_ioport_read(void *opaque, uint32_t addr)
e89f66ec 360{
43bf782b 361 VGACommonState *s = opaque;
e89f66ec
FB		 362 int val, index;
363
bd8f2f5d
JK		 364 qemu_flush_coalesced_mmio_buffer();
365
25a18cbd 366 if (vga_ioport_invalid(s, addr)) {
e89f66ec
FB		 367 val = 0xff;
368 } else {
369 switch(addr) {
5e55efc9 370 case VGA_ATT_W:
e89f66ec
FB		 371 if (s->ar_flip_flop == 0) {
372 val = s->ar_index;
373 } else {
374 val = 0;
375 }
376 break;
5e55efc9 377 case VGA_ATT_R:
e89f66ec 378 index = s->ar_index & 0x1f;
5e55efc9 379 if (index < VGA_ATT_C) {
e89f66ec 380 val = s->ar[index];
5e55efc9 381 } else {
e89f66ec 382 val = 0;
5e55efc9 383 }
e89f66ec 384 break;
5e55efc9 385 case VGA_MIS_W:
e89f66ec
FB		 386 val = s->st00;
387 break;
5e55efc9 388 case VGA_SEQ_I:
e89f66ec
FB		 389 val = s->sr_index;
390 break;
5e55efc9 391 case VGA_SEQ_D:
e89f66ec 392 val = s->sr[s->sr_index];
a41bc9af
FB		 393#ifdef DEBUG_VGA_REG
394 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
395#endif
e89f66ec 396 break;
5e55efc9 397 case VGA_PEL_IR:
e89f66ec
FB		 398 val = s->dac_state;
399 break;
5e55efc9 400 case VGA_PEL_IW:
e9b43ea3
JQ		 401 val = s->dac_write_index;
402 break;
5e55efc9 403 case VGA_PEL_D:
e89f66ec
FB		 404 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
405 if (++s->dac_sub_index == 3) {
406 s->dac_sub_index = 0;
407 s->dac_read_index++;
408 }
409 break;
5e55efc9 410 case VGA_FTC_R:
e89f66ec
FB		 411 val = s->fcr;
412 break;
5e55efc9 413 case VGA_MIS_R:
e89f66ec
FB		 414 val = s->msr;
415 break;
5e55efc9 416 case VGA_GFX_I:
e89f66ec
FB		 417 val = s->gr_index;
418 break;
5e55efc9 419 case VGA_GFX_D:
e89f66ec 420 val = s->gr[s->gr_index];
a41bc9af
FB		 421#ifdef DEBUG_VGA_REG
422 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
423#endif
e89f66ec 424 break;
5e55efc9
BS		 425 case VGA_CRT_IM:
426 case VGA_CRT_IC:
e89f66ec
FB		 427 val = s->cr_index;
428 break;
5e55efc9
BS		 429 case VGA_CRT_DM:
430 case VGA_CRT_DC:
e89f66ec 431 val = s->cr[s->cr_index];
a41bc9af
FB		 432#ifdef DEBUG_VGA_REG
433 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
a41bc9af 434#endif
e89f66ec 435 break;
5e55efc9
BS		 436 case VGA_IS1_RM:
437 case VGA_IS1_RC:
e89f66ec 438 /* just toggle to fool polling */
cb5a7aa8 439 val = s->st01 = s->retrace(s);
e89f66ec
FB		 440 s->ar_flip_flop = 0;
441 break;
442 default:
443 val = 0x00;
444 break;
445 }
446 }
4fa0f5d2 447#if defined(DEBUG_VGA)
e89f66ec
FB		 448 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
449#endif
450 return val;
451}
452
43bf782b 453void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e89f66ec 454{
43bf782b 455 VGACommonState *s = opaque;
5467a722 456 int index;
e89f66ec 457
bd8f2f5d
JK		 458 qemu_flush_coalesced_mmio_buffer();
459
e89f66ec 460 /* check port range access depending on color/monochrome mode */
25a18cbd 461 if (vga_ioport_invalid(s, addr)) {
e89f66ec 462 return;
25a18cbd 463 }
e89f66ec
FB		 464#ifdef DEBUG_VGA
465 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
466#endif
467
468 switch(addr) {
5e55efc9 469 case VGA_ATT_W:
e89f66ec
FB		 470 if (s->ar_flip_flop == 0) {
471 val &= 0x3f;
472 s->ar_index = val;
473 } else {
474 index = s->ar_index & 0x1f;
475 switch(index) {
5e55efc9 476 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
e89f66ec
FB		 477 s->ar[index] = val & 0x3f;
478 break;
5e55efc9 479 case VGA_ATC_MODE:
e89f66ec
FB		 480 s->ar[index] = val & ~0x10;
481 break;
5e55efc9 482 case VGA_ATC_OVERSCAN:
e89f66ec
FB		 483 s->ar[index] = val;
484 break;
5e55efc9 485 case VGA_ATC_PLANE_ENABLE:
e89f66ec
FB		 486 s->ar[index] = val & ~0xc0;
487 break;
5e55efc9 488 case VGA_ATC_PEL:
e89f66ec
FB		 489 s->ar[index] = val & ~0xf0;
490 break;
5e55efc9 491 case VGA_ATC_COLOR_PAGE:
e89f66ec
FB		 492 s->ar[index] = val & ~0xf0;
493 break;
494 default:
495 break;
496 }
497 }
498 s->ar_flip_flop ^= 1;
499 break;
5e55efc9 500 case VGA_MIS_W:
e89f66ec 501 s->msr = val & ~0x10;
cb5a7aa8 502 s->update_retrace_info(s);
e89f66ec 503 break;
5e55efc9 504 case VGA_SEQ_I:
e89f66ec
FB		 505 s->sr_index = val & 7;
506 break;
5e55efc9 507 case VGA_SEQ_D:
a41bc9af
FB		 508#ifdef DEBUG_VGA_REG
509 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
510#endif
e89f66ec 511 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
5e55efc9
BS		 512 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
513 s->update_retrace_info(s);
514 }
80763888 515 vga_update_memory_access(s);
e89f66ec 516 break;
5e55efc9 517 case VGA_PEL_IR:
e89f66ec
FB		 518 s->dac_read_index = val;
519 s->dac_sub_index = 0;
520 s->dac_state = 3;
521 break;
5e55efc9 522 case VGA_PEL_IW:
e89f66ec
FB		 523 s->dac_write_index = val;
524 s->dac_sub_index = 0;
525 s->dac_state = 0;
526 break;
5e55efc9 527 case VGA_PEL_D:
e89f66ec
FB		 528 s->dac_cache[s->dac_sub_index] = val;
529 if (++s->dac_sub_index == 3) {
530 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
531 s->dac_sub_index = 0;
532 s->dac_write_index++;
533 }
534 break;
5e55efc9 535 case VGA_GFX_I:
e89f66ec
FB		 536 s->gr_index = val & 0x0f;
537 break;
5e55efc9 538 case VGA_GFX_D:
a41bc9af
FB		 539#ifdef DEBUG_VGA_REG
540 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
541#endif
e89f66ec 542 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
80763888 543 vga_update_memory_access(s);
e89f66ec 544 break;
5e55efc9
BS		 545 case VGA_CRT_IM:
546 case VGA_CRT_IC:
e89f66ec
FB		 547 s->cr_index = val;
548 break;
5e55efc9
BS		 549 case VGA_CRT_DM:
550 case VGA_CRT_DC:
a41bc9af
FB		 551#ifdef DEBUG_VGA_REG
552 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
553#endif
e89f66ec 554 /* handle CR0-7 protection */
df800210 555 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
556 s->cr_index <= VGA_CRTC_OVERFLOW) {
557 /* can always write bit 4 of CR7 */
558 if (s->cr_index == VGA_CRTC_OVERFLOW) {
559 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
560 (val & 0x10);
5e55efc9 561 }
df800210 562 return;
e89f66ec 563 }
a46007a0 564 s->cr[s->cr_index] = val;
cb5a7aa8 565
566 switch(s->cr_index) {
5e55efc9
BS		 567 case VGA_CRTC_H_TOTAL:
568 case VGA_CRTC_H_SYNC_START:
569 case VGA_CRTC_H_SYNC_END:
570 case VGA_CRTC_V_TOTAL:
571 case VGA_CRTC_OVERFLOW:
572 case VGA_CRTC_V_SYNC_END:
573 case VGA_CRTC_MODE:
cb5a7aa8 574 s->update_retrace_info(s);
575 break;
576 }
e89f66ec 577 break;
5e55efc9
BS		 578 case VGA_IS1_RM:
579 case VGA_IS1_RC:
e89f66ec
FB		 580 s->fcr = val & 0x10;
581 break;
582 }
583}
584
09a79b49 585static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
4fa0f5d2 586{
cedd91d2 587 VGACommonState *s = opaque;
4fa0f5d2 588 uint32_t val;
09a79b49
FB		 589 val = s->vbe_index;
590 return val;
591}
4fa0f5d2 592
803ff052 593uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
09a79b49 594{
cedd91d2 595 VGACommonState *s = opaque;
09a79b49
FB		 596 uint32_t val;
597
af92284b 598 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
8454df8b
FB		 599 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
600 switch(s->vbe_index) {
601 /* XXX: do not hardcode ? */
602 case VBE_DISPI_INDEX_XRES:
603 val = VBE_DISPI_MAX_XRES;
604 break;
605 case VBE_DISPI_INDEX_YRES:
606 val = VBE_DISPI_MAX_YRES;
607 break;
608 case VBE_DISPI_INDEX_BPP:
609 val = VBE_DISPI_MAX_BPP;
610 break;
611 default:
5fafdf24 612 val = s->vbe_regs[s->vbe_index];
8454df8b
FB		 613 break;
614 }
615 } else {
5fafdf24 616 val = s->vbe_regs[s->vbe_index];
8454df8b 617 }
af92284b
GH		 618 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
619 val = s->vram_size / (64 * 1024);
8454df8b 620 } else {
09a79b49 621 val = 0;
8454df8b 622 }
4fa0f5d2 623#ifdef DEBUG_BOCHS_VBE
09a79b49 624 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
4fa0f5d2 625#endif
4fa0f5d2
FB		 626 return val;
627}
628
803ff052 629void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
09a79b49 630{
cedd91d2 631 VGACommonState *s = opaque;
09a79b49
FB		 632 s->vbe_index = val;
633}
634
803ff052 635void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
4fa0f5d2 636{
cedd91d2 637 VGACommonState *s = opaque;
4fa0f5d2 638
09a79b49 639 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
4fa0f5d2
FB		 640#ifdef DEBUG_BOCHS_VBE
641 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
642#endif
643 switch(s->vbe_index) {
644 case VBE_DISPI_INDEX_ID:
cae61cef
FB		 645 if (val == VBE_DISPI_ID0 ||
646 val == VBE_DISPI_ID1 ||
37dd208d
FB		 647 val == VBE_DISPI_ID2 ||
648 val == VBE_DISPI_ID3 ||
649 val == VBE_DISPI_ID4) {
cae61cef
FB		 650 s->vbe_regs[s->vbe_index] = val;
651 }
4fa0f5d2
FB		 652 break;
653 case VBE_DISPI_INDEX_XRES:
cae61cef
FB		 654 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
655 s->vbe_regs[s->vbe_index] = val;
656 }
4fa0f5d2
FB		 657 break;
658 case VBE_DISPI_INDEX_YRES:
cae61cef
FB		 659 if (val <= VBE_DISPI_MAX_YRES) {
660 s->vbe_regs[s->vbe_index] = val;
661 }
4fa0f5d2
FB		 662 break;
663 case VBE_DISPI_INDEX_BPP:
664 if (val == 0)
665 val = 8;
5fafdf24 666 if (val == 4 || val == 8 || val == 15 ||
cae61cef
FB		 667 val == 16 || val == 24 || val == 32) {
668 s->vbe_regs[s->vbe_index] = val;
669 }
4fa0f5d2
FB		 670 break;
671 case VBE_DISPI_INDEX_BANK:
42fc925e
FB		 672 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
673 val &= (s->vbe_bank_mask >> 2);
674 } else {
675 val &= s->vbe_bank_mask;
676 }
cae61cef 677 s->vbe_regs[s->vbe_index] = val;
26aa7d72 678 s->bank_offset = (val << 16);
80763888 679 vga_update_memory_access(s);
4fa0f5d2
FB		 680 break;
681 case VBE_DISPI_INDEX_ENABLE:
8454df8b
FB		 682 if ((val & VBE_DISPI_ENABLED) &&
683 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
4fa0f5d2
FB		 684 int h, shift_control;
685
5fafdf24 686 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
4fa0f5d2 687 s->vbe_regs[VBE_DISPI_INDEX_XRES];
5fafdf24 688 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
4fa0f5d2
FB		 689 s->vbe_regs[VBE_DISPI_INDEX_YRES];
690 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
691 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
3b46e624 692
4fa0f5d2
FB		 693 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
694 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
695 else
5fafdf24 696 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
4fa0f5d2
FB		 697 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr = 0;
8454df8b 699
4fa0f5d2
FB		 700 /* clear the screen (should be done in BIOS) */
701 if (!(val & VBE_DISPI_NOCLEARMEM)) {
5fafdf24 702 memset(s->vram_ptr, 0,
4fa0f5d2
FB		 703 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
704 }
3b46e624 705
cae61cef
FB		 706 /* we initialize the VGA graphic mode (should be done
707 in BIOS) */
5e55efc9
BS		 708 /* graphic mode + memory map 1 */
709 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
710 VGA_GR06_GRAPHICS_MODE;
711 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
712 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
4fa0f5d2 713 /* width */
5e55efc9
BS		 714 s->cr[VGA_CRTC_H_DISP] =
715 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
8454df8b 716 /* height (only meaningful if < 1024) */
4fa0f5d2 717 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
5e55efc9
BS		 718 s->cr[VGA_CRTC_V_DISP_END] = h;
719 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
4fa0f5d2
FB		 720 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
721 /* line compare to 1023 */
5e55efc9
BS		 722 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
723 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
724 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
3b46e624 725
4fa0f5d2
FB		 726 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
727 shift_control = 0;
5e55efc9 728 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
4fa0f5d2
FB		 729 } else {
730 shift_control = 2;
5e55efc9
BS		 731 /* set chain 4 mode */
732 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
733 /* activate all planes */
734 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
4fa0f5d2 735 }
5e55efc9
BS		 736 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
737 (shift_control << 5);
738 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
cae61cef
FB		 739 } else {
740 /* XXX: the bios should do that */
26aa7d72 741 s->bank_offset = 0;
cae61cef 742 }
37dd208d 743 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
141253b2 744 s->vbe_regs[s->vbe_index] = val;
80763888 745 vga_update_memory_access(s);
cae61cef
FB		 746 break;
747 case VBE_DISPI_INDEX_VIRT_WIDTH:
748 {
749 int w, h, line_offset;
750
751 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
752 return;
753 w = val;
754 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
755 line_offset = w >> 1;
756 else
757 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
758 h = s->vram_size / line_offset;
759 /* XXX: support weird bochs semantics ? */
760 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
761 return;
762 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
763 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
764 s->vbe_line_offset = line_offset;
765 }
766 break;
767 case VBE_DISPI_INDEX_X_OFFSET:
768 case VBE_DISPI_INDEX_Y_OFFSET:
769 {
770 int x;
771 s->vbe_regs[s->vbe_index] = val;
772 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
773 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
774 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
775 s->vbe_start_addr += x >> 1;
776 else
777 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
778 s->vbe_start_addr >>= 2;
4fa0f5d2
FB		 779 }
780 break;
781 default:
782 break;
783 }
4fa0f5d2
FB		 784 }
785}
4fa0f5d2 786
e89f66ec 787/* called for accesses between 0xa0000 and 0xc0000 */
a8170e5e 788uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
e89f66ec 789{
e89f66ec
FB		 790 int memory_map_mode, plane;
791 uint32_t ret;
3b46e624 792
e89f66ec 793 /* convert to VGA memory offset */
5e55efc9 794 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 795 addr &= 0x1ffff;
e89f66ec
FB		 796 switch(memory_map_mode) {
797 case 0:
e89f66ec
FB		 798 break;
799 case 1:
26aa7d72 800 if (addr >= 0x10000)
e89f66ec 801 return 0xff;
cae61cef 802 addr += s->bank_offset;
e89f66ec
FB		 803 break;
804 case 2:
26aa7d72 805 addr -= 0x10000;
e89f66ec
FB		 806 if (addr >= 0x8000)
807 return 0xff;
808 break;
809 default:
810 case 3:
26aa7d72 811 addr -= 0x18000;
c92b2e84
FB		 812 if (addr >= 0x8000)
813 return 0xff;
e89f66ec
FB		 814 break;
815 }
3b46e624 816
5e55efc9 817 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 818 /* chain 4 mode : simplest access */
819 ret = s->vram_ptr[addr];
5e55efc9 820 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 821 /* odd/even mode (aka text mode mapping) */
5e55efc9 822 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
e89f66ec
FB		 823 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
824 } else {
825 /* standard VGA latched access */
826 s->latch = ((uint32_t *)s->vram_ptr)[addr];
827
5e55efc9 828 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
e89f66ec 829 /* read mode 0 */
5e55efc9 830 plane = s->gr[VGA_GFX_PLANE_READ];
b8ed223b 831 ret = GET_PLANE(s->latch, plane);
e89f66ec
FB		 832 } else {
833 /* read mode 1 */
5e55efc9
BS		 834 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
835 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
e89f66ec
FB		 836 ret |= ret >> 16;
837 ret |= ret >> 8;
838 ret = (~ret) & 0xff;
839 }
840 }
841 return ret;
842}
843
e89f66ec 844/* called for accesses between 0xa0000 and 0xc0000 */
a8170e5e 845void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
e89f66ec 846{
546fa6ab 847 int memory_map_mode, plane, write_mode, b, func_select, mask;
e89f66ec
FB		 848 uint32_t write_mask, bit_mask, set_mask;
849
17b0018b 850#ifdef DEBUG_VGA_MEM
0bf9e31a 851 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
e89f66ec
FB		 852#endif
853 /* convert to VGA memory offset */
5e55efc9 854 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 855 addr &= 0x1ffff;
e89f66ec
FB		 856 switch(memory_map_mode) {
857 case 0:
e89f66ec
FB		 858 break;
859 case 1:
26aa7d72 860 if (addr >= 0x10000)
e89f66ec 861 return;
cae61cef 862 addr += s->bank_offset;
e89f66ec
FB		 863 break;
864 case 2:
26aa7d72 865 addr -= 0x10000;
e89f66ec
FB		 866 if (addr >= 0x8000)
867 return;
868 break;
869 default:
870 case 3:
26aa7d72 871 addr -= 0x18000;
c92b2e84
FB		 872 if (addr >= 0x8000)
873 return;
e89f66ec
FB		 874 break;
875 }
3b46e624 876
5e55efc9 877 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 878 /* chain 4 mode : simplest access */
879 plane = addr & 3;
546fa6ab 880 mask = (1 << plane);
5e55efc9 881 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec 882 s->vram_ptr[addr] = val;
17b0018b 883#ifdef DEBUG_VGA_MEM
0bf9e31a 884 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 885#endif
546fa6ab 886 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 887 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec 888 }
5e55efc9 889 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 890 /* odd/even mode (aka text mode mapping) */
5e55efc9 891 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
546fa6ab 892 mask = (1 << plane);
5e55efc9 893 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec
FB		 894 addr = ((addr & ~1) << 1) | plane;
895 s->vram_ptr[addr] = val;
17b0018b 896#ifdef DEBUG_VGA_MEM
0bf9e31a 897 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 898#endif
546fa6ab 899 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 900 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec
FB		 901 }
902 } else {
903 /* standard VGA latched access */
5e55efc9 904 write_mode = s->gr[VGA_GFX_MODE] & 3;
e89f66ec
FB		 905 switch(write_mode) {
906 default:
907 case 0:
908 /* rotate */
5e55efc9 909 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
e89f66ec
FB		 910 val = ((val >> b) | (val << (8 - b))) & 0xff;
911 val |= val << 8;
912 val |= val << 16;
913
914 /* apply set/reset mask */
5e55efc9
BS		 915 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
916 val = (val & ~set_mask) |
917 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
918 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 919 break;
920 case 1:
921 val = s->latch;
922 goto do_write;
923 case 2:
924 val = mask16[val & 0x0f];
5e55efc9 925 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 926 break;
927 case 3:
928 /* rotate */
5e55efc9 929 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
a41bc9af 930 val = (val >> b) | (val << (8 - b));
e89f66ec 931
5e55efc9
BS		 932 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
933 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
e89f66ec
FB		 934 break;
935 }
936
937 /* apply logical operation */
5e55efc9 938 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
e89f66ec
FB		 939 switch(func_select) {
940 case 0:
941 default:
942 /* nothing to do */
943 break;
944 case 1:
945 /* and */
946 val &= s->latch;
947 break;
948 case 2:
949 /* or */
950 val |= s->latch;
951 break;
952 case 3:
953 /* xor */
954 val ^= s->latch;
955 break;
956 }
957
958 /* apply bit mask */
959 bit_mask |= bit_mask << 8;
960 bit_mask |= bit_mask << 16;
961 val = (val & bit_mask) | (s->latch & ~bit_mask);
962
963 do_write:
964 /* mask data according to sr[2] */
5e55efc9 965 mask = s->sr[VGA_SEQ_PLANE_WRITE];
546fa6ab
FB		 966 s->plane_updated |= mask; /* only used to detect font change */
967 write_mask = mask16[mask];
5fafdf24
TS		 968 ((uint32_t *)s->vram_ptr)[addr] =
969 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
e89f66ec 970 (val & write_mask);
17b0018b 971#ifdef DEBUG_VGA_MEM
0bf9e31a
BS		 972 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
973 addr * 4, write_mask, val);
e89f66ec 974#endif
fd4aa979 975 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
e89f66ec
FB		 976 }
977}
978
e89f66ec
FB		 979typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
980 const uint8_t *font_ptr, int h,
981 uint32_t fgcol, uint32_t bgcol);
982typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
5fafdf24 983 const uint8_t *font_ptr, int h,
e89f66ec 984 uint32_t fgcol, uint32_t bgcol, int dup9);
cedd91d2 985typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
e89f66ec
FB		 986 const uint8_t *s, int width);
987
e89f66ec
FB		 988#define DEPTH 8
989#include "vga_template.h"
990
991#define DEPTH 15
992#include "vga_template.h"
993
a2502b58
BS		 994#define BGR_FORMAT
995#define DEPTH 15
996#include "vga_template.h"
997
998#define DEPTH 16
999#include "vga_template.h"
1000
1001#define BGR_FORMAT
e89f66ec
FB		 1002#define DEPTH 16
1003#include "vga_template.h"
1004
1005#define DEPTH 32
1006#include "vga_template.h"
1007
d3079cd2
FB		 1008#define BGR_FORMAT
1009#define DEPTH 32
1010#include "vga_template.h"
1011
17b0018b
FB		 1012static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1013{
1014 unsigned int col;
1015 col = rgb_to_pixel8(r, g, b);
1016 col |= col << 8;
1017 col |= col << 16;
1018 return col;
1019}
1020
1021static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1022{
1023 unsigned int col;
1024 col = rgb_to_pixel15(r, g, b);
1025 col |= col << 16;
1026 return col;
1027}
1028
b29169d2
BS		 1029static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1030 unsigned int b)
1031{
1032 unsigned int col;
1033 col = rgb_to_pixel15bgr(r, g, b);
1034 col |= col << 16;
1035 return col;
1036}
1037
17b0018b
FB		 1038static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1039{
1040 unsigned int col;
1041 col = rgb_to_pixel16(r, g, b);
1042 col |= col << 16;
1043 return col;
1044}
1045
b29169d2
BS		 1046static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1047 unsigned int b)
1048{
1049 unsigned int col;
1050 col = rgb_to_pixel16bgr(r, g, b);
1051 col |= col << 16;
1052 return col;
1053}
1054
17b0018b
FB		 1055static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1056{
1057 unsigned int col;
1058 col = rgb_to_pixel32(r, g, b);
1059 return col;
1060}
1061
d3079cd2
FB		 1062static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1063{
1064 unsigned int col;
1065 col = rgb_to_pixel32bgr(r, g, b);
1066 return col;
1067}
1068
e89f66ec 1069/* return true if the palette was modified */
cedd91d2 1070static int update_palette16(VGACommonState *s)
e89f66ec 1071{
17b0018b 1072 int full_update, i;
e89f66ec 1073 uint32_t v, col, *palette;
e89f66ec
FB		 1074
1075 full_update = 0;
1076 palette = s->last_palette;
1077 for(i = 0; i < 16; i++) {
1078 v = s->ar[i];
5e55efc9
BS		 1079 if (s->ar[VGA_ATC_MODE] & 0x80) {
1080 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1081 } else {
1082 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1083 }
e89f66ec 1084 v = v * 3;
5fafdf24
TS		 1085 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1086 c6_to_8(s->palette[v + 1]),
17b0018b
FB		 1087 c6_to_8(s->palette[v + 2]));
1088 if (col != palette[i]) {
1089 full_update = 1;
1090 palette[i] = col;
e89f66ec 1091 }
17b0018b
FB		 1092 }
1093 return full_update;
1094}
1095
1096/* return true if the palette was modified */
cedd91d2 1097static int update_palette256(VGACommonState *s)
17b0018b
FB		 1098{
1099 int full_update, i;
1100 uint32_t v, col, *palette;
1101
1102 full_update = 0;
1103 palette = s->last_palette;
1104 v = 0;
1105 for(i = 0; i < 256; i++) {
37dd208d 1106 if (s->dac_8bit) {
5fafdf24
TS		 1107 col = s->rgb_to_pixel(s->palette[v],
1108 s->palette[v + 1],
37dd208d
FB		 1109 s->palette[v + 2]);
1110 } else {
5fafdf24
TS		 1111 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1112 c6_to_8(s->palette[v + 1]),
37dd208d
FB		 1113 c6_to_8(s->palette[v + 2]));
1114 }
e89f66ec
FB		 1115 if (col != palette[i]) {
1116 full_update = 1;
1117 palette[i] = col;
1118 }
17b0018b 1119 v += 3;
e89f66ec
FB		 1120 }
1121 return full_update;
1122}
1123
cedd91d2 1124static void vga_get_offsets(VGACommonState *s,
5fafdf24 1125 uint32_t *pline_offset,
83acc96b
FB		 1126 uint32_t *pstart_addr,
1127 uint32_t *pline_compare)
e89f66ec 1128{
83acc96b 1129 uint32_t start_addr, line_offset, line_compare;
a96d8bea 1130
4fa0f5d2
FB		 1131 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1132 line_offset = s->vbe_line_offset;
1133 start_addr = s->vbe_start_addr;
83acc96b 1134 line_compare = 65535;
a96d8bea 1135 } else {
4fa0f5d2 1136 /* compute line_offset in bytes */
5e55efc9 1137 line_offset = s->cr[VGA_CRTC_OFFSET];
4fa0f5d2 1138 line_offset <<= 3;
08e48902 1139
4fa0f5d2 1140 /* starting address */
5e55efc9
BS		 1141 start_addr = s->cr[VGA_CRTC_START_LO] |
1142 (s->cr[VGA_CRTC_START_HI] << 8);
83acc96b
FB		 1143
1144 /* line compare */
5e55efc9
BS		 1145 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1146 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1147 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
4fa0f5d2 1148 }
798b0c25
FB		 1149 *pline_offset = line_offset;
1150 *pstart_addr = start_addr;
83acc96b 1151 *pline_compare = line_compare;
798b0c25
FB		 1152}
1153
1154/* update start_addr and line_offset. Return TRUE if modified */
cedd91d2 1155static int update_basic_params(VGACommonState *s)
798b0c25
FB		 1156{
1157 int full_update;
1158 uint32_t start_addr, line_offset, line_compare;
3b46e624 1159
798b0c25
FB		 1160 full_update = 0;
1161
83acc96b 1162 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
e89f66ec
FB		 1163
1164 if (line_offset != s->line_offset ||
1165 start_addr != s->start_addr ||
1166 line_compare != s->line_compare) {
1167 s->line_offset = line_offset;
1168 s->start_addr = start_addr;
1169 s->line_compare = line_compare;
1170 full_update = 1;
1171 }
1172 return full_update;
1173}
1174
b29169d2 1175#define NB_DEPTHS 7
d3079cd2
FB		 1176
1177static inline int get_depth_index(DisplayState *s)
e89f66ec 1178{
0e1f5a0c 1179 switch(ds_get_bits_per_pixel(s)) {
e89f66ec
FB		 1180 default:
1181 case 8:
1182 return 0;
1183 case 15:
8927bcfd 1184 return 1;
e89f66ec 1185 case 16:
8927bcfd 1186 return 2;
e89f66ec 1187 case 32:
7b5d76da
AL		 1188 if (is_surface_bgr(s->surface))
1189 return 4;
1190 else
1191 return 3;
e89f66ec
FB		 1192 }
1193}
1194
68f04a3c 1195static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
e89f66ec
FB		 1196 vga_draw_glyph8_8,
1197 vga_draw_glyph8_16,
1198 vga_draw_glyph8_16,
1199 vga_draw_glyph8_32,
d3079cd2 1200 vga_draw_glyph8_32,
b29169d2
BS		 1201 vga_draw_glyph8_16,
1202 vga_draw_glyph8_16,
e89f66ec
FB		 1203};
1204
68f04a3c 1205static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
17b0018b
FB		 1206 vga_draw_glyph16_8,
1207 vga_draw_glyph16_16,
1208 vga_draw_glyph16_16,
1209 vga_draw_glyph16_32,
d3079cd2 1210 vga_draw_glyph16_32,
b29169d2
BS		 1211 vga_draw_glyph16_16,
1212 vga_draw_glyph16_16,
17b0018b
FB		 1213};
1214
68f04a3c 1215static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
e89f66ec
FB		 1216 vga_draw_glyph9_8,
1217 vga_draw_glyph9_16,
1218 vga_draw_glyph9_16,
1219 vga_draw_glyph9_32,
d3079cd2 1220 vga_draw_glyph9_32,
b29169d2
BS		 1221 vga_draw_glyph9_16,
1222 vga_draw_glyph9_16,
e89f66ec 1223};
3b46e624 1224
e89f66ec
FB		 1225static const uint8_t cursor_glyph[32 * 4] = {
1226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1238 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1239 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1240 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1241 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
3b46e624 1242};
e89f66ec 1243
cedd91d2 1244static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
4c5e8c5c
BS		 1245 int *pcwidth, int *pcheight)
1246{
1247 int width, cwidth, height, cheight;
1248
1249 /* total width & height */
5e55efc9 1250 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
4c5e8c5c 1251 cwidth = 8;
5e55efc9 1252 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
4c5e8c5c 1253 cwidth = 9;
5e55efc9
BS		 1254 }
1255 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
4c5e8c5c 1256 cwidth = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 1257 }
1258 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1259 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
4c5e8c5c
BS		 1260 /* ugly hack for CGA 160x100x16 - explain me the logic */
1261 height = 100;
1262 } else {
5e55efc9
BS		 1263 height = s->cr[VGA_CRTC_V_DISP_END] |
1264 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1265 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
4c5e8c5c
BS		 1266 height = (height + 1) / cheight;
1267 }
1268
1269 *pwidth = width;
1270 *pheight = height;
1271 *pcwidth = cwidth;
1272 *pcheight = cheight;
1273}
1274
7d957bd8
AL		 1275typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1276
68f04a3c 1277static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
bdb19571
AL		 1278 rgb_to_pixel8_dup,
1279 rgb_to_pixel15_dup,
1280 rgb_to_pixel16_dup,
1281 rgb_to_pixel32_dup,
1282 rgb_to_pixel32bgr_dup,
1283 rgb_to_pixel15bgr_dup,
1284 rgb_to_pixel16bgr_dup,
1285};
7d957bd8 1286
5fafdf24
TS		 1287/*
1288 * Text mode update
e89f66ec
FB		 1289 * Missing:
1290 * - double scan
5fafdf24 1291 * - double width
e89f66ec
FB		 1292 * - underline
1293 * - flashing
1294 */
cedd91d2 1295static void vga_draw_text(VGACommonState *s, int full_update)
e89f66ec
FB		 1296{
1297 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
cae334cd 1298 int cx_min, cx_max, linesize, x_incr, line, line1;
e89f66ec 1299 uint32_t offset, fgcol, bgcol, v, cursor_offset;
d1984194 1300 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
e89f66ec
FB		 1301 const uint8_t *font_ptr, *font_base[2];
1302 int dup9, line_offset, depth_index;
1303 uint32_t *palette;
1304 uint32_t *ch_attr_ptr;
1305 vga_draw_glyph8_func *vga_draw_glyph8;
1306 vga_draw_glyph9_func *vga_draw_glyph9;
9aa0ff0b 1307 int64_t now = qemu_get_clock_ms(vm_clock);
e89f66ec 1308
e89f66ec 1309 /* compute font data address (in plane 2) */
5e55efc9 1310 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1078f663 1311 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1312 if (offset != s->font_offsets[0]) {
1313 s->font_offsets[0] = offset;
1314 full_update = 1;
1315 }
1316 font_base[0] = s->vram_ptr + offset;
1317
1078f663 1318 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1319 font_base[1] = s->vram_ptr + offset;
1320 if (offset != s->font_offsets[1]) {
1321 s->font_offsets[1] = offset;
1322 full_update = 1;
1323 }
80763888 1324 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
546fa6ab
FB		 1325 /* if the plane 2 was modified since the last display, it
1326 indicates the font may have been modified */
1327 s->plane_updated = 0;
1328 full_update = 1;
1329 }
799e709b 1330 full_update |= update_basic_params(s);
e89f66ec
FB		 1331
1332 line_offset = s->line_offset;
e89f66ec 1333
4c5e8c5c 1334 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1b296044
SW		 1335 if ((height * width) <= 1) {
1336 /* better than nothing: exit if transient size is too small */
1337 return;
1338 }
3294b949
FB		 1339 if ((height * width) > CH_ATTR_SIZE) {
1340 /* better than nothing: exit if transient size is too big */
1341 return;
1342 }
1343
799e709b
AL		 1344 if (width != s->last_width || height != s->last_height ||
1345 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1346 s->last_scr_width = width * cw;
1347 s->last_scr_height = height * cheight;
1348 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
9678aedd 1349 dpy_text_resize(s->ds, width, height);
799e709b
AL		 1350 s->last_depth = 0;
1351 s->last_width = width;
1352 s->last_height = height;
1353 s->last_ch = cheight;
1354 s->last_cw = cw;
1355 full_update = 1;
1356 }
7d957bd8
AL		 1357 s->rgb_to_pixel =
1358 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1359 full_update |= update_palette16(s);
1360 palette = s->last_palette;
1361 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1362
9678aedd
GH		 1363 if (full_update) {
1364 s->full_update_text = 1;
1365 }
1366 if (s->full_update_gfx) {
1367 s->full_update_gfx = 0;
1368 full_update |= 1;
1369 }
1370
5e55efc9
BS		 1371 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1372 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
e89f66ec 1373 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 1374 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1375 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
e89f66ec
FB		 1376 /* if the cursor position changed, we update the old and new
1377 chars */
1378 if (s->cursor_offset < CH_ATTR_SIZE)
1379 s->last_ch_attr[s->cursor_offset] = -1;
1380 if (cursor_offset < CH_ATTR_SIZE)
1381 s->last_ch_attr[cursor_offset] = -1;
1382 s->cursor_offset = cursor_offset;
5e55efc9
BS		 1383 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1384 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
e89f66ec 1385 }
39cf7803 1386 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
9aa0ff0b
JK		 1387 if (now >= s->cursor_blink_time) {
1388 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1389 s->cursor_visible_phase = !s->cursor_visible_phase;
1390 }
3b46e624 1391
d3079cd2 1392 depth_index = get_depth_index(s->ds);
17b0018b
FB		 1393 if (cw == 16)
1394 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1395 else
1396 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
e89f66ec 1397 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
3b46e624 1398
0e1f5a0c
AL		 1399 dest = ds_get_data(s->ds);
1400 linesize = ds_get_linesize(s->ds);
e89f66ec 1401 ch_attr_ptr = s->last_ch_attr;
d1984194 1402 line = 0;
1403 offset = s->start_addr * 4;
e89f66ec
FB		 1404 for(cy = 0; cy < height; cy++) {
1405 d1 = dest;
d1984194 1406 src = s->vram_ptr + offset;
e89f66ec
FB		 1407 cx_min = width;
1408 cx_max = -1;
1409 for(cx = 0; cx < width; cx++) {
1410 ch_attr = *(uint16_t *)src;
9aa0ff0b 1411 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
e89f66ec
FB		 1412 if (cx < cx_min)
1413 cx_min = cx;
1414 if (cx > cx_max)
1415 cx_max = cx;
1416 *ch_attr_ptr = ch_attr;
e2542fe2 1417#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 1418 ch = ch_attr >> 8;
1419 cattr = ch_attr & 0xff;
1420#else
1421 ch = ch_attr & 0xff;
1422 cattr = ch_attr >> 8;
1423#endif
1424 font_ptr = font_base[(cattr >> 3) & 1];
1425 font_ptr += 32 * 4 * ch;
1426 bgcol = palette[cattr >> 4];
1427 fgcol = palette[cattr & 0x0f];
17b0018b 1428 if (cw != 9) {
5fafdf24 1429 vga_draw_glyph8(d1, linesize,
e89f66ec
FB		 1430 font_ptr, cheight, fgcol, bgcol);
1431 } else {
1432 dup9 = 0;
5e55efc9
BS		 1433 if (ch >= 0xb0 && ch <= 0xdf &&
1434 (s->ar[VGA_ATC_MODE] & 0x04)) {
e89f66ec 1435 dup9 = 1;
5e55efc9 1436 }
5fafdf24 1437 vga_draw_glyph9(d1, linesize,
e89f66ec
FB		 1438 font_ptr, cheight, fgcol, bgcol, dup9);
1439 }
1440 if (src == cursor_ptr &&
9aa0ff0b
JK		 1441 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1442 s->cursor_visible_phase) {
e89f66ec
FB		 1443 int line_start, line_last, h;
1444 /* draw the cursor */
5e55efc9
BS		 1445 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1446 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
e89f66ec
FB		 1447 /* XXX: check that */
1448 if (line_last > cheight - 1)
1449 line_last = cheight - 1;
1450 if (line_last >= line_start && line_start < cheight) {
1451 h = line_last - line_start + 1;
1452 d = d1 + linesize * line_start;
17b0018b 1453 if (cw != 9) {
5fafdf24 1454 vga_draw_glyph8(d, linesize,
e89f66ec
FB		 1455 cursor_glyph, h, fgcol, bgcol);
1456 } else {
5fafdf24 1457 vga_draw_glyph9(d, linesize,
e89f66ec
FB		 1458 cursor_glyph, h, fgcol, bgcol, 1);
1459 }
1460 }
1461 }
1462 }
1463 d1 += x_incr;
1464 src += 4;
1465 ch_attr_ptr++;
1466 }
1467 if (cx_max != -1) {
a93a4a22
GH		 1468 dpy_gfx_update(s->ds, cx_min * cw, cy * cheight,
1469 (cx_max - cx_min + 1) * cw, cheight);
e89f66ec
FB		 1470 }
1471 dest += linesize * cheight;
cae334cd 1472 line1 = line + cheight;
1473 offset += line_offset;
1474 if (line < s->line_compare && line1 >= s->line_compare) {
d1984194 1475 offset = 0;
1476 }
cae334cd 1477 line = line1;
e89f66ec
FB		 1478 }
1479}
1480
17b0018b
FB		 1481enum {
1482 VGA_DRAW_LINE2,
1483 VGA_DRAW_LINE2D2,
1484 VGA_DRAW_LINE4,
1485 VGA_DRAW_LINE4D2,
1486 VGA_DRAW_LINE8D2,
1487 VGA_DRAW_LINE8,
1488 VGA_DRAW_LINE15,
1489 VGA_DRAW_LINE16,
4fa0f5d2 1490 VGA_DRAW_LINE24,
17b0018b
FB		 1491 VGA_DRAW_LINE32,
1492 VGA_DRAW_LINE_NB,
1493};
1494
68f04a3c 1495static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
e89f66ec
FB		 1496 vga_draw_line2_8,
1497 vga_draw_line2_16,
1498 vga_draw_line2_16,
1499 vga_draw_line2_32,
d3079cd2 1500 vga_draw_line2_32,
b29169d2
BS		 1501 vga_draw_line2_16,
1502 vga_draw_line2_16,
e89f66ec 1503
17b0018b
FB		 1504 vga_draw_line2d2_8,
1505 vga_draw_line2d2_16,
1506 vga_draw_line2d2_16,
1507 vga_draw_line2d2_32,
d3079cd2 1508 vga_draw_line2d2_32,
b29169d2
BS		 1509 vga_draw_line2d2_16,
1510 vga_draw_line2d2_16,
17b0018b 1511
e89f66ec
FB		 1512 vga_draw_line4_8,
1513 vga_draw_line4_16,
1514 vga_draw_line4_16,
1515 vga_draw_line4_32,
d3079cd2 1516 vga_draw_line4_32,
b29169d2
BS		 1517 vga_draw_line4_16,
1518 vga_draw_line4_16,
e89f66ec 1519
17b0018b
FB		 1520 vga_draw_line4d2_8,
1521 vga_draw_line4d2_16,
1522 vga_draw_line4d2_16,
1523 vga_draw_line4d2_32,
d3079cd2 1524 vga_draw_line4d2_32,
b29169d2
BS		 1525 vga_draw_line4d2_16,
1526 vga_draw_line4d2_16,
17b0018b
FB		 1527
1528 vga_draw_line8d2_8,
1529 vga_draw_line8d2_16,
1530 vga_draw_line8d2_16,
1531 vga_draw_line8d2_32,
d3079cd2 1532 vga_draw_line8d2_32,
b29169d2
BS		 1533 vga_draw_line8d2_16,
1534 vga_draw_line8d2_16,
17b0018b 1535
e89f66ec
FB		 1536 vga_draw_line8_8,
1537 vga_draw_line8_16,
1538 vga_draw_line8_16,
1539 vga_draw_line8_32,
d3079cd2 1540 vga_draw_line8_32,
b29169d2
BS		 1541 vga_draw_line8_16,
1542 vga_draw_line8_16,
e89f66ec
FB		 1543
1544 vga_draw_line15_8,
1545 vga_draw_line15_15,
1546 vga_draw_line15_16,
1547 vga_draw_line15_32,
d3079cd2 1548 vga_draw_line15_32bgr,
b29169d2
BS		 1549 vga_draw_line15_15bgr,
1550 vga_draw_line15_16bgr,
e89f66ec
FB		 1551
1552 vga_draw_line16_8,
1553 vga_draw_line16_15,
1554 vga_draw_line16_16,
1555 vga_draw_line16_32,
d3079cd2 1556 vga_draw_line16_32bgr,
b29169d2
BS		 1557 vga_draw_line16_15bgr,
1558 vga_draw_line16_16bgr,
e89f66ec 1559
4fa0f5d2
FB		 1560 vga_draw_line24_8,
1561 vga_draw_line24_15,
1562 vga_draw_line24_16,
1563 vga_draw_line24_32,
d3079cd2 1564 vga_draw_line24_32bgr,
b29169d2
BS		 1565 vga_draw_line24_15bgr,
1566 vga_draw_line24_16bgr,
4fa0f5d2 1567
e89f66ec
FB		 1568 vga_draw_line32_8,
1569 vga_draw_line32_15,
1570 vga_draw_line32_16,
1571 vga_draw_line32_32,
d3079cd2 1572 vga_draw_line32_32bgr,
b29169d2
BS		 1573 vga_draw_line32_15bgr,
1574 vga_draw_line32_16bgr,
d3079cd2
FB		 1575};
1576
cedd91d2 1577static int vga_get_bpp(VGACommonState *s)
798b0c25
FB		 1578{
1579 int ret;
a96d8bea 1580
798b0c25
FB		 1581 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1582 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
a96d8bea 1583 } else {
798b0c25
FB		 1584 ret = 0;
1585 }
1586 return ret;
1587}
1588
cedd91d2 1589static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
a130a41e
FB		 1590{
1591 int width, height;
3b46e624 1592
8454df8b
FB		 1593 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1594 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1595 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
a96d8bea 1596 } else {
5e55efc9
BS		 1597 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1598 height = s->cr[VGA_CRTC_V_DISP_END] |
1599 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1600 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
8454df8b
FB		 1601 height = (height + 1);
1602 }
a130a41e
FB		 1603 *pwidth = width;
1604 *pheight = height;
1605}
1606
cedd91d2 1607void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
a8aa669b
FB		 1608{
1609 int y;
1610 if (y1 >= VGA_MAX_HEIGHT)
1611 return;
1612 if (y2 >= VGA_MAX_HEIGHT)
1613 y2 = VGA_MAX_HEIGHT;
1614 for(y = y1; y < y2; y++) {
1615 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1616 }
1617}
1618
cedd91d2 1619static void vga_sync_dirty_bitmap(VGACommonState *s)
2bec46dc 1620{
b1950430 1621 memory_region_sync_dirty_bitmap(&s->vram);
2bec46dc
AL		 1622}
1623
50af3246
JQ		 1624void vga_dirty_log_start(VGACommonState *s)
1625{
b1950430 1626 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1627}
1628
1629void vga_dirty_log_stop(VGACommonState *s)
1630{
b1950430 1631 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1632}
1633
799e709b
AL		 1634/*
1635 * graphic modes
1636 */
cedd91d2 1637static void vga_draw_graphic(VGACommonState *s, int full_update)
e89f66ec 1638{
12c7e75a
AK		 1639 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1640 int width, height, shift_control, line_offset, bwidth, bits;
c227f099 1641 ram_addr_t page0, page1, page_min, page_max;
a07cf92a 1642 int disp_width, multi_scan, multi_run;
799e709b
AL		 1643 uint8_t *d;
1644 uint32_t v, addr1, addr;
1645 vga_draw_line_func *vga_draw_line;
1646
1647 full_update |= update_basic_params(s);
1648
1649 if (!full_update)
1650 vga_sync_dirty_bitmap(s);
2bec46dc 1651
a130a41e 1652 s->get_resolution(s, &width, &height);
17b0018b 1653 disp_width = width;
09a79b49 1654
5e55efc9
BS		 1655 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1656 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
799e709b 1657 if (shift_control != 1) {
5e55efc9
BS		 1658 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1659 - 1;
799e709b
AL		 1660 } else {
1661 /* in CGA modes, multi_scan is ignored */
1662 /* XXX: is it correct ? */
1663 multi_scan = double_scan;
1664 }
1665 multi_run = multi_scan;
17b0018b
FB		 1666 if (shift_control != s->shift_control ||
1667 double_scan != s->double_scan) {
799e709b 1668 full_update = 1;
e89f66ec 1669 s->shift_control = shift_control;
17b0018b 1670 s->double_scan = double_scan;
e89f66ec 1671 }
3b46e624 1672
aba35a6c 1673 if (shift_control == 0) {
5e55efc9 1674 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1675 disp_width <<= 1;
1676 }
1677 } else if (shift_control == 1) {
5e55efc9 1678 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1679 disp_width <<= 1;
1680 }
1681 }
1682
799e709b 1683 depth = s->get_bpp(s);
e3697092
AJ		 1684 if (s->line_offset != s->last_line_offset ||
1685 disp_width != s->last_width ||
1686 height != s->last_height ||
799e709b 1687 s->last_depth != depth) {
e2542fe2 1688#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
e3697092 1689 if (depth == 16 || depth == 32) {
0da2ea1b 1690#else
1691 if (depth == 32) {
1692#endif
b8c18e4c
AL		 1693 qemu_free_displaysurface(s->ds);
1694 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1695 s->line_offset,
1696 s->vram_ptr + (s->start_addr * 4));
e2542fe2 1697#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
b8c18e4c 1698 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
0da2ea1b 1699#endif
a93a4a22 1700 dpy_gfx_resize(s->ds);
e3697092
AJ		 1701 } else {
1702 qemu_console_resize(s->ds, disp_width, height);
1703 }
1704 s->last_scr_width = disp_width;
1705 s->last_scr_height = height;
1706 s->last_width = disp_width;
1707 s->last_height = height;
1708 s->last_line_offset = s->line_offset;
1709 s->last_depth = depth;
799e709b
AL		 1710 full_update = 1;
1711 } else if (is_buffer_shared(s->ds->surface) &&
e3697092
AJ		 1712 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1713 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
a93a4a22 1714 dpy_gfx_setdata(s->ds);
e3697092
AJ		 1715 }
1716
1717 s->rgb_to_pixel =
1718 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1719
799e709b 1720 if (shift_control == 0) {
17b0018b 1721 full_update |= update_palette16(s);
5e55efc9 1722 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1723 v = VGA_DRAW_LINE4D2;
17b0018b
FB		 1724 } else {
1725 v = VGA_DRAW_LINE4;
1726 }
15342721 1727 bits = 4;
799e709b 1728 } else if (shift_control == 1) {
17b0018b 1729 full_update |= update_palette16(s);
5e55efc9 1730 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1731 v = VGA_DRAW_LINE2D2;
17b0018b
FB		 1732 } else {
1733 v = VGA_DRAW_LINE2;
1734 }
15342721 1735 bits = 4;
17b0018b 1736 } else {
798b0c25
FB		 1737 switch(s->get_bpp(s)) {
1738 default:
1739 case 0:
4fa0f5d2
FB		 1740 full_update |= update_palette256(s);
1741 v = VGA_DRAW_LINE8D2;
15342721 1742 bits = 4;
798b0c25
FB		 1743 break;
1744 case 8:
1745 full_update |= update_palette256(s);
1746 v = VGA_DRAW_LINE8;
15342721 1747 bits = 8;
798b0c25
FB		 1748 break;
1749 case 15:
1750 v = VGA_DRAW_LINE15;
15342721 1751 bits = 16;
798b0c25
FB		 1752 break;
1753 case 16:
1754 v = VGA_DRAW_LINE16;
15342721 1755 bits = 16;
798b0c25
FB		 1756 break;
1757 case 24:
1758 v = VGA_DRAW_LINE24;
15342721 1759 bits = 24;
798b0c25
FB		 1760 break;
1761 case 32:
1762 v = VGA_DRAW_LINE32;
15342721 1763 bits = 32;
798b0c25 1764 break;
4fa0f5d2 1765 }
17b0018b 1766 }
d3079cd2 1767 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
17b0018b 1768
7d957bd8 1769 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
a8aa669b 1770 s->cursor_invalidate(s);
3b46e624 1771
e89f66ec 1772 line_offset = s->line_offset;
17b0018b 1773#if 0
f6c958c8 1774 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
5e55efc9
BS		 1775 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1776 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
17b0018b 1777#endif
e89f66ec 1778 addr1 = (s->start_addr * 4);
15342721 1779 bwidth = (width * bits + 7) / 8;
39cf7803 1780 y_start = -1;
12c7e75a
AK		 1781 page_min = -1;
1782 page_max = 0;
0e1f5a0c
AL		 1783 d = ds_get_data(s->ds);
1784 linesize = ds_get_linesize(s->ds);
17b0018b 1785 y1 = 0;
e89f66ec
FB		 1786 for(y = 0; y < height; y++) {
1787 addr = addr1;
5e55efc9 1788 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
17b0018b 1789 int shift;
e89f66ec 1790 /* CGA compatibility handling */
5e55efc9 1791 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
17b0018b 1792 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
e89f66ec 1793 }
5e55efc9 1794 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
17b0018b 1795 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
e89f66ec 1796 }
734781c9 1797 update = full_update;
cd7a45c9
BS		 1798 page0 = addr;
1799 page1 = addr + bwidth - 1;
734781c9
JK		 1800 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1801 DIRTY_MEMORY_VGA);
a8aa669b
FB		 1802 /* explicit invalidation for the hardware cursor */
1803 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
e89f66ec 1804 if (update) {
39cf7803
FB		 1805 if (y_start < 0)
1806 y_start = y;
e89f66ec
FB		 1807 if (page0 < page_min)
1808 page_min = page0;
1809 if (page1 > page_max)
1810 page_max = page1;
7d957bd8
AL		 1811 if (!(is_buffer_shared(s->ds->surface))) {
1812 vga_draw_line(s, d, s->vram_ptr + addr, width);
1813 if (s->cursor_draw_line)
1814 s->cursor_draw_line(s, d, y);
1815 }
39cf7803
FB		 1816 } else {
1817 if (y_start >= 0) {
1818 /* flush to display */
a93a4a22
GH		 1819 dpy_gfx_update(s->ds, 0, y_start,
1820 disp_width, y - y_start);
39cf7803
FB		 1821 y_start = -1;
1822 }
e89f66ec 1823 }
a07cf92a 1824 if (!multi_run) {
5e55efc9 1825 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
f6c958c8
FB		 1826 if ((y1 & mask) == mask)
1827 addr1 += line_offset;
1828 y1++;
799e709b 1829 multi_run = multi_scan;
a07cf92a
FB		 1830 } else {
1831 multi_run--;
e89f66ec 1832 }
f6c958c8
FB		 1833 /* line compare acts on the displayed lines */
1834 if (y == s->line_compare)
1835 addr1 = 0;
e89f66ec
FB		 1836 d += linesize;
1837 }
39cf7803
FB		 1838 if (y_start >= 0) {
1839 /* flush to display */
a93a4a22
GH		 1840 dpy_gfx_update(s->ds, 0, y_start,
1841 disp_width, y - y_start);
39cf7803 1842 }
e89f66ec 1843 /* reset modified pages */
12c7e75a 1844 if (page_max >= page_min) {
b1950430
AK		 1845 memory_region_reset_dirty(&s->vram,
1846 page_min,
cd7a45c9 1847 page_max - page_min,
b1950430 1848 DIRTY_MEMORY_VGA);
e89f66ec 1849 }
a8aa669b 1850 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
e89f66ec
FB		 1851}
1852
cedd91d2 1853static void vga_draw_blank(VGACommonState *s, int full_update)
2aebb3eb
FB		 1854{
1855 int i, w, val;
1856 uint8_t *d;
1857
1858 if (!full_update)
1859 return;
1860 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1861 return;
2bec46dc 1862
7d957bd8
AL		 1863 s->rgb_to_pixel =
1864 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
0e1f5a0c 1865 if (ds_get_bits_per_pixel(s->ds) == 8)
2aebb3eb
FB		 1866 val = s->rgb_to_pixel(0, 0, 0);
1867 else
1868 val = 0;
0e1f5a0c
AL		 1869 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1870 d = ds_get_data(s->ds);
2aebb3eb
FB		 1871 for(i = 0; i < s->last_scr_height; i++) {
1872 memset(d, val, w);
0e1f5a0c 1873 d += ds_get_linesize(s->ds);
2aebb3eb 1874 }
a93a4a22
GH		 1875 dpy_gfx_update(s->ds, 0, 0,
1876 s->last_scr_width, s->last_scr_height);
2aebb3eb
FB		 1877}
1878
799e709b
AL		 1879#define GMODE_TEXT 0
1880#define GMODE_GRAPH 1
1881#define GMODE_BLANK 2
1882
95219897 1883static void vga_update_display(void *opaque)
e89f66ec 1884{
cedd91d2 1885 VGACommonState *s = opaque;
799e709b 1886 int full_update, graphic_mode;
e89f66ec 1887
e9a07334
JK		 1888 qemu_flush_coalesced_mmio_buffer();
1889
0e1f5a0c 1890 if (ds_get_bits_per_pixel(s->ds) == 0) {
0f35920c 1891 /* nothing to do */
59a983b9 1892 } else {
3098b9fd 1893 full_update = 0;
df800210 1894 if (!(s->ar_index & 0x20)) {
799e709b
AL		 1895 graphic_mode = GMODE_BLANK;
1896 } else {
5e55efc9 1897 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 1898 }
1899 if (graphic_mode != s->graphic_mode) {
1900 s->graphic_mode = graphic_mode;
9aa0ff0b 1901 s->cursor_blink_time = qemu_get_clock_ms(vm_clock);
799e709b
AL		 1902 full_update = 1;
1903 }
1904 switch(graphic_mode) {
2aebb3eb 1905 case GMODE_TEXT:
e89f66ec 1906 vga_draw_text(s, full_update);
2aebb3eb
FB		 1907 break;
1908 case GMODE_GRAPH:
1909 vga_draw_graphic(s, full_update);
1910 break;
1911 case GMODE_BLANK:
1912 default:
1913 vga_draw_blank(s, full_update);
1914 break;
1915 }
e89f66ec
FB		 1916 }
1917}
1918
a130a41e 1919/* force a full display refresh */
95219897 1920static void vga_invalidate_display(void *opaque)
a130a41e 1921{
cedd91d2 1922 VGACommonState *s = opaque;
3b46e624 1923
3098b9fd
AJ		 1924 s->last_width = -1;
1925 s->last_height = -1;
a130a41e
FB		 1926}
1927
03a3e7ba 1928void vga_common_reset(VGACommonState *s)
e89f66ec 1929{
6e6b7363
BS		 1930 s->sr_index = 0;
1931 memset(s->sr, '\0', sizeof(s->sr));
1932 s->gr_index = 0;
1933 memset(s->gr, '\0', sizeof(s->gr));
1934 s->ar_index = 0;
1935 memset(s->ar, '\0', sizeof(s->ar));
1936 s->ar_flip_flop = 0;
1937 s->cr_index = 0;
1938 memset(s->cr, '\0', sizeof(s->cr));
1939 s->msr = 0;
1940 s->fcr = 0;
1941 s->st00 = 0;
1942 s->st01 = 0;
1943 s->dac_state = 0;
1944 s->dac_sub_index = 0;
1945 s->dac_read_index = 0;
1946 s->dac_write_index = 0;
1947 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1948 s->dac_8bit = 0;
1949 memset(s->palette, '\0', sizeof(s->palette));
1950 s->bank_offset = 0;
6e6b7363
BS		 1951 s->vbe_index = 0;
1952 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
af92284b 1953 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
6e6b7363
BS		 1954 s->vbe_start_addr = 0;
1955 s->vbe_line_offset = 0;
1956 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
6e6b7363 1957 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
799e709b 1958 s->graphic_mode = -1; /* force full update */
6e6b7363
BS		 1959 s->shift_control = 0;
1960 s->double_scan = 0;
1961 s->line_offset = 0;
1962 s->line_compare = 0;
1963 s->start_addr = 0;
1964 s->plane_updated = 0;
1965 s->last_cw = 0;
1966 s->last_ch = 0;
1967 s->last_width = 0;
1968 s->last_height = 0;
1969 s->last_scr_width = 0;
1970 s->last_scr_height = 0;
1971 s->cursor_start = 0;
1972 s->cursor_end = 0;
1973 s->cursor_offset = 0;
1974 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1975 memset(s->last_palette, '\0', sizeof(s->last_palette));
1976 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1977 switch (vga_retrace_method) {
1978 case VGA_RETRACE_DUMB:
1979 break;
1980 case VGA_RETRACE_PRECISE:
1981 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1982 break;
1983 }
80763888 1984 vga_update_memory_access(s);
e89f66ec
FB		 1985}
1986
03a3e7ba
JQ		 1987static void vga_reset(void *opaque)
1988{
cedd91d2 1989 VGACommonState *s = opaque;
03a3e7ba
JQ		 1990 vga_common_reset(s);
1991}
1992
4d3b6f6e
AZ		 1993#define TEXTMODE_X(x) ((x) % width)
1994#define TEXTMODE_Y(x) ((x) / width)
1995#define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1996 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1997/* relay text rendering to the display driver
1998 * instead of doing a full vga_update_display() */
c227f099 1999static void vga_update_text(void *opaque, console_ch_t *chardata)
4d3b6f6e 2000{
cedd91d2 2001 VGACommonState *s = opaque;
799e709b 2002 int graphic_mode, i, cursor_offset, cursor_visible;
4d3b6f6e
AZ		 2003 int cw, cheight, width, height, size, c_min, c_max;
2004 uint32_t *src;
c227f099 2005 console_ch_t *dst, val;
4d3b6f6e 2006 char msg_buffer[80];
799e709b
AL		 2007 int full_update = 0;
2008
e9a07334
JK		 2009 qemu_flush_coalesced_mmio_buffer();
2010
799e709b
AL		 2011 if (!(s->ar_index & 0x20)) {
2012 graphic_mode = GMODE_BLANK;
2013 } else {
5e55efc9 2014 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 2015 }
2016 if (graphic_mode != s->graphic_mode) {
2017 s->graphic_mode = graphic_mode;
2018 full_update = 1;
2019 }
2020 if (s->last_width == -1) {
2021 s->last_width = 0;
2022 full_update = 1;
2023 }
4d3b6f6e 2024
799e709b 2025 switch (graphic_mode) {
4d3b6f6e
AZ		 2026 case GMODE_TEXT:
2027 /* TODO: update palette */
799e709b 2028 full_update |= update_basic_params(s);
4d3b6f6e 2029
799e709b 2030 /* total width & height */
5e55efc9 2031 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
799e709b 2032 cw = 8;
5e55efc9 2033 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
799e709b 2034 cw = 9;
5e55efc9
BS		 2035 }
2036 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
799e709b 2037 cw = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 2038 }
2039 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2040 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
799e709b
AL		 2041 /* ugly hack for CGA 160x100x16 - explain me the logic */
2042 height = 100;
2043 } else {
5e55efc9
BS		 2044 height = s->cr[VGA_CRTC_V_DISP_END] |
2045 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2046 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
799e709b 2047 height = (height + 1) / cheight;
4d3b6f6e
AZ		 2048 }
2049
2050 size = (height * width);
2051 if (size > CH_ATTR_SIZE) {
2052 if (!full_update)
2053 return;
2054
363a37d5
BS		 2055 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2056 width, height);
4d3b6f6e
AZ		 2057 break;
2058 }
2059
799e709b
AL		 2060 if (width != s->last_width || height != s->last_height ||
2061 cw != s->last_cw || cheight != s->last_ch) {
2062 s->last_scr_width = width * cw;
2063 s->last_scr_height = height * cheight;
9678aedd 2064 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
a93a4a22 2065 dpy_text_resize(s->ds, width, height);
9678aedd 2066 s->last_depth = 0;
799e709b
AL		 2067 s->last_width = width;
2068 s->last_height = height;
2069 s->last_ch = cheight;
2070 s->last_cw = cw;
2071 full_update = 1;
2072 }
2073
9678aedd
GH		 2074 if (full_update) {
2075 s->full_update_gfx = 1;
2076 }
2077 if (s->full_update_text) {
2078 s->full_update_text = 0;
2079 full_update |= 1;
2080 }
2081
4d3b6f6e 2082 /* Update "hardware" cursor */
5e55efc9
BS		 2083 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2084 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
4d3b6f6e 2085 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 2086 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2087 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2088 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
4d3b6f6e 2089 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
bf2fde70
GH		 2090 dpy_text_cursor(s->ds,
2091 TEXTMODE_X(cursor_offset),
2092 TEXTMODE_Y(cursor_offset));
4d3b6f6e 2093 else
bf2fde70 2094 dpy_text_cursor(s->ds, -1, -1);
4d3b6f6e 2095 s->cursor_offset = cursor_offset;
5e55efc9
BS		 2096 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2097 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
4d3b6f6e
AZ		 2098 }
2099
2100 src = (uint32_t *) s->vram_ptr + s->start_addr;
2101 dst = chardata;
2102
2103 if (full_update) {
2104 for (i = 0; i < size; src ++, dst ++, i ++)
9ae19b65 2105 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e 2106
a93a4a22 2107 dpy_text_update(s->ds, 0, 0, width, height);
4d3b6f6e
AZ		 2108 } else {
2109 c_max = 0;
2110
2111 for (i = 0; i < size; src ++, dst ++, i ++) {
9ae19b65 2112 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2113 if (*dst != val) {
2114 *dst = val;
2115 c_max = i;
2116 break;
2117 }
2118 }
2119 c_min = i;
2120 for (; i < size; src ++, dst ++, i ++) {
9ae19b65 2121 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2122 if (*dst != val) {
2123 *dst = val;
2124 c_max = i;
2125 }
2126 }
2127
2128 if (c_min <= c_max) {
2129 i = TEXTMODE_Y(c_min);
a93a4a22 2130 dpy_text_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
4d3b6f6e
AZ		 2131 }
2132 }
2133
2134 return;
2135 case GMODE_GRAPH:
2136 if (!full_update)
2137 return;
2138
2139 s->get_resolution(s, &width, &height);
363a37d5
BS		 2140 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2141 width, height);
4d3b6f6e
AZ		 2142 break;
2143 case GMODE_BLANK:
2144 default:
2145 if (!full_update)
2146 return;
2147
363a37d5 2148 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
4d3b6f6e
AZ		 2149 break;
2150 }
2151
2152 /* Display a message */
5228c2d3
AZ		 2153 s->last_width = 60;
2154 s->last_height = height = 3;
bf2fde70 2155 dpy_text_cursor(s->ds, -1, -1);
a93a4a22 2156 dpy_text_resize(s->ds, s->last_width, height);
4d3b6f6e 2157
5228c2d3 2158 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
4d3b6f6e
AZ		 2159 console_write_ch(dst ++, ' ');
2160
2161 size = strlen(msg_buffer);
5228c2d3
AZ		 2162 width = (s->last_width - size) / 2;
2163 dst = chardata + s->last_width + width;
4d3b6f6e
AZ		 2164 for (i = 0; i < size; i ++)
2165 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2166
a93a4a22 2167 dpy_text_update(s->ds, 0, 0, s->last_width, height);
4d3b6f6e
AZ		 2168}
2169
a8170e5e 2170static uint64_t vga_mem_read(void *opaque, hwaddr addr,
b1950430
AK		 2171 unsigned size)
2172{
2173 VGACommonState *s = opaque;
2174
b2a5e761 2175 return vga_mem_readb(s, addr);
b1950430 2176}
e89f66ec 2177
a8170e5e 2178static void vga_mem_write(void *opaque, hwaddr addr,
b1950430
AK		 2179 uint64_t data, unsigned size)
2180{
2181 VGACommonState *s = opaque;
2182
b2a5e761 2183 return vga_mem_writeb(s, addr, data);
b1950430
AK		 2184}
2185
2186const MemoryRegionOps vga_mem_ops = {
2187 .read = vga_mem_read,
2188 .write = vga_mem_write,
2189 .endianness = DEVICE_LITTLE_ENDIAN,
b2a5e761
AK		 2190 .impl = {
2191 .min_access_size = 1,
2192 .max_access_size = 1,
2193 },
e89f66ec
FB		 2194};
2195
11b6b345 2196static int vga_common_post_load(void *opaque, int version_id)
b0a21b53 2197{
0d65ddc3 2198 VGACommonState *s = opaque;
11b6b345
JQ		 2199
2200 /* force refresh */
2201 s->graphic_mode = -1;
2202 return 0;
2203}
2204
2205const VMStateDescription vmstate_vga_common = {
2206 .name = "vga",
2207 .version_id = 2,
2208 .minimum_version_id = 2,
2209 .minimum_version_id_old = 2,
2210 .post_load = vga_common_post_load,
2211 .fields = (VMStateField []) {
2212 VMSTATE_UINT32(latch, VGACommonState),
2213 VMSTATE_UINT8(sr_index, VGACommonState),
2214 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2215 VMSTATE_UINT8(gr_index, VGACommonState),
2216 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2217 VMSTATE_UINT8(ar_index, VGACommonState),
2218 VMSTATE_BUFFER(ar, VGACommonState),
2219 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2220 VMSTATE_UINT8(cr_index, VGACommonState),
2221 VMSTATE_BUFFER(cr, VGACommonState),
2222 VMSTATE_UINT8(msr, VGACommonState),
2223 VMSTATE_UINT8(fcr, VGACommonState),
2224 VMSTATE_UINT8(st00, VGACommonState),
2225 VMSTATE_UINT8(st01, VGACommonState),
2226
2227 VMSTATE_UINT8(dac_state, VGACommonState),
2228 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2229 VMSTATE_UINT8(dac_read_index, VGACommonState),
2230 VMSTATE_UINT8(dac_write_index, VGACommonState),
2231 VMSTATE_BUFFER(dac_cache, VGACommonState),
2232 VMSTATE_BUFFER(palette, VGACommonState),
2233
2234 VMSTATE_INT32(bank_offset, VGACommonState),
2235 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
11b6b345
JQ		 2236 VMSTATE_UINT16(vbe_index, VGACommonState),
2237 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2238 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2239 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2240 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
11b6b345
JQ		 2241 VMSTATE_END_OF_LIST()
2242 }
2243};
2244
4a1e244e 2245void vga_common_init(VGACommonState *s)
e89f66ec 2246{
17b0018b 2247 int i, j, v, b;
e89f66ec
FB		 2248
2249 for(i = 0;i < 256; i++) {
2250 v = 0;
2251 for(j = 0; j < 8; j++) {
2252 v |= ((i >> j) & 1) << (j * 4);
2253 }
2254 expand4[i] = v;
2255
2256 v = 0;
2257 for(j = 0; j < 4; j++) {
2258 v |= ((i >> (2 * j)) & 3) << (j * 4);
2259 }
2260 expand2[i] = v;
2261 }
17b0018b
FB		 2262 for(i = 0; i < 16; i++) {
2263 v = 0;
2264 for(j = 0; j < 4; j++) {
2265 b = ((i >> j) & 1);
2266 v |= b << (2 * j);
2267 v |= b << (2 * j + 1);
2268 }
2269 expand4to8[i] = v;
2270 }
e89f66ec 2271
4a1e244e
GH		 2272 /* valid range: 1 MB -> 256 MB */
2273 s->vram_size = 1024 * 1024;
2274 while (s->vram_size < (s->vram_size_mb << 20) &&
2275 s->vram_size < (256 << 20)) {
2276 s->vram_size <<= 1;
2277 }
2278 s->vram_size_mb = s->vram_size >> 20;
2279
2a3138ab 2280 s->is_vbe_vmstate = 1;
4a1e244e 2281 memory_region_init_ram(&s->vram, "vga.vram", s->vram_size);
c5705a77 2282 vmstate_register_ram_global(&s->vram);
c65adf9b 2283 xen_register_framebuffer(&s->vram);
b1950430 2284 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
798b0c25
FB		 2285 s->get_bpp = vga_get_bpp;
2286 s->get_offsets = vga_get_offsets;
a130a41e 2287 s->get_resolution = vga_get_resolution;
d34cab9f
TS		 2288 s->update = vga_update_display;
2289 s->invalidate = vga_invalidate_display;
2290 s->screen_dump = vga_screen_dump;
4d3b6f6e 2291 s->text_update = vga_update_text;
cb5a7aa8 2292 switch (vga_retrace_method) {
2293 case VGA_RETRACE_DUMB:
2294 s->retrace = vga_dumb_retrace;
2295 s->update_retrace_info = vga_dumb_update_retrace_info;
2296 break;
2297
2298 case VGA_RETRACE_PRECISE:
2299 s->retrace = vga_precise_retrace;
2300 s->update_retrace_info = vga_precise_update_retrace_info;
cb5a7aa8 2301 break;
2302 }
b1950430 2303 vga_dirty_log_start(s);
798b0c25
FB		 2304}
2305
0a039dc7
RH		 2306static const MemoryRegionPortio vga_portio_list[] = {
2307 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2308 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2309 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2310 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2311 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2312 PORTIO_END_OF_LIST(),
2313};
e89f66ec 2314
0a039dc7
RH		 2315static const MemoryRegionPortio vbe_portio_list[] = {
2316 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2317# ifdef TARGET_I386
2318 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2319# else
2320 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2321# endif
2322 PORTIO_END_OF_LIST(),
2323};
4fa0f5d2 2324
0a039dc7
RH		 2325/* Used by both ISA and PCI */
2326MemoryRegion *vga_init_io(VGACommonState *s,
2327 const MemoryRegionPortio **vga_ports,
2328 const MemoryRegionPortio **vbe_ports)
2329{
2330 MemoryRegion *vga_mem;
09a79b49 2331
0a039dc7 2332 *vga_ports = vga_portio_list;
0a039dc7 2333 *vbe_ports = vbe_portio_list;
4fa0f5d2 2334
7267c094 2335 vga_mem = g_malloc(sizeof(*vga_mem));
b1950430
AK		 2336 memory_region_init_io(vga_mem, &vga_mem_ops, s,
2337 "vga-lowmem", 0x20000);
bd8f2f5d 2338 memory_region_set_flush_coalesced(vga_mem);
b1950430
AK		 2339
2340 return vga_mem;
7435b791
BS		 2341}
2342
0a039dc7
RH		 2343void vga_init(VGACommonState *s, MemoryRegion *address_space,
2344 MemoryRegion *address_space_io, bool init_vga_ports)
7435b791 2345{
b1950430 2346 MemoryRegion *vga_io_memory;
0a039dc7
RH		 2347 const MemoryRegionPortio *vga_ports, *vbe_ports;
2348 PortioList *vga_port_list = g_new(PortioList, 1);
2349 PortioList *vbe_port_list = g_new(PortioList, 1);
7435b791
BS		 2350
2351 qemu_register_reset(vga_reset, s);
2352
2353 s->bank_offset = 0;
2354
80763888
JK		 2355 s->legacy_address_space = address_space;
2356
0a039dc7 2357 vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
be20f9e9 2358 memory_region_add_subregion_overlap(address_space,
b1950430
AK		 2359 isa_mem_base + 0x000a0000,
2360 vga_io_memory,
2361 1);
2362 memory_region_set_coalescing(vga_io_memory);
0a039dc7
RH		 2363 if (init_vga_ports) {
2364 portio_list_init(vga_port_list, vga_ports, s, "vga");
2365 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2366 }
2367 if (vbe_ports) {
2368 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2369 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2370 }
d2269f6f
FB		 2371}
2372
be20f9e9 2373void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
f0138a63 2374{
8294a64d
AK		 2375 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2376 * so use an alias to avoid double-mapping the same region.
2377 */
2378 memory_region_init_alias(&s->vram_vbe, "vram.vbe",
2379 &s->vram, 0, memory_region_size(&s->vram));
f0138a63 2380 /* XXX: use optimized standard vga accesses */
be20f9e9 2381 memory_region_add_subregion(system_memory,
b1950430 2382 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
8294a64d 2383 &s->vram_vbe);
f0138a63 2384 s->vbe_mapped = 1;
f0138a63 2385}
59a983b9
FB		 2386/********************************************************/
2387/* vga screen dump */
2388
d663174d 2389void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp)
59a983b9
FB		 2390{
2391 FILE *f;
2392 uint8_t *d, *d1;
e07d630a 2393 uint32_t v;
59a983b9 2394 int y, x;
e07d630a 2395 uint8_t r, g, b;
f8e378f2
AK		 2396 int ret;
2397 char *linebuf, *pbuf;
59a983b9 2398
72750018 2399 trace_ppm_save(filename, ds);
59a983b9 2400 f = fopen(filename, "wb");
d663174d
LC		 2401 if (!f) {
2402 error_setg(errp, "failed to open file '%s': %s", filename,
2403 strerror(errno));
2404 return;
2405 }
2406 ret = fprintf(f, "P6\n%d %d\n%d\n", ds->width, ds->height, 255);
2407 if (ret < 0) {
2408 linebuf = NULL;
2409 goto write_err;
2410 }
7267c094 2411 linebuf = g_malloc(ds->width * 3);
e07d630a
AL		 2412 d1 = ds->data;
2413 for(y = 0; y < ds->height; y++) {
59a983b9 2414 d = d1;
f8e378f2 2415 pbuf = linebuf;
e07d630a
AL		 2416 for(x = 0; x < ds->width; x++) {
2417 if (ds->pf.bits_per_pixel == 32)
2418 v = *(uint32_t *)d;
2419 else
2420 v = (uint32_t) (*(uint16_t *)d);
a0f42610
AK		 2421 /* Limited to 8 or fewer bits per channel: */
2422 r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits);
2423 g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits);
2424 b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits);
f8e378f2
AK		 2425 *pbuf++ = r;
2426 *pbuf++ = g;
2427 *pbuf++ = b;
e07d630a 2428 d += ds->pf.bytes_per_pixel;
59a983b9 2429 }
e07d630a 2430 d1 += ds->linesize;
d663174d 2431 clearerr(f);
f8e378f2
AK		 2432 ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2433 (void)ret;
d663174d
LC		 2434 if (ferror(f)) {
2435 goto write_err;
2436 }
59a983b9 2437 }
d663174d
LC		 2438
2439out:
7267c094 2440 g_free(linebuf);
59a983b9 2441 fclose(f);
d663174d
LC		 2442 return;
2443
2444write_err:
2445 error_setg(errp, "failed to write to file '%s': %s", filename,
2446 strerror(errno));
2447 unlink(filename);
2448 goto out;
59a983b9
FB		 2449}
2450
4c5e8c5c
BS		 2451/* save the vga display in a PPM image even if no display is
2452 available */
d7098135
LC		 2453static void vga_screen_dump(void *opaque, const char *filename, bool cswitch,
2454 Error **errp)
4c5e8c5c 2455{
cedd91d2 2456 VGACommonState *s = opaque;
4c5e8c5c 2457
45efb161
GH		 2458 if (cswitch) {
2459 vga_invalidate_display(s);
45efb161 2460 }
08c4ea29 2461 vga_hw_update();
d663174d 2462 ppm_save(filename, s->ds->surface, errp);
4c5e8c5c 2463}
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