projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 798b0c25 FB |
1 | /* |
| 2 | * QEMU internal VGA defines. | |
| 3 | * | |
| 4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | * of this software and associated documentation files (the "Software"), to deal | |
| 8 | * in the Software without restriction, including without limitation the rights | |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | * copies of the Software, and to permit persons to whom the Software is | |
| 11 | * furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | * THE SOFTWARE. | |
| 23 | */ | |
| 24 | #define MSR_COLOR_EMULATION 0x01 | |
| 25 | #define MSR_PAGE_SELECT 0x20 | |
| 26 | ||
| 27 | #define ST01_V_RETRACE 0x08 | |
| 28 | #define ST01_DISP_ENABLE 0x01 | |
| 29 | ||
| 30 | /* bochs VBE support */ | |
| 31 | #define CONFIG_BOCHS_VBE | |
| 32 | ||
| 33 | #define VBE_DISPI_MAX_XRES 1024 | |
| 34 | #define VBE_DISPI_MAX_YRES 768 | |
| 35 | ||
| 36 | #define VBE_DISPI_INDEX_ID 0x0 | |
| 37 | #define VBE_DISPI_INDEX_XRES 0x1 | |
| 38 | #define VBE_DISPI_INDEX_YRES 0x2 | |
| 39 | #define VBE_DISPI_INDEX_BPP 0x3 | |
| 40 | #define VBE_DISPI_INDEX_ENABLE 0x4 | |
| 41 | #define VBE_DISPI_INDEX_BANK 0x5 | |
| 42 | #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 | |
| 43 | #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 | |
| 44 | #define VBE_DISPI_INDEX_X_OFFSET 0x8 | |
| 45 | #define VBE_DISPI_INDEX_Y_OFFSET 0x9 | |
| 46 | #define VBE_DISPI_INDEX_NB 0xa | |
| 47 | ||
| 48 | #define VBE_DISPI_ID0 0xB0C0 | |
| 49 | #define VBE_DISPI_ID1 0xB0C1 | |
| 50 | #define VBE_DISPI_ID2 0xB0C2 | |
| 51 | ||
| 52 | #define VBE_DISPI_DISABLED 0x00 | |
| 53 | #define VBE_DISPI_ENABLED 0x01 | |
| 54 | #define VBE_DISPI_LFB_ENABLED 0x40 | |
| 55 | #define VBE_DISPI_NOCLEARMEM 0x80 | |
| 56 | ||
| 57 | #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000 | |
| 58 | ||
| 59 | typedef struct VGAState { | |
| 60 | uint8_t *vram_ptr; | |
| 61 | unsigned long vram_offset; | |
| 62 | unsigned int vram_size; | |
| 63 | uint32_t latch; | |
| 64 | uint8_t sr_index; | |
| 65 | uint8_t sr[256]; | |
| 66 | uint8_t gr_index; | |
| 67 | uint8_t gr[256]; | |
| 68 | uint8_t ar_index; | |
| 69 | uint8_t ar[21]; | |
| 70 | int ar_flip_flop; | |
| 71 | uint8_t cr_index; | |
| 72 | uint8_t cr[256]; /* CRT registers */ | |
| 73 | uint8_t msr; /* Misc Output Register */ | |
| 74 | uint8_t fcr; /* Feature Control Register */ | |
| 75 | uint8_t st00; /* status 0 */ | |
| 76 | uint8_t st01; /* status 1 */ | |
| 77 | uint8_t dac_state; | |
| 78 | uint8_t dac_sub_index; | |
| 79 | uint8_t dac_read_index; | |
| 80 | uint8_t dac_write_index; | |
| 81 | uint8_t dac_cache[3]; /* used when writing */ | |
| 82 | uint8_t palette[768]; | |
| 83 | int32_t bank_offset; | |
| 84 | int (*get_bpp)(struct VGAState *s); | |
| 85 | void (*get_offsets)(struct VGAState *s, | |
| 86 | uint32_t *pline_offset, | |
| 87 | uint32_t *pstart_addr); | |
| 88 | #ifdef CONFIG_BOCHS_VBE | |
| 89 | uint16_t vbe_index; | |
| 90 | uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; | |
| 91 | uint32_t vbe_start_addr; | |
| 92 | uint32_t vbe_line_offset; | |
| 93 | uint32_t vbe_bank_mask; | |
| 94 | #endif | |
| 95 | /* display refresh support */ | |
| 96 | DisplayState *ds; | |
| 97 | uint32_t font_offsets[2]; | |
| 98 | int graphic_mode; | |
| 99 | uint8_t shift_control; | |
| 100 | uint8_t double_scan; | |
| 101 | uint32_t line_offset; | |
| 102 | uint32_t line_compare; | |
| 103 | uint32_t start_addr; | |
| 104 | uint8_t last_cw, last_ch; | |
| 105 | uint32_t last_width, last_height; /* in chars or pixels */ | |
| 106 | uint32_t last_scr_width, last_scr_height; /* in pixels */ | |
| 107 | uint8_t cursor_start, cursor_end; | |
| 108 | uint32_t cursor_offset; | |
| 109 | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b); | |
| 110 | /* tell for each page if it has been updated since the last time */ | |
| 111 | uint32_t last_palette[256]; | |
| 112 | #define CH_ATTR_SIZE (160 * 100) | |
| 113 | uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */ | |
| 114 | } VGAState; | |
| 115 | ||
| 116 | void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base, | |
| 117 | unsigned long vga_ram_offset, int vga_ram_size); | |
| 118 | uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr); | |
| 119 | void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val); | |
| 120 | ||
| 121 | extern const uint8_t sr_mask[8]; | |
| 122 | extern const uint8_t gr_mask[16]; |