]>
Commit | Line | Data |
---|---|---|
53c25cea PB |
1 | /* |
2 | * Virtio PCI Bindings | |
3 | * | |
4 | * Copyright IBM, Corp. 2007 | |
5 | * Copyright (c) 2009 CodeSourcery | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * Paul Brook <paul@codesourcery.com> | |
10 | * | |
11 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
12 | * the COPYING file in the top-level directory. | |
13 | * | |
6b620ca3 PB |
14 | * Contributions after 2012-01-13 are licensed under the terms of the |
15 | * GNU GPL, version 2 or (at your option) any later version. | |
53c25cea PB |
16 | */ |
17 | ||
9b8bfe21 | 18 | #include "qemu/osdep.h" |
53c25cea | 19 | |
cbbe4f50 | 20 | #include "standard-headers/linux/virtio_pci.h" |
0d09e41a | 21 | #include "hw/virtio/virtio.h" |
ca77ee28 | 22 | #include "migration/qemu-file-types.h" |
83c9f4ca | 23 | #include "hw/pci/pci.h" |
b0e5196a | 24 | #include "hw/pci/pci_bus.h" |
a27bd6c7 | 25 | #include "hw/qdev-properties.h" |
da34e65c | 26 | #include "qapi/error.h" |
1de7afc9 | 27 | #include "qemu/error-report.h" |
0b8fa32f | 28 | #include "qemu/module.h" |
83c9f4ca PB |
29 | #include "hw/pci/msi.h" |
30 | #include "hw/pci/msix.h" | |
31 | #include "hw/loader.h" | |
9c17d615 | 32 | #include "sysemu/kvm.h" |
47b43a1f | 33 | #include "virtio-pci.h" |
1de7afc9 | 34 | #include "qemu/range.h" |
0d09e41a | 35 | #include "hw/virtio/virtio-bus.h" |
24a6e7f4 | 36 | #include "qapi/visitor.h" |
53c25cea | 37 | |
cbbe4f50 | 38 | #define VIRTIO_PCI_REGION_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_present(dev)) |
aba800a3 | 39 | |
c17bef33 MT |
40 | #undef VIRTIO_PCI_CONFIG |
41 | ||
aba800a3 MT |
42 | /* The remaining space is defined by each driver as the per-driver |
43 | * configuration space */ | |
cbbe4f50 | 44 | #define VIRTIO_PCI_CONFIG_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_enabled(dev)) |
53c25cea | 45 | |
ac7af112 AF |
46 | static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size, |
47 | VirtIOPCIProxy *dev); | |
75fd6f13 | 48 | static void virtio_pci_reset(DeviceState *qdev); |
d51fcfac | 49 | |
53c25cea | 50 | /* virtio device */ |
d2a0ccc6 MT |
51 | /* DeviceState to VirtIOPCIProxy. For use off data-path. TODO: use QOM. */ |
52 | static inline VirtIOPCIProxy *to_virtio_pci_proxy(DeviceState *d) | |
53 | { | |
54 | return container_of(d, VirtIOPCIProxy, pci_dev.qdev); | |
55 | } | |
53c25cea | 56 | |
d2a0ccc6 MT |
57 | /* DeviceState to VirtIOPCIProxy. Note: used on datapath, |
58 | * be careful and test performance if you change this. | |
59 | */ | |
60 | static inline VirtIOPCIProxy *to_virtio_pci_proxy_fast(DeviceState *d) | |
53c25cea | 61 | { |
d2a0ccc6 MT |
62 | return container_of(d, VirtIOPCIProxy, pci_dev.qdev); |
63 | } | |
64 | ||
65 | static void virtio_pci_notify(DeviceState *d, uint16_t vector) | |
66 | { | |
67 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy_fast(d); | |
a3fc66d9 | 68 | |
aba800a3 MT |
69 | if (msix_enabled(&proxy->pci_dev)) |
70 | msix_notify(&proxy->pci_dev, vector); | |
a3fc66d9 PB |
71 | else { |
72 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); | |
0687c37c | 73 | pci_set_irq(&proxy->pci_dev, atomic_read(&vdev->isr) & 1); |
a3fc66d9 | 74 | } |
53c25cea PB |
75 | } |
76 | ||
d2a0ccc6 | 77 | static void virtio_pci_save_config(DeviceState *d, QEMUFile *f) |
ff24bd58 | 78 | { |
d2a0ccc6 | 79 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 PB |
80 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
81 | ||
ff24bd58 MT |
82 | pci_device_save(&proxy->pci_dev, f); |
83 | msix_save(&proxy->pci_dev, f); | |
84 | if (msix_present(&proxy->pci_dev)) | |
a3fc66d9 | 85 | qemu_put_be16(f, vdev->config_vector); |
ff24bd58 MT |
86 | } |
87 | ||
b81b948e DDAG |
88 | static const VMStateDescription vmstate_virtio_pci_modern_queue_state = { |
89 | .name = "virtio_pci/modern_queue_state", | |
90 | .version_id = 1, | |
91 | .minimum_version_id = 1, | |
92 | .fields = (VMStateField[]) { | |
93 | VMSTATE_UINT16(num, VirtIOPCIQueue), | |
94 | VMSTATE_UNUSED(1), /* enabled was stored as be16 */ | |
95 | VMSTATE_BOOL(enabled, VirtIOPCIQueue), | |
96 | VMSTATE_UINT32_ARRAY(desc, VirtIOPCIQueue, 2), | |
97 | VMSTATE_UINT32_ARRAY(avail, VirtIOPCIQueue, 2), | |
98 | VMSTATE_UINT32_ARRAY(used, VirtIOPCIQueue, 2), | |
99 | VMSTATE_END_OF_LIST() | |
a6df8adf | 100 | } |
a6df8adf JW |
101 | }; |
102 | ||
103 | static bool virtio_pci_modern_state_needed(void *opaque) | |
104 | { | |
105 | VirtIOPCIProxy *proxy = opaque; | |
106 | ||
9a4c0e22 | 107 | return virtio_pci_modern(proxy); |
a6df8adf JW |
108 | } |
109 | ||
b81b948e | 110 | static const VMStateDescription vmstate_virtio_pci_modern_state_sub = { |
a6df8adf JW |
111 | .name = "virtio_pci/modern_state", |
112 | .version_id = 1, | |
113 | .minimum_version_id = 1, | |
114 | .needed = &virtio_pci_modern_state_needed, | |
115 | .fields = (VMStateField[]) { | |
b81b948e DDAG |
116 | VMSTATE_UINT32(dfselect, VirtIOPCIProxy), |
117 | VMSTATE_UINT32(gfselect, VirtIOPCIProxy), | |
118 | VMSTATE_UINT32_ARRAY(guest_features, VirtIOPCIProxy, 2), | |
119 | VMSTATE_STRUCT_ARRAY(vqs, VirtIOPCIProxy, VIRTIO_QUEUE_MAX, 0, | |
120 | vmstate_virtio_pci_modern_queue_state, | |
121 | VirtIOPCIQueue), | |
a6df8adf JW |
122 | VMSTATE_END_OF_LIST() |
123 | } | |
124 | }; | |
125 | ||
126 | static const VMStateDescription vmstate_virtio_pci = { | |
127 | .name = "virtio_pci", | |
128 | .version_id = 1, | |
129 | .minimum_version_id = 1, | |
130 | .minimum_version_id_old = 1, | |
131 | .fields = (VMStateField[]) { | |
132 | VMSTATE_END_OF_LIST() | |
133 | }, | |
134 | .subsections = (const VMStateDescription*[]) { | |
b81b948e | 135 | &vmstate_virtio_pci_modern_state_sub, |
a6df8adf JW |
136 | NULL |
137 | } | |
138 | }; | |
139 | ||
b81b948e DDAG |
140 | static bool virtio_pci_has_extra_state(DeviceState *d) |
141 | { | |
142 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); | |
143 | ||
144 | return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA; | |
145 | } | |
146 | ||
a6df8adf JW |
147 | static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f) |
148 | { | |
149 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); | |
150 | ||
151 | vmstate_save_state(f, &vmstate_virtio_pci, proxy, NULL); | |
152 | } | |
153 | ||
154 | static int virtio_pci_load_extra_state(DeviceState *d, QEMUFile *f) | |
155 | { | |
156 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); | |
157 | ||
158 | return vmstate_load_state(f, &vmstate_virtio_pci, proxy, 1); | |
159 | } | |
160 | ||
d2a0ccc6 | 161 | static void virtio_pci_save_queue(DeviceState *d, int n, QEMUFile *f) |
ff24bd58 | 162 | { |
d2a0ccc6 | 163 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 PB |
164 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
165 | ||
ff24bd58 | 166 | if (msix_present(&proxy->pci_dev)) |
a3fc66d9 | 167 | qemu_put_be16(f, virtio_queue_vector(vdev, n)); |
ff24bd58 MT |
168 | } |
169 | ||
d2a0ccc6 | 170 | static int virtio_pci_load_config(DeviceState *d, QEMUFile *f) |
ff24bd58 | 171 | { |
d2a0ccc6 | 172 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 PB |
173 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
174 | ||
ff24bd58 MT |
175 | int ret; |
176 | ret = pci_device_load(&proxy->pci_dev, f); | |
e6da7680 | 177 | if (ret) { |
ff24bd58 | 178 | return ret; |
e6da7680 | 179 | } |
3cac001e | 180 | msix_unuse_all_vectors(&proxy->pci_dev); |
ff24bd58 | 181 | msix_load(&proxy->pci_dev, f); |
e6da7680 | 182 | if (msix_present(&proxy->pci_dev)) { |
a3fc66d9 | 183 | qemu_get_be16s(f, &vdev->config_vector); |
e6da7680 | 184 | } else { |
a3fc66d9 | 185 | vdev->config_vector = VIRTIO_NO_VECTOR; |
e6da7680 | 186 | } |
a3fc66d9 PB |
187 | if (vdev->config_vector != VIRTIO_NO_VECTOR) { |
188 | return msix_vector_use(&proxy->pci_dev, vdev->config_vector); | |
e6da7680 | 189 | } |
ff24bd58 MT |
190 | return 0; |
191 | } | |
192 | ||
d2a0ccc6 | 193 | static int virtio_pci_load_queue(DeviceState *d, int n, QEMUFile *f) |
ff24bd58 | 194 | { |
d2a0ccc6 | 195 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 PB |
196 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
197 | ||
ff24bd58 | 198 | uint16_t vector; |
e6da7680 MT |
199 | if (msix_present(&proxy->pci_dev)) { |
200 | qemu_get_be16s(f, &vector); | |
201 | } else { | |
202 | vector = VIRTIO_NO_VECTOR; | |
203 | } | |
a3fc66d9 | 204 | virtio_queue_set_vector(vdev, n, vector); |
e6da7680 MT |
205 | if (vector != VIRTIO_NO_VECTOR) { |
206 | return msix_vector_use(&proxy->pci_dev, vector); | |
207 | } | |
a6df8adf | 208 | |
ff24bd58 MT |
209 | return 0; |
210 | } | |
211 | ||
8e93cef1 | 212 | static bool virtio_pci_ioeventfd_enabled(DeviceState *d) |
9f06e71a CH |
213 | { |
214 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); | |
215 | ||
8e93cef1 | 216 | return (proxy->flags & VIRTIO_PCI_FLAG_USE_IOEVENTFD) != 0; |
9f06e71a CH |
217 | } |
218 | ||
975acc0a JW |
219 | #define QEMU_VIRTIO_PCI_QUEUE_MEM_MULT 0x1000 |
220 | ||
d9997d89 MA |
221 | static inline int virtio_pci_queue_mem_mult(struct VirtIOPCIProxy *proxy) |
222 | { | |
223 | return (proxy->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ) ? | |
224 | QEMU_VIRTIO_PCI_QUEUE_MEM_MULT : 4; | |
225 | } | |
226 | ||
9f06e71a CH |
227 | static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier, |
228 | int n, bool assign) | |
25db9ebe | 229 | { |
9f06e71a | 230 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 PB |
231 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
232 | VirtQueue *vq = virtio_get_queue(vdev, n); | |
9a4c0e22 MA |
233 | bool legacy = virtio_pci_legacy(proxy); |
234 | bool modern = virtio_pci_modern(proxy); | |
bc85ccfd | 235 | bool fast_mmio = kvm_ioeventfd_any_length_enabled(); |
9824d2a3 | 236 | bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY; |
588255ad | 237 | MemoryRegion *modern_mr = &proxy->notify.mr; |
9824d2a3 | 238 | MemoryRegion *modern_notify_mr = &proxy->notify_pio.mr; |
975acc0a | 239 | MemoryRegion *legacy_mr = &proxy->bar; |
d9997d89 | 240 | hwaddr modern_addr = virtio_pci_queue_mem_mult(proxy) * |
975acc0a JW |
241 | virtio_get_queue_index(vq); |
242 | hwaddr legacy_addr = VIRTIO_PCI_QUEUE_NOTIFY; | |
da146d0a | 243 | |
25db9ebe | 244 | if (assign) { |
975acc0a | 245 | if (modern) { |
bc85ccfd JW |
246 | if (fast_mmio) { |
247 | memory_region_add_eventfd(modern_mr, modern_addr, 0, | |
248 | false, n, notifier); | |
249 | } else { | |
250 | memory_region_add_eventfd(modern_mr, modern_addr, 2, | |
251 | false, n, notifier); | |
252 | } | |
9824d2a3 JW |
253 | if (modern_pio) { |
254 | memory_region_add_eventfd(modern_notify_mr, 0, 2, | |
255 | true, n, notifier); | |
256 | } | |
975acc0a JW |
257 | } |
258 | if (legacy) { | |
259 | memory_region_add_eventfd(legacy_mr, legacy_addr, 2, | |
260 | true, n, notifier); | |
261 | } | |
25db9ebe | 262 | } else { |
975acc0a | 263 | if (modern) { |
bc85ccfd JW |
264 | if (fast_mmio) { |
265 | memory_region_del_eventfd(modern_mr, modern_addr, 0, | |
266 | false, n, notifier); | |
267 | } else { | |
268 | memory_region_del_eventfd(modern_mr, modern_addr, 2, | |
269 | false, n, notifier); | |
270 | } | |
9824d2a3 JW |
271 | if (modern_pio) { |
272 | memory_region_del_eventfd(modern_notify_mr, 0, 2, | |
273 | true, n, notifier); | |
274 | } | |
975acc0a JW |
275 | } |
276 | if (legacy) { | |
277 | memory_region_del_eventfd(legacy_mr, legacy_addr, 2, | |
278 | true, n, notifier); | |
279 | } | |
25db9ebe | 280 | } |
9f06e71a | 281 | return 0; |
25db9ebe SH |
282 | } |
283 | ||
b36e3914 | 284 | static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy) |
25db9ebe | 285 | { |
9f06e71a | 286 | virtio_bus_start_ioeventfd(&proxy->bus); |
25db9ebe SH |
287 | } |
288 | ||
b36e3914 | 289 | static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy) |
25db9ebe | 290 | { |
9f06e71a | 291 | virtio_bus_stop_ioeventfd(&proxy->bus); |
25db9ebe SH |
292 | } |
293 | ||
53c25cea PB |
294 | static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
295 | { | |
296 | VirtIOPCIProxy *proxy = opaque; | |
a3fc66d9 | 297 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
a8170e5e | 298 | hwaddr pa; |
53c25cea | 299 | |
53c25cea PB |
300 | switch (addr) { |
301 | case VIRTIO_PCI_GUEST_FEATURES: | |
181103cd FK |
302 | /* Guest does not negotiate properly? We have to assume nothing. */ |
303 | if (val & (1 << VIRTIO_F_BAD_FEATURE)) { | |
304 | val = virtio_bus_get_vdev_bad_features(&proxy->bus); | |
305 | } | |
ad0c9332 | 306 | virtio_set_features(vdev, val); |
53c25cea PB |
307 | break; |
308 | case VIRTIO_PCI_QUEUE_PFN: | |
a8170e5e | 309 | pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT; |
1b8e9b27 | 310 | if (pa == 0) { |
75fd6f13 | 311 | virtio_pci_reset(DEVICE(proxy)); |
1b8e9b27 | 312 | } |
7055e687 MT |
313 | else |
314 | virtio_queue_set_addr(vdev, vdev->queue_sel, pa); | |
53c25cea PB |
315 | break; |
316 | case VIRTIO_PCI_QUEUE_SEL: | |
87b3bd1c | 317 | if (val < VIRTIO_QUEUE_MAX) |
53c25cea PB |
318 | vdev->queue_sel = val; |
319 | break; | |
320 | case VIRTIO_PCI_QUEUE_NOTIFY: | |
87b3bd1c | 321 | if (val < VIRTIO_QUEUE_MAX) { |
7157e2e2 SH |
322 | virtio_queue_notify(vdev, val); |
323 | } | |
53c25cea PB |
324 | break; |
325 | case VIRTIO_PCI_STATUS: | |
25db9ebe SH |
326 | if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) { |
327 | virtio_pci_stop_ioeventfd(proxy); | |
328 | } | |
329 | ||
3e607cb5 | 330 | virtio_set_status(vdev, val & 0xFF); |
25db9ebe SH |
331 | |
332 | if (val & VIRTIO_CONFIG_S_DRIVER_OK) { | |
333 | virtio_pci_start_ioeventfd(proxy); | |
334 | } | |
335 | ||
1b8e9b27 | 336 | if (vdev->status == 0) { |
75fd6f13 | 337 | virtio_pci_reset(DEVICE(proxy)); |
1b8e9b27 | 338 | } |
c81131db | 339 | |
e43c0b2e MT |
340 | /* Linux before 2.6.34 drives the device without enabling |
341 | the PCI device bus master bit. Enable it automatically | |
342 | for the guest. This is a PCI spec violation but so is | |
343 | initiating DMA with bus master bit clear. */ | |
344 | if (val == (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER)) { | |
345 | pci_default_write_config(&proxy->pci_dev, PCI_COMMAND, | |
346 | proxy->pci_dev.config[PCI_COMMAND] | | |
347 | PCI_COMMAND_MASTER, 1); | |
348 | } | |
53c25cea | 349 | break; |
aba800a3 MT |
350 | case VIRTIO_MSI_CONFIG_VECTOR: |
351 | msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); | |
352 | /* Make it possible for guest to discover an error took place. */ | |
353 | if (msix_vector_use(&proxy->pci_dev, val) < 0) | |
354 | val = VIRTIO_NO_VECTOR; | |
355 | vdev->config_vector = val; | |
356 | break; | |
357 | case VIRTIO_MSI_QUEUE_VECTOR: | |
358 | msix_vector_unuse(&proxy->pci_dev, | |
359 | virtio_queue_vector(vdev, vdev->queue_sel)); | |
360 | /* Make it possible for guest to discover an error took place. */ | |
361 | if (msix_vector_use(&proxy->pci_dev, val) < 0) | |
362 | val = VIRTIO_NO_VECTOR; | |
363 | virtio_queue_set_vector(vdev, vdev->queue_sel, val); | |
364 | break; | |
365 | default: | |
4e02d460 SH |
366 | error_report("%s: unexpected address 0x%x value 0x%x", |
367 | __func__, addr, val); | |
aba800a3 | 368 | break; |
53c25cea PB |
369 | } |
370 | } | |
371 | ||
aba800a3 | 372 | static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr) |
53c25cea | 373 | { |
a3fc66d9 | 374 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
53c25cea PB |
375 | uint32_t ret = 0xFFFFFFFF; |
376 | ||
53c25cea PB |
377 | switch (addr) { |
378 | case VIRTIO_PCI_HOST_FEATURES: | |
6b8f1020 | 379 | ret = vdev->host_features; |
53c25cea PB |
380 | break; |
381 | case VIRTIO_PCI_GUEST_FEATURES: | |
704a76fc | 382 | ret = vdev->guest_features; |
53c25cea PB |
383 | break; |
384 | case VIRTIO_PCI_QUEUE_PFN: | |
385 | ret = virtio_queue_get_addr(vdev, vdev->queue_sel) | |
386 | >> VIRTIO_PCI_QUEUE_ADDR_SHIFT; | |
387 | break; | |
388 | case VIRTIO_PCI_QUEUE_NUM: | |
389 | ret = virtio_queue_get_num(vdev, vdev->queue_sel); | |
390 | break; | |
391 | case VIRTIO_PCI_QUEUE_SEL: | |
392 | ret = vdev->queue_sel; | |
393 | break; | |
394 | case VIRTIO_PCI_STATUS: | |
395 | ret = vdev->status; | |
396 | break; | |
397 | case VIRTIO_PCI_ISR: | |
398 | /* reading from the ISR also clears it. */ | |
0687c37c | 399 | ret = atomic_xchg(&vdev->isr, 0); |
9e64f8a3 | 400 | pci_irq_deassert(&proxy->pci_dev); |
53c25cea | 401 | break; |
aba800a3 MT |
402 | case VIRTIO_MSI_CONFIG_VECTOR: |
403 | ret = vdev->config_vector; | |
404 | break; | |
405 | case VIRTIO_MSI_QUEUE_VECTOR: | |
406 | ret = virtio_queue_vector(vdev, vdev->queue_sel); | |
407 | break; | |
53c25cea PB |
408 | default: |
409 | break; | |
410 | } | |
411 | ||
412 | return ret; | |
413 | } | |
414 | ||
df6db5b3 AG |
415 | static uint64_t virtio_pci_config_read(void *opaque, hwaddr addr, |
416 | unsigned size) | |
53c25cea PB |
417 | { |
418 | VirtIOPCIProxy *proxy = opaque; | |
a3fc66d9 | 419 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
cbbe4f50 | 420 | uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev); |
df6db5b3 | 421 | uint64_t val = 0; |
aba800a3 | 422 | if (addr < config) { |
df6db5b3 | 423 | return virtio_ioport_read(proxy, addr); |
aba800a3 MT |
424 | } |
425 | addr -= config; | |
53c25cea | 426 | |
df6db5b3 AG |
427 | switch (size) { |
428 | case 1: | |
a3fc66d9 | 429 | val = virtio_config_readb(vdev, addr); |
df6db5b3 AG |
430 | break; |
431 | case 2: | |
a3fc66d9 | 432 | val = virtio_config_readw(vdev, addr); |
616a6552 | 433 | if (virtio_is_big_endian(vdev)) { |
8e4a424b BS |
434 | val = bswap16(val); |
435 | } | |
df6db5b3 AG |
436 | break; |
437 | case 4: | |
a3fc66d9 | 438 | val = virtio_config_readl(vdev, addr); |
616a6552 | 439 | if (virtio_is_big_endian(vdev)) { |
8e4a424b BS |
440 | val = bswap32(val); |
441 | } | |
df6db5b3 | 442 | break; |
82afa586 | 443 | } |
df6db5b3 | 444 | return val; |
53c25cea PB |
445 | } |
446 | ||
df6db5b3 AG |
447 | static void virtio_pci_config_write(void *opaque, hwaddr addr, |
448 | uint64_t val, unsigned size) | |
53c25cea PB |
449 | { |
450 | VirtIOPCIProxy *proxy = opaque; | |
cbbe4f50 | 451 | uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev); |
a3fc66d9 | 452 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
aba800a3 MT |
453 | if (addr < config) { |
454 | virtio_ioport_write(proxy, addr, val); | |
455 | return; | |
456 | } | |
457 | addr -= config; | |
df6db5b3 AG |
458 | /* |
459 | * Virtio-PCI is odd. Ioports are LE but config space is target native | |
460 | * endian. | |
461 | */ | |
462 | switch (size) { | |
463 | case 1: | |
a3fc66d9 | 464 | virtio_config_writeb(vdev, addr, val); |
df6db5b3 AG |
465 | break; |
466 | case 2: | |
616a6552 | 467 | if (virtio_is_big_endian(vdev)) { |
8e4a424b BS |
468 | val = bswap16(val); |
469 | } | |
a3fc66d9 | 470 | virtio_config_writew(vdev, addr, val); |
df6db5b3 AG |
471 | break; |
472 | case 4: | |
616a6552 | 473 | if (virtio_is_big_endian(vdev)) { |
8e4a424b BS |
474 | val = bswap32(val); |
475 | } | |
a3fc66d9 | 476 | virtio_config_writel(vdev, addr, val); |
df6db5b3 | 477 | break; |
82afa586 | 478 | } |
53c25cea PB |
479 | } |
480 | ||
da146d0a | 481 | static const MemoryRegionOps virtio_pci_config_ops = { |
df6db5b3 AG |
482 | .read = virtio_pci_config_read, |
483 | .write = virtio_pci_config_write, | |
484 | .impl = { | |
485 | .min_access_size = 1, | |
486 | .max_access_size = 4, | |
487 | }, | |
8e4a424b | 488 | .endianness = DEVICE_LITTLE_ENDIAN, |
da146d0a | 489 | }; |
aba800a3 | 490 | |
a93c8d82 AK |
491 | static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy, |
492 | hwaddr *off, int len) | |
493 | { | |
494 | int i; | |
495 | VirtIOPCIRegion *reg; | |
496 | ||
497 | for (i = 0; i < ARRAY_SIZE(proxy->regs); ++i) { | |
498 | reg = &proxy->regs[i]; | |
499 | if (*off >= reg->offset && | |
500 | *off + len <= reg->offset + reg->size) { | |
501 | *off -= reg->offset; | |
502 | return ®->mr; | |
503 | } | |
504 | } | |
505 | ||
506 | return NULL; | |
507 | } | |
508 | ||
1e40356c MT |
509 | /* Below are generic functions to do memcpy from/to an address space, |
510 | * without byteswaps, with input validation. | |
511 | * | |
512 | * As regular address_space_* APIs all do some kind of byteswap at least for | |
513 | * some host/target combinations, we are forced to explicitly convert to a | |
514 | * known-endianness integer value. | |
515 | * It doesn't really matter which endian format to go through, so the code | |
516 | * below selects the endian that causes the least amount of work on the given | |
517 | * host. | |
518 | * | |
519 | * Note: host pointer must be aligned. | |
520 | */ | |
521 | static | |
a93c8d82 | 522 | void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr, |
1e40356c MT |
523 | const uint8_t *buf, int len) |
524 | { | |
a93c8d82 AK |
525 | uint64_t val; |
526 | MemoryRegion *mr; | |
1e40356c MT |
527 | |
528 | /* address_space_* APIs assume an aligned address. | |
529 | * As address is under guest control, handle illegal values. | |
530 | */ | |
531 | addr &= ~(len - 1); | |
532 | ||
a93c8d82 AK |
533 | mr = virtio_address_space_lookup(proxy, &addr, len); |
534 | if (!mr) { | |
535 | return; | |
536 | } | |
537 | ||
1e40356c MT |
538 | /* Make sure caller aligned buf properly */ |
539 | assert(!(((uintptr_t)buf) & (len - 1))); | |
540 | ||
541 | switch (len) { | |
542 | case 1: | |
543 | val = pci_get_byte(buf); | |
1e40356c MT |
544 | break; |
545 | case 2: | |
a93c8d82 | 546 | val = cpu_to_le16(pci_get_word(buf)); |
1e40356c MT |
547 | break; |
548 | case 4: | |
a93c8d82 | 549 | val = cpu_to_le32(pci_get_long(buf)); |
1e40356c MT |
550 | break; |
551 | default: | |
552 | /* As length is under guest control, handle illegal values. */ | |
a93c8d82 | 553 | return; |
1e40356c | 554 | } |
a93c8d82 | 555 | memory_region_dispatch_write(mr, addr, val, len, MEMTXATTRS_UNSPECIFIED); |
1e40356c MT |
556 | } |
557 | ||
558 | static void | |
a93c8d82 AK |
559 | virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr, |
560 | uint8_t *buf, int len) | |
1e40356c | 561 | { |
a93c8d82 AK |
562 | uint64_t val; |
563 | MemoryRegion *mr; | |
1e40356c MT |
564 | |
565 | /* address_space_* APIs assume an aligned address. | |
566 | * As address is under guest control, handle illegal values. | |
567 | */ | |
568 | addr &= ~(len - 1); | |
569 | ||
a93c8d82 AK |
570 | mr = virtio_address_space_lookup(proxy, &addr, len); |
571 | if (!mr) { | |
572 | return; | |
573 | } | |
574 | ||
1e40356c MT |
575 | /* Make sure caller aligned buf properly */ |
576 | assert(!(((uintptr_t)buf) & (len - 1))); | |
577 | ||
a93c8d82 | 578 | memory_region_dispatch_read(mr, addr, &val, len, MEMTXATTRS_UNSPECIFIED); |
1e40356c MT |
579 | switch (len) { |
580 | case 1: | |
1e40356c MT |
581 | pci_set_byte(buf, val); |
582 | break; | |
583 | case 2: | |
a93c8d82 | 584 | pci_set_word(buf, le16_to_cpu(val)); |
1e40356c MT |
585 | break; |
586 | case 4: | |
a93c8d82 | 587 | pci_set_long(buf, le32_to_cpu(val)); |
1e40356c MT |
588 | break; |
589 | default: | |
590 | /* As length is under guest control, handle illegal values. */ | |
591 | break; | |
592 | } | |
593 | } | |
594 | ||
aba800a3 MT |
595 | static void virtio_write_config(PCIDevice *pci_dev, uint32_t address, |
596 | uint32_t val, int len) | |
597 | { | |
3f262b26 | 598 | VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev); |
a3fc66d9 | 599 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
ada434cd | 600 | struct virtio_pci_cfg_cap *cfg; |
ed757e14 | 601 | |
1129714f MT |
602 | pci_default_write_config(pci_dev, address, val, len); |
603 | ||
604 | if (range_covers_byte(address, len, PCI_COMMAND) && | |
68a27b20 | 605 | !(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { |
1129714f | 606 | virtio_pci_stop_ioeventfd(proxy); |
45363e46 | 607 | virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK); |
ed757e14 | 608 | } |
ada434cd MT |
609 | |
610 | if (proxy->config_cap && | |
611 | ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap, | |
612 | pci_cfg_data), | |
613 | sizeof cfg->pci_cfg_data)) { | |
614 | uint32_t off; | |
615 | uint32_t len; | |
616 | ||
617 | cfg = (void *)(proxy->pci_dev.config + proxy->config_cap); | |
618 | off = le32_to_cpu(cfg->cap.offset); | |
619 | len = le32_to_cpu(cfg->cap.length); | |
620 | ||
2a639123 MT |
621 | if (len == 1 || len == 2 || len == 4) { |
622 | assert(len <= sizeof cfg->pci_cfg_data); | |
a93c8d82 | 623 | virtio_address_space_write(proxy, off, cfg->pci_cfg_data, len); |
ada434cd MT |
624 | } |
625 | } | |
626 | } | |
627 | ||
628 | static uint32_t virtio_read_config(PCIDevice *pci_dev, | |
629 | uint32_t address, int len) | |
630 | { | |
3f262b26 | 631 | VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev); |
ada434cd MT |
632 | struct virtio_pci_cfg_cap *cfg; |
633 | ||
634 | if (proxy->config_cap && | |
635 | ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap, | |
636 | pci_cfg_data), | |
637 | sizeof cfg->pci_cfg_data)) { | |
638 | uint32_t off; | |
639 | uint32_t len; | |
640 | ||
641 | cfg = (void *)(proxy->pci_dev.config + proxy->config_cap); | |
642 | off = le32_to_cpu(cfg->cap.offset); | |
643 | len = le32_to_cpu(cfg->cap.length); | |
644 | ||
2a639123 MT |
645 | if (len == 1 || len == 2 || len == 4) { |
646 | assert(len <= sizeof cfg->pci_cfg_data); | |
a93c8d82 | 647 | virtio_address_space_read(proxy, off, cfg->pci_cfg_data, len); |
ada434cd MT |
648 | } |
649 | } | |
650 | ||
651 | return pci_default_read_config(pci_dev, address, len); | |
53c25cea PB |
652 | } |
653 | ||
7d37d351 JK |
654 | static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy, |
655 | unsigned int queue_no, | |
d1f6af6a | 656 | unsigned int vector) |
7d37d351 | 657 | { |
7d37d351 | 658 | VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector]; |
15b2bd18 | 659 | int ret; |
7d37d351 JK |
660 | |
661 | if (irqfd->users == 0) { | |
d1f6af6a | 662 | ret = kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_dev); |
7d37d351 JK |
663 | if (ret < 0) { |
664 | return ret; | |
665 | } | |
666 | irqfd->virq = ret; | |
667 | } | |
668 | irqfd->users++; | |
7d37d351 JK |
669 | return 0; |
670 | } | |
671 | ||
672 | static void kvm_virtio_pci_vq_vector_release(VirtIOPCIProxy *proxy, | |
7d37d351 | 673 | unsigned int vector) |
774345f9 MT |
674 | { |
675 | VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector]; | |
676 | if (--irqfd->users == 0) { | |
677 | kvm_irqchip_release_virq(kvm_state, irqfd->virq); | |
678 | } | |
679 | } | |
680 | ||
f1d0f15a MT |
681 | static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy, |
682 | unsigned int queue_no, | |
683 | unsigned int vector) | |
684 | { | |
685 | VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector]; | |
a3fc66d9 PB |
686 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
687 | VirtQueue *vq = virtio_get_queue(vdev, queue_no); | |
f1d0f15a | 688 | EventNotifier *n = virtio_queue_get_guest_notifier(vq); |
9be38598 | 689 | return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq); |
f1d0f15a MT |
690 | } |
691 | ||
692 | static void kvm_virtio_pci_irqfd_release(VirtIOPCIProxy *proxy, | |
693 | unsigned int queue_no, | |
694 | unsigned int vector) | |
7d37d351 | 695 | { |
a3fc66d9 PB |
696 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
697 | VirtQueue *vq = virtio_get_queue(vdev, queue_no); | |
15b2bd18 | 698 | EventNotifier *n = virtio_queue_get_guest_notifier(vq); |
7d37d351 | 699 | VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector]; |
15b2bd18 | 700 | int ret; |
7d37d351 | 701 | |
1c9b71a7 | 702 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, irqfd->virq); |
7d37d351 | 703 | assert(ret == 0); |
f1d0f15a | 704 | } |
7d37d351 | 705 | |
774345f9 MT |
706 | static int kvm_virtio_pci_vector_use(VirtIOPCIProxy *proxy, int nvqs) |
707 | { | |
708 | PCIDevice *dev = &proxy->pci_dev; | |
a3fc66d9 | 709 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
181103cd | 710 | VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); |
774345f9 MT |
711 | unsigned int vector; |
712 | int ret, queue_no; | |
774345f9 MT |
713 | |
714 | for (queue_no = 0; queue_no < nvqs; queue_no++) { | |
715 | if (!virtio_queue_get_num(vdev, queue_no)) { | |
716 | break; | |
717 | } | |
718 | vector = virtio_queue_vector(vdev, queue_no); | |
719 | if (vector >= msix_nr_vectors_allocated(dev)) { | |
720 | continue; | |
721 | } | |
d1f6af6a | 722 | ret = kvm_virtio_pci_vq_vector_use(proxy, queue_no, vector); |
774345f9 MT |
723 | if (ret < 0) { |
724 | goto undo; | |
7d37d351 | 725 | } |
f1d0f15a MT |
726 | /* If guest supports masking, set up irqfd now. |
727 | * Otherwise, delay until unmasked in the frontend. | |
728 | */ | |
5669655a | 729 | if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) { |
f1d0f15a MT |
730 | ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector); |
731 | if (ret < 0) { | |
732 | kvm_virtio_pci_vq_vector_release(proxy, vector); | |
733 | goto undo; | |
734 | } | |
735 | } | |
7d37d351 | 736 | } |
7d37d351 | 737 | return 0; |
774345f9 MT |
738 | |
739 | undo: | |
740 | while (--queue_no >= 0) { | |
741 | vector = virtio_queue_vector(vdev, queue_no); | |
742 | if (vector >= msix_nr_vectors_allocated(dev)) { | |
743 | continue; | |
744 | } | |
5669655a | 745 | if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) { |
e387f99e | 746 | kvm_virtio_pci_irqfd_release(proxy, queue_no, vector); |
f1d0f15a | 747 | } |
774345f9 MT |
748 | kvm_virtio_pci_vq_vector_release(proxy, vector); |
749 | } | |
750 | return ret; | |
7d37d351 JK |
751 | } |
752 | ||
774345f9 MT |
753 | static void kvm_virtio_pci_vector_release(VirtIOPCIProxy *proxy, int nvqs) |
754 | { | |
755 | PCIDevice *dev = &proxy->pci_dev; | |
a3fc66d9 | 756 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
774345f9 MT |
757 | unsigned int vector; |
758 | int queue_no; | |
181103cd | 759 | VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); |
774345f9 MT |
760 | |
761 | for (queue_no = 0; queue_no < nvqs; queue_no++) { | |
762 | if (!virtio_queue_get_num(vdev, queue_no)) { | |
763 | break; | |
764 | } | |
765 | vector = virtio_queue_vector(vdev, queue_no); | |
766 | if (vector >= msix_nr_vectors_allocated(dev)) { | |
767 | continue; | |
768 | } | |
f1d0f15a MT |
769 | /* If guest supports masking, clean up irqfd now. |
770 | * Otherwise, it was cleaned when masked in the frontend. | |
771 | */ | |
5669655a | 772 | if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) { |
e387f99e | 773 | kvm_virtio_pci_irqfd_release(proxy, queue_no, vector); |
f1d0f15a | 774 | } |
774345f9 MT |
775 | kvm_virtio_pci_vq_vector_release(proxy, vector); |
776 | } | |
777 | } | |
778 | ||
a38b2c49 MT |
779 | static int virtio_pci_vq_vector_unmask(VirtIOPCIProxy *proxy, |
780 | unsigned int queue_no, | |
781 | unsigned int vector, | |
782 | MSIMessage msg) | |
774345f9 | 783 | { |
a3fc66d9 PB |
784 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
785 | VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); | |
786 | VirtQueue *vq = virtio_get_queue(vdev, queue_no); | |
774345f9 | 787 | EventNotifier *n = virtio_queue_get_guest_notifier(vq); |
a38b2c49 | 788 | VirtIOIRQFD *irqfd; |
53510bfc | 789 | int ret = 0; |
774345f9 | 790 | |
a38b2c49 MT |
791 | if (proxy->vector_irqfd) { |
792 | irqfd = &proxy->vector_irqfd[vector]; | |
793 | if (irqfd->msg.data != msg.data || irqfd->msg.address != msg.address) { | |
dc9f06ca PF |
794 | ret = kvm_irqchip_update_msi_route(kvm_state, irqfd->virq, msg, |
795 | &proxy->pci_dev); | |
a38b2c49 MT |
796 | if (ret < 0) { |
797 | return ret; | |
798 | } | |
3f1fea0f | 799 | kvm_irqchip_commit_routes(kvm_state); |
774345f9 MT |
800 | } |
801 | } | |
802 | ||
f1d0f15a MT |
803 | /* If guest supports masking, irqfd is already setup, unmask it. |
804 | * Otherwise, set it up now. | |
805 | */ | |
5669655a | 806 | if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) { |
a3fc66d9 | 807 | k->guest_notifier_mask(vdev, queue_no, false); |
f1d0f15a | 808 | /* Test after unmasking to avoid losing events. */ |
181103cd | 809 | if (k->guest_notifier_pending && |
a3fc66d9 | 810 | k->guest_notifier_pending(vdev, queue_no)) { |
f1d0f15a MT |
811 | event_notifier_set(n); |
812 | } | |
813 | } else { | |
814 | ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector); | |
7d37d351 | 815 | } |
774345f9 | 816 | return ret; |
7d37d351 JK |
817 | } |
818 | ||
a38b2c49 | 819 | static void virtio_pci_vq_vector_mask(VirtIOPCIProxy *proxy, |
7d37d351 JK |
820 | unsigned int queue_no, |
821 | unsigned int vector) | |
822 | { | |
a3fc66d9 PB |
823 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
824 | VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); | |
181103cd | 825 | |
f1d0f15a MT |
826 | /* If guest supports masking, keep irqfd but mask it. |
827 | * Otherwise, clean it up now. | |
828 | */ | |
5669655a | 829 | if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) { |
a3fc66d9 | 830 | k->guest_notifier_mask(vdev, queue_no, true); |
f1d0f15a | 831 | } else { |
e387f99e | 832 | kvm_virtio_pci_irqfd_release(proxy, queue_no, vector); |
f1d0f15a | 833 | } |
7d37d351 JK |
834 | } |
835 | ||
a38b2c49 MT |
836 | static int virtio_pci_vector_unmask(PCIDevice *dev, unsigned vector, |
837 | MSIMessage msg) | |
7d37d351 JK |
838 | { |
839 | VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev); | |
a3fc66d9 | 840 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
851c2a75 JW |
841 | VirtQueue *vq = virtio_vector_first_queue(vdev, vector); |
842 | int ret, index, unmasked = 0; | |
7d37d351 | 843 | |
851c2a75 JW |
844 | while (vq) { |
845 | index = virtio_get_queue_index(vq); | |
846 | if (!virtio_queue_get_num(vdev, index)) { | |
7d37d351 JK |
847 | break; |
848 | } | |
6652d081 JW |
849 | if (index < proxy->nvqs_with_notifiers) { |
850 | ret = virtio_pci_vq_vector_unmask(proxy, index, vector, msg); | |
851 | if (ret < 0) { | |
852 | goto undo; | |
853 | } | |
854 | ++unmasked; | |
7d37d351 | 855 | } |
851c2a75 | 856 | vq = virtio_vector_next_queue(vq); |
7d37d351 | 857 | } |
851c2a75 | 858 | |
7d37d351 JK |
859 | return 0; |
860 | ||
861 | undo: | |
851c2a75 | 862 | vq = virtio_vector_first_queue(vdev, vector); |
6652d081 | 863 | while (vq && unmasked >= 0) { |
851c2a75 | 864 | index = virtio_get_queue_index(vq); |
6652d081 JW |
865 | if (index < proxy->nvqs_with_notifiers) { |
866 | virtio_pci_vq_vector_mask(proxy, index, vector); | |
867 | --unmasked; | |
868 | } | |
851c2a75 | 869 | vq = virtio_vector_next_queue(vq); |
7d37d351 JK |
870 | } |
871 | return ret; | |
872 | } | |
873 | ||
a38b2c49 | 874 | static void virtio_pci_vector_mask(PCIDevice *dev, unsigned vector) |
7d37d351 JK |
875 | { |
876 | VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev); | |
a3fc66d9 | 877 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
851c2a75 JW |
878 | VirtQueue *vq = virtio_vector_first_queue(vdev, vector); |
879 | int index; | |
7d37d351 | 880 | |
851c2a75 JW |
881 | while (vq) { |
882 | index = virtio_get_queue_index(vq); | |
883 | if (!virtio_queue_get_num(vdev, index)) { | |
7d37d351 JK |
884 | break; |
885 | } | |
6652d081 JW |
886 | if (index < proxy->nvqs_with_notifiers) { |
887 | virtio_pci_vq_vector_mask(proxy, index, vector); | |
888 | } | |
851c2a75 | 889 | vq = virtio_vector_next_queue(vq); |
7d37d351 JK |
890 | } |
891 | } | |
892 | ||
a38b2c49 MT |
893 | static void virtio_pci_vector_poll(PCIDevice *dev, |
894 | unsigned int vector_start, | |
895 | unsigned int vector_end) | |
89d62be9 MT |
896 | { |
897 | VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev); | |
a3fc66d9 | 898 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
181103cd | 899 | VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); |
89d62be9 MT |
900 | int queue_no; |
901 | unsigned int vector; | |
902 | EventNotifier *notifier; | |
903 | VirtQueue *vq; | |
904 | ||
2d620f59 | 905 | for (queue_no = 0; queue_no < proxy->nvqs_with_notifiers; queue_no++) { |
89d62be9 MT |
906 | if (!virtio_queue_get_num(vdev, queue_no)) { |
907 | break; | |
908 | } | |
909 | vector = virtio_queue_vector(vdev, queue_no); | |
910 | if (vector < vector_start || vector >= vector_end || | |
911 | !msix_is_masked(dev, vector)) { | |
912 | continue; | |
913 | } | |
914 | vq = virtio_get_queue(vdev, queue_no); | |
915 | notifier = virtio_queue_get_guest_notifier(vq); | |
181103cd FK |
916 | if (k->guest_notifier_pending) { |
917 | if (k->guest_notifier_pending(vdev, queue_no)) { | |
f1d0f15a MT |
918 | msix_set_pending(dev, vector); |
919 | } | |
920 | } else if (event_notifier_test_and_clear(notifier)) { | |
89d62be9 MT |
921 | msix_set_pending(dev, vector); |
922 | } | |
923 | } | |
924 | } | |
925 | ||
926 | static int virtio_pci_set_guest_notifier(DeviceState *d, int n, bool assign, | |
927 | bool with_irqfd) | |
ade80dc8 | 928 | { |
d2a0ccc6 | 929 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 PB |
930 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
931 | VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev); | |
932 | VirtQueue *vq = virtio_get_queue(vdev, n); | |
ade80dc8 MT |
933 | EventNotifier *notifier = virtio_queue_get_guest_notifier(vq); |
934 | ||
935 | if (assign) { | |
936 | int r = event_notifier_init(notifier, 0); | |
937 | if (r < 0) { | |
938 | return r; | |
939 | } | |
89d62be9 | 940 | virtio_queue_set_guest_notifier_fd_handler(vq, true, with_irqfd); |
ade80dc8 | 941 | } else { |
89d62be9 | 942 | virtio_queue_set_guest_notifier_fd_handler(vq, false, with_irqfd); |
ade80dc8 MT |
943 | event_notifier_cleanup(notifier); |
944 | } | |
945 | ||
5669655a VK |
946 | if (!msix_enabled(&proxy->pci_dev) && |
947 | vdev->use_guest_notifier_mask && | |
948 | vdc->guest_notifier_mask) { | |
a3fc66d9 | 949 | vdc->guest_notifier_mask(vdev, n, !assign); |
62c96360 MT |
950 | } |
951 | ||
ade80dc8 MT |
952 | return 0; |
953 | } | |
954 | ||
d2a0ccc6 | 955 | static bool virtio_pci_query_guest_notifiers(DeviceState *d) |
5430a28f | 956 | { |
d2a0ccc6 | 957 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
5430a28f MT |
958 | return msix_enabled(&proxy->pci_dev); |
959 | } | |
960 | ||
2d620f59 | 961 | static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign) |
54dd9321 | 962 | { |
d2a0ccc6 | 963 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 | 964 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
181103cd | 965 | VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev); |
54dd9321 | 966 | int r, n; |
89d62be9 MT |
967 | bool with_irqfd = msix_enabled(&proxy->pci_dev) && |
968 | kvm_msi_via_irqfd_enabled(); | |
54dd9321 | 969 | |
87b3bd1c | 970 | nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX); |
2d620f59 MT |
971 | |
972 | /* When deassigning, pass a consistent nvqs value | |
973 | * to avoid leaking notifiers. | |
974 | */ | |
975 | assert(assign || nvqs == proxy->nvqs_with_notifiers); | |
976 | ||
977 | proxy->nvqs_with_notifiers = nvqs; | |
978 | ||
7d37d351 | 979 | /* Must unset vector notifier while guest notifier is still assigned */ |
181103cd | 980 | if ((proxy->vector_irqfd || k->guest_notifier_mask) && !assign) { |
7d37d351 | 981 | msix_unset_vector_notifiers(&proxy->pci_dev); |
a38b2c49 MT |
982 | if (proxy->vector_irqfd) { |
983 | kvm_virtio_pci_vector_release(proxy, nvqs); | |
984 | g_free(proxy->vector_irqfd); | |
985 | proxy->vector_irqfd = NULL; | |
986 | } | |
7d37d351 JK |
987 | } |
988 | ||
2d620f59 | 989 | for (n = 0; n < nvqs; n++) { |
54dd9321 MT |
990 | if (!virtio_queue_get_num(vdev, n)) { |
991 | break; | |
992 | } | |
993 | ||
23fe2b3f | 994 | r = virtio_pci_set_guest_notifier(d, n, assign, with_irqfd); |
54dd9321 MT |
995 | if (r < 0) { |
996 | goto assign_error; | |
997 | } | |
998 | } | |
999 | ||
7d37d351 | 1000 | /* Must set vector notifier after guest notifier has been assigned */ |
181103cd | 1001 | if ((with_irqfd || k->guest_notifier_mask) && assign) { |
a38b2c49 MT |
1002 | if (with_irqfd) { |
1003 | proxy->vector_irqfd = | |
1004 | g_malloc0(sizeof(*proxy->vector_irqfd) * | |
1005 | msix_nr_vectors_allocated(&proxy->pci_dev)); | |
1006 | r = kvm_virtio_pci_vector_use(proxy, nvqs); | |
1007 | if (r < 0) { | |
1008 | goto assign_error; | |
1009 | } | |
774345f9 | 1010 | } |
7d37d351 | 1011 | r = msix_set_vector_notifiers(&proxy->pci_dev, |
a38b2c49 MT |
1012 | virtio_pci_vector_unmask, |
1013 | virtio_pci_vector_mask, | |
1014 | virtio_pci_vector_poll); | |
7d37d351 | 1015 | if (r < 0) { |
774345f9 | 1016 | goto notifiers_error; |
7d37d351 JK |
1017 | } |
1018 | } | |
1019 | ||
54dd9321 MT |
1020 | return 0; |
1021 | ||
774345f9 | 1022 | notifiers_error: |
a38b2c49 MT |
1023 | if (with_irqfd) { |
1024 | assert(assign); | |
1025 | kvm_virtio_pci_vector_release(proxy, nvqs); | |
1026 | } | |
774345f9 | 1027 | |
54dd9321 MT |
1028 | assign_error: |
1029 | /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */ | |
7d37d351 | 1030 | assert(assign); |
54dd9321 | 1031 | while (--n >= 0) { |
89d62be9 | 1032 | virtio_pci_set_guest_notifier(d, n, !assign, with_irqfd); |
54dd9321 MT |
1033 | } |
1034 | return r; | |
1035 | } | |
1036 | ||
6f80e617 TB |
1037 | static int virtio_pci_set_host_notifier_mr(DeviceState *d, int n, |
1038 | MemoryRegion *mr, bool assign) | |
1039 | { | |
1040 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); | |
1041 | int offset; | |
1042 | ||
1043 | if (n >= VIRTIO_QUEUE_MAX || !virtio_pci_modern(proxy) || | |
1044 | virtio_pci_queue_mem_mult(proxy) != memory_region_size(mr)) { | |
1045 | return -1; | |
1046 | } | |
1047 | ||
1048 | if (assign) { | |
1049 | offset = virtio_pci_queue_mem_mult(proxy) * n; | |
1050 | memory_region_add_subregion_overlap(&proxy->notify.mr, offset, mr, 1); | |
1051 | } else { | |
1052 | memory_region_del_subregion(&proxy->notify.mr, mr); | |
1053 | } | |
1054 | ||
1055 | return 0; | |
1056 | } | |
1057 | ||
d2a0ccc6 | 1058 | static void virtio_pci_vmstate_change(DeviceState *d, bool running) |
25db9ebe | 1059 | { |
d2a0ccc6 | 1060 | VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d); |
a3fc66d9 | 1061 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
25db9ebe SH |
1062 | |
1063 | if (running) { | |
68a27b20 MT |
1064 | /* Old QEMU versions did not set bus master enable on status write. |
1065 | * Detect DRIVER set and enable it. | |
1066 | */ | |
1067 | if ((proxy->flags & VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION) && | |
1068 | (vdev->status & VIRTIO_CONFIG_S_DRIVER) && | |
45363e46 | 1069 | !(proxy->pci_dev.config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { |
68a27b20 MT |
1070 | pci_default_write_config(&proxy->pci_dev, PCI_COMMAND, |
1071 | proxy->pci_dev.config[PCI_COMMAND] | | |
1072 | PCI_COMMAND_MASTER, 1); | |
89c473fd | 1073 | } |
25db9ebe | 1074 | virtio_pci_start_ioeventfd(proxy); |
ade80dc8 | 1075 | } else { |
25db9ebe | 1076 | virtio_pci_stop_ioeventfd(proxy); |
ade80dc8 | 1077 | } |
ade80dc8 MT |
1078 | } |
1079 | ||
085bccb7 FK |
1080 | /* |
1081 | * virtio-pci: This is the PCIDevice which has a virtio-pci-bus. | |
1082 | */ | |
1083 | ||
e0d686bf JW |
1084 | static int virtio_pci_query_nvectors(DeviceState *d) |
1085 | { | |
1086 | VirtIOPCIProxy *proxy = VIRTIO_PCI(d); | |
1087 | ||
1088 | return proxy->nvectors; | |
1089 | } | |
1090 | ||
8607f5c3 JW |
1091 | static AddressSpace *virtio_pci_get_dma_as(DeviceState *d) |
1092 | { | |
1093 | VirtIOPCIProxy *proxy = VIRTIO_PCI(d); | |
1094 | PCIDevice *dev = &proxy->pci_dev; | |
1095 | ||
f0edf239 | 1096 | return pci_get_address_space(dev); |
8607f5c3 JW |
1097 | } |
1098 | ||
ada434cd | 1099 | static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy, |
dfb8e184 MT |
1100 | struct virtio_pci_cap *cap) |
1101 | { | |
1102 | PCIDevice *dev = &proxy->pci_dev; | |
1103 | int offset; | |
1104 | ||
9a7c2a59 MZ |
1105 | offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, |
1106 | cap->cap_len, &error_abort); | |
dfb8e184 MT |
1107 | |
1108 | assert(cap->cap_len >= sizeof *cap); | |
1109 | memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, | |
1110 | cap->cap_len - PCI_CAP_FLAGS); | |
ada434cd MT |
1111 | |
1112 | return offset; | |
dfb8e184 MT |
1113 | } |
1114 | ||
dfb8e184 MT |
1115 | static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr, |
1116 | unsigned size) | |
1117 | { | |
1118 | VirtIOPCIProxy *proxy = opaque; | |
1119 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); | |
1120 | uint32_t val = 0; | |
1121 | int i; | |
1122 | ||
1123 | switch (addr) { | |
1124 | case VIRTIO_PCI_COMMON_DFSELECT: | |
1125 | val = proxy->dfselect; | |
1126 | break; | |
1127 | case VIRTIO_PCI_COMMON_DF: | |
1128 | if (proxy->dfselect <= 1) { | |
9b706dbb MT |
1129 | VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev); |
1130 | ||
1131 | val = (vdev->host_features & ~vdc->legacy_features) >> | |
5f456073 | 1132 | (32 * proxy->dfselect); |
dfb8e184 MT |
1133 | } |
1134 | break; | |
1135 | case VIRTIO_PCI_COMMON_GFSELECT: | |
1136 | val = proxy->gfselect; | |
1137 | break; | |
1138 | case VIRTIO_PCI_COMMON_GF: | |
3750dabc | 1139 | if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) { |
dfb8e184 MT |
1140 | val = proxy->guest_features[proxy->gfselect]; |
1141 | } | |
1142 | break; | |
1143 | case VIRTIO_PCI_COMMON_MSIX: | |
1144 | val = vdev->config_vector; | |
1145 | break; | |
1146 | case VIRTIO_PCI_COMMON_NUMQ: | |
1147 | for (i = 0; i < VIRTIO_QUEUE_MAX; ++i) { | |
1148 | if (virtio_queue_get_num(vdev, i)) { | |
1149 | val = i + 1; | |
1150 | } | |
1151 | } | |
1152 | break; | |
1153 | case VIRTIO_PCI_COMMON_STATUS: | |
1154 | val = vdev->status; | |
1155 | break; | |
1156 | case VIRTIO_PCI_COMMON_CFGGENERATION: | |
b8f05908 | 1157 | val = vdev->generation; |
dfb8e184 MT |
1158 | break; |
1159 | case VIRTIO_PCI_COMMON_Q_SELECT: | |
1160 | val = vdev->queue_sel; | |
1161 | break; | |
1162 | case VIRTIO_PCI_COMMON_Q_SIZE: | |
1163 | val = virtio_queue_get_num(vdev, vdev->queue_sel); | |
1164 | break; | |
1165 | case VIRTIO_PCI_COMMON_Q_MSIX: | |
1166 | val = virtio_queue_vector(vdev, vdev->queue_sel); | |
1167 | break; | |
1168 | case VIRTIO_PCI_COMMON_Q_ENABLE: | |
1169 | val = proxy->vqs[vdev->queue_sel].enabled; | |
1170 | break; | |
1171 | case VIRTIO_PCI_COMMON_Q_NOFF: | |
1172 | /* Simply map queues in order */ | |
1173 | val = vdev->queue_sel; | |
1174 | break; | |
1175 | case VIRTIO_PCI_COMMON_Q_DESCLO: | |
1176 | val = proxy->vqs[vdev->queue_sel].desc[0]; | |
1177 | break; | |
1178 | case VIRTIO_PCI_COMMON_Q_DESCHI: | |
1179 | val = proxy->vqs[vdev->queue_sel].desc[1]; | |
1180 | break; | |
1181 | case VIRTIO_PCI_COMMON_Q_AVAILLO: | |
1182 | val = proxy->vqs[vdev->queue_sel].avail[0]; | |
1183 | break; | |
1184 | case VIRTIO_PCI_COMMON_Q_AVAILHI: | |
1185 | val = proxy->vqs[vdev->queue_sel].avail[1]; | |
1186 | break; | |
1187 | case VIRTIO_PCI_COMMON_Q_USEDLO: | |
1188 | val = proxy->vqs[vdev->queue_sel].used[0]; | |
1189 | break; | |
1190 | case VIRTIO_PCI_COMMON_Q_USEDHI: | |
1191 | val = proxy->vqs[vdev->queue_sel].used[1]; | |
1192 | break; | |
1193 | default: | |
1194 | val = 0; | |
1195 | } | |
1196 | ||
1197 | return val; | |
1198 | } | |
1199 | ||
1200 | static void virtio_pci_common_write(void *opaque, hwaddr addr, | |
1201 | uint64_t val, unsigned size) | |
1202 | { | |
1203 | VirtIOPCIProxy *proxy = opaque; | |
1204 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); | |
1205 | ||
1206 | switch (addr) { | |
1207 | case VIRTIO_PCI_COMMON_DFSELECT: | |
1208 | proxy->dfselect = val; | |
1209 | break; | |
1210 | case VIRTIO_PCI_COMMON_GFSELECT: | |
1211 | proxy->gfselect = val; | |
1212 | break; | |
1213 | case VIRTIO_PCI_COMMON_GF: | |
3750dabc | 1214 | if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) { |
dfb8e184 MT |
1215 | proxy->guest_features[proxy->gfselect] = val; |
1216 | virtio_set_features(vdev, | |
1217 | (((uint64_t)proxy->guest_features[1]) << 32) | | |
1218 | proxy->guest_features[0]); | |
1219 | } | |
1220 | break; | |
1221 | case VIRTIO_PCI_COMMON_MSIX: | |
1222 | msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); | |
1223 | /* Make it possible for guest to discover an error took place. */ | |
1224 | if (msix_vector_use(&proxy->pci_dev, val) < 0) { | |
1225 | val = VIRTIO_NO_VECTOR; | |
1226 | } | |
1227 | vdev->config_vector = val; | |
1228 | break; | |
1229 | case VIRTIO_PCI_COMMON_STATUS: | |
1230 | if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) { | |
1231 | virtio_pci_stop_ioeventfd(proxy); | |
1232 | } | |
1233 | ||
1234 | virtio_set_status(vdev, val & 0xFF); | |
1235 | ||
1236 | if (val & VIRTIO_CONFIG_S_DRIVER_OK) { | |
1237 | virtio_pci_start_ioeventfd(proxy); | |
1238 | } | |
1239 | ||
1240 | if (vdev->status == 0) { | |
75fd6f13 | 1241 | virtio_pci_reset(DEVICE(proxy)); |
dfb8e184 MT |
1242 | } |
1243 | ||
1244 | break; | |
1245 | case VIRTIO_PCI_COMMON_Q_SELECT: | |
1246 | if (val < VIRTIO_QUEUE_MAX) { | |
1247 | vdev->queue_sel = val; | |
1248 | } | |
1249 | break; | |
1250 | case VIRTIO_PCI_COMMON_Q_SIZE: | |
1251 | proxy->vqs[vdev->queue_sel].num = val; | |
1252 | break; | |
1253 | case VIRTIO_PCI_COMMON_Q_MSIX: | |
1254 | msix_vector_unuse(&proxy->pci_dev, | |
1255 | virtio_queue_vector(vdev, vdev->queue_sel)); | |
1256 | /* Make it possible for guest to discover an error took place. */ | |
1257 | if (msix_vector_use(&proxy->pci_dev, val) < 0) { | |
1258 | val = VIRTIO_NO_VECTOR; | |
1259 | } | |
1260 | virtio_queue_set_vector(vdev, vdev->queue_sel, val); | |
1261 | break; | |
1262 | case VIRTIO_PCI_COMMON_Q_ENABLE: | |
dfb8e184 MT |
1263 | virtio_queue_set_num(vdev, vdev->queue_sel, |
1264 | proxy->vqs[vdev->queue_sel].num); | |
1265 | virtio_queue_set_rings(vdev, vdev->queue_sel, | |
1266 | ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 | | |
1267 | proxy->vqs[vdev->queue_sel].desc[0], | |
1268 | ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 | | |
1269 | proxy->vqs[vdev->queue_sel].avail[0], | |
1270 | ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 | | |
1271 | proxy->vqs[vdev->queue_sel].used[0]); | |
393f04d3 | 1272 | proxy->vqs[vdev->queue_sel].enabled = 1; |
dfb8e184 MT |
1273 | break; |
1274 | case VIRTIO_PCI_COMMON_Q_DESCLO: | |
1275 | proxy->vqs[vdev->queue_sel].desc[0] = val; | |
1276 | break; | |
1277 | case VIRTIO_PCI_COMMON_Q_DESCHI: | |
1278 | proxy->vqs[vdev->queue_sel].desc[1] = val; | |
1279 | break; | |
1280 | case VIRTIO_PCI_COMMON_Q_AVAILLO: | |
1281 | proxy->vqs[vdev->queue_sel].avail[0] = val; | |
1282 | break; | |
1283 | case VIRTIO_PCI_COMMON_Q_AVAILHI: | |
1284 | proxy->vqs[vdev->queue_sel].avail[1] = val; | |
1285 | break; | |
1286 | case VIRTIO_PCI_COMMON_Q_USEDLO: | |
1287 | proxy->vqs[vdev->queue_sel].used[0] = val; | |
1288 | break; | |
1289 | case VIRTIO_PCI_COMMON_Q_USEDHI: | |
1290 | proxy->vqs[vdev->queue_sel].used[1] = val; | |
1291 | break; | |
1292 | default: | |
1293 | break; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | ||
1298 | static uint64_t virtio_pci_notify_read(void *opaque, hwaddr addr, | |
1299 | unsigned size) | |
1300 | { | |
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static void virtio_pci_notify_write(void *opaque, hwaddr addr, | |
1305 | uint64_t val, unsigned size) | |
1306 | { | |
1307 | VirtIODevice *vdev = opaque; | |
d9997d89 MA |
1308 | VirtIOPCIProxy *proxy = VIRTIO_PCI(DEVICE(vdev)->parent_bus->parent); |
1309 | unsigned queue = addr / virtio_pci_queue_mem_mult(proxy); | |
dfb8e184 MT |
1310 | |
1311 | if (queue < VIRTIO_QUEUE_MAX) { | |
1312 | virtio_queue_notify(vdev, queue); | |
1313 | } | |
1314 | } | |
1315 | ||
9824d2a3 JW |
1316 | static void virtio_pci_notify_write_pio(void *opaque, hwaddr addr, |
1317 | uint64_t val, unsigned size) | |
1318 | { | |
1319 | VirtIODevice *vdev = opaque; | |
1320 | unsigned queue = val; | |
1321 | ||
1322 | if (queue < VIRTIO_QUEUE_MAX) { | |
1323 | virtio_queue_notify(vdev, queue); | |
1324 | } | |
1325 | } | |
1326 | ||
dfb8e184 MT |
1327 | static uint64_t virtio_pci_isr_read(void *opaque, hwaddr addr, |
1328 | unsigned size) | |
1329 | { | |
1330 | VirtIOPCIProxy *proxy = opaque; | |
1331 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); | |
0687c37c | 1332 | uint64_t val = atomic_xchg(&vdev->isr, 0); |
dfb8e184 MT |
1333 | pci_irq_deassert(&proxy->pci_dev); |
1334 | ||
1335 | return val; | |
1336 | } | |
1337 | ||
1338 | static void virtio_pci_isr_write(void *opaque, hwaddr addr, | |
1339 | uint64_t val, unsigned size) | |
1340 | { | |
1341 | } | |
1342 | ||
1343 | static uint64_t virtio_pci_device_read(void *opaque, hwaddr addr, | |
1344 | unsigned size) | |
1345 | { | |
1346 | VirtIODevice *vdev = opaque; | |
1347 | uint64_t val = 0; | |
1348 | ||
1349 | switch (size) { | |
1350 | case 1: | |
54c720d4 | 1351 | val = virtio_config_modern_readb(vdev, addr); |
dfb8e184 MT |
1352 | break; |
1353 | case 2: | |
54c720d4 | 1354 | val = virtio_config_modern_readw(vdev, addr); |
dfb8e184 MT |
1355 | break; |
1356 | case 4: | |
54c720d4 | 1357 | val = virtio_config_modern_readl(vdev, addr); |
dfb8e184 MT |
1358 | break; |
1359 | } | |
1360 | return val; | |
1361 | } | |
1362 | ||
1363 | static void virtio_pci_device_write(void *opaque, hwaddr addr, | |
1364 | uint64_t val, unsigned size) | |
1365 | { | |
1366 | VirtIODevice *vdev = opaque; | |
1367 | switch (size) { | |
1368 | case 1: | |
54c720d4 | 1369 | virtio_config_modern_writeb(vdev, addr, val); |
dfb8e184 MT |
1370 | break; |
1371 | case 2: | |
54c720d4 | 1372 | virtio_config_modern_writew(vdev, addr, val); |
dfb8e184 MT |
1373 | break; |
1374 | case 4: | |
54c720d4 | 1375 | virtio_config_modern_writel(vdev, addr, val); |
dfb8e184 MT |
1376 | break; |
1377 | } | |
1378 | } | |
1379 | ||
1141ce21 GH |
1380 | static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy) |
1381 | { | |
1382 | static const MemoryRegionOps common_ops = { | |
1383 | .read = virtio_pci_common_read, | |
1384 | .write = virtio_pci_common_write, | |
1385 | .impl = { | |
1386 | .min_access_size = 1, | |
1387 | .max_access_size = 4, | |
1388 | }, | |
1389 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1390 | }; | |
1391 | static const MemoryRegionOps isr_ops = { | |
1392 | .read = virtio_pci_isr_read, | |
1393 | .write = virtio_pci_isr_write, | |
1394 | .impl = { | |
1395 | .min_access_size = 1, | |
1396 | .max_access_size = 4, | |
1397 | }, | |
1398 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1399 | }; | |
1400 | static const MemoryRegionOps device_ops = { | |
1401 | .read = virtio_pci_device_read, | |
1402 | .write = virtio_pci_device_write, | |
1403 | .impl = { | |
1404 | .min_access_size = 1, | |
1405 | .max_access_size = 4, | |
1406 | }, | |
1407 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1408 | }; | |
1409 | static const MemoryRegionOps notify_ops = { | |
1410 | .read = virtio_pci_notify_read, | |
1411 | .write = virtio_pci_notify_write, | |
1412 | .impl = { | |
1413 | .min_access_size = 1, | |
1414 | .max_access_size = 4, | |
1415 | }, | |
1416 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1417 | }; | |
9824d2a3 JW |
1418 | static const MemoryRegionOps notify_pio_ops = { |
1419 | .read = virtio_pci_notify_read, | |
1420 | .write = virtio_pci_notify_write_pio, | |
1421 | .impl = { | |
1422 | .min_access_size = 1, | |
1423 | .max_access_size = 4, | |
1424 | }, | |
1425 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1426 | }; | |
1427 | ||
1141ce21 GH |
1428 | |
1429 | memory_region_init_io(&proxy->common.mr, OBJECT(proxy), | |
1430 | &common_ops, | |
1431 | proxy, | |
b6ce27a5 GH |
1432 | "virtio-pci-common", |
1433 | proxy->common.size); | |
a3cc2e81 | 1434 | |
1141ce21 GH |
1435 | memory_region_init_io(&proxy->isr.mr, OBJECT(proxy), |
1436 | &isr_ops, | |
1437 | proxy, | |
b6ce27a5 GH |
1438 | "virtio-pci-isr", |
1439 | proxy->isr.size); | |
a3cc2e81 | 1440 | |
1141ce21 GH |
1441 | memory_region_init_io(&proxy->device.mr, OBJECT(proxy), |
1442 | &device_ops, | |
1443 | virtio_bus_get_device(&proxy->bus), | |
b6ce27a5 GH |
1444 | "virtio-pci-device", |
1445 | proxy->device.size); | |
a3cc2e81 | 1446 | |
1141ce21 GH |
1447 | memory_region_init_io(&proxy->notify.mr, OBJECT(proxy), |
1448 | ¬ify_ops, | |
1449 | virtio_bus_get_device(&proxy->bus), | |
1450 | "virtio-pci-notify", | |
b6ce27a5 | 1451 | proxy->notify.size); |
9824d2a3 JW |
1452 | |
1453 | memory_region_init_io(&proxy->notify_pio.mr, OBJECT(proxy), | |
1454 | ¬ify_pio_ops, | |
1455 | virtio_bus_get_device(&proxy->bus), | |
1456 | "virtio-pci-notify-pio", | |
e3aab6c7 | 1457 | proxy->notify_pio.size); |
a3cc2e81 GH |
1458 | } |
1459 | ||
1460 | static void virtio_pci_modern_region_map(VirtIOPCIProxy *proxy, | |
54790d71 | 1461 | VirtIOPCIRegion *region, |
9824d2a3 JW |
1462 | struct virtio_pci_cap *cap, |
1463 | MemoryRegion *mr, | |
1464 | uint8_t bar) | |
a3cc2e81 | 1465 | { |
9824d2a3 | 1466 | memory_region_add_subregion(mr, region->offset, ®ion->mr); |
54790d71 | 1467 | |
fc004905 | 1468 | cap->cfg_type = region->type; |
9824d2a3 | 1469 | cap->bar = bar; |
54790d71 | 1470 | cap->offset = cpu_to_le32(region->offset); |
b6ce27a5 | 1471 | cap->length = cpu_to_le32(region->size); |
54790d71 | 1472 | virtio_pci_add_mem_cap(proxy, cap); |
9824d2a3 JW |
1473 | |
1474 | } | |
1475 | ||
1476 | static void virtio_pci_modern_mem_region_map(VirtIOPCIProxy *proxy, | |
1477 | VirtIOPCIRegion *region, | |
1478 | struct virtio_pci_cap *cap) | |
1479 | { | |
1480 | virtio_pci_modern_region_map(proxy, region, cap, | |
7a25126d | 1481 | &proxy->modern_bar, proxy->modern_mem_bar_idx); |
1141ce21 | 1482 | } |
dfb8e184 | 1483 | |
9824d2a3 JW |
1484 | static void virtio_pci_modern_io_region_map(VirtIOPCIProxy *proxy, |
1485 | VirtIOPCIRegion *region, | |
1486 | struct virtio_pci_cap *cap) | |
1487 | { | |
1488 | virtio_pci_modern_region_map(proxy, region, cap, | |
7a25126d | 1489 | &proxy->io_bar, proxy->modern_io_bar_idx); |
9824d2a3 JW |
1490 | } |
1491 | ||
1492 | static void virtio_pci_modern_mem_region_unmap(VirtIOPCIProxy *proxy, | |
1493 | VirtIOPCIRegion *region) | |
27462695 MT |
1494 | { |
1495 | memory_region_del_subregion(&proxy->modern_bar, | |
1496 | ®ion->mr); | |
1497 | } | |
1498 | ||
9824d2a3 JW |
1499 | static void virtio_pci_modern_io_region_unmap(VirtIOPCIProxy *proxy, |
1500 | VirtIOPCIRegion *region) | |
1501 | { | |
1502 | memory_region_del_subregion(&proxy->io_bar, | |
1503 | ®ion->mr); | |
1504 | } | |
1505 | ||
d1b4259f MC |
1506 | static void virtio_pci_pre_plugged(DeviceState *d, Error **errp) |
1507 | { | |
1508 | VirtIOPCIProxy *proxy = VIRTIO_PCI(d); | |
1509 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); | |
1510 | ||
1511 | if (virtio_pci_modern(proxy)) { | |
1512 | virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1); | |
1513 | } | |
1514 | ||
1515 | virtio_add_feature(&vdev->host_features, VIRTIO_F_BAD_FEATURE); | |
1516 | } | |
1517 | ||
085bccb7 | 1518 | /* This is called by virtio-bus just after the device is plugged. */ |
e8398045 | 1519 | static void virtio_pci_device_plugged(DeviceState *d, Error **errp) |
085bccb7 FK |
1520 | { |
1521 | VirtIOPCIProxy *proxy = VIRTIO_PCI(d); | |
1522 | VirtioBusState *bus = &proxy->bus; | |
9a4c0e22 | 1523 | bool legacy = virtio_pci_legacy(proxy); |
d1b4259f | 1524 | bool modern; |
9824d2a3 | 1525 | bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY; |
085bccb7 FK |
1526 | uint8_t *config; |
1527 | uint32_t size; | |
6b8f1020 | 1528 | VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); |
085bccb7 | 1529 | |
d1b4259f MC |
1530 | /* |
1531 | * Virtio capabilities present without | |
1532 | * VIRTIO_F_VERSION_1 confuses guests | |
1533 | */ | |
66d1c4c1 MC |
1534 | if (!proxy->ignore_backend_features && |
1535 | !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) { | |
d1b4259f MC |
1536 | virtio_pci_disable_modern(proxy); |
1537 | ||
1538 | if (!legacy) { | |
1539 | error_setg(errp, "Device doesn't support modern mode, and legacy" | |
1540 | " mode is disabled"); | |
1541 | error_append_hint(errp, "Set disable-legacy to off\n"); | |
1542 | ||
1543 | return; | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | modern = virtio_pci_modern(proxy); | |
1548 | ||
085bccb7 FK |
1549 | config = proxy->pci_dev.config; |
1550 | if (proxy->class_code) { | |
1551 | pci_config_set_class(config, proxy->class_code); | |
1552 | } | |
e266d421 GH |
1553 | |
1554 | if (legacy) { | |
8607f5c3 JW |
1555 | if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) { |
1556 | error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by" | |
2080a29f | 1557 | " neither legacy nor transitional device"); |
8607f5c3 JW |
1558 | return ; |
1559 | } | |
f2bc54de LP |
1560 | /* |
1561 | * Legacy and transitional devices use specific subsystem IDs. | |
1562 | * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID) | |
1563 | * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default. | |
1564 | */ | |
e266d421 GH |
1565 | pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus)); |
1566 | } else { | |
1567 | /* pure virtio-1.0 */ | |
1568 | pci_set_word(config + PCI_VENDOR_ID, | |
1569 | PCI_VENDOR_ID_REDHAT_QUMRANET); | |
1570 | pci_set_word(config + PCI_DEVICE_ID, | |
1571 | 0x1040 + virtio_bus_get_vdev_id(bus)); | |
1572 | pci_config_set_revision(config, 1); | |
1573 | } | |
085bccb7 FK |
1574 | config[PCI_INTERRUPT_PIN] = 1; |
1575 | ||
dfb8e184 | 1576 | |
e266d421 | 1577 | if (modern) { |
cc52ea90 GH |
1578 | struct virtio_pci_cap cap = { |
1579 | .cap_len = sizeof cap, | |
dfb8e184 MT |
1580 | }; |
1581 | struct virtio_pci_notify_cap notify = { | |
dfb8e184 | 1582 | .cap.cap_len = sizeof notify, |
dfb8e184 | 1583 | .notify_off_multiplier = |
d9997d89 | 1584 | cpu_to_le32(virtio_pci_queue_mem_mult(proxy)), |
dfb8e184 | 1585 | }; |
ada434cd MT |
1586 | struct virtio_pci_cfg_cap cfg = { |
1587 | .cap.cap_len = sizeof cfg, | |
1588 | .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG, | |
1589 | }; | |
9824d2a3 JW |
1590 | struct virtio_pci_notify_cap notify_pio = { |
1591 | .cap.cap_len = sizeof notify, | |
1592 | .notify_off_multiplier = cpu_to_le32(0x0), | |
1593 | }; | |
dfb8e184 | 1594 | |
9824d2a3 | 1595 | struct virtio_pci_cfg_cap *cfg_mask; |
dfb8e184 | 1596 | |
1141ce21 | 1597 | virtio_pci_modern_regions_init(proxy); |
9824d2a3 JW |
1598 | |
1599 | virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap); | |
1600 | virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap); | |
1601 | virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap); | |
1602 | virtio_pci_modern_mem_region_map(proxy, &proxy->notify, ¬ify.cap); | |
1603 | ||
1604 | if (modern_pio) { | |
1605 | memory_region_init(&proxy->io_bar, OBJECT(proxy), | |
1606 | "virtio-pci-io", 0x4); | |
1607 | ||
7a25126d | 1608 | pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx, |
9824d2a3 JW |
1609 | PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar); |
1610 | ||
1611 | virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio, | |
1612 | ¬ify_pio.cap); | |
1613 | } | |
ada434cd | 1614 | |
7a25126d | 1615 | pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx, |
4e93a68e GH |
1616 | PCI_BASE_ADDRESS_SPACE_MEMORY | |
1617 | PCI_BASE_ADDRESS_MEM_PREFETCH | | |
1618 | PCI_BASE_ADDRESS_MEM_TYPE_64, | |
dfb8e184 | 1619 | &proxy->modern_bar); |
ada434cd MT |
1620 | |
1621 | proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap); | |
1622 | cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap); | |
1623 | pci_set_byte(&cfg_mask->cap.bar, ~0x0); | |
1624 | pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0); | |
1625 | pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0); | |
1626 | pci_set_long(cfg_mask->pci_cfg_data, ~0x0); | |
dfb8e184 MT |
1627 | } |
1628 | ||
0d583647 RH |
1629 | if (proxy->nvectors) { |
1630 | int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors, | |
ee640c62 | 1631 | proxy->msix_bar_idx, NULL); |
0d583647 | 1632 | if (err) { |
ee640c62 | 1633 | /* Notice when a system that supports MSIx can't initialize it */ |
0d583647 | 1634 | if (err != -ENOTSUP) { |
0765691e MA |
1635 | warn_report("unable to init msix vectors to %" PRIu32, |
1636 | proxy->nvectors); | |
0d583647 RH |
1637 | } |
1638 | proxy->nvectors = 0; | |
1639 | } | |
085bccb7 FK |
1640 | } |
1641 | ||
1642 | proxy->pci_dev.config_write = virtio_write_config; | |
ada434cd | 1643 | proxy->pci_dev.config_read = virtio_read_config; |
085bccb7 | 1644 | |
e266d421 GH |
1645 | if (legacy) { |
1646 | size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev) | |
1647 | + virtio_bus_get_vdev_config_len(bus); | |
1d0148fe | 1648 | size = pow2ceil(size); |
085bccb7 | 1649 | |
e266d421 GH |
1650 | memory_region_init_io(&proxy->bar, OBJECT(proxy), |
1651 | &virtio_pci_config_ops, | |
1652 | proxy, "virtio-pci", size); | |
dfb8e184 | 1653 | |
7a25126d | 1654 | pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx, |
23c5e397 | 1655 | PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar); |
e266d421 | 1656 | } |
085bccb7 FK |
1657 | } |
1658 | ||
06a13073 PB |
1659 | static void virtio_pci_device_unplugged(DeviceState *d) |
1660 | { | |
06a13073 | 1661 | VirtIOPCIProxy *proxy = VIRTIO_PCI(d); |
9a4c0e22 | 1662 | bool modern = virtio_pci_modern(proxy); |
9824d2a3 | 1663 | bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY; |
06a13073 PB |
1664 | |
1665 | virtio_pci_stop_ioeventfd(proxy); | |
27462695 MT |
1666 | |
1667 | if (modern) { | |
9824d2a3 JW |
1668 | virtio_pci_modern_mem_region_unmap(proxy, &proxy->common); |
1669 | virtio_pci_modern_mem_region_unmap(proxy, &proxy->isr); | |
1670 | virtio_pci_modern_mem_region_unmap(proxy, &proxy->device); | |
1671 | virtio_pci_modern_mem_region_unmap(proxy, &proxy->notify); | |
1672 | if (modern_pio) { | |
1673 | virtio_pci_modern_io_region_unmap(proxy, &proxy->notify_pio); | |
1674 | } | |
27462695 | 1675 | } |
06a13073 PB |
1676 | } |
1677 | ||
fc079951 | 1678 | static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) |
085bccb7 | 1679 | { |
b6ce27a5 | 1680 | VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev); |
085bccb7 | 1681 | VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev); |
fd56e061 DG |
1682 | bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) && |
1683 | !pci_bus_is_root(pci_get_bus(pci_dev)); | |
fc079951 | 1684 | |
c324fd0a | 1685 | if (kvm_enabled() && !kvm_has_many_ioeventfds()) { |
ca2b413c PB |
1686 | proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD; |
1687 | } | |
1688 | ||
b6ce27a5 GH |
1689 | /* |
1690 | * virtio pci bar layout used by default. | |
1691 | * subclasses can re-arrange things if needed. | |
1692 | * | |
1693 | * region 0 -- virtio legacy io bar | |
1694 | * region 1 -- msi-x bar | |
1695 | * region 4+5 -- virtio modern memory (64bit) bar | |
1696 | * | |
1697 | */ | |
7a25126d CF |
1698 | proxy->legacy_io_bar_idx = 0; |
1699 | proxy->msix_bar_idx = 1; | |
1700 | proxy->modern_io_bar_idx = 2; | |
1701 | proxy->modern_mem_bar_idx = 4; | |
b6ce27a5 GH |
1702 | |
1703 | proxy->common.offset = 0x0; | |
1704 | proxy->common.size = 0x1000; | |
1705 | proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG; | |
1706 | ||
1707 | proxy->isr.offset = 0x1000; | |
1708 | proxy->isr.size = 0x1000; | |
1709 | proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG; | |
1710 | ||
1711 | proxy->device.offset = 0x2000; | |
1712 | proxy->device.size = 0x1000; | |
1713 | proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG; | |
1714 | ||
1715 | proxy->notify.offset = 0x3000; | |
d9997d89 | 1716 | proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX; |
b6ce27a5 GH |
1717 | proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG; |
1718 | ||
9824d2a3 JW |
1719 | proxy->notify_pio.offset = 0x0; |
1720 | proxy->notify_pio.size = 0x4; | |
1721 | proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG; | |
1722 | ||
b6ce27a5 GH |
1723 | /* subclasses can enforce modern, so do this unconditionally */ |
1724 | memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci", | |
d9997d89 MA |
1725 | /* PCI BAR regions must be powers of 2 */ |
1726 | pow2ceil(proxy->notify.offset + proxy->notify.size)); | |
b6ce27a5 | 1727 | |
dd56040d DDAG |
1728 | if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) { |
1729 | proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | |
1730 | } | |
1731 | ||
1732 | if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) { | |
1733 | error_setg(errp, "device cannot work as neither modern nor legacy mode" | |
1734 | " is enabled"); | |
1735 | error_append_hint(errp, "Set either disable-modern or disable-legacy" | |
1736 | " to off\n"); | |
1737 | return; | |
3eff3769 GK |
1738 | } |
1739 | ||
9a4c0e22 | 1740 | if (pcie_port && pci_is_express(pci_dev)) { |
1811e64c MA |
1741 | int pos; |
1742 | ||
1811e64c MA |
1743 | pos = pcie_endpoint_cap_init(pci_dev, 0); |
1744 | assert(pos > 0); | |
1745 | ||
9a7c2a59 MZ |
1746 | pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, |
1747 | PCI_PM_SIZEOF, errp); | |
1748 | if (pos < 0) { | |
1749 | return; | |
1750 | } | |
1751 | ||
27ce0f3a | 1752 | pci_dev->exp.pm_cap = pos; |
1811e64c MA |
1753 | |
1754 | /* | |
1755 | * Indicates that this function complies with revision 1.2 of the | |
1756 | * PCI Power Management Interface Specification. | |
1757 | */ | |
1758 | pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3); | |
615c4ed2 | 1759 | |
c2cabb34 MA |
1760 | if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) { |
1761 | /* Init error enabling flags */ | |
1762 | pcie_cap_deverr_init(pci_dev); | |
1763 | } | |
1764 | ||
d584f1b9 MA |
1765 | if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) { |
1766 | /* Init Link Control Register */ | |
1767 | pcie_cap_lnkctl_init(pci_dev); | |
1768 | } | |
1769 | ||
27ce0f3a MA |
1770 | if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) { |
1771 | /* Init Power Management Control Register */ | |
1772 | pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL, | |
1773 | PCI_PM_CTRL_STATE_MASK); | |
1774 | } | |
1775 | ||
615c4ed2 JW |
1776 | if (proxy->flags & VIRTIO_PCI_FLAG_ATS) { |
1777 | pcie_ats_init(pci_dev, 256); | |
1778 | } | |
1779 | ||
0560b0e9 SL |
1780 | } else { |
1781 | /* | |
1782 | * make future invocations of pci_is_express() return false | |
1783 | * and pci_config_size() return PCI_CONFIG_SPACE_SIZE. | |
1784 | */ | |
1785 | pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS; | |
1811e64c MA |
1786 | } |
1787 | ||
b6ce27a5 | 1788 | virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy); |
fc079951 | 1789 | if (k->realize) { |
b6ce27a5 | 1790 | k->realize(proxy, errp); |
085bccb7 | 1791 | } |
085bccb7 FK |
1792 | } |
1793 | ||
1794 | static void virtio_pci_exit(PCIDevice *pci_dev) | |
1795 | { | |
8b81bb3b | 1796 | msix_uninit_exclusive_bar(pci_dev); |
085bccb7 FK |
1797 | } |
1798 | ||
59ccd20a | 1799 | static void virtio_pci_reset(DeviceState *qdev) |
085bccb7 FK |
1800 | { |
1801 | VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev); | |
1802 | VirtioBusState *bus = VIRTIO_BUS(&proxy->bus); | |
c2cabb34 | 1803 | PCIDevice *dev = PCI_DEVICE(qdev); |
393f04d3 JW |
1804 | int i; |
1805 | ||
085bccb7 FK |
1806 | virtio_pci_stop_ioeventfd(proxy); |
1807 | virtio_bus_reset(bus); | |
1808 | msix_unuse_all_vectors(&proxy->pci_dev); | |
393f04d3 JW |
1809 | |
1810 | for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { | |
1811 | proxy->vqs[i].enabled = 0; | |
60a8d802 JW |
1812 | proxy->vqs[i].num = 0; |
1813 | proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0; | |
1814 | proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0; | |
1815 | proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0; | |
393f04d3 | 1816 | } |
c2cabb34 MA |
1817 | |
1818 | if (pci_is_express(dev)) { | |
1819 | pcie_cap_deverr_reset(dev); | |
d584f1b9 | 1820 | pcie_cap_lnkctl_reset(dev); |
27ce0f3a MA |
1821 | |
1822 | pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0); | |
c2cabb34 | 1823 | } |
085bccb7 FK |
1824 | } |
1825 | ||
85d1277e | 1826 | static Property virtio_pci_properties[] = { |
68a27b20 MT |
1827 | DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags, |
1828 | VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false), | |
a6df8adf JW |
1829 | DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags, |
1830 | VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true), | |
9824d2a3 JW |
1831 | DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags, |
1832 | VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false), | |
1811e64c MA |
1833 | DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags, |
1834 | VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false), | |
d9997d89 MA |
1835 | DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags, |
1836 | VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false), | |
66d1c4c1 MC |
1837 | DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy, |
1838 | ignore_backend_features, false), | |
615c4ed2 JW |
1839 | DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags, |
1840 | VIRTIO_PCI_FLAG_ATS_BIT, false), | |
c2cabb34 MA |
1841 | DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags, |
1842 | VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true), | |
d584f1b9 MA |
1843 | DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags, |
1844 | VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), | |
27ce0f3a MA |
1845 | DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, |
1846 | VIRTIO_PCI_FLAG_INIT_PM_BIT, true), | |
85d1277e ML |
1847 | DEFINE_PROP_END_OF_LIST(), |
1848 | }; | |
1849 | ||
0560b0e9 SL |
1850 | static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp) |
1851 | { | |
1852 | VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev); | |
1853 | VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev); | |
1854 | PCIDevice *pci_dev = &proxy->pci_dev; | |
1855 | ||
1856 | if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) && | |
9a4c0e22 | 1857 | virtio_pci_modern(proxy)) { |
0560b0e9 SL |
1858 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1859 | } | |
1860 | ||
1861 | vpciklass->parent_dc_realize(qdev, errp); | |
1862 | } | |
1863 | ||
085bccb7 FK |
1864 | static void virtio_pci_class_init(ObjectClass *klass, void *data) |
1865 | { | |
1866 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1867 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
0560b0e9 | 1868 | VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass); |
085bccb7 | 1869 | |
85d1277e | 1870 | dc->props = virtio_pci_properties; |
fc079951 | 1871 | k->realize = virtio_pci_realize; |
085bccb7 FK |
1872 | k->exit = virtio_pci_exit; |
1873 | k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; | |
1874 | k->revision = VIRTIO_PCI_ABI_VERSION; | |
1875 | k->class_id = PCI_CLASS_OTHERS; | |
bf853881 PMD |
1876 | device_class_set_parent_realize(dc, virtio_pci_dc_realize, |
1877 | &vpciklass->parent_dc_realize); | |
59ccd20a | 1878 | dc->reset = virtio_pci_reset; |
085bccb7 FK |
1879 | } |
1880 | ||
1881 | static const TypeInfo virtio_pci_info = { | |
1882 | .name = TYPE_VIRTIO_PCI, | |
1883 | .parent = TYPE_PCI_DEVICE, | |
1884 | .instance_size = sizeof(VirtIOPCIProxy), | |
1885 | .class_init = virtio_pci_class_init, | |
1886 | .class_size = sizeof(VirtioPCIClass), | |
1887 | .abstract = true, | |
1888 | }; | |
1889 | ||
a4ee4c8b EH |
1890 | static Property virtio_pci_generic_properties[] = { |
1891 | DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy, | |
1892 | ON_OFF_AUTO_AUTO), | |
1893 | DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false), | |
1894 | DEFINE_PROP_END_OF_LIST(), | |
1895 | }; | |
1896 | ||
1897 | static void virtio_pci_base_class_init(ObjectClass *klass, void *data) | |
1898 | { | |
1899 | const VirtioPCIDeviceTypeInfo *t = data; | |
1900 | if (t->class_init) { | |
1901 | t->class_init(klass, NULL); | |
1902 | } | |
1903 | } | |
1904 | ||
1905 | static void virtio_pci_generic_class_init(ObjectClass *klass, void *data) | |
1906 | { | |
1907 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1908 | ||
1909 | dc->props = virtio_pci_generic_properties; | |
1910 | } | |
1911 | ||
a4ee4c8b EH |
1912 | static void virtio_pci_transitional_instance_init(Object *obj) |
1913 | { | |
1914 | VirtIOPCIProxy *proxy = VIRTIO_PCI(obj); | |
1915 | ||
1916 | proxy->disable_legacy = ON_OFF_AUTO_OFF; | |
1917 | proxy->disable_modern = false; | |
1918 | } | |
1919 | ||
1920 | static void virtio_pci_non_transitional_instance_init(Object *obj) | |
1921 | { | |
1922 | VirtIOPCIProxy *proxy = VIRTIO_PCI(obj); | |
1923 | ||
1924 | proxy->disable_legacy = ON_OFF_AUTO_ON; | |
1925 | proxy->disable_modern = false; | |
1926 | } | |
1927 | ||
1928 | void virtio_pci_types_register(const VirtioPCIDeviceTypeInfo *t) | |
1929 | { | |
683c1d89 | 1930 | char *base_name = NULL; |
a4ee4c8b EH |
1931 | TypeInfo base_type_info = { |
1932 | .name = t->base_name, | |
1933 | .parent = t->parent ? t->parent : TYPE_VIRTIO_PCI, | |
1934 | .instance_size = t->instance_size, | |
1935 | .instance_init = t->instance_init, | |
8ea90ee6 | 1936 | .class_size = t->class_size, |
a4ee4c8b | 1937 | .abstract = true, |
1e33b513 | 1938 | .interfaces = t->interfaces, |
a4ee4c8b EH |
1939 | }; |
1940 | TypeInfo generic_type_info = { | |
1941 | .name = t->generic_name, | |
1942 | .parent = base_type_info.name, | |
1943 | .class_init = virtio_pci_generic_class_init, | |
1944 | .interfaces = (InterfaceInfo[]) { | |
1945 | { INTERFACE_PCIE_DEVICE }, | |
1946 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1947 | { } | |
1948 | }, | |
1949 | }; | |
1950 | ||
1951 | if (!base_type_info.name) { | |
1952 | /* No base type -> register a single generic device type */ | |
683c1d89 MAL |
1953 | /* use intermediate %s-base-type to add generic device props */ |
1954 | base_name = g_strdup_printf("%s-base-type", t->generic_name); | |
1955 | base_type_info.name = base_name; | |
1956 | base_type_info.class_init = virtio_pci_generic_class_init; | |
1957 | ||
1958 | generic_type_info.parent = base_name; | |
1959 | generic_type_info.class_init = virtio_pci_base_class_init; | |
1960 | generic_type_info.class_data = (void *)t; | |
1961 | ||
a4ee4c8b EH |
1962 | assert(!t->non_transitional_name); |
1963 | assert(!t->transitional_name); | |
683c1d89 MAL |
1964 | } else { |
1965 | base_type_info.class_init = virtio_pci_base_class_init; | |
1966 | base_type_info.class_data = (void *)t; | |
a4ee4c8b EH |
1967 | } |
1968 | ||
1969 | type_register(&base_type_info); | |
1970 | if (generic_type_info.name) { | |
1971 | type_register(&generic_type_info); | |
1972 | } | |
1973 | ||
1974 | if (t->non_transitional_name) { | |
1975 | const TypeInfo non_transitional_type_info = { | |
1976 | .name = t->non_transitional_name, | |
1977 | .parent = base_type_info.name, | |
1978 | .instance_init = virtio_pci_non_transitional_instance_init, | |
1979 | .interfaces = (InterfaceInfo[]) { | |
1980 | { INTERFACE_PCIE_DEVICE }, | |
1981 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1982 | { } | |
1983 | }, | |
1984 | }; | |
1985 | type_register(&non_transitional_type_info); | |
1986 | } | |
1987 | ||
1988 | if (t->transitional_name) { | |
1989 | const TypeInfo transitional_type_info = { | |
1990 | .name = t->transitional_name, | |
1991 | .parent = base_type_info.name, | |
1992 | .instance_init = virtio_pci_transitional_instance_init, | |
1993 | .interfaces = (InterfaceInfo[]) { | |
1994 | /* | |
1995 | * Transitional virtio devices work only as Conventional PCI | |
1996 | * devices because they require PIO ports. | |
1997 | */ | |
1998 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1999 | { } | |
2000 | }, | |
2001 | }; | |
2002 | type_register(&transitional_type_info); | |
2003 | } | |
683c1d89 | 2004 | g_free(base_name); |
a4ee4c8b EH |
2005 | } |
2006 | ||
0a2acf5e FK |
2007 | /* virtio-pci-bus */ |
2008 | ||
ac7af112 AF |
2009 | static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size, |
2010 | VirtIOPCIProxy *dev) | |
0a2acf5e FK |
2011 | { |
2012 | DeviceState *qdev = DEVICE(dev); | |
f4dd69aa FK |
2013 | char virtio_bus_name[] = "virtio-bus"; |
2014 | ||
fb17dfe0 | 2015 | qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, |
f4dd69aa | 2016 | virtio_bus_name); |
0a2acf5e FK |
2017 | } |
2018 | ||
2019 | static void virtio_pci_bus_class_init(ObjectClass *klass, void *data) | |
2020 | { | |
2021 | BusClass *bus_class = BUS_CLASS(klass); | |
2022 | VirtioBusClass *k = VIRTIO_BUS_CLASS(klass); | |
2023 | bus_class->max_dev = 1; | |
2024 | k->notify = virtio_pci_notify; | |
2025 | k->save_config = virtio_pci_save_config; | |
2026 | k->load_config = virtio_pci_load_config; | |
2027 | k->save_queue = virtio_pci_save_queue; | |
2028 | k->load_queue = virtio_pci_load_queue; | |
a6df8adf JW |
2029 | k->save_extra_state = virtio_pci_save_extra_state; |
2030 | k->load_extra_state = virtio_pci_load_extra_state; | |
2031 | k->has_extra_state = virtio_pci_has_extra_state; | |
0a2acf5e | 2032 | k->query_guest_notifiers = virtio_pci_query_guest_notifiers; |
0a2acf5e | 2033 | k->set_guest_notifiers = virtio_pci_set_guest_notifiers; |
6f80e617 | 2034 | k->set_host_notifier_mr = virtio_pci_set_host_notifier_mr; |
0a2acf5e | 2035 | k->vmstate_change = virtio_pci_vmstate_change; |
d1b4259f | 2036 | k->pre_plugged = virtio_pci_pre_plugged; |
085bccb7 | 2037 | k->device_plugged = virtio_pci_device_plugged; |
06a13073 | 2038 | k->device_unplugged = virtio_pci_device_unplugged; |
e0d686bf | 2039 | k->query_nvectors = virtio_pci_query_nvectors; |
8e93cef1 | 2040 | k->ioeventfd_enabled = virtio_pci_ioeventfd_enabled; |
9f06e71a | 2041 | k->ioeventfd_assign = virtio_pci_ioeventfd_assign; |
8607f5c3 | 2042 | k->get_dma_as = virtio_pci_get_dma_as; |
0a2acf5e FK |
2043 | } |
2044 | ||
2045 | static const TypeInfo virtio_pci_bus_info = { | |
2046 | .name = TYPE_VIRTIO_PCI_BUS, | |
2047 | .parent = TYPE_VIRTIO_BUS, | |
2048 | .instance_size = sizeof(VirtioPCIBusState), | |
2049 | .class_init = virtio_pci_bus_class_init, | |
2050 | }; | |
2051 | ||
83f7d43a | 2052 | static void virtio_pci_register_types(void) |
53c25cea | 2053 | { |
a4ee4c8b EH |
2054 | /* Base types: */ |
2055 | type_register_static(&virtio_pci_bus_info); | |
2056 | type_register_static(&virtio_pci_info); | |
53c25cea PB |
2057 | } |
2058 | ||
83f7d43a | 2059 | type_init(virtio_pci_register_types) |
271458d7 | 2060 |