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53c25cea
PB		 1/*
2 * Virtio PCI Bindings
3 *
4 * Copyright IBM, Corp. 2007
5 * Copyright (c) 2009 CodeSourcery
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 * Paul Brook <paul@codesourcery.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 *
6b620ca3
PB		 14 * Contributions after 2012-01-13 are licensed under the terms of the
15 * GNU GPL, version 2 or (at your option) any later version.
53c25cea
PB		 16 */
17
9b8bfe21 18#include "qemu/osdep.h"
53c25cea 19
cbbe4f50 20#include "standard-headers/linux/virtio_pci.h"
0d09e41a
PB		 21#include "hw/virtio/virtio.h"
22#include "hw/virtio/virtio-blk.h"
23#include "hw/virtio/virtio-net.h"
24#include "hw/virtio/virtio-serial.h"
25#include "hw/virtio/virtio-scsi.h"
26#include "hw/virtio/virtio-balloon.h"
f958c8aa 27#include "hw/virtio/virtio-input.h"
83c9f4ca 28#include "hw/pci/pci.h"
da34e65c 29#include "qapi/error.h"
1de7afc9 30#include "qemu/error-report.h"
83c9f4ca
PB		 31#include "hw/pci/msi.h"
32#include "hw/pci/msix.h"
33#include "hw/loader.h"
9c17d615 34#include "sysemu/kvm.h"
47b43a1f 35#include "virtio-pci.h"
1de7afc9 36#include "qemu/range.h"
0d09e41a 37#include "hw/virtio/virtio-bus.h"
24a6e7f4 38#include "qapi/visitor.h"
53c25cea 39
cbbe4f50 40#define VIRTIO_PCI_REGION_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_present(dev))
aba800a3 41
c17bef33
MT		 42#undef VIRTIO_PCI_CONFIG
43
aba800a3
MT		 44/* The remaining space is defined by each driver as the per-driver
45 * configuration space */
cbbe4f50 46#define VIRTIO_PCI_CONFIG_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_enabled(dev))
53c25cea 47
ac7af112
AF		 48static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
49 VirtIOPCIProxy *dev);
75fd6f13 50static void virtio_pci_reset(DeviceState *qdev);
d51fcfac 51
53c25cea 52/* virtio device */
d2a0ccc6
MT		 53/* DeviceState to VirtIOPCIProxy. For use off data-path. TODO: use QOM. */
54static inline VirtIOPCIProxy *to_virtio_pci_proxy(DeviceState *d)
55{
56 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
57}
53c25cea 58
d2a0ccc6
MT		 59/* DeviceState to VirtIOPCIProxy. Note: used on datapath,
60 * be careful and test performance if you change this.
61 */
62static inline VirtIOPCIProxy *to_virtio_pci_proxy_fast(DeviceState *d)
53c25cea 63{
d2a0ccc6
MT		 64 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
65}
66
67static void virtio_pci_notify(DeviceState *d, uint16_t vector)
68{
69 VirtIOPCIProxy *proxy = to_virtio_pci_proxy_fast(d);
a3fc66d9 70
aba800a3
MT		 71 if (msix_enabled(&proxy->pci_dev))
72 msix_notify(&proxy->pci_dev, vector);
a3fc66d9
PB		 73 else {
74 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
0687c37c 75 pci_set_irq(&proxy->pci_dev, atomic_read(&vdev->isr) & 1);
a3fc66d9 76 }
53c25cea
PB		 77}
78
d2a0ccc6 79static void virtio_pci_save_config(DeviceState *d, QEMUFile *f)
ff24bd58 80{
d2a0ccc6 81 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 82 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
83
ff24bd58
MT		 84 pci_device_save(&proxy->pci_dev, f);
85 msix_save(&proxy->pci_dev, f);
86 if (msix_present(&proxy->pci_dev))
a3fc66d9 87 qemu_put_be16(f, vdev->config_vector);
ff24bd58
MT		 88}
89
b81b948e
DDAG		 90static const VMStateDescription vmstate_virtio_pci_modern_queue_state = {
91 .name = "virtio_pci/modern_queue_state",
92 .version_id = 1,
93 .minimum_version_id = 1,
94 .fields = (VMStateField[]) {
95 VMSTATE_UINT16(num, VirtIOPCIQueue),
96 VMSTATE_UNUSED(1), /* enabled was stored as be16 */
97 VMSTATE_BOOL(enabled, VirtIOPCIQueue),
98 VMSTATE_UINT32_ARRAY(desc, VirtIOPCIQueue, 2),
99 VMSTATE_UINT32_ARRAY(avail, VirtIOPCIQueue, 2),
100 VMSTATE_UINT32_ARRAY(used, VirtIOPCIQueue, 2),
101 VMSTATE_END_OF_LIST()
a6df8adf 102 }
a6df8adf
JW		 103};
104
105static bool virtio_pci_modern_state_needed(void *opaque)
106{
107 VirtIOPCIProxy *proxy = opaque;
108
9a4c0e22 109 return virtio_pci_modern(proxy);
a6df8adf
JW		 110}
111
b81b948e 112static const VMStateDescription vmstate_virtio_pci_modern_state_sub = {
a6df8adf
JW		 113 .name = "virtio_pci/modern_state",
114 .version_id = 1,
115 .minimum_version_id = 1,
116 .needed = &virtio_pci_modern_state_needed,
117 .fields = (VMStateField[]) {
b81b948e
DDAG		 118 VMSTATE_UINT32(dfselect, VirtIOPCIProxy),
119 VMSTATE_UINT32(gfselect, VirtIOPCIProxy),
120 VMSTATE_UINT32_ARRAY(guest_features, VirtIOPCIProxy, 2),
121 VMSTATE_STRUCT_ARRAY(vqs, VirtIOPCIProxy, VIRTIO_QUEUE_MAX, 0,
122 vmstate_virtio_pci_modern_queue_state,
123 VirtIOPCIQueue),
a6df8adf
JW		 124 VMSTATE_END_OF_LIST()
125 }
126};
127
128static const VMStateDescription vmstate_virtio_pci = {
129 .name = "virtio_pci",
130 .version_id = 1,
131 .minimum_version_id = 1,
132 .minimum_version_id_old = 1,
133 .fields = (VMStateField[]) {
134 VMSTATE_END_OF_LIST()
135 },
136 .subsections = (const VMStateDescription*[]) {
b81b948e 137 &vmstate_virtio_pci_modern_state_sub,
a6df8adf
JW		 138 NULL
139 }
140};
141
b81b948e
DDAG		 142static bool virtio_pci_has_extra_state(DeviceState *d)
143{
144 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
145
146 return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
147}
148
a6df8adf
JW		 149static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
150{
151 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
152
153 vmstate_save_state(f, &vmstate_virtio_pci, proxy, NULL);
154}
155
156static int virtio_pci_load_extra_state(DeviceState *d, QEMUFile *f)
157{
158 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
159
160 return vmstate_load_state(f, &vmstate_virtio_pci, proxy, 1);
161}
162
d2a0ccc6 163static void virtio_pci_save_queue(DeviceState *d, int n, QEMUFile *f)
ff24bd58 164{
d2a0ccc6 165 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 166 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
167
ff24bd58 168 if (msix_present(&proxy->pci_dev))
a3fc66d9 169 qemu_put_be16(f, virtio_queue_vector(vdev, n));
ff24bd58
MT		 170}
171
d2a0ccc6 172static int virtio_pci_load_config(DeviceState *d, QEMUFile *f)
ff24bd58 173{
d2a0ccc6 174 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 175 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
176
ff24bd58
MT		 177 int ret;
178 ret = pci_device_load(&proxy->pci_dev, f);
e6da7680 179 if (ret) {
ff24bd58 180 return ret;
e6da7680 181 }
3cac001e 182 msix_unuse_all_vectors(&proxy->pci_dev);
ff24bd58 183 msix_load(&proxy->pci_dev, f);
e6da7680 184 if (msix_present(&proxy->pci_dev)) {
a3fc66d9 185 qemu_get_be16s(f, &vdev->config_vector);
e6da7680 186 } else {
a3fc66d9 187 vdev->config_vector = VIRTIO_NO_VECTOR;
e6da7680 188 }
a3fc66d9
PB		 189 if (vdev->config_vector != VIRTIO_NO_VECTOR) {
190 return msix_vector_use(&proxy->pci_dev, vdev->config_vector);
e6da7680 191 }
ff24bd58
MT		 192 return 0;
193}
194
d2a0ccc6 195static int virtio_pci_load_queue(DeviceState *d, int n, QEMUFile *f)
ff24bd58 196{
d2a0ccc6 197 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 198 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
199
ff24bd58 200 uint16_t vector;
e6da7680
MT		 201 if (msix_present(&proxy->pci_dev)) {
202 qemu_get_be16s(f, &vector);
203 } else {
204 vector = VIRTIO_NO_VECTOR;
205 }
a3fc66d9 206 virtio_queue_set_vector(vdev, n, vector);
e6da7680
MT		 207 if (vector != VIRTIO_NO_VECTOR) {
208 return msix_vector_use(&proxy->pci_dev, vector);
209 }
a6df8adf 210
ff24bd58
MT		 211 return 0;
212}
213
8e93cef1 214static bool virtio_pci_ioeventfd_enabled(DeviceState *d)
9f06e71a
CH		 215{
216 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
217
8e93cef1 218 return (proxy->flags & VIRTIO_PCI_FLAG_USE_IOEVENTFD) != 0;
9f06e71a
CH		 219}
220
975acc0a
JW		 221#define QEMU_VIRTIO_PCI_QUEUE_MEM_MULT 0x1000
222
d9997d89
MA		 223static inline int virtio_pci_queue_mem_mult(struct VirtIOPCIProxy *proxy)
224{
225 return (proxy->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ) ?
226 QEMU_VIRTIO_PCI_QUEUE_MEM_MULT : 4;
227}
228
9f06e71a
CH		 229static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier,
230 int n, bool assign)
25db9ebe 231{
9f06e71a 232 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 233 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
234 VirtQueue *vq = virtio_get_queue(vdev, n);
9a4c0e22
MA		 235 bool legacy = virtio_pci_legacy(proxy);
236 bool modern = virtio_pci_modern(proxy);
bc85ccfd 237 bool fast_mmio = kvm_ioeventfd_any_length_enabled();
9824d2a3 238 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
588255ad 239 MemoryRegion *modern_mr = &proxy->notify.mr;
9824d2a3 240 MemoryRegion *modern_notify_mr = &proxy->notify_pio.mr;
975acc0a 241 MemoryRegion *legacy_mr = &proxy->bar;
d9997d89 242 hwaddr modern_addr = virtio_pci_queue_mem_mult(proxy) *
975acc0a
JW		 243 virtio_get_queue_index(vq);
244 hwaddr legacy_addr = VIRTIO_PCI_QUEUE_NOTIFY;
da146d0a 245
25db9ebe 246 if (assign) {
975acc0a 247 if (modern) {
bc85ccfd
JW		 248 if (fast_mmio) {
249 memory_region_add_eventfd(modern_mr, modern_addr, 0,
250 false, n, notifier);
251 } else {
252 memory_region_add_eventfd(modern_mr, modern_addr, 2,
253 false, n, notifier);
254 }
9824d2a3
JW		 255 if (modern_pio) {
256 memory_region_add_eventfd(modern_notify_mr, 0, 2,
257 true, n, notifier);
258 }
975acc0a
JW		 259 }
260 if (legacy) {
261 memory_region_add_eventfd(legacy_mr, legacy_addr, 2,
262 true, n, notifier);
263 }
25db9ebe 264 } else {
975acc0a 265 if (modern) {
bc85ccfd
JW		 266 if (fast_mmio) {
267 memory_region_del_eventfd(modern_mr, modern_addr, 0,
268 false, n, notifier);
269 } else {
270 memory_region_del_eventfd(modern_mr, modern_addr, 2,
271 false, n, notifier);
272 }
9824d2a3
JW		 273 if (modern_pio) {
274 memory_region_del_eventfd(modern_notify_mr, 0, 2,
275 true, n, notifier);
276 }
975acc0a
JW		 277 }
278 if (legacy) {
279 memory_region_del_eventfd(legacy_mr, legacy_addr, 2,
280 true, n, notifier);
281 }
25db9ebe 282 }
9f06e71a 283 return 0;
25db9ebe
SH		 284}
285
b36e3914 286static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy)
25db9ebe 287{
9f06e71a 288 virtio_bus_start_ioeventfd(&proxy->bus);
25db9ebe
SH		 289}
290
b36e3914 291static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy)
25db9ebe 292{
9f06e71a 293 virtio_bus_stop_ioeventfd(&proxy->bus);
25db9ebe
SH		 294}
295
53c25cea
PB		 296static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
297{
298 VirtIOPCIProxy *proxy = opaque;
a3fc66d9 299 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
a8170e5e 300 hwaddr pa;
53c25cea 301
53c25cea
PB		 302 switch (addr) {
303 case VIRTIO_PCI_GUEST_FEATURES:
181103cd
FK		 304 /* Guest does not negotiate properly? We have to assume nothing. */
305 if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
306 val = virtio_bus_get_vdev_bad_features(&proxy->bus);
307 }
ad0c9332 308 virtio_set_features(vdev, val);
53c25cea
PB		 309 break;
310 case VIRTIO_PCI_QUEUE_PFN:
a8170e5e 311 pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
1b8e9b27 312 if (pa == 0) {
75fd6f13 313 virtio_pci_reset(DEVICE(proxy));
1b8e9b27 314 }
7055e687
MT		 315 else
316 virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
53c25cea
PB		 317 break;
318 case VIRTIO_PCI_QUEUE_SEL:
87b3bd1c 319 if (val < VIRTIO_QUEUE_MAX)
53c25cea
PB		 320 vdev->queue_sel = val;
321 break;
322 case VIRTIO_PCI_QUEUE_NOTIFY:
87b3bd1c 323 if (val < VIRTIO_QUEUE_MAX) {
7157e2e2
SH		 324 virtio_queue_notify(vdev, val);
325 }
53c25cea
PB		 326 break;
327 case VIRTIO_PCI_STATUS:
25db9ebe
SH		 328 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
329 virtio_pci_stop_ioeventfd(proxy);
330 }
331
3e607cb5 332 virtio_set_status(vdev, val & 0xFF);
25db9ebe
SH		 333
334 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
335 virtio_pci_start_ioeventfd(proxy);
336 }
337
1b8e9b27 338 if (vdev->status == 0) {
75fd6f13 339 virtio_pci_reset(DEVICE(proxy));
1b8e9b27 340 }
c81131db 341
e43c0b2e
MT		 342 /* Linux before 2.6.34 drives the device without enabling
343 the PCI device bus master bit. Enable it automatically
344 for the guest. This is a PCI spec violation but so is
345 initiating DMA with bus master bit clear. */
346 if (val == (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER)) {
347 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
348 proxy->pci_dev.config[PCI_COMMAND] |
349 PCI_COMMAND_MASTER, 1);
350 }
53c25cea 351 break;
aba800a3
MT		 352 case VIRTIO_MSI_CONFIG_VECTOR:
353 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
354 /* Make it possible for guest to discover an error took place. */
355 if (msix_vector_use(&proxy->pci_dev, val) < 0)
356 val = VIRTIO_NO_VECTOR;
357 vdev->config_vector = val;
358 break;
359 case VIRTIO_MSI_QUEUE_VECTOR:
360 msix_vector_unuse(&proxy->pci_dev,
361 virtio_queue_vector(vdev, vdev->queue_sel));
362 /* Make it possible for guest to discover an error took place. */
363 if (msix_vector_use(&proxy->pci_dev, val) < 0)
364 val = VIRTIO_NO_VECTOR;
365 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
366 break;
367 default:
4e02d460
SH		 368 error_report("%s: unexpected address 0x%x value 0x%x",
369 __func__, addr, val);
aba800a3 370 break;
53c25cea
PB		 371 }
372}
373
aba800a3 374static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
53c25cea 375{
a3fc66d9 376 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
53c25cea
PB		 377 uint32_t ret = 0xFFFFFFFF;
378
53c25cea
PB		 379 switch (addr) {
380 case VIRTIO_PCI_HOST_FEATURES:
6b8f1020 381 ret = vdev->host_features;
53c25cea
PB		 382 break;
383 case VIRTIO_PCI_GUEST_FEATURES:
704a76fc 384 ret = vdev->guest_features;
53c25cea
PB		 385 break;
386 case VIRTIO_PCI_QUEUE_PFN:
387 ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
388 >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
389 break;
390 case VIRTIO_PCI_QUEUE_NUM:
391 ret = virtio_queue_get_num(vdev, vdev->queue_sel);
392 break;
393 case VIRTIO_PCI_QUEUE_SEL:
394 ret = vdev->queue_sel;
395 break;
396 case VIRTIO_PCI_STATUS:
397 ret = vdev->status;
398 break;
399 case VIRTIO_PCI_ISR:
400 /* reading from the ISR also clears it. */
0687c37c 401 ret = atomic_xchg(&vdev->isr, 0);
9e64f8a3 402 pci_irq_deassert(&proxy->pci_dev);
53c25cea 403 break;
aba800a3
MT		 404 case VIRTIO_MSI_CONFIG_VECTOR:
405 ret = vdev->config_vector;
406 break;
407 case VIRTIO_MSI_QUEUE_VECTOR:
408 ret = virtio_queue_vector(vdev, vdev->queue_sel);
409 break;
53c25cea
PB		 410 default:
411 break;
412 }
413
414 return ret;
415}
416
df6db5b3
AG		 417static uint64_t virtio_pci_config_read(void *opaque, hwaddr addr,
418 unsigned size)
53c25cea
PB		 419{
420 VirtIOPCIProxy *proxy = opaque;
a3fc66d9 421 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
cbbe4f50 422 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
df6db5b3 423 uint64_t val = 0;
aba800a3 424 if (addr < config) {
df6db5b3 425 return virtio_ioport_read(proxy, addr);
aba800a3
MT		 426 }
427 addr -= config;
53c25cea 428
df6db5b3
AG		 429 switch (size) {
430 case 1:
a3fc66d9 431 val = virtio_config_readb(vdev, addr);
df6db5b3
AG		 432 break;
433 case 2:
a3fc66d9 434 val = virtio_config_readw(vdev, addr);
616a6552 435 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 436 val = bswap16(val);
437 }
df6db5b3
AG		 438 break;
439 case 4:
a3fc66d9 440 val = virtio_config_readl(vdev, addr);
616a6552 441 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 442 val = bswap32(val);
443 }
df6db5b3 444 break;
82afa586 445 }
df6db5b3 446 return val;
53c25cea
PB		 447}
448
df6db5b3
AG		 449static void virtio_pci_config_write(void *opaque, hwaddr addr,
450 uint64_t val, unsigned size)
53c25cea
PB		 451{
452 VirtIOPCIProxy *proxy = opaque;
cbbe4f50 453 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
a3fc66d9 454 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
aba800a3
MT		 455 if (addr < config) {
456 virtio_ioport_write(proxy, addr, val);
457 return;
458 }
459 addr -= config;
df6db5b3
AG		 460 /*
461 * Virtio-PCI is odd. Ioports are LE but config space is target native
462 * endian.
463 */
464 switch (size) {
465 case 1:
a3fc66d9 466 virtio_config_writeb(vdev, addr, val);
df6db5b3
AG		 467 break;
468 case 2:
616a6552 469 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 470 val = bswap16(val);
471 }
a3fc66d9 472 virtio_config_writew(vdev, addr, val);
df6db5b3
AG		 473 break;
474 case 4:
616a6552 475 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 476 val = bswap32(val);
477 }
a3fc66d9 478 virtio_config_writel(vdev, addr, val);
df6db5b3 479 break;
82afa586 480 }
53c25cea
PB		 481}
482
da146d0a 483static const MemoryRegionOps virtio_pci_config_ops = {
df6db5b3
AG		 484 .read = virtio_pci_config_read,
485 .write = virtio_pci_config_write,
486 .impl = {
487 .min_access_size = 1,
488 .max_access_size = 4,
489 },
8e4a424b 490 .endianness = DEVICE_LITTLE_ENDIAN,
da146d0a 491};
aba800a3 492
a93c8d82
AK		 493static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy,
494 hwaddr *off, int len)
495{
496 int i;
497 VirtIOPCIRegion *reg;
498
499 for (i = 0; i < ARRAY_SIZE(proxy->regs); ++i) {
500 reg = &proxy->regs[i];
501 if (*off >= reg->offset &&
502 *off + len <= reg->offset + reg->size) {
503 *off -= reg->offset;
504 return &reg->mr;
505 }
506 }
507
508 return NULL;
509}
510
1e40356c
MT		 511/* Below are generic functions to do memcpy from/to an address space,
512 * without byteswaps, with input validation.
513 *
514 * As regular address_space_* APIs all do some kind of byteswap at least for
515 * some host/target combinations, we are forced to explicitly convert to a
516 * known-endianness integer value.
517 * It doesn't really matter which endian format to go through, so the code
518 * below selects the endian that causes the least amount of work on the given
519 * host.
520 *
521 * Note: host pointer must be aligned.
522 */
523static
a93c8d82 524void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
1e40356c
MT		 525 const uint8_t *buf, int len)
526{
a93c8d82
AK		 527 uint64_t val;
528 MemoryRegion *mr;
1e40356c
MT		 529
530 /* address_space_* APIs assume an aligned address.
531 * As address is under guest control, handle illegal values.
532 */
533 addr &= ~(len - 1);
534
a93c8d82
AK		 535 mr = virtio_address_space_lookup(proxy, &addr, len);
536 if (!mr) {
537 return;
538 }
539
1e40356c
MT		 540 /* Make sure caller aligned buf properly */
541 assert(!(((uintptr_t)buf) & (len - 1)));
542
543 switch (len) {
544 case 1:
545 val = pci_get_byte(buf);
1e40356c
MT		 546 break;
547 case 2:
a93c8d82 548 val = cpu_to_le16(pci_get_word(buf));
1e40356c
MT		 549 break;
550 case 4:
a93c8d82 551 val = cpu_to_le32(pci_get_long(buf));
1e40356c
MT		 552 break;
553 default:
554 /* As length is under guest control, handle illegal values. */
a93c8d82 555 return;
1e40356c 556 }
a93c8d82 557 memory_region_dispatch_write(mr, addr, val, len, MEMTXATTRS_UNSPECIFIED);
1e40356c
MT		 558}
559
560static void
a93c8d82
AK		 561virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
562 uint8_t *buf, int len)
1e40356c 563{
a93c8d82
AK		 564 uint64_t val;
565 MemoryRegion *mr;
1e40356c
MT		 566
567 /* address_space_* APIs assume an aligned address.
568 * As address is under guest control, handle illegal values.
569 */
570 addr &= ~(len - 1);
571
a93c8d82
AK		 572 mr = virtio_address_space_lookup(proxy, &addr, len);
573 if (!mr) {
574 return;
575 }
576
1e40356c
MT		 577 /* Make sure caller aligned buf properly */
578 assert(!(((uintptr_t)buf) & (len - 1)));
579
a93c8d82 580 memory_region_dispatch_read(mr, addr, &val, len, MEMTXATTRS_UNSPECIFIED);
1e40356c
MT		 581 switch (len) {
582 case 1:
1e40356c
MT		 583 pci_set_byte(buf, val);
584 break;
585 case 2:
a93c8d82 586 pci_set_word(buf, le16_to_cpu(val));
1e40356c
MT		 587 break;
588 case 4:
a93c8d82 589 pci_set_long(buf, le32_to_cpu(val));
1e40356c
MT		 590 break;
591 default:
592 /* As length is under guest control, handle illegal values. */
593 break;
594 }
595}
596
aba800a3
MT		 597static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
598 uint32_t val, int len)
599{
ed757e14 600 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
a3fc66d9 601 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
ada434cd 602 struct virtio_pci_cfg_cap *cfg;
ed757e14 603
1129714f
MT		 604 pci_default_write_config(pci_dev, address, val, len);
605
606 if (range_covers_byte(address, len, PCI_COMMAND) &&
68a27b20 607 !(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
1129714f 608 virtio_pci_stop_ioeventfd(proxy);
45363e46 609 virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK);
ed757e14 610 }
ada434cd
MT		 611
612 if (proxy->config_cap &&
613 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
614 pci_cfg_data),
615 sizeof cfg->pci_cfg_data)) {
616 uint32_t off;
617 uint32_t len;
618
619 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
620 off = le32_to_cpu(cfg->cap.offset);
621 len = le32_to_cpu(cfg->cap.length);
622
2a639123
MT		 623 if (len == 1 || len == 2 || len == 4) {
624 assert(len <= sizeof cfg->pci_cfg_data);
a93c8d82 625 virtio_address_space_write(proxy, off, cfg->pci_cfg_data, len);
ada434cd
MT		 626 }
627 }
628}
629
630static uint32_t virtio_read_config(PCIDevice *pci_dev,
631 uint32_t address, int len)
632{
633 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
634 struct virtio_pci_cfg_cap *cfg;
635
636 if (proxy->config_cap &&
637 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
638 pci_cfg_data),
639 sizeof cfg->pci_cfg_data)) {
640 uint32_t off;
641 uint32_t len;
642
643 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
644 off = le32_to_cpu(cfg->cap.offset);
645 len = le32_to_cpu(cfg->cap.length);
646
2a639123
MT		 647 if (len == 1 || len == 2 || len == 4) {
648 assert(len <= sizeof cfg->pci_cfg_data);
a93c8d82 649 virtio_address_space_read(proxy, off, cfg->pci_cfg_data, len);
ada434cd
MT		 650 }
651 }
652
653 return pci_default_read_config(pci_dev, address, len);
53c25cea
PB		 654}
655
7d37d351
JK		 656static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
657 unsigned int queue_no,
d1f6af6a 658 unsigned int vector)
7d37d351 659{
7d37d351 660 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
15b2bd18 661 int ret;
7d37d351
JK		 662
663 if (irqfd->users == 0) {
d1f6af6a 664 ret = kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_dev);
7d37d351
JK		 665 if (ret < 0) {
666 return ret;
667 }
668 irqfd->virq = ret;
669 }
670 irqfd->users++;
7d37d351
JK		 671 return 0;
672}
673
674static void kvm_virtio_pci_vq_vector_release(VirtIOPCIProxy *proxy,
7d37d351 675 unsigned int vector)
774345f9
MT		 676{
677 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
678 if (--irqfd->users == 0) {
679 kvm_irqchip_release_virq(kvm_state, irqfd->virq);
680 }
681}
682
f1d0f15a
MT		 683static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy,
684 unsigned int queue_no,
685 unsigned int vector)
686{
687 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
a3fc66d9
PB		 688 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
689 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
f1d0f15a 690 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
9be38598 691 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq);
f1d0f15a
MT		 692}
693
694static void kvm_virtio_pci_irqfd_release(VirtIOPCIProxy *proxy,
695 unsigned int queue_no,
696 unsigned int vector)
7d37d351 697{
a3fc66d9
PB		 698 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
699 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
15b2bd18 700 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
7d37d351 701 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
15b2bd18 702 int ret;
7d37d351 703
1c9b71a7 704 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, irqfd->virq);
7d37d351 705 assert(ret == 0);
f1d0f15a 706}
7d37d351 707
774345f9
MT		 708static int kvm_virtio_pci_vector_use(VirtIOPCIProxy *proxy, int nvqs)
709{
710 PCIDevice *dev = &proxy->pci_dev;
a3fc66d9 711 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 712 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
774345f9
MT		 713 unsigned int vector;
714 int ret, queue_no;
774345f9
MT		 715
716 for (queue_no = 0; queue_no < nvqs; queue_no++) {
717 if (!virtio_queue_get_num(vdev, queue_no)) {
718 break;
719 }
720 vector = virtio_queue_vector(vdev, queue_no);
721 if (vector >= msix_nr_vectors_allocated(dev)) {
722 continue;
723 }
d1f6af6a 724 ret = kvm_virtio_pci_vq_vector_use(proxy, queue_no, vector);
774345f9
MT		 725 if (ret < 0) {
726 goto undo;
7d37d351 727 }
f1d0f15a
MT		 728 /* If guest supports masking, set up irqfd now.
729 * Otherwise, delay until unmasked in the frontend.
730 */
5669655a 731 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
f1d0f15a
MT		 732 ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
733 if (ret < 0) {
734 kvm_virtio_pci_vq_vector_release(proxy, vector);
735 goto undo;
736 }
737 }
7d37d351 738 }
7d37d351 739 return 0;
774345f9
MT		 740
741undo:
742 while (--queue_no >= 0) {
743 vector = virtio_queue_vector(vdev, queue_no);
744 if (vector >= msix_nr_vectors_allocated(dev)) {
745 continue;
746 }
5669655a 747 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
e387f99e 748 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
f1d0f15a 749 }
774345f9
MT		 750 kvm_virtio_pci_vq_vector_release(proxy, vector);
751 }
752 return ret;
7d37d351
JK		 753}
754
774345f9
MT		 755static void kvm_virtio_pci_vector_release(VirtIOPCIProxy *proxy, int nvqs)
756{
757 PCIDevice *dev = &proxy->pci_dev;
a3fc66d9 758 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
774345f9
MT		 759 unsigned int vector;
760 int queue_no;
181103cd 761 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
774345f9
MT		 762
763 for (queue_no = 0; queue_no < nvqs; queue_no++) {
764 if (!virtio_queue_get_num(vdev, queue_no)) {
765 break;
766 }
767 vector = virtio_queue_vector(vdev, queue_no);
768 if (vector >= msix_nr_vectors_allocated(dev)) {
769 continue;
770 }
f1d0f15a
MT		 771 /* If guest supports masking, clean up irqfd now.
772 * Otherwise, it was cleaned when masked in the frontend.
773 */
5669655a 774 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
e387f99e 775 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
f1d0f15a 776 }
774345f9
MT		 777 kvm_virtio_pci_vq_vector_release(proxy, vector);
778 }
779}
780
a38b2c49
MT		 781static int virtio_pci_vq_vector_unmask(VirtIOPCIProxy *proxy,
782 unsigned int queue_no,
783 unsigned int vector,
784 MSIMessage msg)
774345f9 785{
a3fc66d9
PB		 786 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
787 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
788 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
774345f9 789 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
a38b2c49 790 VirtIOIRQFD *irqfd;
53510bfc 791 int ret = 0;
774345f9 792
a38b2c49
MT		 793 if (proxy->vector_irqfd) {
794 irqfd = &proxy->vector_irqfd[vector];
795 if (irqfd->msg.data != msg.data || irqfd->msg.address != msg.address) {
dc9f06ca
PF		 796 ret = kvm_irqchip_update_msi_route(kvm_state, irqfd->virq, msg,
797 &proxy->pci_dev);
a38b2c49
MT		 798 if (ret < 0) {
799 return ret;
800 }
3f1fea0f 801 kvm_irqchip_commit_routes(kvm_state);
774345f9
MT		 802 }
803 }
804
f1d0f15a
MT		 805 /* If guest supports masking, irqfd is already setup, unmask it.
806 * Otherwise, set it up now.
807 */
5669655a 808 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
a3fc66d9 809 k->guest_notifier_mask(vdev, queue_no, false);
f1d0f15a 810 /* Test after unmasking to avoid losing events. */
181103cd 811 if (k->guest_notifier_pending &&
a3fc66d9 812 k->guest_notifier_pending(vdev, queue_no)) {
f1d0f15a
MT		 813 event_notifier_set(n);
814 }
815 } else {
816 ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
7d37d351 817 }
774345f9 818 return ret;
7d37d351
JK		 819}
820
a38b2c49 821static void virtio_pci_vq_vector_mask(VirtIOPCIProxy *proxy,
7d37d351
JK		 822 unsigned int queue_no,
823 unsigned int vector)
824{
a3fc66d9
PB		 825 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
826 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
181103cd 827
f1d0f15a
MT		 828 /* If guest supports masking, keep irqfd but mask it.
829 * Otherwise, clean it up now.
830 */
5669655a 831 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
a3fc66d9 832 k->guest_notifier_mask(vdev, queue_no, true);
f1d0f15a 833 } else {
e387f99e 834 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
f1d0f15a 835 }
7d37d351
JK		 836}
837
a38b2c49
MT		 838static int virtio_pci_vector_unmask(PCIDevice *dev, unsigned vector,
839 MSIMessage msg)
7d37d351
JK		 840{
841 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 842 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
851c2a75
JW		 843 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
844 int ret, index, unmasked = 0;
7d37d351 845
851c2a75
JW		 846 while (vq) {
847 index = virtio_get_queue_index(vq);
848 if (!virtio_queue_get_num(vdev, index)) {
7d37d351
JK		 849 break;
850 }
6652d081
JW		 851 if (index < proxy->nvqs_with_notifiers) {
852 ret = virtio_pci_vq_vector_unmask(proxy, index, vector, msg);
853 if (ret < 0) {
854 goto undo;
855 }
856 ++unmasked;
7d37d351 857 }
851c2a75 858 vq = virtio_vector_next_queue(vq);
7d37d351 859 }
851c2a75 860
7d37d351
JK		 861 return 0;
862
863undo:
851c2a75 864 vq = virtio_vector_first_queue(vdev, vector);
6652d081 865 while (vq && unmasked >= 0) {
851c2a75 866 index = virtio_get_queue_index(vq);
6652d081
JW		 867 if (index < proxy->nvqs_with_notifiers) {
868 virtio_pci_vq_vector_mask(proxy, index, vector);
869 --unmasked;
870 }
851c2a75 871 vq = virtio_vector_next_queue(vq);
7d37d351
JK		 872 }
873 return ret;
874}
875
a38b2c49 876static void virtio_pci_vector_mask(PCIDevice *dev, unsigned vector)
7d37d351
JK		 877{
878 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 879 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
851c2a75
JW		 880 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
881 int index;
7d37d351 882
851c2a75
JW		 883 while (vq) {
884 index = virtio_get_queue_index(vq);
885 if (!virtio_queue_get_num(vdev, index)) {
7d37d351
JK		 886 break;
887 }
6652d081
JW		 888 if (index < proxy->nvqs_with_notifiers) {
889 virtio_pci_vq_vector_mask(proxy, index, vector);
890 }
851c2a75 891 vq = virtio_vector_next_queue(vq);
7d37d351
JK		 892 }
893}
894
a38b2c49
MT		 895static void virtio_pci_vector_poll(PCIDevice *dev,
896 unsigned int vector_start,
897 unsigned int vector_end)
89d62be9
MT		 898{
899 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 900 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 901 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
89d62be9
MT		 902 int queue_no;
903 unsigned int vector;
904 EventNotifier *notifier;
905 VirtQueue *vq;
906
2d620f59 907 for (queue_no = 0; queue_no < proxy->nvqs_with_notifiers; queue_no++) {
89d62be9
MT		 908 if (!virtio_queue_get_num(vdev, queue_no)) {
909 break;
910 }
911 vector = virtio_queue_vector(vdev, queue_no);
912 if (vector < vector_start || vector >= vector_end ||
913 !msix_is_masked(dev, vector)) {
914 continue;
915 }
916 vq = virtio_get_queue(vdev, queue_no);
917 notifier = virtio_queue_get_guest_notifier(vq);
181103cd
FK		 918 if (k->guest_notifier_pending) {
919 if (k->guest_notifier_pending(vdev, queue_no)) {
f1d0f15a
MT		 920 msix_set_pending(dev, vector);
921 }
922 } else if (event_notifier_test_and_clear(notifier)) {
89d62be9
MT		 923 msix_set_pending(dev, vector);
924 }
925 }
926}
927
928static int virtio_pci_set_guest_notifier(DeviceState *d, int n, bool assign,
929 bool with_irqfd)
ade80dc8 930{
d2a0ccc6 931 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 932 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
933 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
934 VirtQueue *vq = virtio_get_queue(vdev, n);
ade80dc8
MT		 935 EventNotifier *notifier = virtio_queue_get_guest_notifier(vq);
936
937 if (assign) {
938 int r = event_notifier_init(notifier, 0);
939 if (r < 0) {
940 return r;
941 }
89d62be9 942 virtio_queue_set_guest_notifier_fd_handler(vq, true, with_irqfd);
ade80dc8 943 } else {
89d62be9 944 virtio_queue_set_guest_notifier_fd_handler(vq, false, with_irqfd);
ade80dc8
MT		 945 event_notifier_cleanup(notifier);
946 }
947
5669655a
VK		 948 if (!msix_enabled(&proxy->pci_dev) &&
949 vdev->use_guest_notifier_mask &&
950 vdc->guest_notifier_mask) {
a3fc66d9 951 vdc->guest_notifier_mask(vdev, n, !assign);
62c96360
MT		 952 }
953
ade80dc8
MT		 954 return 0;
955}
956
d2a0ccc6 957static bool virtio_pci_query_guest_notifiers(DeviceState *d)
5430a28f 958{
d2a0ccc6 959 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
5430a28f
MT		 960 return msix_enabled(&proxy->pci_dev);
961}
962
2d620f59 963static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign)
54dd9321 964{
d2a0ccc6 965 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 966 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 967 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
54dd9321 968 int r, n;
89d62be9
MT		 969 bool with_irqfd = msix_enabled(&proxy->pci_dev) &&
970 kvm_msi_via_irqfd_enabled();
54dd9321 971
87b3bd1c 972 nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX);
2d620f59
MT		 973
974 /* When deassigning, pass a consistent nvqs value
975 * to avoid leaking notifiers.
976 */
977 assert(assign || nvqs == proxy->nvqs_with_notifiers);
978
979 proxy->nvqs_with_notifiers = nvqs;
980
7d37d351 981 /* Must unset vector notifier while guest notifier is still assigned */
181103cd 982 if ((proxy->vector_irqfd || k->guest_notifier_mask) && !assign) {
7d37d351 983 msix_unset_vector_notifiers(&proxy->pci_dev);
a38b2c49
MT		 984 if (proxy->vector_irqfd) {
985 kvm_virtio_pci_vector_release(proxy, nvqs);
986 g_free(proxy->vector_irqfd);
987 proxy->vector_irqfd = NULL;
988 }
7d37d351
JK		 989 }
990
2d620f59 991 for (n = 0; n < nvqs; n++) {
54dd9321
MT		 992 if (!virtio_queue_get_num(vdev, n)) {
993 break;
994 }
995
23fe2b3f 996 r = virtio_pci_set_guest_notifier(d, n, assign, with_irqfd);
54dd9321
MT		 997 if (r < 0) {
998 goto assign_error;
999 }
1000 }
1001
7d37d351 1002 /* Must set vector notifier after guest notifier has been assigned */
181103cd 1003 if ((with_irqfd || k->guest_notifier_mask) && assign) {
a38b2c49
MT		 1004 if (with_irqfd) {
1005 proxy->vector_irqfd =
1006 g_malloc0(sizeof(*proxy->vector_irqfd) *
1007 msix_nr_vectors_allocated(&proxy->pci_dev));
1008 r = kvm_virtio_pci_vector_use(proxy, nvqs);
1009 if (r < 0) {
1010 goto assign_error;
1011 }
774345f9 1012 }
7d37d351 1013 r = msix_set_vector_notifiers(&proxy->pci_dev,
a38b2c49
MT		 1014 virtio_pci_vector_unmask,
1015 virtio_pci_vector_mask,
1016 virtio_pci_vector_poll);
7d37d351 1017 if (r < 0) {
774345f9 1018 goto notifiers_error;
7d37d351
JK		 1019 }
1020 }
1021
54dd9321
MT		 1022 return 0;
1023
774345f9 1024notifiers_error:
a38b2c49
MT		 1025 if (with_irqfd) {
1026 assert(assign);
1027 kvm_virtio_pci_vector_release(proxy, nvqs);
1028 }
774345f9 1029
54dd9321
MT		 1030assign_error:
1031 /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */
7d37d351 1032 assert(assign);
54dd9321 1033 while (--n >= 0) {
89d62be9 1034 virtio_pci_set_guest_notifier(d, n, !assign, with_irqfd);
54dd9321
MT		 1035 }
1036 return r;
1037}
1038
6f80e617
TB		 1039static int virtio_pci_set_host_notifier_mr(DeviceState *d, int n,
1040 MemoryRegion *mr, bool assign)
1041{
1042 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
1043 int offset;
1044
1045 if (n >= VIRTIO_QUEUE_MAX || !virtio_pci_modern(proxy) ||
1046 virtio_pci_queue_mem_mult(proxy) != memory_region_size(mr)) {
1047 return -1;
1048 }
1049
1050 if (assign) {
1051 offset = virtio_pci_queue_mem_mult(proxy) * n;
1052 memory_region_add_subregion_overlap(&proxy->notify.mr, offset, mr, 1);
1053 } else {
1054 memory_region_del_subregion(&proxy->notify.mr, mr);
1055 }
1056
1057 return 0;
1058}
1059
d2a0ccc6 1060static void virtio_pci_vmstate_change(DeviceState *d, bool running)
25db9ebe 1061{
d2a0ccc6 1062 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 1063 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
25db9ebe
SH		 1064
1065 if (running) {
68a27b20
MT		 1066 /* Old QEMU versions did not set bus master enable on status write.
1067 * Detect DRIVER set and enable it.
1068 */
1069 if ((proxy->flags & VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION) &&
1070 (vdev->status & VIRTIO_CONFIG_S_DRIVER) &&
45363e46 1071 !(proxy->pci_dev.config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
68a27b20
MT		 1072 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
1073 proxy->pci_dev.config[PCI_COMMAND] |
1074 PCI_COMMAND_MASTER, 1);
89c473fd 1075 }
25db9ebe 1076 virtio_pci_start_ioeventfd(proxy);
ade80dc8 1077 } else {
25db9ebe 1078 virtio_pci_stop_ioeventfd(proxy);
ade80dc8 1079 }
ade80dc8
MT		 1080}
1081
60653b28 1082#ifdef CONFIG_VIRTFS
fc079951 1083static void virtio_9p_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
60653b28 1084{
234a336f
FK		 1085 V9fsPCIState *dev = VIRTIO_9P_PCI(vpci_dev);
1086 DeviceState *vdev = DEVICE(&dev->vdev);
60653b28 1087
234a336f 1088 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 1089 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
60653b28
PB		 1090}
1091
234a336f
FK		 1092static Property virtio_9p_pci_properties[] = {
1093 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
1094 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
60653b28 1095 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
60653b28
PB		 1096 DEFINE_PROP_END_OF_LIST(),
1097};
1098
234a336f 1099static void virtio_9p_pci_class_init(ObjectClass *klass, void *data)
60653b28
PB		 1100{
1101 DeviceClass *dc = DEVICE_CLASS(klass);
234a336f
FK		 1102 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
1103 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
60653b28 1104
fc079951 1105 k->realize = virtio_9p_pci_realize;
234a336f
FK		 1106 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1107 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_9P;
1108 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
1109 pcidev_k->class_id = 0x2;
125ee0ed 1110 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
234a336f 1111 dc->props = virtio_9p_pci_properties;
60653b28
PB		 1112}
1113
234a336f
FK		 1114static void virtio_9p_pci_instance_init(Object *obj)
1115{
1116 V9fsPCIState *dev = VIRTIO_9P_PCI(obj);
c8075caf
GA		 1117
1118 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
1119 TYPE_VIRTIO_9P);
234a336f
FK		 1120}
1121
1122static const TypeInfo virtio_9p_pci_info = {
1123 .name = TYPE_VIRTIO_9P_PCI,
1124 .parent = TYPE_VIRTIO_PCI,
1125 .instance_size = sizeof(V9fsPCIState),
1126 .instance_init = virtio_9p_pci_instance_init,
1127 .class_init = virtio_9p_pci_class_init,
60653b28 1128};
234a336f 1129#endif /* CONFIG_VIRTFS */
60653b28 1130
085bccb7
FK		 1131/*
1132 * virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
1133 */
1134
e0d686bf
JW		 1135static int virtio_pci_query_nvectors(DeviceState *d)
1136{
1137 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1138
1139 return proxy->nvectors;
1140}
1141
8607f5c3
JW		 1142static AddressSpace *virtio_pci_get_dma_as(DeviceState *d)
1143{
1144 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1145 PCIDevice *dev = &proxy->pci_dev;
1146
f0edf239 1147 return pci_get_address_space(dev);
8607f5c3
JW		 1148}
1149
ada434cd 1150static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
dfb8e184
MT		 1151 struct virtio_pci_cap *cap)
1152{
1153 PCIDevice *dev = &proxy->pci_dev;
1154 int offset;
1155
9a7c2a59
MZ		 1156 offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
1157 cap->cap_len, &error_abort);
dfb8e184
MT		 1158
1159 assert(cap->cap_len >= sizeof *cap);
1160 memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
1161 cap->cap_len - PCI_CAP_FLAGS);
ada434cd
MT		 1162
1163 return offset;
dfb8e184
MT		 1164}
1165
dfb8e184
MT		 1166static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr,
1167 unsigned size)
1168{
1169 VirtIOPCIProxy *proxy = opaque;
1170 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1171 uint32_t val = 0;
1172 int i;
1173
1174 switch (addr) {
1175 case VIRTIO_PCI_COMMON_DFSELECT:
1176 val = proxy->dfselect;
1177 break;
1178 case VIRTIO_PCI_COMMON_DF:
1179 if (proxy->dfselect <= 1) {
9b706dbb
MT		 1180 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
1181
1182 val = (vdev->host_features & ~vdc->legacy_features) >>
5f456073 1183 (32 * proxy->dfselect);
dfb8e184
MT		 1184 }
1185 break;
1186 case VIRTIO_PCI_COMMON_GFSELECT:
1187 val = proxy->gfselect;
1188 break;
1189 case VIRTIO_PCI_COMMON_GF:
3750dabc 1190 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
dfb8e184
MT		 1191 val = proxy->guest_features[proxy->gfselect];
1192 }
1193 break;
1194 case VIRTIO_PCI_COMMON_MSIX:
1195 val = vdev->config_vector;
1196 break;
1197 case VIRTIO_PCI_COMMON_NUMQ:
1198 for (i = 0; i < VIRTIO_QUEUE_MAX; ++i) {
1199 if (virtio_queue_get_num(vdev, i)) {
1200 val = i + 1;
1201 }
1202 }
1203 break;
1204 case VIRTIO_PCI_COMMON_STATUS:
1205 val = vdev->status;
1206 break;
1207 case VIRTIO_PCI_COMMON_CFGGENERATION:
b8f05908 1208 val = vdev->generation;
dfb8e184
MT		 1209 break;
1210 case VIRTIO_PCI_COMMON_Q_SELECT:
1211 val = vdev->queue_sel;
1212 break;
1213 case VIRTIO_PCI_COMMON_Q_SIZE:
1214 val = virtio_queue_get_num(vdev, vdev->queue_sel);
1215 break;
1216 case VIRTIO_PCI_COMMON_Q_MSIX:
1217 val = virtio_queue_vector(vdev, vdev->queue_sel);
1218 break;
1219 case VIRTIO_PCI_COMMON_Q_ENABLE:
1220 val = proxy->vqs[vdev->queue_sel].enabled;
1221 break;
1222 case VIRTIO_PCI_COMMON_Q_NOFF:
1223 /* Simply map queues in order */
1224 val = vdev->queue_sel;
1225 break;
1226 case VIRTIO_PCI_COMMON_Q_DESCLO:
1227 val = proxy->vqs[vdev->queue_sel].desc[0];
1228 break;
1229 case VIRTIO_PCI_COMMON_Q_DESCHI:
1230 val = proxy->vqs[vdev->queue_sel].desc[1];
1231 break;
1232 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1233 val = proxy->vqs[vdev->queue_sel].avail[0];
1234 break;
1235 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1236 val = proxy->vqs[vdev->queue_sel].avail[1];
1237 break;
1238 case VIRTIO_PCI_COMMON_Q_USEDLO:
1239 val = proxy->vqs[vdev->queue_sel].used[0];
1240 break;
1241 case VIRTIO_PCI_COMMON_Q_USEDHI:
1242 val = proxy->vqs[vdev->queue_sel].used[1];
1243 break;
1244 default:
1245 val = 0;
1246 }
1247
1248 return val;
1249}
1250
1251static void virtio_pci_common_write(void *opaque, hwaddr addr,
1252 uint64_t val, unsigned size)
1253{
1254 VirtIOPCIProxy *proxy = opaque;
1255 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1256
1257 switch (addr) {
1258 case VIRTIO_PCI_COMMON_DFSELECT:
1259 proxy->dfselect = val;
1260 break;
1261 case VIRTIO_PCI_COMMON_GFSELECT:
1262 proxy->gfselect = val;
1263 break;
1264 case VIRTIO_PCI_COMMON_GF:
3750dabc 1265 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
dfb8e184
MT		 1266 proxy->guest_features[proxy->gfselect] = val;
1267 virtio_set_features(vdev,
1268 (((uint64_t)proxy->guest_features[1]) << 32) |
1269 proxy->guest_features[0]);
1270 }
1271 break;
1272 case VIRTIO_PCI_COMMON_MSIX:
1273 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
1274 /* Make it possible for guest to discover an error took place. */
1275 if (msix_vector_use(&proxy->pci_dev, val) < 0) {
1276 val = VIRTIO_NO_VECTOR;
1277 }
1278 vdev->config_vector = val;
1279 break;
1280 case VIRTIO_PCI_COMMON_STATUS:
1281 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
1282 virtio_pci_stop_ioeventfd(proxy);
1283 }
1284
1285 virtio_set_status(vdev, val & 0xFF);
1286
1287 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
1288 virtio_pci_start_ioeventfd(proxy);
1289 }
1290
1291 if (vdev->status == 0) {
75fd6f13 1292 virtio_pci_reset(DEVICE(proxy));
dfb8e184
MT		 1293 }
1294
1295 break;
1296 case VIRTIO_PCI_COMMON_Q_SELECT:
1297 if (val < VIRTIO_QUEUE_MAX) {
1298 vdev->queue_sel = val;
1299 }
1300 break;
1301 case VIRTIO_PCI_COMMON_Q_SIZE:
1302 proxy->vqs[vdev->queue_sel].num = val;
1303 break;
1304 case VIRTIO_PCI_COMMON_Q_MSIX:
1305 msix_vector_unuse(&proxy->pci_dev,
1306 virtio_queue_vector(vdev, vdev->queue_sel));
1307 /* Make it possible for guest to discover an error took place. */
1308 if (msix_vector_use(&proxy->pci_dev, val) < 0) {
1309 val = VIRTIO_NO_VECTOR;
1310 }
1311 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
1312 break;
1313 case VIRTIO_PCI_COMMON_Q_ENABLE:
dfb8e184
MT		 1314 virtio_queue_set_num(vdev, vdev->queue_sel,
1315 proxy->vqs[vdev->queue_sel].num);
1316 virtio_queue_set_rings(vdev, vdev->queue_sel,
1317 ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 |
1318 proxy->vqs[vdev->queue_sel].desc[0],
1319 ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 |
1320 proxy->vqs[vdev->queue_sel].avail[0],
1321 ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 |
1322 proxy->vqs[vdev->queue_sel].used[0]);
393f04d3 1323 proxy->vqs[vdev->queue_sel].enabled = 1;
dfb8e184
MT		 1324 break;
1325 case VIRTIO_PCI_COMMON_Q_DESCLO:
1326 proxy->vqs[vdev->queue_sel].desc[0] = val;
1327 break;
1328 case VIRTIO_PCI_COMMON_Q_DESCHI:
1329 proxy->vqs[vdev->queue_sel].desc[1] = val;
1330 break;
1331 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1332 proxy->vqs[vdev->queue_sel].avail[0] = val;
1333 break;
1334 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1335 proxy->vqs[vdev->queue_sel].avail[1] = val;
1336 break;
1337 case VIRTIO_PCI_COMMON_Q_USEDLO:
1338 proxy->vqs[vdev->queue_sel].used[0] = val;
1339 break;
1340 case VIRTIO_PCI_COMMON_Q_USEDHI:
1341 proxy->vqs[vdev->queue_sel].used[1] = val;
1342 break;
1343 default:
1344 break;
1345 }
1346}
1347
1348
1349static uint64_t virtio_pci_notify_read(void *opaque, hwaddr addr,
1350 unsigned size)
1351{
1352 return 0;
1353}
1354
1355static void virtio_pci_notify_write(void *opaque, hwaddr addr,
1356 uint64_t val, unsigned size)
1357{
1358 VirtIODevice *vdev = opaque;
d9997d89
MA		 1359 VirtIOPCIProxy *proxy = VIRTIO_PCI(DEVICE(vdev)->parent_bus->parent);
1360 unsigned queue = addr / virtio_pci_queue_mem_mult(proxy);
dfb8e184
MT		 1361
1362 if (queue < VIRTIO_QUEUE_MAX) {
1363 virtio_queue_notify(vdev, queue);
1364 }
1365}
1366
9824d2a3
JW		 1367static void virtio_pci_notify_write_pio(void *opaque, hwaddr addr,
1368 uint64_t val, unsigned size)
1369{
1370 VirtIODevice *vdev = opaque;
1371 unsigned queue = val;
1372
1373 if (queue < VIRTIO_QUEUE_MAX) {
1374 virtio_queue_notify(vdev, queue);
1375 }
1376}
1377
dfb8e184
MT		 1378static uint64_t virtio_pci_isr_read(void *opaque, hwaddr addr,
1379 unsigned size)
1380{
1381 VirtIOPCIProxy *proxy = opaque;
1382 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
0687c37c 1383 uint64_t val = atomic_xchg(&vdev->isr, 0);
dfb8e184
MT		 1384 pci_irq_deassert(&proxy->pci_dev);
1385
1386 return val;
1387}
1388
1389static void virtio_pci_isr_write(void *opaque, hwaddr addr,
1390 uint64_t val, unsigned size)
1391{
1392}
1393
1394static uint64_t virtio_pci_device_read(void *opaque, hwaddr addr,
1395 unsigned size)
1396{
1397 VirtIODevice *vdev = opaque;
1398 uint64_t val = 0;
1399
1400 switch (size) {
1401 case 1:
54c720d4 1402 val = virtio_config_modern_readb(vdev, addr);
dfb8e184
MT		 1403 break;
1404 case 2:
54c720d4 1405 val = virtio_config_modern_readw(vdev, addr);
dfb8e184
MT		 1406 break;
1407 case 4:
54c720d4 1408 val = virtio_config_modern_readl(vdev, addr);
dfb8e184
MT		 1409 break;
1410 }
1411 return val;
1412}
1413
1414static void virtio_pci_device_write(void *opaque, hwaddr addr,
1415 uint64_t val, unsigned size)
1416{
1417 VirtIODevice *vdev = opaque;
1418 switch (size) {
1419 case 1:
54c720d4 1420 virtio_config_modern_writeb(vdev, addr, val);
dfb8e184
MT		 1421 break;
1422 case 2:
54c720d4 1423 virtio_config_modern_writew(vdev, addr, val);
dfb8e184
MT		 1424 break;
1425 case 4:
54c720d4 1426 virtio_config_modern_writel(vdev, addr, val);
dfb8e184
MT		 1427 break;
1428 }
1429}
1430
1141ce21
GH		 1431static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy)
1432{
1433 static const MemoryRegionOps common_ops = {
1434 .read = virtio_pci_common_read,
1435 .write = virtio_pci_common_write,
1436 .impl = {
1437 .min_access_size = 1,
1438 .max_access_size = 4,
1439 },
1440 .endianness = DEVICE_LITTLE_ENDIAN,
1441 };
1442 static const MemoryRegionOps isr_ops = {
1443 .read = virtio_pci_isr_read,
1444 .write = virtio_pci_isr_write,
1445 .impl = {
1446 .min_access_size = 1,
1447 .max_access_size = 4,
1448 },
1449 .endianness = DEVICE_LITTLE_ENDIAN,
1450 };
1451 static const MemoryRegionOps device_ops = {
1452 .read = virtio_pci_device_read,
1453 .write = virtio_pci_device_write,
1454 .impl = {
1455 .min_access_size = 1,
1456 .max_access_size = 4,
1457 },
1458 .endianness = DEVICE_LITTLE_ENDIAN,
1459 };
1460 static const MemoryRegionOps notify_ops = {
1461 .read = virtio_pci_notify_read,
1462 .write = virtio_pci_notify_write,
1463 .impl = {
1464 .min_access_size = 1,
1465 .max_access_size = 4,
1466 },
1467 .endianness = DEVICE_LITTLE_ENDIAN,
1468 };
9824d2a3
JW		 1469 static const MemoryRegionOps notify_pio_ops = {
1470 .read = virtio_pci_notify_read,
1471 .write = virtio_pci_notify_write_pio,
1472 .impl = {
1473 .min_access_size = 1,
1474 .max_access_size = 4,
1475 },
1476 .endianness = DEVICE_LITTLE_ENDIAN,
1477 };
1478
1141ce21
GH		 1479
1480 memory_region_init_io(&proxy->common.mr, OBJECT(proxy),
1481 &common_ops,
1482 proxy,
b6ce27a5
GH		 1483 "virtio-pci-common",
1484 proxy->common.size);
a3cc2e81 1485
1141ce21
GH		 1486 memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),
1487 &isr_ops,
1488 proxy,
b6ce27a5
GH		 1489 "virtio-pci-isr",
1490 proxy->isr.size);
a3cc2e81 1491
1141ce21
GH		 1492 memory_region_init_io(&proxy->device.mr, OBJECT(proxy),
1493 &device_ops,
1494 virtio_bus_get_device(&proxy->bus),
b6ce27a5
GH		 1495 "virtio-pci-device",
1496 proxy->device.size);
a3cc2e81 1497
1141ce21
GH		 1498 memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),
1499 &notify_ops,
1500 virtio_bus_get_device(&proxy->bus),
1501 "virtio-pci-notify",
b6ce27a5 1502 proxy->notify.size);
9824d2a3
JW		 1503
1504 memory_region_init_io(&proxy->notify_pio.mr, OBJECT(proxy),
1505 &notify_pio_ops,
1506 virtio_bus_get_device(&proxy->bus),
1507 "virtio-pci-notify-pio",
e3aab6c7 1508 proxy->notify_pio.size);
a3cc2e81
GH		 1509}
1510
1511static void virtio_pci_modern_region_map(VirtIOPCIProxy *proxy,
54790d71 1512 VirtIOPCIRegion *region,
9824d2a3
JW		 1513 struct virtio_pci_cap *cap,
1514 MemoryRegion *mr,
1515 uint8_t bar)
a3cc2e81 1516{
9824d2a3 1517 memory_region_add_subregion(mr, region->offset, &region->mr);
54790d71 1518
fc004905 1519 cap->cfg_type = region->type;
9824d2a3 1520 cap->bar = bar;
54790d71 1521 cap->offset = cpu_to_le32(region->offset);
b6ce27a5 1522 cap->length = cpu_to_le32(region->size);
54790d71 1523 virtio_pci_add_mem_cap(proxy, cap);
9824d2a3
JW		 1524
1525}
1526
1527static void virtio_pci_modern_mem_region_map(VirtIOPCIProxy *proxy,
1528 VirtIOPCIRegion *region,
1529 struct virtio_pci_cap *cap)
1530{
1531 virtio_pci_modern_region_map(proxy, region, cap,
7a25126d 1532 &proxy->modern_bar, proxy->modern_mem_bar_idx);
1141ce21 1533}
dfb8e184 1534
9824d2a3
JW		 1535static void virtio_pci_modern_io_region_map(VirtIOPCIProxy *proxy,
1536 VirtIOPCIRegion *region,
1537 struct virtio_pci_cap *cap)
1538{
1539 virtio_pci_modern_region_map(proxy, region, cap,
7a25126d 1540 &proxy->io_bar, proxy->modern_io_bar_idx);
9824d2a3
JW		 1541}
1542
1543static void virtio_pci_modern_mem_region_unmap(VirtIOPCIProxy *proxy,
1544 VirtIOPCIRegion *region)
27462695
MT		 1545{
1546 memory_region_del_subregion(&proxy->modern_bar,
1547 &region->mr);
1548}
1549
9824d2a3
JW		 1550static void virtio_pci_modern_io_region_unmap(VirtIOPCIProxy *proxy,
1551 VirtIOPCIRegion *region)
1552{
1553 memory_region_del_subregion(&proxy->io_bar,
1554 &region->mr);
1555}
1556
d1b4259f
MC		 1557static void virtio_pci_pre_plugged(DeviceState *d, Error **errp)
1558{
1559 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1560 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1561
1562 if (virtio_pci_modern(proxy)) {
1563 virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1);
1564 }
1565
1566 virtio_add_feature(&vdev->host_features, VIRTIO_F_BAD_FEATURE);
1567}
1568
085bccb7 1569/* This is called by virtio-bus just after the device is plugged. */
e8398045 1570static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
085bccb7
FK		 1571{
1572 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1573 VirtioBusState *bus = &proxy->bus;
9a4c0e22 1574 bool legacy = virtio_pci_legacy(proxy);
d1b4259f 1575 bool modern;
9824d2a3 1576 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
085bccb7
FK		 1577 uint8_t *config;
1578 uint32_t size;
6b8f1020 1579 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
085bccb7 1580
d1b4259f
MC		 1581 /*
1582 * Virtio capabilities present without
1583 * VIRTIO_F_VERSION_1 confuses guests
1584 */
66d1c4c1
MC		 1585 if (!proxy->ignore_backend_features &&
1586 !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) {
d1b4259f
MC		 1587 virtio_pci_disable_modern(proxy);
1588
1589 if (!legacy) {
1590 error_setg(errp, "Device doesn't support modern mode, and legacy"
1591 " mode is disabled");
1592 error_append_hint(errp, "Set disable-legacy to off\n");
1593
1594 return;
1595 }
1596 }
1597
1598 modern = virtio_pci_modern(proxy);
1599
085bccb7
FK		 1600 config = proxy->pci_dev.config;
1601 if (proxy->class_code) {
1602 pci_config_set_class(config, proxy->class_code);
1603 }
e266d421
GH		 1604
1605 if (legacy) {
8607f5c3
JW		 1606 if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
1607 error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by"
2080a29f 1608 " neither legacy nor transitional device");
8607f5c3
JW		 1609 return ;
1610 }
f2bc54de
LP		 1611 /*
1612 * Legacy and transitional devices use specific subsystem IDs.
1613 * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID)
1614 * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default.
1615 */
e266d421
GH		 1616 pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus));
1617 } else {
1618 /* pure virtio-1.0 */
1619 pci_set_word(config + PCI_VENDOR_ID,
1620 PCI_VENDOR_ID_REDHAT_QUMRANET);
1621 pci_set_word(config + PCI_DEVICE_ID,
1622 0x1040 + virtio_bus_get_vdev_id(bus));
1623 pci_config_set_revision(config, 1);
1624 }
085bccb7
FK		 1625 config[PCI_INTERRUPT_PIN] = 1;
1626
dfb8e184 1627
e266d421 1628 if (modern) {
cc52ea90
GH		 1629 struct virtio_pci_cap cap = {
1630 .cap_len = sizeof cap,
dfb8e184
MT		 1631 };
1632 struct virtio_pci_notify_cap notify = {
dfb8e184 1633 .cap.cap_len = sizeof notify,
dfb8e184 1634 .notify_off_multiplier =
d9997d89 1635 cpu_to_le32(virtio_pci_queue_mem_mult(proxy)),
dfb8e184 1636 };
ada434cd
MT		 1637 struct virtio_pci_cfg_cap cfg = {
1638 .cap.cap_len = sizeof cfg,
1639 .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
1640 };
9824d2a3
JW		 1641 struct virtio_pci_notify_cap notify_pio = {
1642 .cap.cap_len = sizeof notify,
1643 .notify_off_multiplier = cpu_to_le32(0x0),
1644 };
dfb8e184 1645
9824d2a3 1646 struct virtio_pci_cfg_cap *cfg_mask;
dfb8e184 1647
1141ce21 1648 virtio_pci_modern_regions_init(proxy);
9824d2a3
JW		 1649
1650 virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap);
1651 virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap);
1652 virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap);
1653 virtio_pci_modern_mem_region_map(proxy, &proxy->notify, &notify.cap);
1654
1655 if (modern_pio) {
1656 memory_region_init(&proxy->io_bar, OBJECT(proxy),
1657 "virtio-pci-io", 0x4);
1658
7a25126d 1659 pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx,
9824d2a3
JW		 1660 PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar);
1661
1662 virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio,
1663 &notify_pio.cap);
1664 }
ada434cd 1665
7a25126d 1666 pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
4e93a68e
GH		 1667 PCI_BASE_ADDRESS_SPACE_MEMORY |
1668 PCI_BASE_ADDRESS_MEM_PREFETCH |
1669 PCI_BASE_ADDRESS_MEM_TYPE_64,
dfb8e184 1670 &proxy->modern_bar);
ada434cd
MT		 1671
1672 proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
1673 cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
1674 pci_set_byte(&cfg_mask->cap.bar, ~0x0);
1675 pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
1676 pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
1677 pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
dfb8e184
MT		 1678 }
1679
0d583647
RH		 1680 if (proxy->nvectors) {
1681 int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
ee640c62 1682 proxy->msix_bar_idx, NULL);
0d583647 1683 if (err) {
ee640c62 1684 /* Notice when a system that supports MSIx can't initialize it */
0d583647
RH		 1685 if (err != -ENOTSUP) {
1686 error_report("unable to init msix vectors to %" PRIu32,
1687 proxy->nvectors);
1688 }
1689 proxy->nvectors = 0;
1690 }
085bccb7
FK		 1691 }
1692
1693 proxy->pci_dev.config_write = virtio_write_config;
ada434cd 1694 proxy->pci_dev.config_read = virtio_read_config;
085bccb7 1695
e266d421
GH		 1696 if (legacy) {
1697 size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
1698 + virtio_bus_get_vdev_config_len(bus);
1d0148fe 1699 size = pow2ceil(size);
085bccb7 1700
e266d421
GH		 1701 memory_region_init_io(&proxy->bar, OBJECT(proxy),
1702 &virtio_pci_config_ops,
1703 proxy, "virtio-pci", size);
dfb8e184 1704
7a25126d 1705 pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
23c5e397 1706 PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
e266d421 1707 }
085bccb7
FK		 1708}
1709
06a13073
PB		 1710static void virtio_pci_device_unplugged(DeviceState *d)
1711{
06a13073 1712 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
9a4c0e22 1713 bool modern = virtio_pci_modern(proxy);
9824d2a3 1714 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
06a13073
PB		 1715
1716 virtio_pci_stop_ioeventfd(proxy);
27462695
MT		 1717
1718 if (modern) {
9824d2a3
JW		 1719 virtio_pci_modern_mem_region_unmap(proxy, &proxy->common);
1720 virtio_pci_modern_mem_region_unmap(proxy, &proxy->isr);
1721 virtio_pci_modern_mem_region_unmap(proxy, &proxy->device);
1722 virtio_pci_modern_mem_region_unmap(proxy, &proxy->notify);
1723 if (modern_pio) {
1724 virtio_pci_modern_io_region_unmap(proxy, &proxy->notify_pio);
1725 }
27462695 1726 }
06a13073
PB		 1727}
1728
fc079951 1729static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
085bccb7 1730{
b6ce27a5 1731 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
085bccb7 1732 VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev);
fd56e061
DG		 1733 bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
1734 !pci_bus_is_root(pci_get_bus(pci_dev));
fc079951 1735
c324fd0a 1736 if (kvm_enabled() && !kvm_has_many_ioeventfds()) {
ca2b413c
PB		 1737 proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;
1738 }
1739
b6ce27a5
GH		 1740 /*
1741 * virtio pci bar layout used by default.
1742 * subclasses can re-arrange things if needed.
1743 *
1744 * region 0 -- virtio legacy io bar
1745 * region 1 -- msi-x bar
1746 * region 4+5 -- virtio modern memory (64bit) bar
1747 *
1748 */
7a25126d
CF		 1749 proxy->legacy_io_bar_idx = 0;
1750 proxy->msix_bar_idx = 1;
1751 proxy->modern_io_bar_idx = 2;
1752 proxy->modern_mem_bar_idx = 4;
b6ce27a5
GH		 1753
1754 proxy->common.offset = 0x0;
1755 proxy->common.size = 0x1000;
1756 proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;
1757
1758 proxy->isr.offset = 0x1000;
1759 proxy->isr.size = 0x1000;
1760 proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;
1761
1762 proxy->device.offset = 0x2000;
1763 proxy->device.size = 0x1000;
1764 proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;
1765
1766 proxy->notify.offset = 0x3000;
d9997d89 1767 proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;
b6ce27a5
GH		 1768 proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
1769
9824d2a3
JW		 1770 proxy->notify_pio.offset = 0x0;
1771 proxy->notify_pio.size = 0x4;
1772 proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
1773
b6ce27a5
GH		 1774 /* subclasses can enforce modern, so do this unconditionally */
1775 memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",
d9997d89
MA		 1776 /* PCI BAR regions must be powers of 2 */
1777 pow2ceil(proxy->notify.offset + proxy->notify.size));
b6ce27a5 1778
9a4c0e22
MA		 1779 if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {
1780 proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
1781 }
1782
71d19fc5 1783 if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {
3eff3769
GK		 1784 error_setg(errp, "device cannot work as neither modern nor legacy mode"
1785 " is enabled");
1786 error_append_hint(errp, "Set either disable-modern or disable-legacy"
1787 " to off\n");
1788 return;
1789 }
1790
9a4c0e22 1791 if (pcie_port && pci_is_express(pci_dev)) {
1811e64c
MA		 1792 int pos;
1793
1811e64c
MA		 1794 pos = pcie_endpoint_cap_init(pci_dev, 0);
1795 assert(pos > 0);
1796
9a7c2a59
MZ		 1797 pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
1798 PCI_PM_SIZEOF, errp);
1799 if (pos < 0) {
1800 return;
1801 }
1802
27ce0f3a 1803 pci_dev->exp.pm_cap = pos;
1811e64c
MA		 1804
1805 /*
1806 * Indicates that this function complies with revision 1.2 of the
1807 * PCI Power Management Interface Specification.
1808 */
1809 pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
615c4ed2 1810
c2cabb34
MA		 1811 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
1812 /* Init error enabling flags */
1813 pcie_cap_deverr_init(pci_dev);
1814 }
1815
d584f1b9
MA		 1816 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
1817 /* Init Link Control Register */
1818 pcie_cap_lnkctl_init(pci_dev);
1819 }
1820
27ce0f3a
MA		 1821 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
1822 /* Init Power Management Control Register */
1823 pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
1824 PCI_PM_CTRL_STATE_MASK);
1825 }
1826
615c4ed2
JW		 1827 if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
1828 pcie_ats_init(pci_dev, 256);
1829 }
1830
0560b0e9
SL		 1831 } else {
1832 /*
1833 * make future invocations of pci_is_express() return false
1834 * and pci_config_size() return PCI_CONFIG_SPACE_SIZE.
1835 */
1836 pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;
1811e64c
MA		 1837 }
1838
b6ce27a5 1839 virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
fc079951 1840 if (k->realize) {
b6ce27a5 1841 k->realize(proxy, errp);
085bccb7 1842 }
085bccb7
FK		 1843}
1844
1845static void virtio_pci_exit(PCIDevice *pci_dev)
1846{
8b81bb3b 1847 msix_uninit_exclusive_bar(pci_dev);
085bccb7
FK		 1848}
1849
59ccd20a 1850static void virtio_pci_reset(DeviceState *qdev)
085bccb7
FK		 1851{
1852 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
1853 VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
c2cabb34 1854 PCIDevice *dev = PCI_DEVICE(qdev);
393f04d3
JW		 1855 int i;
1856
085bccb7
FK		 1857 virtio_pci_stop_ioeventfd(proxy);
1858 virtio_bus_reset(bus);
1859 msix_unuse_all_vectors(&proxy->pci_dev);
393f04d3
JW		 1860
1861 for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
1862 proxy->vqs[i].enabled = 0;
60a8d802
JW		 1863 proxy->vqs[i].num = 0;
1864 proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0;
1865 proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
1866 proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
393f04d3 1867 }
c2cabb34
MA		 1868
1869 if (pci_is_express(dev)) {
1870 pcie_cap_deverr_reset(dev);
d584f1b9 1871 pcie_cap_lnkctl_reset(dev);
27ce0f3a
MA		 1872
1873 pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
c2cabb34 1874 }
085bccb7
FK		 1875}
1876
85d1277e 1877static Property virtio_pci_properties[] = {
68a27b20
MT		 1878 DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
1879 VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
9a4c0e22
MA		 1880 DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy,
1881 ON_OFF_AUTO_AUTO),
1882 DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false),
a6df8adf
JW		 1883 DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
1884 VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
9824d2a3
JW		 1885 DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
1886 VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
1811e64c
MA		 1887 DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
1888 VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
d9997d89
MA		 1889 DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
1890 VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
66d1c4c1
MC		 1891 DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
1892 ignore_backend_features, false),
615c4ed2
JW		 1893 DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
1894 VIRTIO_PCI_FLAG_ATS_BIT, false),
c2cabb34
MA		 1895 DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
1896 VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
d584f1b9
MA		 1897 DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
1898 VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
27ce0f3a
MA		 1899 DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
1900 VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
85d1277e
ML		 1901 DEFINE_PROP_END_OF_LIST(),
1902};
1903
0560b0e9
SL		 1904static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
1905{
1906 VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev);
1907 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
1908 PCIDevice *pci_dev = &proxy->pci_dev;
1909
1910 if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&
9a4c0e22 1911 virtio_pci_modern(proxy)) {
0560b0e9
SL		 1912 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1913 }
1914
1915 vpciklass->parent_dc_realize(qdev, errp);
1916}
1917
085bccb7
FK		 1918static void virtio_pci_class_init(ObjectClass *klass, void *data)
1919{
1920 DeviceClass *dc = DEVICE_CLASS(klass);
1921 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
0560b0e9 1922 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
085bccb7 1923
85d1277e 1924 dc->props = virtio_pci_properties;
fc079951 1925 k->realize = virtio_pci_realize;
085bccb7
FK		 1926 k->exit = virtio_pci_exit;
1927 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1928 k->revision = VIRTIO_PCI_ABI_VERSION;
1929 k->class_id = PCI_CLASS_OTHERS;
bf853881
PMD		 1930 device_class_set_parent_realize(dc, virtio_pci_dc_realize,
1931 &vpciklass->parent_dc_realize);
59ccd20a 1932 dc->reset = virtio_pci_reset;
085bccb7
FK		 1933}
1934
1935static const TypeInfo virtio_pci_info = {
1936 .name = TYPE_VIRTIO_PCI,
1937 .parent = TYPE_PCI_DEVICE,
1938 .instance_size = sizeof(VirtIOPCIProxy),
1939 .class_init = virtio_pci_class_init,
1940 .class_size = sizeof(VirtioPCIClass),
1941 .abstract = true,
a5fa336f
EH		 1942 .interfaces = (InterfaceInfo[]) {
1943 { INTERFACE_PCIE_DEVICE },
1944 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1945 { }
1946 },
085bccb7
FK		 1947};
1948
653ced07
FK		 1949/* virtio-blk-pci */
1950
1951static Property virtio_blk_pci_properties[] = {
c7bcc85d 1952 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
653ced07
FK		 1953 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
1954 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
0ebf9a74
CL		 1955 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
1956 DEV_NVECTORS_UNSPECIFIED),
653ced07
FK		 1957 DEFINE_PROP_END_OF_LIST(),
1958};
1959
fc079951 1960static void virtio_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
653ced07
FK		 1961{
1962 VirtIOBlkPCI *dev = VIRTIO_BLK_PCI(vpci_dev);
1963 DeviceState *vdev = DEVICE(&dev->vdev);
fc079951 1964
0ebf9a74
CL		 1965 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
1966 vpci_dev->nvectors = dev->vdev.conf.num_queues + 1;
1967 }
1968
653ced07 1969 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 1970 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
653ced07
FK		 1971}
1972
1973static void virtio_blk_pci_class_init(ObjectClass *klass, void *data)
1974{
1975 DeviceClass *dc = DEVICE_CLASS(klass);
1976 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
1977 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
1978
125ee0ed 1979 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
653ced07 1980 dc->props = virtio_blk_pci_properties;
fc079951 1981 k->realize = virtio_blk_pci_realize;
653ced07
FK		 1982 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1983 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
1984 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
1985 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
1986}
1987
1988static void virtio_blk_pci_instance_init(Object *obj)
1989{
1990 VirtIOBlkPCI *dev = VIRTIO_BLK_PCI(obj);
c8075caf
GA		 1991
1992 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
1993 TYPE_VIRTIO_BLK);
aeb98ddc
GA		 1994 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
1995 "bootindex", &error_abort);
653ced07
FK		 1996}
1997
1998static const TypeInfo virtio_blk_pci_info = {
1999 .name = TYPE_VIRTIO_BLK_PCI,
2000 .parent = TYPE_VIRTIO_PCI,
2001 .instance_size = sizeof(VirtIOBlkPCI),
2002 .instance_init = virtio_blk_pci_instance_init,
2003 .class_init = virtio_blk_pci_class_init,
2004};
2005
00343e4b
CL		 2006#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
2007/* vhost-user-blk */
2008
2009static Property vhost_user_blk_pci_properties[] = {
2010 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
0ebf9a74
CL		 2011 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2012 DEV_NVECTORS_UNSPECIFIED),
00343e4b
CL		 2013 DEFINE_PROP_END_OF_LIST(),
2014};
2015
2016static void vhost_user_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2017{
2018 VHostUserBlkPCI *dev = VHOST_USER_BLK_PCI(vpci_dev);
2019 DeviceState *vdev = DEVICE(&dev->vdev);
2020
0ebf9a74
CL		 2021 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2022 vpci_dev->nvectors = dev->vdev.num_queues + 1;
2023 }
2024
00343e4b
CL		 2025 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
2026 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2027}
2028
2029static void vhost_user_blk_pci_class_init(ObjectClass *klass, void *data)
2030{
2031 DeviceClass *dc = DEVICE_CLASS(klass);
2032 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2033 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2034
2035 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2036 dc->props = vhost_user_blk_pci_properties;
2037 k->realize = vhost_user_blk_pci_realize;
2038 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2039 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
2040 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2041 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2042}
2043
2044static void vhost_user_blk_pci_instance_init(Object *obj)
2045{
2046 VHostUserBlkPCI *dev = VHOST_USER_BLK_PCI(obj);
2047
2048 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2049 TYPE_VHOST_USER_BLK);
2050 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2051 "bootindex", &error_abort);
2052}
2053
2054static const TypeInfo vhost_user_blk_pci_info = {
2055 .name = TYPE_VHOST_USER_BLK_PCI,
2056 .parent = TYPE_VIRTIO_PCI,
2057 .instance_size = sizeof(VHostUserBlkPCI),
2058 .instance_init = vhost_user_blk_pci_instance_init,
2059 .class_init = vhost_user_blk_pci_class_init,
2060};
2061#endif
2062
bc7b90a0
FK		 2063/* virtio-scsi-pci */
2064
2065static Property virtio_scsi_pci_properties[] = {
2066 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
2067 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
2068 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2069 DEV_NVECTORS_UNSPECIFIED),
bc7b90a0
FK		 2070 DEFINE_PROP_END_OF_LIST(),
2071};
2072
fc079951 2073static void virtio_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
bc7b90a0
FK		 2074{
2075 VirtIOSCSIPCI *dev = VIRTIO_SCSI_PCI(vpci_dev);
2076 DeviceState *vdev = DEVICE(&dev->vdev);
292c8e50 2077 VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
6f32a6b4
FK		 2078 DeviceState *proxy = DEVICE(vpci_dev);
2079 char *bus_name;
bc7b90a0
FK		 2080
2081 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
292c8e50 2082 vpci_dev->nvectors = vs->conf.num_queues + 3;
bc7b90a0
FK		 2083 }
2084
6f32a6b4
FK		 2085 /*
2086 * For command line compatibility, this sets the virtio-scsi-device bus
2087 * name as before.
2088 */
2089 if (proxy->id) {
2090 bus_name = g_strdup_printf("%s.0", proxy->id);
2091 virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name);
2092 g_free(bus_name);
2093 }
2094
bc7b90a0 2095 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2096 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
bc7b90a0
FK		 2097}
2098
2099static void virtio_scsi_pci_class_init(ObjectClass *klass, void *data)
2100{
2101 DeviceClass *dc = DEVICE_CLASS(klass);
2102 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2103 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951
MA		 2104
2105 k->realize = virtio_scsi_pci_realize;
125ee0ed 2106 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
bc7b90a0
FK		 2107 dc->props = virtio_scsi_pci_properties;
2108 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2109 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
2110 pcidev_k->revision = 0x00;
2111 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2112}
2113
2114static void virtio_scsi_pci_instance_init(Object *obj)
2115{
2116 VirtIOSCSIPCI *dev = VIRTIO_SCSI_PCI(obj);
c8075caf
GA		 2117
2118 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2119 TYPE_VIRTIO_SCSI);
bc7b90a0
FK		 2120}
2121
2122static const TypeInfo virtio_scsi_pci_info = {
2123 .name = TYPE_VIRTIO_SCSI_PCI,
2124 .parent = TYPE_VIRTIO_PCI,
2125 .instance_size = sizeof(VirtIOSCSIPCI),
2126 .instance_init = virtio_scsi_pci_instance_init,
2127 .class_init = virtio_scsi_pci_class_init,
2128};
2129
50787628
NB		 2130/* vhost-scsi-pci */
2131
2132#ifdef CONFIG_VHOST_SCSI
2133static Property vhost_scsi_pci_properties[] = {
2134 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2135 DEV_NVECTORS_UNSPECIFIED),
50787628
NB		 2136 DEFINE_PROP_END_OF_LIST(),
2137};
2138
fc079951 2139static void vhost_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
50787628
NB		 2140{
2141 VHostSCSIPCI *dev = VHOST_SCSI_PCI(vpci_dev);
2142 DeviceState *vdev = DEVICE(&dev->vdev);
2143 VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
2144
2145 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2146 vpci_dev->nvectors = vs->conf.num_queues + 3;
2147 }
2148
2149 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2150 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
50787628
NB		 2151}
2152
2153static void vhost_scsi_pci_class_init(ObjectClass *klass, void *data)
2154{
2155 DeviceClass *dc = DEVICE_CLASS(klass);
2156 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2157 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951 2158 k->realize = vhost_scsi_pci_realize;
125ee0ed 2159 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
50787628
NB		 2160 dc->props = vhost_scsi_pci_properties;
2161 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2162 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
2163 pcidev_k->revision = 0x00;
2164 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2165}
2166
2167static void vhost_scsi_pci_instance_init(Object *obj)
2168{
2169 VHostSCSIPCI *dev = VHOST_SCSI_PCI(obj);
c8075caf
GA		 2170
2171 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2172 TYPE_VHOST_SCSI);
d4433f32
GA		 2173 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2174 "bootindex", &error_abort);
50787628
NB		 2175}
2176
2177static const TypeInfo vhost_scsi_pci_info = {
2178 .name = TYPE_VHOST_SCSI_PCI,
2179 .parent = TYPE_VIRTIO_PCI,
2180 .instance_size = sizeof(VHostSCSIPCI),
2181 .instance_init = vhost_scsi_pci_instance_init,
2182 .class_init = vhost_scsi_pci_class_init,
2183};
2184#endif
2185
e6a74868 2186#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
f12c1ebd
FF		 2187/* vhost-user-scsi-pci */
2188static Property vhost_user_scsi_pci_properties[] = {
2189 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2190 DEV_NVECTORS_UNSPECIFIED),
2191 DEFINE_PROP_END_OF_LIST(),
2192};
2193
2194static void vhost_user_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2195{
2196 VHostUserSCSIPCI *dev = VHOST_USER_SCSI_PCI(vpci_dev);
2197 DeviceState *vdev = DEVICE(&dev->vdev);
2198 VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
2199
2200 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2201 vpci_dev->nvectors = vs->conf.num_queues + 3;
2202 }
2203
2204 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
2205 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2206}
2207
2208static void vhost_user_scsi_pci_class_init(ObjectClass *klass, void *data)
2209{
2210 DeviceClass *dc = DEVICE_CLASS(klass);
2211 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2212 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2213 k->realize = vhost_user_scsi_pci_realize;
2214 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2215 dc->props = vhost_user_scsi_pci_properties;
2216 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2217 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
2218 pcidev_k->revision = 0x00;
2219 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2220}
2221
2222static void vhost_user_scsi_pci_instance_init(Object *obj)
2223{
2224 VHostUserSCSIPCI *dev = VHOST_USER_SCSI_PCI(obj);
2225
2226 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2227 TYPE_VHOST_USER_SCSI);
2228 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2229 "bootindex", &error_abort);
2230}
2231
2232static const TypeInfo vhost_user_scsi_pci_info = {
2233 .name = TYPE_VHOST_USER_SCSI_PCI,
2234 .parent = TYPE_VIRTIO_PCI,
2235 .instance_size = sizeof(VHostUserSCSIPCI),
2236 .instance_init = vhost_user_scsi_pci_instance_init,
2237 .class_init = vhost_user_scsi_pci_class_init,
2238};
2239#endif
2240
fc0b9b0e
SH		 2241/* vhost-vsock-pci */
2242
2243#ifdef CONFIG_VHOST_VSOCK
2244static Property vhost_vsock_pci_properties[] = {
2245 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
2246 DEFINE_PROP_END_OF_LIST(),
2247};
2248
2249static void vhost_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2250{
2251 VHostVSockPCI *dev = VHOST_VSOCK_PCI(vpci_dev);
2252 DeviceState *vdev = DEVICE(&dev->vdev);
2253
2254 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
2255 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2256}
2257
2258static void vhost_vsock_pci_class_init(ObjectClass *klass, void *data)
2259{
2260 DeviceClass *dc = DEVICE_CLASS(klass);
2261 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2262 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2263 k->realize = vhost_vsock_pci_realize;
2264 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
2265 dc->props = vhost_vsock_pci_properties;
2266 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2267 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_VSOCK;
2268 pcidev_k->revision = 0x00;
2269 pcidev_k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
2270}
2271
2272static void vhost_vsock_pci_instance_init(Object *obj)
2273{
2274 VHostVSockPCI *dev = VHOST_VSOCK_PCI(obj);
2275
2276 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2277 TYPE_VHOST_VSOCK);
2278}
2279
2280static const TypeInfo vhost_vsock_pci_info = {
2281 .name = TYPE_VHOST_VSOCK_PCI,
2282 .parent = TYPE_VIRTIO_PCI,
2283 .instance_size = sizeof(VHostVSockPCI),
2284 .instance_init = vhost_vsock_pci_instance_init,
2285 .class_init = vhost_vsock_pci_class_init,
2286};
2287#endif
2288
e378e88d
FK		 2289/* virtio-balloon-pci */
2290
2291static Property virtio_balloon_pci_properties[] = {
c7bcc85d 2292 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
e378e88d
FK		 2293 DEFINE_PROP_END_OF_LIST(),
2294};
2295
fc079951 2296static void virtio_balloon_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
e378e88d
FK		 2297{
2298 VirtIOBalloonPCI *dev = VIRTIO_BALLOON_PCI(vpci_dev);
2299 DeviceState *vdev = DEVICE(&dev->vdev);
2300
2301 if (vpci_dev->class_code != PCI_CLASS_OTHERS &&
2302 vpci_dev->class_code != PCI_CLASS_MEMORY_RAM) { /* qemu < 1.1 */
2303 vpci_dev->class_code = PCI_CLASS_OTHERS;
2304 }
2305
2306 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2307 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
e378e88d
FK		 2308}
2309
2310static void virtio_balloon_pci_class_init(ObjectClass *klass, void *data)
2311{
2312 DeviceClass *dc = DEVICE_CLASS(klass);
2313 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2314 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951 2315 k->realize = virtio_balloon_pci_realize;
125ee0ed 2316 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
e378e88d
FK		 2317 dc->props = virtio_balloon_pci_properties;
2318 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2319 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BALLOON;
2320 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2321 pcidev_k->class_id = PCI_CLASS_OTHERS;
2322}
2323
2324static void virtio_balloon_pci_instance_init(Object *obj)
2325{
2326 VirtIOBalloonPCI *dev = VIRTIO_BALLOON_PCI(obj);
39b87c7b 2327
a6027b0f
DL		 2328 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2329 TYPE_VIRTIO_BALLOON);
39b87c7b
SZ		 2330 object_property_add_alias(obj, "guest-stats", OBJECT(&dev->vdev),
2331 "guest-stats", &error_abort);
2332 object_property_add_alias(obj, "guest-stats-polling-interval",
2333 OBJECT(&dev->vdev),
2334 "guest-stats-polling-interval", &error_abort);
e378e88d
FK		 2335}
2336
2337static const TypeInfo virtio_balloon_pci_info = {
2338 .name = TYPE_VIRTIO_BALLOON_PCI,
2339 .parent = TYPE_VIRTIO_PCI,
2340 .instance_size = sizeof(VirtIOBalloonPCI),
2341 .instance_init = virtio_balloon_pci_instance_init,
2342 .class_init = virtio_balloon_pci_class_init,
2343};
2344
f7f7464a
FK		 2345/* virtio-serial-pci */
2346
fc079951 2347static void virtio_serial_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
f7f7464a
FK		 2348{
2349 VirtIOSerialPCI *dev = VIRTIO_SERIAL_PCI(vpci_dev);
2350 DeviceState *vdev = DEVICE(&dev->vdev);
80270a19
FK		 2351 DeviceState *proxy = DEVICE(vpci_dev);
2352 char *bus_name;
f7f7464a
FK		 2353
2354 if (vpci_dev->class_code != PCI_CLASS_COMMUNICATION_OTHER &&
2355 vpci_dev->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */
2356 vpci_dev->class_code != PCI_CLASS_OTHERS) { /* qemu-kvm */
2357 vpci_dev->class_code = PCI_CLASS_COMMUNICATION_OTHER;
2358 }
2359
2360 /* backwards-compatibility with machines that were created with
2361 DEV_NVECTORS_UNSPECIFIED */
2362 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2363 vpci_dev->nvectors = dev->vdev.serial.max_virtserial_ports + 1;
2364 }
2365
80270a19
FK		 2366 /*
2367 * For command line compatibility, this sets the virtio-serial-device bus
2368 * name as before.
2369 */
2370 if (proxy->id) {
2371 bus_name = g_strdup_printf("%s.0", proxy->id);
2372 virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name);
2373 g_free(bus_name);
2374 }
2375
f7f7464a 2376 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2377 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
f7f7464a
FK		 2378}
2379
2380static Property virtio_serial_pci_properties[] = {
2381 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
2382 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
2383 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
c7bcc85d 2384 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
f7f7464a
FK		 2385 DEFINE_PROP_END_OF_LIST(),
2386};
2387
2388static void virtio_serial_pci_class_init(ObjectClass *klass, void *data)
2389{
2390 DeviceClass *dc = DEVICE_CLASS(klass);
2391 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2392 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951 2393 k->realize = virtio_serial_pci_realize;
125ee0ed 2394 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
f7f7464a
FK		 2395 dc->props = virtio_serial_pci_properties;
2396 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2397 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_CONSOLE;
2398 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2399 pcidev_k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
2400}
2401
2402static void virtio_serial_pci_instance_init(Object *obj)
2403{
2404 VirtIOSerialPCI *dev = VIRTIO_SERIAL_PCI(obj);
c8075caf
GA		 2405
2406 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2407 TYPE_VIRTIO_SERIAL);
f7f7464a
FK		 2408}
2409
2410static const TypeInfo virtio_serial_pci_info = {
2411 .name = TYPE_VIRTIO_SERIAL_PCI,
2412 .parent = TYPE_VIRTIO_PCI,
2413 .instance_size = sizeof(VirtIOSerialPCI),
2414 .instance_init = virtio_serial_pci_instance_init,
2415 .class_init = virtio_serial_pci_class_init,
2416};
2417
e37da394
FK		 2418/* virtio-net-pci */
2419
2420static Property virtio_net_properties[] = {
2421 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
4a3f03ba 2422 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
e37da394 2423 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
e37da394
FK		 2424 DEFINE_PROP_END_OF_LIST(),
2425};
2426
fc079951 2427static void virtio_net_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
e37da394 2428{
800ced8c 2429 DeviceState *qdev = DEVICE(vpci_dev);
e37da394
FK		 2430 VirtIONetPCI *dev = VIRTIO_NET_PCI(vpci_dev);
2431 DeviceState *vdev = DEVICE(&dev->vdev);
2432
800ced8c
FK		 2433 virtio_net_set_netclient_name(&dev->vdev, qdev->id,
2434 object_get_typename(OBJECT(qdev)));
e37da394 2435 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2436 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
e37da394
FK		 2437}
2438
2439static void virtio_net_pci_class_init(ObjectClass *klass, void *data)
2440{
2441 DeviceClass *dc = DEVICE_CLASS(klass);
2442 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2443 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
2444
2445 k->romfile = "efi-virtio.rom";
2446 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2447 k->device_id = PCI_DEVICE_ID_VIRTIO_NET;
2448 k->revision = VIRTIO_PCI_ABI_VERSION;
2449 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
125ee0ed 2450 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
e37da394 2451 dc->props = virtio_net_properties;
fc079951 2452 vpciklass->realize = virtio_net_pci_realize;
e37da394
FK		 2453}
2454
2455static void virtio_net_pci_instance_init(Object *obj)
2456{
2457 VirtIONetPCI *dev = VIRTIO_NET_PCI(obj);
c8075caf
GA		 2458
2459 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2460 TYPE_VIRTIO_NET);
0cf63c3e
GA		 2461 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2462 "bootindex", &error_abort);
e37da394
FK		 2463}
2464
2465static const TypeInfo virtio_net_pci_info = {
2466 .name = TYPE_VIRTIO_NET_PCI,
2467 .parent = TYPE_VIRTIO_PCI,
2468 .instance_size = sizeof(VirtIONetPCI),
2469 .instance_init = virtio_net_pci_instance_init,
2470 .class_init = virtio_net_pci_class_init,
2471};
2472
59ccd20a
FK		 2473/* virtio-rng-pci */
2474
fc079951 2475static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
59ccd20a
FK		 2476{
2477 VirtIORngPCI *vrng = VIRTIO_RNG_PCI(vpci_dev);
2478 DeviceState *vdev = DEVICE(&vrng->vdev);
fc079951 2479 Error *err = NULL;
59ccd20a
FK		 2480
2481 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951
MA		 2482 object_property_set_bool(OBJECT(vdev), true, "realized", &err);
2483 if (err) {
2484 error_propagate(errp, err);
2485 return;
59ccd20a
FK		 2486 }
2487
2488 object_property_set_link(OBJECT(vrng),
5b456438 2489 OBJECT(vrng->vdev.conf.rng), "rng",
59ccd20a 2490 NULL);
59ccd20a
FK		 2491}
2492
2493static void virtio_rng_pci_class_init(ObjectClass *klass, void *data)
2494{
2495 DeviceClass *dc = DEVICE_CLASS(klass);
2496 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2497 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2498
fc079951 2499 k->realize = virtio_rng_pci_realize;
125ee0ed 2500 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
59ccd20a
FK		 2501
2502 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2503 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_RNG;
2504 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2505 pcidev_k->class_id = PCI_CLASS_OTHERS;
2506}
2507
2508static void virtio_rng_initfn(Object *obj)
2509{
2510 VirtIORngPCI *dev = VIRTIO_RNG_PCI(obj);
c8075caf
GA		 2511
2512 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2513 TYPE_VIRTIO_RNG);
59ccd20a
FK		 2514}
2515
2516static const TypeInfo virtio_rng_pci_info = {
2517 .name = TYPE_VIRTIO_RNG_PCI,
2518 .parent = TYPE_VIRTIO_PCI,
2519 .instance_size = sizeof(VirtIORngPCI),
2520 .instance_init = virtio_rng_initfn,
2521 .class_init = virtio_rng_pci_class_init,
2522};
2523
f958c8aa
GH		 2524/* virtio-input-pci */
2525
6f2b9a5b 2526static Property virtio_input_pci_properties[] = {
710e2d90
GH		 2527 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
2528 DEFINE_PROP_END_OF_LIST(),
2529};
2530
f958c8aa
GH		 2531static void virtio_input_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2532{
2533 VirtIOInputPCI *vinput = VIRTIO_INPUT_PCI(vpci_dev);
2534 DeviceState *vdev = DEVICE(&vinput->vdev);
2535
2536 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
9a4c0e22 2537 virtio_pci_force_virtio_1(vpci_dev);
f958c8aa
GH		 2538 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2539}
2540
2541static void virtio_input_pci_class_init(ObjectClass *klass, void *data)
2542{
2543 DeviceClass *dc = DEVICE_CLASS(klass);
2544 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2545 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2546
6f2b9a5b 2547 dc->props = virtio_input_pci_properties;
f958c8aa
GH		 2548 k->realize = virtio_input_pci_realize;
2549 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
2550
2551 pcidev_k->class_id = PCI_CLASS_INPUT_OTHER;
2552}
2553
710e2d90
GH		 2554static void virtio_input_hid_kbd_pci_class_init(ObjectClass *klass, void *data)
2555{
2556 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2557
2558 pcidev_k->class_id = PCI_CLASS_INPUT_KEYBOARD;
2559}
2560
2561static void virtio_input_hid_mouse_pci_class_init(ObjectClass *klass,
2562 void *data)
2563{
2564 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2565
2566 pcidev_k->class_id = PCI_CLASS_INPUT_MOUSE;
2567}
2568
2569static void virtio_keyboard_initfn(Object *obj)
2570{
2571 VirtIOInputHIDPCI *dev = VIRTIO_INPUT_HID_PCI(obj);
6f2b9a5b
GH		 2572
2573 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2574 TYPE_VIRTIO_KEYBOARD);
710e2d90
GH		 2575}
2576
2577static void virtio_mouse_initfn(Object *obj)
2578{
2579 VirtIOInputHIDPCI *dev = VIRTIO_INPUT_HID_PCI(obj);
6f2b9a5b
GH		 2580
2581 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2582 TYPE_VIRTIO_MOUSE);
710e2d90
GH		 2583}
2584
2585static void virtio_tablet_initfn(Object *obj)
2586{
2587 VirtIOInputHIDPCI *dev = VIRTIO_INPUT_HID_PCI(obj);
6f2b9a5b
GH		 2588
2589 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2590 TYPE_VIRTIO_TABLET);
710e2d90
GH		 2591}
2592
f958c8aa
GH		 2593static const TypeInfo virtio_input_pci_info = {
2594 .name = TYPE_VIRTIO_INPUT_PCI,
2595 .parent = TYPE_VIRTIO_PCI,
2596 .instance_size = sizeof(VirtIOInputPCI),
2597 .class_init = virtio_input_pci_class_init,
2598 .abstract = true,
2599};
2600
710e2d90
GH		 2601static const TypeInfo virtio_input_hid_pci_info = {
2602 .name = TYPE_VIRTIO_INPUT_HID_PCI,
2603 .parent = TYPE_VIRTIO_INPUT_PCI,
2604 .instance_size = sizeof(VirtIOInputHIDPCI),
710e2d90
GH		 2605 .abstract = true,
2606};
2607
2608static const TypeInfo virtio_keyboard_pci_info = {
2609 .name = TYPE_VIRTIO_KEYBOARD_PCI,
2610 .parent = TYPE_VIRTIO_INPUT_HID_PCI,
2611 .class_init = virtio_input_hid_kbd_pci_class_init,
2612 .instance_size = sizeof(VirtIOInputHIDPCI),
2613 .instance_init = virtio_keyboard_initfn,
2614};
2615
2616static const TypeInfo virtio_mouse_pci_info = {
2617 .name = TYPE_VIRTIO_MOUSE_PCI,
2618 .parent = TYPE_VIRTIO_INPUT_HID_PCI,
2619 .class_init = virtio_input_hid_mouse_pci_class_init,
2620 .instance_size = sizeof(VirtIOInputHIDPCI),
2621 .instance_init = virtio_mouse_initfn,
2622};
2623
2624static const TypeInfo virtio_tablet_pci_info = {
2625 .name = TYPE_VIRTIO_TABLET_PCI,
2626 .parent = TYPE_VIRTIO_INPUT_HID_PCI,
2627 .instance_size = sizeof(VirtIOInputHIDPCI),
2628 .instance_init = virtio_tablet_initfn,
2629};
2630
c6047e96
MA		 2631#ifdef CONFIG_LINUX
2632static void virtio_host_initfn(Object *obj)
2633{
2634 VirtIOInputHostPCI *dev = VIRTIO_INPUT_HOST_PCI(obj);
2635
2636 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2637 TYPE_VIRTIO_INPUT_HOST);
2638}
2639
006a5ede
GH		 2640static const TypeInfo virtio_host_pci_info = {
2641 .name = TYPE_VIRTIO_INPUT_HOST_PCI,
2642 .parent = TYPE_VIRTIO_INPUT_PCI,
2643 .instance_size = sizeof(VirtIOInputHostPCI),
2644 .instance_init = virtio_host_initfn,
2645};
c6047e96 2646#endif
006a5ede 2647
0a2acf5e
FK		 2648/* virtio-pci-bus */
2649
ac7af112
AF		 2650static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
2651 VirtIOPCIProxy *dev)
0a2acf5e
FK		 2652{
2653 DeviceState *qdev = DEVICE(dev);
f4dd69aa
FK		 2654 char virtio_bus_name[] = "virtio-bus";
2655
fb17dfe0 2656 qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
f4dd69aa 2657 virtio_bus_name);
0a2acf5e
FK		 2658}
2659
2660static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
2661{
2662 BusClass *bus_class = BUS_CLASS(klass);
2663 VirtioBusClass *k = VIRTIO_BUS_CLASS(klass);
2664 bus_class->max_dev = 1;
2665 k->notify = virtio_pci_notify;
2666 k->save_config = virtio_pci_save_config;
2667 k->load_config = virtio_pci_load_config;
2668 k->save_queue = virtio_pci_save_queue;
2669 k->load_queue = virtio_pci_load_queue;
a6df8adf
JW		 2670 k->save_extra_state = virtio_pci_save_extra_state;
2671 k->load_extra_state = virtio_pci_load_extra_state;
2672 k->has_extra_state = virtio_pci_has_extra_state;
0a2acf5e 2673 k->query_guest_notifiers = virtio_pci_query_guest_notifiers;
0a2acf5e 2674 k->set_guest_notifiers = virtio_pci_set_guest_notifiers;
6f80e617 2675 k->set_host_notifier_mr = virtio_pci_set_host_notifier_mr;
0a2acf5e 2676 k->vmstate_change = virtio_pci_vmstate_change;
d1b4259f 2677 k->pre_plugged = virtio_pci_pre_plugged;
085bccb7 2678 k->device_plugged = virtio_pci_device_plugged;
06a13073 2679 k->device_unplugged = virtio_pci_device_unplugged;
e0d686bf 2680 k->query_nvectors = virtio_pci_query_nvectors;
8e93cef1 2681 k->ioeventfd_enabled = virtio_pci_ioeventfd_enabled;
9f06e71a 2682 k->ioeventfd_assign = virtio_pci_ioeventfd_assign;
8607f5c3 2683 k->get_dma_as = virtio_pci_get_dma_as;
0a2acf5e
FK		 2684}
2685
2686static const TypeInfo virtio_pci_bus_info = {
2687 .name = TYPE_VIRTIO_PCI_BUS,
2688 .parent = TYPE_VIRTIO_BUS,
2689 .instance_size = sizeof(VirtioPCIBusState),
2690 .class_init = virtio_pci_bus_class_init,
2691};
2692
83f7d43a 2693static void virtio_pci_register_types(void)
53c25cea 2694{
59ccd20a 2695 type_register_static(&virtio_rng_pci_info);
f958c8aa 2696 type_register_static(&virtio_input_pci_info);
710e2d90
GH		 2697 type_register_static(&virtio_input_hid_pci_info);
2698 type_register_static(&virtio_keyboard_pci_info);
2699 type_register_static(&virtio_mouse_pci_info);
2700 type_register_static(&virtio_tablet_pci_info);
c6047e96 2701#ifdef CONFIG_LINUX
006a5ede 2702 type_register_static(&virtio_host_pci_info);
c6047e96 2703#endif
0a2acf5e 2704 type_register_static(&virtio_pci_bus_info);
085bccb7 2705 type_register_static(&virtio_pci_info);
60653b28 2706#ifdef CONFIG_VIRTFS
234a336f 2707 type_register_static(&virtio_9p_pci_info);
60653b28 2708#endif
653ced07 2709 type_register_static(&virtio_blk_pci_info);
00343e4b
CL		 2710#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
2711 type_register_static(&vhost_user_blk_pci_info);
2712#endif
bc7b90a0 2713 type_register_static(&virtio_scsi_pci_info);
e378e88d 2714 type_register_static(&virtio_balloon_pci_info);
f7f7464a 2715 type_register_static(&virtio_serial_pci_info);
e37da394 2716 type_register_static(&virtio_net_pci_info);
50787628
NB		 2717#ifdef CONFIG_VHOST_SCSI
2718 type_register_static(&vhost_scsi_pci_info);
2719#endif
e6a74868 2720#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
f12c1ebd
FF		 2721 type_register_static(&vhost_user_scsi_pci_info);
2722#endif
fc0b9b0e
SH		 2723#ifdef CONFIG_VHOST_VSOCK
2724 type_register_static(&vhost_vsock_pci_info);
2725#endif
53c25cea
PB		 2726}
2727
83f7d43a 2728type_init(virtio_pci_register_types)
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