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qdev: use device_class_set_parent_realize/unrealize/reset()
[mirror_qemu.git] / hw / virtio / virtio-pci.c
CommitLineData
53c25cea
PB		 1/*
2 * Virtio PCI Bindings
3 *
4 * Copyright IBM, Corp. 2007
5 * Copyright (c) 2009 CodeSourcery
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 * Paul Brook <paul@codesourcery.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 *
6b620ca3
PB		 14 * Contributions after 2012-01-13 are licensed under the terms of the
15 * GNU GPL, version 2 or (at your option) any later version.
53c25cea
PB		 16 */
17
9b8bfe21 18#include "qemu/osdep.h"
53c25cea 19
cbbe4f50 20#include "standard-headers/linux/virtio_pci.h"
0d09e41a
PB		 21#include "hw/virtio/virtio.h"
22#include "hw/virtio/virtio-blk.h"
23#include "hw/virtio/virtio-net.h"
24#include "hw/virtio/virtio-serial.h"
25#include "hw/virtio/virtio-scsi.h"
26#include "hw/virtio/virtio-balloon.h"
f958c8aa 27#include "hw/virtio/virtio-input.h"
83c9f4ca 28#include "hw/pci/pci.h"
da34e65c 29#include "qapi/error.h"
1de7afc9 30#include "qemu/error-report.h"
83c9f4ca
PB		 31#include "hw/pci/msi.h"
32#include "hw/pci/msix.h"
33#include "hw/loader.h"
9c17d615 34#include "sysemu/kvm.h"
4be74634 35#include "sysemu/block-backend.h"
47b43a1f 36#include "virtio-pci.h"
1de7afc9 37#include "qemu/range.h"
0d09e41a 38#include "hw/virtio/virtio-bus.h"
24a6e7f4 39#include "qapi/visitor.h"
53c25cea 40
cbbe4f50 41#define VIRTIO_PCI_REGION_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_present(dev))
aba800a3 42
c17bef33
MT		 43#undef VIRTIO_PCI_CONFIG
44
aba800a3
MT		 45/* The remaining space is defined by each driver as the per-driver
46 * configuration space */
cbbe4f50 47#define VIRTIO_PCI_CONFIG_SIZE(dev) VIRTIO_PCI_CONFIG_OFF(msix_enabled(dev))
53c25cea 48
ac7af112
AF		 49static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
50 VirtIOPCIProxy *dev);
75fd6f13 51static void virtio_pci_reset(DeviceState *qdev);
d51fcfac 52
53c25cea 53/* virtio device */
d2a0ccc6
MT		 54/* DeviceState to VirtIOPCIProxy. For use off data-path. TODO: use QOM. */
55static inline VirtIOPCIProxy *to_virtio_pci_proxy(DeviceState *d)
56{
57 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
58}
53c25cea 59
d2a0ccc6
MT		 60/* DeviceState to VirtIOPCIProxy. Note: used on datapath,
61 * be careful and test performance if you change this.
62 */
63static inline VirtIOPCIProxy *to_virtio_pci_proxy_fast(DeviceState *d)
53c25cea 64{
d2a0ccc6
MT		 65 return container_of(d, VirtIOPCIProxy, pci_dev.qdev);
66}
67
68static void virtio_pci_notify(DeviceState *d, uint16_t vector)
69{
70 VirtIOPCIProxy *proxy = to_virtio_pci_proxy_fast(d);
a3fc66d9 71
aba800a3
MT		 72 if (msix_enabled(&proxy->pci_dev))
73 msix_notify(&proxy->pci_dev, vector);
a3fc66d9
PB		 74 else {
75 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
0687c37c 76 pci_set_irq(&proxy->pci_dev, atomic_read(&vdev->isr) & 1);
a3fc66d9 77 }
53c25cea
PB		 78}
79
d2a0ccc6 80static void virtio_pci_save_config(DeviceState *d, QEMUFile *f)
ff24bd58 81{
d2a0ccc6 82 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 83 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
84
ff24bd58
MT		 85 pci_device_save(&proxy->pci_dev, f);
86 msix_save(&proxy->pci_dev, f);
87 if (msix_present(&proxy->pci_dev))
a3fc66d9 88 qemu_put_be16(f, vdev->config_vector);
ff24bd58
MT		 89}
90
b81b948e
DDAG		 91static const VMStateDescription vmstate_virtio_pci_modern_queue_state = {
92 .name = "virtio_pci/modern_queue_state",
93 .version_id = 1,
94 .minimum_version_id = 1,
95 .fields = (VMStateField[]) {
96 VMSTATE_UINT16(num, VirtIOPCIQueue),
97 VMSTATE_UNUSED(1), /* enabled was stored as be16 */
98 VMSTATE_BOOL(enabled, VirtIOPCIQueue),
99 VMSTATE_UINT32_ARRAY(desc, VirtIOPCIQueue, 2),
100 VMSTATE_UINT32_ARRAY(avail, VirtIOPCIQueue, 2),
101 VMSTATE_UINT32_ARRAY(used, VirtIOPCIQueue, 2),
102 VMSTATE_END_OF_LIST()
a6df8adf 103 }
a6df8adf
JW		 104};
105
106static bool virtio_pci_modern_state_needed(void *opaque)
107{
108 VirtIOPCIProxy *proxy = opaque;
109
9a4c0e22 110 return virtio_pci_modern(proxy);
a6df8adf
JW		 111}
112
b81b948e 113static const VMStateDescription vmstate_virtio_pci_modern_state_sub = {
a6df8adf
JW		 114 .name = "virtio_pci/modern_state",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .needed = &virtio_pci_modern_state_needed,
118 .fields = (VMStateField[]) {
b81b948e
DDAG		 119 VMSTATE_UINT32(dfselect, VirtIOPCIProxy),
120 VMSTATE_UINT32(gfselect, VirtIOPCIProxy),
121 VMSTATE_UINT32_ARRAY(guest_features, VirtIOPCIProxy, 2),
122 VMSTATE_STRUCT_ARRAY(vqs, VirtIOPCIProxy, VIRTIO_QUEUE_MAX, 0,
123 vmstate_virtio_pci_modern_queue_state,
124 VirtIOPCIQueue),
a6df8adf
JW		 125 VMSTATE_END_OF_LIST()
126 }
127};
128
129static const VMStateDescription vmstate_virtio_pci = {
130 .name = "virtio_pci",
131 .version_id = 1,
132 .minimum_version_id = 1,
133 .minimum_version_id_old = 1,
134 .fields = (VMStateField[]) {
135 VMSTATE_END_OF_LIST()
136 },
137 .subsections = (const VMStateDescription*[]) {
b81b948e 138 &vmstate_virtio_pci_modern_state_sub,
a6df8adf
JW		 139 NULL
140 }
141};
142
b81b948e
DDAG		 143static bool virtio_pci_has_extra_state(DeviceState *d)
144{
145 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
146
147 return proxy->flags & VIRTIO_PCI_FLAG_MIGRATE_EXTRA;
148}
149
a6df8adf
JW		 150static void virtio_pci_save_extra_state(DeviceState *d, QEMUFile *f)
151{
152 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
153
154 vmstate_save_state(f, &vmstate_virtio_pci, proxy, NULL);
155}
156
157static int virtio_pci_load_extra_state(DeviceState *d, QEMUFile *f)
158{
159 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
160
161 return vmstate_load_state(f, &vmstate_virtio_pci, proxy, 1);
162}
163
d2a0ccc6 164static void virtio_pci_save_queue(DeviceState *d, int n, QEMUFile *f)
ff24bd58 165{
d2a0ccc6 166 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 167 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
168
ff24bd58 169 if (msix_present(&proxy->pci_dev))
a3fc66d9 170 qemu_put_be16(f, virtio_queue_vector(vdev, n));
ff24bd58
MT		 171}
172
d2a0ccc6 173static int virtio_pci_load_config(DeviceState *d, QEMUFile *f)
ff24bd58 174{
d2a0ccc6 175 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 176 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
177
ff24bd58
MT		 178 int ret;
179 ret = pci_device_load(&proxy->pci_dev, f);
e6da7680 180 if (ret) {
ff24bd58 181 return ret;
e6da7680 182 }
3cac001e 183 msix_unuse_all_vectors(&proxy->pci_dev);
ff24bd58 184 msix_load(&proxy->pci_dev, f);
e6da7680 185 if (msix_present(&proxy->pci_dev)) {
a3fc66d9 186 qemu_get_be16s(f, &vdev->config_vector);
e6da7680 187 } else {
a3fc66d9 188 vdev->config_vector = VIRTIO_NO_VECTOR;
e6da7680 189 }
a3fc66d9
PB		 190 if (vdev->config_vector != VIRTIO_NO_VECTOR) {
191 return msix_vector_use(&proxy->pci_dev, vdev->config_vector);
e6da7680 192 }
ff24bd58
MT		 193 return 0;
194}
195
d2a0ccc6 196static int virtio_pci_load_queue(DeviceState *d, int n, QEMUFile *f)
ff24bd58 197{
d2a0ccc6 198 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 199 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
200
ff24bd58 201 uint16_t vector;
e6da7680
MT		 202 if (msix_present(&proxy->pci_dev)) {
203 qemu_get_be16s(f, &vector);
204 } else {
205 vector = VIRTIO_NO_VECTOR;
206 }
a3fc66d9 207 virtio_queue_set_vector(vdev, n, vector);
e6da7680
MT		 208 if (vector != VIRTIO_NO_VECTOR) {
209 return msix_vector_use(&proxy->pci_dev, vector);
210 }
a6df8adf 211
ff24bd58
MT		 212 return 0;
213}
214
8e93cef1 215static bool virtio_pci_ioeventfd_enabled(DeviceState *d)
9f06e71a
CH		 216{
217 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
218
8e93cef1 219 return (proxy->flags & VIRTIO_PCI_FLAG_USE_IOEVENTFD) != 0;
9f06e71a
CH		 220}
221
975acc0a
JW		 222#define QEMU_VIRTIO_PCI_QUEUE_MEM_MULT 0x1000
223
d9997d89
MA		 224static inline int virtio_pci_queue_mem_mult(struct VirtIOPCIProxy *proxy)
225{
226 return (proxy->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ) ?
227 QEMU_VIRTIO_PCI_QUEUE_MEM_MULT : 4;
228}
229
9f06e71a
CH		 230static int virtio_pci_ioeventfd_assign(DeviceState *d, EventNotifier *notifier,
231 int n, bool assign)
25db9ebe 232{
9f06e71a 233 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 234 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
235 VirtQueue *vq = virtio_get_queue(vdev, n);
9a4c0e22
MA		 236 bool legacy = virtio_pci_legacy(proxy);
237 bool modern = virtio_pci_modern(proxy);
bc85ccfd 238 bool fast_mmio = kvm_ioeventfd_any_length_enabled();
9824d2a3 239 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
588255ad 240 MemoryRegion *modern_mr = &proxy->notify.mr;
9824d2a3 241 MemoryRegion *modern_notify_mr = &proxy->notify_pio.mr;
975acc0a 242 MemoryRegion *legacy_mr = &proxy->bar;
d9997d89 243 hwaddr modern_addr = virtio_pci_queue_mem_mult(proxy) *
975acc0a
JW		 244 virtio_get_queue_index(vq);
245 hwaddr legacy_addr = VIRTIO_PCI_QUEUE_NOTIFY;
da146d0a 246
25db9ebe 247 if (assign) {
975acc0a 248 if (modern) {
bc85ccfd
JW		 249 if (fast_mmio) {
250 memory_region_add_eventfd(modern_mr, modern_addr, 0,
251 false, n, notifier);
252 } else {
253 memory_region_add_eventfd(modern_mr, modern_addr, 2,
254 false, n, notifier);
255 }
9824d2a3
JW		 256 if (modern_pio) {
257 memory_region_add_eventfd(modern_notify_mr, 0, 2,
258 true, n, notifier);
259 }
975acc0a
JW		 260 }
261 if (legacy) {
262 memory_region_add_eventfd(legacy_mr, legacy_addr, 2,
263 true, n, notifier);
264 }
25db9ebe 265 } else {
975acc0a 266 if (modern) {
bc85ccfd
JW		 267 if (fast_mmio) {
268 memory_region_del_eventfd(modern_mr, modern_addr, 0,
269 false, n, notifier);
270 } else {
271 memory_region_del_eventfd(modern_mr, modern_addr, 2,
272 false, n, notifier);
273 }
9824d2a3
JW		 274 if (modern_pio) {
275 memory_region_del_eventfd(modern_notify_mr, 0, 2,
276 true, n, notifier);
277 }
975acc0a
JW		 278 }
279 if (legacy) {
280 memory_region_del_eventfd(legacy_mr, legacy_addr, 2,
281 true, n, notifier);
282 }
25db9ebe 283 }
9f06e71a 284 return 0;
25db9ebe
SH		 285}
286
b36e3914 287static void virtio_pci_start_ioeventfd(VirtIOPCIProxy *proxy)
25db9ebe 288{
9f06e71a 289 virtio_bus_start_ioeventfd(&proxy->bus);
25db9ebe
SH		 290}
291
b36e3914 292static void virtio_pci_stop_ioeventfd(VirtIOPCIProxy *proxy)
25db9ebe 293{
9f06e71a 294 virtio_bus_stop_ioeventfd(&proxy->bus);
25db9ebe
SH		 295}
296
53c25cea
PB		 297static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
298{
299 VirtIOPCIProxy *proxy = opaque;
a3fc66d9 300 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
a8170e5e 301 hwaddr pa;
53c25cea 302
53c25cea
PB		 303 switch (addr) {
304 case VIRTIO_PCI_GUEST_FEATURES:
181103cd
FK		 305 /* Guest does not negotiate properly? We have to assume nothing. */
306 if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
307 val = virtio_bus_get_vdev_bad_features(&proxy->bus);
308 }
ad0c9332 309 virtio_set_features(vdev, val);
53c25cea
PB		 310 break;
311 case VIRTIO_PCI_QUEUE_PFN:
a8170e5e 312 pa = (hwaddr)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
1b8e9b27 313 if (pa == 0) {
75fd6f13 314 virtio_pci_reset(DEVICE(proxy));
1b8e9b27 315 }
7055e687
MT		 316 else
317 virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
53c25cea
PB		 318 break;
319 case VIRTIO_PCI_QUEUE_SEL:
87b3bd1c 320 if (val < VIRTIO_QUEUE_MAX)
53c25cea
PB		 321 vdev->queue_sel = val;
322 break;
323 case VIRTIO_PCI_QUEUE_NOTIFY:
87b3bd1c 324 if (val < VIRTIO_QUEUE_MAX) {
7157e2e2
SH		 325 virtio_queue_notify(vdev, val);
326 }
53c25cea
PB		 327 break;
328 case VIRTIO_PCI_STATUS:
25db9ebe
SH		 329 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
330 virtio_pci_stop_ioeventfd(proxy);
331 }
332
3e607cb5 333 virtio_set_status(vdev, val & 0xFF);
25db9ebe
SH		 334
335 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
336 virtio_pci_start_ioeventfd(proxy);
337 }
338
1b8e9b27 339 if (vdev->status == 0) {
75fd6f13 340 virtio_pci_reset(DEVICE(proxy));
1b8e9b27 341 }
c81131db 342
e43c0b2e
MT		 343 /* Linux before 2.6.34 drives the device without enabling
344 the PCI device bus master bit. Enable it automatically
345 for the guest. This is a PCI spec violation but so is
346 initiating DMA with bus master bit clear. */
347 if (val == (VIRTIO_CONFIG_S_ACKNOWLEDGE | VIRTIO_CONFIG_S_DRIVER)) {
348 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
349 proxy->pci_dev.config[PCI_COMMAND] |
350 PCI_COMMAND_MASTER, 1);
351 }
53c25cea 352 break;
aba800a3
MT		 353 case VIRTIO_MSI_CONFIG_VECTOR:
354 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
355 /* Make it possible for guest to discover an error took place. */
356 if (msix_vector_use(&proxy->pci_dev, val) < 0)
357 val = VIRTIO_NO_VECTOR;
358 vdev->config_vector = val;
359 break;
360 case VIRTIO_MSI_QUEUE_VECTOR:
361 msix_vector_unuse(&proxy->pci_dev,
362 virtio_queue_vector(vdev, vdev->queue_sel));
363 /* Make it possible for guest to discover an error took place. */
364 if (msix_vector_use(&proxy->pci_dev, val) < 0)
365 val = VIRTIO_NO_VECTOR;
366 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
367 break;
368 default:
4e02d460
SH		 369 error_report("%s: unexpected address 0x%x value 0x%x",
370 __func__, addr, val);
aba800a3 371 break;
53c25cea
PB		 372 }
373}
374
aba800a3 375static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
53c25cea 376{
a3fc66d9 377 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
53c25cea
PB		 378 uint32_t ret = 0xFFFFFFFF;
379
53c25cea
PB		 380 switch (addr) {
381 case VIRTIO_PCI_HOST_FEATURES:
6b8f1020 382 ret = vdev->host_features;
53c25cea
PB		 383 break;
384 case VIRTIO_PCI_GUEST_FEATURES:
704a76fc 385 ret = vdev->guest_features;
53c25cea
PB		 386 break;
387 case VIRTIO_PCI_QUEUE_PFN:
388 ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
389 >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
390 break;
391 case VIRTIO_PCI_QUEUE_NUM:
392 ret = virtio_queue_get_num(vdev, vdev->queue_sel);
393 break;
394 case VIRTIO_PCI_QUEUE_SEL:
395 ret = vdev->queue_sel;
396 break;
397 case VIRTIO_PCI_STATUS:
398 ret = vdev->status;
399 break;
400 case VIRTIO_PCI_ISR:
401 /* reading from the ISR also clears it. */
0687c37c 402 ret = atomic_xchg(&vdev->isr, 0);
9e64f8a3 403 pci_irq_deassert(&proxy->pci_dev);
53c25cea 404 break;
aba800a3
MT		 405 case VIRTIO_MSI_CONFIG_VECTOR:
406 ret = vdev->config_vector;
407 break;
408 case VIRTIO_MSI_QUEUE_VECTOR:
409 ret = virtio_queue_vector(vdev, vdev->queue_sel);
410 break;
53c25cea
PB		 411 default:
412 break;
413 }
414
415 return ret;
416}
417
df6db5b3
AG		 418static uint64_t virtio_pci_config_read(void *opaque, hwaddr addr,
419 unsigned size)
53c25cea
PB		 420{
421 VirtIOPCIProxy *proxy = opaque;
a3fc66d9 422 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
cbbe4f50 423 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
df6db5b3 424 uint64_t val = 0;
aba800a3 425 if (addr < config) {
df6db5b3 426 return virtio_ioport_read(proxy, addr);
aba800a3
MT		 427 }
428 addr -= config;
53c25cea 429
df6db5b3
AG		 430 switch (size) {
431 case 1:
a3fc66d9 432 val = virtio_config_readb(vdev, addr);
df6db5b3
AG		 433 break;
434 case 2:
a3fc66d9 435 val = virtio_config_readw(vdev, addr);
616a6552 436 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 437 val = bswap16(val);
438 }
df6db5b3
AG		 439 break;
440 case 4:
a3fc66d9 441 val = virtio_config_readl(vdev, addr);
616a6552 442 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 443 val = bswap32(val);
444 }
df6db5b3 445 break;
82afa586 446 }
df6db5b3 447 return val;
53c25cea
PB		 448}
449
df6db5b3
AG		 450static void virtio_pci_config_write(void *opaque, hwaddr addr,
451 uint64_t val, unsigned size)
53c25cea
PB		 452{
453 VirtIOPCIProxy *proxy = opaque;
cbbe4f50 454 uint32_t config = VIRTIO_PCI_CONFIG_SIZE(&proxy->pci_dev);
a3fc66d9 455 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
aba800a3
MT		 456 if (addr < config) {
457 virtio_ioport_write(proxy, addr, val);
458 return;
459 }
460 addr -= config;
df6db5b3
AG		 461 /*
462 * Virtio-PCI is odd. Ioports are LE but config space is target native
463 * endian.
464 */
465 switch (size) {
466 case 1:
a3fc66d9 467 virtio_config_writeb(vdev, addr, val);
df6db5b3
AG		 468 break;
469 case 2:
616a6552 470 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 471 val = bswap16(val);
472 }
a3fc66d9 473 virtio_config_writew(vdev, addr, val);
df6db5b3
AG		 474 break;
475 case 4:
616a6552 476 if (virtio_is_big_endian(vdev)) {
8e4a424b
BS		 477 val = bswap32(val);
478 }
a3fc66d9 479 virtio_config_writel(vdev, addr, val);
df6db5b3 480 break;
82afa586 481 }
53c25cea
PB		 482}
483
da146d0a 484static const MemoryRegionOps virtio_pci_config_ops = {
df6db5b3
AG		 485 .read = virtio_pci_config_read,
486 .write = virtio_pci_config_write,
487 .impl = {
488 .min_access_size = 1,
489 .max_access_size = 4,
490 },
8e4a424b 491 .endianness = DEVICE_LITTLE_ENDIAN,
da146d0a 492};
aba800a3 493
a93c8d82
AK		 494static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy,
495 hwaddr *off, int len)
496{
497 int i;
498 VirtIOPCIRegion *reg;
499
500 for (i = 0; i < ARRAY_SIZE(proxy->regs); ++i) {
501 reg = &proxy->regs[i];
502 if (*off >= reg->offset &&
503 *off + len <= reg->offset + reg->size) {
504 *off -= reg->offset;
505 return &reg->mr;
506 }
507 }
508
509 return NULL;
510}
511
1e40356c
MT		 512/* Below are generic functions to do memcpy from/to an address space,
513 * without byteswaps, with input validation.
514 *
515 * As regular address_space_* APIs all do some kind of byteswap at least for
516 * some host/target combinations, we are forced to explicitly convert to a
517 * known-endianness integer value.
518 * It doesn't really matter which endian format to go through, so the code
519 * below selects the endian that causes the least amount of work on the given
520 * host.
521 *
522 * Note: host pointer must be aligned.
523 */
524static
a93c8d82 525void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
1e40356c
MT		 526 const uint8_t *buf, int len)
527{
a93c8d82
AK		 528 uint64_t val;
529 MemoryRegion *mr;
1e40356c
MT		 530
531 /* address_space_* APIs assume an aligned address.
532 * As address is under guest control, handle illegal values.
533 */
534 addr &= ~(len - 1);
535
a93c8d82
AK		 536 mr = virtio_address_space_lookup(proxy, &addr, len);
537 if (!mr) {
538 return;
539 }
540
1e40356c
MT		 541 /* Make sure caller aligned buf properly */
542 assert(!(((uintptr_t)buf) & (len - 1)));
543
544 switch (len) {
545 case 1:
546 val = pci_get_byte(buf);
1e40356c
MT		 547 break;
548 case 2:
a93c8d82 549 val = cpu_to_le16(pci_get_word(buf));
1e40356c
MT		 550 break;
551 case 4:
a93c8d82 552 val = cpu_to_le32(pci_get_long(buf));
1e40356c
MT		 553 break;
554 default:
555 /* As length is under guest control, handle illegal values. */
a93c8d82 556 return;
1e40356c 557 }
a93c8d82 558 memory_region_dispatch_write(mr, addr, val, len, MEMTXATTRS_UNSPECIFIED);
1e40356c
MT		 559}
560
561static void
a93c8d82
AK		 562virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
563 uint8_t *buf, int len)
1e40356c 564{
a93c8d82
AK		 565 uint64_t val;
566 MemoryRegion *mr;
1e40356c
MT		 567
568 /* address_space_* APIs assume an aligned address.
569 * As address is under guest control, handle illegal values.
570 */
571 addr &= ~(len - 1);
572
a93c8d82
AK		 573 mr = virtio_address_space_lookup(proxy, &addr, len);
574 if (!mr) {
575 return;
576 }
577
1e40356c
MT		 578 /* Make sure caller aligned buf properly */
579 assert(!(((uintptr_t)buf) & (len - 1)));
580
a93c8d82 581 memory_region_dispatch_read(mr, addr, &val, len, MEMTXATTRS_UNSPECIFIED);
1e40356c
MT		 582 switch (len) {
583 case 1:
1e40356c
MT		 584 pci_set_byte(buf, val);
585 break;
586 case 2:
a93c8d82 587 pci_set_word(buf, le16_to_cpu(val));
1e40356c
MT		 588 break;
589 case 4:
a93c8d82 590 pci_set_long(buf, le32_to_cpu(val));
1e40356c
MT		 591 break;
592 default:
593 /* As length is under guest control, handle illegal values. */
594 break;
595 }
596}
597
aba800a3
MT		 598static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
599 uint32_t val, int len)
600{
ed757e14 601 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
a3fc66d9 602 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
ada434cd 603 struct virtio_pci_cfg_cap *cfg;
ed757e14 604
1129714f
MT		 605 pci_default_write_config(pci_dev, address, val, len);
606
607 if (range_covers_byte(address, len, PCI_COMMAND) &&
68a27b20 608 !(pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
1129714f 609 virtio_pci_stop_ioeventfd(proxy);
45363e46 610 virtio_set_status(vdev, vdev->status & ~VIRTIO_CONFIG_S_DRIVER_OK);
ed757e14 611 }
ada434cd
MT		 612
613 if (proxy->config_cap &&
614 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
615 pci_cfg_data),
616 sizeof cfg->pci_cfg_data)) {
617 uint32_t off;
618 uint32_t len;
619
620 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
621 off = le32_to_cpu(cfg->cap.offset);
622 len = le32_to_cpu(cfg->cap.length);
623
2a639123
MT		 624 if (len == 1 || len == 2 || len == 4) {
625 assert(len <= sizeof cfg->pci_cfg_data);
a93c8d82 626 virtio_address_space_write(proxy, off, cfg->pci_cfg_data, len);
ada434cd
MT		 627 }
628 }
629}
630
631static uint32_t virtio_read_config(PCIDevice *pci_dev,
632 uint32_t address, int len)
633{
634 VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
635 struct virtio_pci_cfg_cap *cfg;
636
637 if (proxy->config_cap &&
638 ranges_overlap(address, len, proxy->config_cap + offsetof(struct virtio_pci_cfg_cap,
639 pci_cfg_data),
640 sizeof cfg->pci_cfg_data)) {
641 uint32_t off;
642 uint32_t len;
643
644 cfg = (void *)(proxy->pci_dev.config + proxy->config_cap);
645 off = le32_to_cpu(cfg->cap.offset);
646 len = le32_to_cpu(cfg->cap.length);
647
2a639123
MT		 648 if (len == 1 || len == 2 || len == 4) {
649 assert(len <= sizeof cfg->pci_cfg_data);
a93c8d82 650 virtio_address_space_read(proxy, off, cfg->pci_cfg_data, len);
ada434cd
MT		 651 }
652 }
653
654 return pci_default_read_config(pci_dev, address, len);
53c25cea
PB		 655}
656
7d37d351
JK		 657static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
658 unsigned int queue_no,
d1f6af6a 659 unsigned int vector)
7d37d351 660{
7d37d351 661 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
15b2bd18 662 int ret;
7d37d351
JK		 663
664 if (irqfd->users == 0) {
d1f6af6a 665 ret = kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_dev);
7d37d351
JK		 666 if (ret < 0) {
667 return ret;
668 }
669 irqfd->virq = ret;
670 }
671 irqfd->users++;
7d37d351
JK		 672 return 0;
673}
674
675static void kvm_virtio_pci_vq_vector_release(VirtIOPCIProxy *proxy,
7d37d351 676 unsigned int vector)
774345f9
MT		 677{
678 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
679 if (--irqfd->users == 0) {
680 kvm_irqchip_release_virq(kvm_state, irqfd->virq);
681 }
682}
683
f1d0f15a
MT		 684static int kvm_virtio_pci_irqfd_use(VirtIOPCIProxy *proxy,
685 unsigned int queue_no,
686 unsigned int vector)
687{
688 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
a3fc66d9
PB		 689 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
690 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
f1d0f15a 691 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
9be38598 692 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, irqfd->virq);
f1d0f15a
MT		 693}
694
695static void kvm_virtio_pci_irqfd_release(VirtIOPCIProxy *proxy,
696 unsigned int queue_no,
697 unsigned int vector)
7d37d351 698{
a3fc66d9
PB		 699 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
700 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
15b2bd18 701 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
7d37d351 702 VirtIOIRQFD *irqfd = &proxy->vector_irqfd[vector];
15b2bd18 703 int ret;
7d37d351 704
1c9b71a7 705 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, irqfd->virq);
7d37d351 706 assert(ret == 0);
f1d0f15a 707}
7d37d351 708
774345f9
MT		 709static int kvm_virtio_pci_vector_use(VirtIOPCIProxy *proxy, int nvqs)
710{
711 PCIDevice *dev = &proxy->pci_dev;
a3fc66d9 712 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 713 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
774345f9
MT		 714 unsigned int vector;
715 int ret, queue_no;
774345f9
MT		 716
717 for (queue_no = 0; queue_no < nvqs; queue_no++) {
718 if (!virtio_queue_get_num(vdev, queue_no)) {
719 break;
720 }
721 vector = virtio_queue_vector(vdev, queue_no);
722 if (vector >= msix_nr_vectors_allocated(dev)) {
723 continue;
724 }
d1f6af6a 725 ret = kvm_virtio_pci_vq_vector_use(proxy, queue_no, vector);
774345f9
MT		 726 if (ret < 0) {
727 goto undo;
7d37d351 728 }
f1d0f15a
MT		 729 /* If guest supports masking, set up irqfd now.
730 * Otherwise, delay until unmasked in the frontend.
731 */
5669655a 732 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
f1d0f15a
MT		 733 ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
734 if (ret < 0) {
735 kvm_virtio_pci_vq_vector_release(proxy, vector);
736 goto undo;
737 }
738 }
7d37d351 739 }
7d37d351 740 return 0;
774345f9
MT		 741
742undo:
743 while (--queue_no >= 0) {
744 vector = virtio_queue_vector(vdev, queue_no);
745 if (vector >= msix_nr_vectors_allocated(dev)) {
746 continue;
747 }
5669655a 748 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
e387f99e 749 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
f1d0f15a 750 }
774345f9
MT		 751 kvm_virtio_pci_vq_vector_release(proxy, vector);
752 }
753 return ret;
7d37d351
JK		 754}
755
774345f9
MT		 756static void kvm_virtio_pci_vector_release(VirtIOPCIProxy *proxy, int nvqs)
757{
758 PCIDevice *dev = &proxy->pci_dev;
a3fc66d9 759 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
774345f9
MT		 760 unsigned int vector;
761 int queue_no;
181103cd 762 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
774345f9
MT		 763
764 for (queue_no = 0; queue_no < nvqs; queue_no++) {
765 if (!virtio_queue_get_num(vdev, queue_no)) {
766 break;
767 }
768 vector = virtio_queue_vector(vdev, queue_no);
769 if (vector >= msix_nr_vectors_allocated(dev)) {
770 continue;
771 }
f1d0f15a
MT		 772 /* If guest supports masking, clean up irqfd now.
773 * Otherwise, it was cleaned when masked in the frontend.
774 */
5669655a 775 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
e387f99e 776 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
f1d0f15a 777 }
774345f9
MT		 778 kvm_virtio_pci_vq_vector_release(proxy, vector);
779 }
780}
781
a38b2c49
MT		 782static int virtio_pci_vq_vector_unmask(VirtIOPCIProxy *proxy,
783 unsigned int queue_no,
784 unsigned int vector,
785 MSIMessage msg)
774345f9 786{
a3fc66d9
PB		 787 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
788 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
789 VirtQueue *vq = virtio_get_queue(vdev, queue_no);
774345f9 790 EventNotifier *n = virtio_queue_get_guest_notifier(vq);
a38b2c49 791 VirtIOIRQFD *irqfd;
53510bfc 792 int ret = 0;
774345f9 793
a38b2c49
MT		 794 if (proxy->vector_irqfd) {
795 irqfd = &proxy->vector_irqfd[vector];
796 if (irqfd->msg.data != msg.data || irqfd->msg.address != msg.address) {
dc9f06ca
PF		 797 ret = kvm_irqchip_update_msi_route(kvm_state, irqfd->virq, msg,
798 &proxy->pci_dev);
a38b2c49
MT		 799 if (ret < 0) {
800 return ret;
801 }
3f1fea0f 802 kvm_irqchip_commit_routes(kvm_state);
774345f9
MT		 803 }
804 }
805
f1d0f15a
MT		 806 /* If guest supports masking, irqfd is already setup, unmask it.
807 * Otherwise, set it up now.
808 */
5669655a 809 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
a3fc66d9 810 k->guest_notifier_mask(vdev, queue_no, false);
f1d0f15a 811 /* Test after unmasking to avoid losing events. */
181103cd 812 if (k->guest_notifier_pending &&
a3fc66d9 813 k->guest_notifier_pending(vdev, queue_no)) {
f1d0f15a
MT		 814 event_notifier_set(n);
815 }
816 } else {
817 ret = kvm_virtio_pci_irqfd_use(proxy, queue_no, vector);
7d37d351 818 }
774345f9 819 return ret;
7d37d351
JK		 820}
821
a38b2c49 822static void virtio_pci_vq_vector_mask(VirtIOPCIProxy *proxy,
7d37d351
JK		 823 unsigned int queue_no,
824 unsigned int vector)
825{
a3fc66d9
PB		 826 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
827 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
181103cd 828
f1d0f15a
MT		 829 /* If guest supports masking, keep irqfd but mask it.
830 * Otherwise, clean it up now.
831 */
5669655a 832 if (vdev->use_guest_notifier_mask && k->guest_notifier_mask) {
a3fc66d9 833 k->guest_notifier_mask(vdev, queue_no, true);
f1d0f15a 834 } else {
e387f99e 835 kvm_virtio_pci_irqfd_release(proxy, queue_no, vector);
f1d0f15a 836 }
7d37d351
JK		 837}
838
a38b2c49
MT		 839static int virtio_pci_vector_unmask(PCIDevice *dev, unsigned vector,
840 MSIMessage msg)
7d37d351
JK		 841{
842 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 843 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
851c2a75
JW		 844 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
845 int ret, index, unmasked = 0;
7d37d351 846
851c2a75
JW		 847 while (vq) {
848 index = virtio_get_queue_index(vq);
849 if (!virtio_queue_get_num(vdev, index)) {
7d37d351
JK		 850 break;
851 }
6652d081
JW		 852 if (index < proxy->nvqs_with_notifiers) {
853 ret = virtio_pci_vq_vector_unmask(proxy, index, vector, msg);
854 if (ret < 0) {
855 goto undo;
856 }
857 ++unmasked;
7d37d351 858 }
851c2a75 859 vq = virtio_vector_next_queue(vq);
7d37d351 860 }
851c2a75 861
7d37d351
JK		 862 return 0;
863
864undo:
851c2a75 865 vq = virtio_vector_first_queue(vdev, vector);
6652d081 866 while (vq && unmasked >= 0) {
851c2a75 867 index = virtio_get_queue_index(vq);
6652d081
JW		 868 if (index < proxy->nvqs_with_notifiers) {
869 virtio_pci_vq_vector_mask(proxy, index, vector);
870 --unmasked;
871 }
851c2a75 872 vq = virtio_vector_next_queue(vq);
7d37d351
JK		 873 }
874 return ret;
875}
876
a38b2c49 877static void virtio_pci_vector_mask(PCIDevice *dev, unsigned vector)
7d37d351
JK		 878{
879 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 880 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
851c2a75
JW		 881 VirtQueue *vq = virtio_vector_first_queue(vdev, vector);
882 int index;
7d37d351 883
851c2a75
JW		 884 while (vq) {
885 index = virtio_get_queue_index(vq);
886 if (!virtio_queue_get_num(vdev, index)) {
7d37d351
JK		 887 break;
888 }
6652d081
JW		 889 if (index < proxy->nvqs_with_notifiers) {
890 virtio_pci_vq_vector_mask(proxy, index, vector);
891 }
851c2a75 892 vq = virtio_vector_next_queue(vq);
7d37d351
JK		 893 }
894}
895
a38b2c49
MT		 896static void virtio_pci_vector_poll(PCIDevice *dev,
897 unsigned int vector_start,
898 unsigned int vector_end)
89d62be9
MT		 899{
900 VirtIOPCIProxy *proxy = container_of(dev, VirtIOPCIProxy, pci_dev);
a3fc66d9 901 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 902 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
89d62be9
MT		 903 int queue_no;
904 unsigned int vector;
905 EventNotifier *notifier;
906 VirtQueue *vq;
907
2d620f59 908 for (queue_no = 0; queue_no < proxy->nvqs_with_notifiers; queue_no++) {
89d62be9
MT		 909 if (!virtio_queue_get_num(vdev, queue_no)) {
910 break;
911 }
912 vector = virtio_queue_vector(vdev, queue_no);
913 if (vector < vector_start || vector >= vector_end ||
914 !msix_is_masked(dev, vector)) {
915 continue;
916 }
917 vq = virtio_get_queue(vdev, queue_no);
918 notifier = virtio_queue_get_guest_notifier(vq);
181103cd
FK		 919 if (k->guest_notifier_pending) {
920 if (k->guest_notifier_pending(vdev, queue_no)) {
f1d0f15a
MT		 921 msix_set_pending(dev, vector);
922 }
923 } else if (event_notifier_test_and_clear(notifier)) {
89d62be9
MT		 924 msix_set_pending(dev, vector);
925 }
926 }
927}
928
929static int virtio_pci_set_guest_notifier(DeviceState *d, int n, bool assign,
930 bool with_irqfd)
ade80dc8 931{
d2a0ccc6 932 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9
PB		 933 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
934 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
935 VirtQueue *vq = virtio_get_queue(vdev, n);
ade80dc8
MT		 936 EventNotifier *notifier = virtio_queue_get_guest_notifier(vq);
937
938 if (assign) {
939 int r = event_notifier_init(notifier, 0);
940 if (r < 0) {
941 return r;
942 }
89d62be9 943 virtio_queue_set_guest_notifier_fd_handler(vq, true, with_irqfd);
ade80dc8 944 } else {
89d62be9 945 virtio_queue_set_guest_notifier_fd_handler(vq, false, with_irqfd);
ade80dc8
MT		 946 event_notifier_cleanup(notifier);
947 }
948
5669655a
VK		 949 if (!msix_enabled(&proxy->pci_dev) &&
950 vdev->use_guest_notifier_mask &&
951 vdc->guest_notifier_mask) {
a3fc66d9 952 vdc->guest_notifier_mask(vdev, n, !assign);
62c96360
MT		 953 }
954
ade80dc8
MT		 955 return 0;
956}
957
d2a0ccc6 958static bool virtio_pci_query_guest_notifiers(DeviceState *d)
5430a28f 959{
d2a0ccc6 960 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
5430a28f
MT		 961 return msix_enabled(&proxy->pci_dev);
962}
963
2d620f59 964static int virtio_pci_set_guest_notifiers(DeviceState *d, int nvqs, bool assign)
54dd9321 965{
d2a0ccc6 966 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 967 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
181103cd 968 VirtioDeviceClass *k = VIRTIO_DEVICE_GET_CLASS(vdev);
54dd9321 969 int r, n;
89d62be9
MT		 970 bool with_irqfd = msix_enabled(&proxy->pci_dev) &&
971 kvm_msi_via_irqfd_enabled();
54dd9321 972
87b3bd1c 973 nvqs = MIN(nvqs, VIRTIO_QUEUE_MAX);
2d620f59
MT		 974
975 /* When deassigning, pass a consistent nvqs value
976 * to avoid leaking notifiers.
977 */
978 assert(assign || nvqs == proxy->nvqs_with_notifiers);
979
980 proxy->nvqs_with_notifiers = nvqs;
981
7d37d351 982 /* Must unset vector notifier while guest notifier is still assigned */
181103cd 983 if ((proxy->vector_irqfd || k->guest_notifier_mask) && !assign) {
7d37d351 984 msix_unset_vector_notifiers(&proxy->pci_dev);
a38b2c49
MT		 985 if (proxy->vector_irqfd) {
986 kvm_virtio_pci_vector_release(proxy, nvqs);
987 g_free(proxy->vector_irqfd);
988 proxy->vector_irqfd = NULL;
989 }
7d37d351
JK		 990 }
991
2d620f59 992 for (n = 0; n < nvqs; n++) {
54dd9321
MT		 993 if (!virtio_queue_get_num(vdev, n)) {
994 break;
995 }
996
23fe2b3f 997 r = virtio_pci_set_guest_notifier(d, n, assign, with_irqfd);
54dd9321
MT		 998 if (r < 0) {
999 goto assign_error;
1000 }
1001 }
1002
7d37d351 1003 /* Must set vector notifier after guest notifier has been assigned */
181103cd 1004 if ((with_irqfd || k->guest_notifier_mask) && assign) {
a38b2c49
MT		 1005 if (with_irqfd) {
1006 proxy->vector_irqfd =
1007 g_malloc0(sizeof(*proxy->vector_irqfd) *
1008 msix_nr_vectors_allocated(&proxy->pci_dev));
1009 r = kvm_virtio_pci_vector_use(proxy, nvqs);
1010 if (r < 0) {
1011 goto assign_error;
1012 }
774345f9 1013 }
7d37d351 1014 r = msix_set_vector_notifiers(&proxy->pci_dev,
a38b2c49
MT		 1015 virtio_pci_vector_unmask,
1016 virtio_pci_vector_mask,
1017 virtio_pci_vector_poll);
7d37d351 1018 if (r < 0) {
774345f9 1019 goto notifiers_error;
7d37d351
JK		 1020 }
1021 }
1022
54dd9321
MT		 1023 return 0;
1024
774345f9 1025notifiers_error:
a38b2c49
MT		 1026 if (with_irqfd) {
1027 assert(assign);
1028 kvm_virtio_pci_vector_release(proxy, nvqs);
1029 }
774345f9 1030
54dd9321
MT		 1031assign_error:
1032 /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */
7d37d351 1033 assert(assign);
54dd9321 1034 while (--n >= 0) {
89d62be9 1035 virtio_pci_set_guest_notifier(d, n, !assign, with_irqfd);
54dd9321
MT		 1036 }
1037 return r;
1038}
1039
d2a0ccc6 1040static void virtio_pci_vmstate_change(DeviceState *d, bool running)
25db9ebe 1041{
d2a0ccc6 1042 VirtIOPCIProxy *proxy = to_virtio_pci_proxy(d);
a3fc66d9 1043 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
25db9ebe
SH		 1044
1045 if (running) {
68a27b20
MT		 1046 /* Old QEMU versions did not set bus master enable on status write.
1047 * Detect DRIVER set and enable it.
1048 */
1049 if ((proxy->flags & VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION) &&
1050 (vdev->status & VIRTIO_CONFIG_S_DRIVER) &&
45363e46 1051 !(proxy->pci_dev.config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
68a27b20
MT		 1052 pci_default_write_config(&proxy->pci_dev, PCI_COMMAND,
1053 proxy->pci_dev.config[PCI_COMMAND] |
1054 PCI_COMMAND_MASTER, 1);
89c473fd 1055 }
25db9ebe 1056 virtio_pci_start_ioeventfd(proxy);
ade80dc8 1057 } else {
25db9ebe 1058 virtio_pci_stop_ioeventfd(proxy);
ade80dc8 1059 }
ade80dc8
MT		 1060}
1061
60653b28 1062#ifdef CONFIG_VIRTFS
fc079951 1063static void virtio_9p_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
60653b28 1064{
234a336f
FK		 1065 V9fsPCIState *dev = VIRTIO_9P_PCI(vpci_dev);
1066 DeviceState *vdev = DEVICE(&dev->vdev);
60653b28 1067
234a336f 1068 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 1069 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
60653b28
PB		 1070}
1071
234a336f
FK		 1072static Property virtio_9p_pci_properties[] = {
1073 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
1074 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
60653b28 1075 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
60653b28
PB		 1076 DEFINE_PROP_END_OF_LIST(),
1077};
1078
234a336f 1079static void virtio_9p_pci_class_init(ObjectClass *klass, void *data)
60653b28
PB		 1080{
1081 DeviceClass *dc = DEVICE_CLASS(klass);
234a336f
FK		 1082 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
1083 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
60653b28 1084
fc079951 1085 k->realize = virtio_9p_pci_realize;
234a336f
FK		 1086 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1087 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_9P;
1088 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
1089 pcidev_k->class_id = 0x2;
125ee0ed 1090 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
234a336f 1091 dc->props = virtio_9p_pci_properties;
60653b28
PB		 1092}
1093
234a336f
FK		 1094static void virtio_9p_pci_instance_init(Object *obj)
1095{
1096 V9fsPCIState *dev = VIRTIO_9P_PCI(obj);
c8075caf
GA		 1097
1098 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
1099 TYPE_VIRTIO_9P);
234a336f
FK		 1100}
1101
1102static const TypeInfo virtio_9p_pci_info = {
1103 .name = TYPE_VIRTIO_9P_PCI,
1104 .parent = TYPE_VIRTIO_PCI,
1105 .instance_size = sizeof(V9fsPCIState),
1106 .instance_init = virtio_9p_pci_instance_init,
1107 .class_init = virtio_9p_pci_class_init,
60653b28 1108};
234a336f 1109#endif /* CONFIG_VIRTFS */
60653b28 1110
085bccb7
FK		 1111/*
1112 * virtio-pci: This is the PCIDevice which has a virtio-pci-bus.
1113 */
1114
e0d686bf
JW		 1115static int virtio_pci_query_nvectors(DeviceState *d)
1116{
1117 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1118
1119 return proxy->nvectors;
1120}
1121
8607f5c3
JW		 1122static AddressSpace *virtio_pci_get_dma_as(DeviceState *d)
1123{
1124 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1125 PCIDevice *dev = &proxy->pci_dev;
1126
f0edf239 1127 return pci_get_address_space(dev);
8607f5c3
JW		 1128}
1129
ada434cd 1130static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy,
dfb8e184
MT		 1131 struct virtio_pci_cap *cap)
1132{
1133 PCIDevice *dev = &proxy->pci_dev;
1134 int offset;
1135
9a7c2a59
MZ		 1136 offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0,
1137 cap->cap_len, &error_abort);
dfb8e184
MT		 1138
1139 assert(cap->cap_len >= sizeof *cap);
1140 memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len,
1141 cap->cap_len - PCI_CAP_FLAGS);
ada434cd
MT		 1142
1143 return offset;
dfb8e184
MT		 1144}
1145
dfb8e184
MT		 1146static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr,
1147 unsigned size)
1148{
1149 VirtIOPCIProxy *proxy = opaque;
1150 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1151 uint32_t val = 0;
1152 int i;
1153
1154 switch (addr) {
1155 case VIRTIO_PCI_COMMON_DFSELECT:
1156 val = proxy->dfselect;
1157 break;
1158 case VIRTIO_PCI_COMMON_DF:
1159 if (proxy->dfselect <= 1) {
9b706dbb
MT		 1160 VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev);
1161
1162 val = (vdev->host_features & ~vdc->legacy_features) >>
5f456073 1163 (32 * proxy->dfselect);
dfb8e184
MT		 1164 }
1165 break;
1166 case VIRTIO_PCI_COMMON_GFSELECT:
1167 val = proxy->gfselect;
1168 break;
1169 case VIRTIO_PCI_COMMON_GF:
3750dabc 1170 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
dfb8e184
MT		 1171 val = proxy->guest_features[proxy->gfselect];
1172 }
1173 break;
1174 case VIRTIO_PCI_COMMON_MSIX:
1175 val = vdev->config_vector;
1176 break;
1177 case VIRTIO_PCI_COMMON_NUMQ:
1178 for (i = 0; i < VIRTIO_QUEUE_MAX; ++i) {
1179 if (virtio_queue_get_num(vdev, i)) {
1180 val = i + 1;
1181 }
1182 }
1183 break;
1184 case VIRTIO_PCI_COMMON_STATUS:
1185 val = vdev->status;
1186 break;
1187 case VIRTIO_PCI_COMMON_CFGGENERATION:
b8f05908 1188 val = vdev->generation;
dfb8e184
MT		 1189 break;
1190 case VIRTIO_PCI_COMMON_Q_SELECT:
1191 val = vdev->queue_sel;
1192 break;
1193 case VIRTIO_PCI_COMMON_Q_SIZE:
1194 val = virtio_queue_get_num(vdev, vdev->queue_sel);
1195 break;
1196 case VIRTIO_PCI_COMMON_Q_MSIX:
1197 val = virtio_queue_vector(vdev, vdev->queue_sel);
1198 break;
1199 case VIRTIO_PCI_COMMON_Q_ENABLE:
1200 val = proxy->vqs[vdev->queue_sel].enabled;
1201 break;
1202 case VIRTIO_PCI_COMMON_Q_NOFF:
1203 /* Simply map queues in order */
1204 val = vdev->queue_sel;
1205 break;
1206 case VIRTIO_PCI_COMMON_Q_DESCLO:
1207 val = proxy->vqs[vdev->queue_sel].desc[0];
1208 break;
1209 case VIRTIO_PCI_COMMON_Q_DESCHI:
1210 val = proxy->vqs[vdev->queue_sel].desc[1];
1211 break;
1212 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1213 val = proxy->vqs[vdev->queue_sel].avail[0];
1214 break;
1215 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1216 val = proxy->vqs[vdev->queue_sel].avail[1];
1217 break;
1218 case VIRTIO_PCI_COMMON_Q_USEDLO:
1219 val = proxy->vqs[vdev->queue_sel].used[0];
1220 break;
1221 case VIRTIO_PCI_COMMON_Q_USEDHI:
1222 val = proxy->vqs[vdev->queue_sel].used[1];
1223 break;
1224 default:
1225 val = 0;
1226 }
1227
1228 return val;
1229}
1230
1231static void virtio_pci_common_write(void *opaque, hwaddr addr,
1232 uint64_t val, unsigned size)
1233{
1234 VirtIOPCIProxy *proxy = opaque;
1235 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1236
1237 switch (addr) {
1238 case VIRTIO_PCI_COMMON_DFSELECT:
1239 proxy->dfselect = val;
1240 break;
1241 case VIRTIO_PCI_COMMON_GFSELECT:
1242 proxy->gfselect = val;
1243 break;
1244 case VIRTIO_PCI_COMMON_GF:
3750dabc 1245 if (proxy->gfselect < ARRAY_SIZE(proxy->guest_features)) {
dfb8e184
MT		 1246 proxy->guest_features[proxy->gfselect] = val;
1247 virtio_set_features(vdev,
1248 (((uint64_t)proxy->guest_features[1]) << 32) |
1249 proxy->guest_features[0]);
1250 }
1251 break;
1252 case VIRTIO_PCI_COMMON_MSIX:
1253 msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
1254 /* Make it possible for guest to discover an error took place. */
1255 if (msix_vector_use(&proxy->pci_dev, val) < 0) {
1256 val = VIRTIO_NO_VECTOR;
1257 }
1258 vdev->config_vector = val;
1259 break;
1260 case VIRTIO_PCI_COMMON_STATUS:
1261 if (!(val & VIRTIO_CONFIG_S_DRIVER_OK)) {
1262 virtio_pci_stop_ioeventfd(proxy);
1263 }
1264
1265 virtio_set_status(vdev, val & 0xFF);
1266
1267 if (val & VIRTIO_CONFIG_S_DRIVER_OK) {
1268 virtio_pci_start_ioeventfd(proxy);
1269 }
1270
1271 if (vdev->status == 0) {
75fd6f13 1272 virtio_pci_reset(DEVICE(proxy));
dfb8e184
MT		 1273 }
1274
1275 break;
1276 case VIRTIO_PCI_COMMON_Q_SELECT:
1277 if (val < VIRTIO_QUEUE_MAX) {
1278 vdev->queue_sel = val;
1279 }
1280 break;
1281 case VIRTIO_PCI_COMMON_Q_SIZE:
1282 proxy->vqs[vdev->queue_sel].num = val;
1283 break;
1284 case VIRTIO_PCI_COMMON_Q_MSIX:
1285 msix_vector_unuse(&proxy->pci_dev,
1286 virtio_queue_vector(vdev, vdev->queue_sel));
1287 /* Make it possible for guest to discover an error took place. */
1288 if (msix_vector_use(&proxy->pci_dev, val) < 0) {
1289 val = VIRTIO_NO_VECTOR;
1290 }
1291 virtio_queue_set_vector(vdev, vdev->queue_sel, val);
1292 break;
1293 case VIRTIO_PCI_COMMON_Q_ENABLE:
dfb8e184
MT		 1294 virtio_queue_set_num(vdev, vdev->queue_sel,
1295 proxy->vqs[vdev->queue_sel].num);
1296 virtio_queue_set_rings(vdev, vdev->queue_sel,
1297 ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 |
1298 proxy->vqs[vdev->queue_sel].desc[0],
1299 ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 |
1300 proxy->vqs[vdev->queue_sel].avail[0],
1301 ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 |
1302 proxy->vqs[vdev->queue_sel].used[0]);
393f04d3 1303 proxy->vqs[vdev->queue_sel].enabled = 1;
dfb8e184
MT		 1304 break;
1305 case VIRTIO_PCI_COMMON_Q_DESCLO:
1306 proxy->vqs[vdev->queue_sel].desc[0] = val;
1307 break;
1308 case VIRTIO_PCI_COMMON_Q_DESCHI:
1309 proxy->vqs[vdev->queue_sel].desc[1] = val;
1310 break;
1311 case VIRTIO_PCI_COMMON_Q_AVAILLO:
1312 proxy->vqs[vdev->queue_sel].avail[0] = val;
1313 break;
1314 case VIRTIO_PCI_COMMON_Q_AVAILHI:
1315 proxy->vqs[vdev->queue_sel].avail[1] = val;
1316 break;
1317 case VIRTIO_PCI_COMMON_Q_USEDLO:
1318 proxy->vqs[vdev->queue_sel].used[0] = val;
1319 break;
1320 case VIRTIO_PCI_COMMON_Q_USEDHI:
1321 proxy->vqs[vdev->queue_sel].used[1] = val;
1322 break;
1323 default:
1324 break;
1325 }
1326}
1327
1328
1329static uint64_t virtio_pci_notify_read(void *opaque, hwaddr addr,
1330 unsigned size)
1331{
1332 return 0;
1333}
1334
1335static void virtio_pci_notify_write(void *opaque, hwaddr addr,
1336 uint64_t val, unsigned size)
1337{
1338 VirtIODevice *vdev = opaque;
d9997d89
MA		 1339 VirtIOPCIProxy *proxy = VIRTIO_PCI(DEVICE(vdev)->parent_bus->parent);
1340 unsigned queue = addr / virtio_pci_queue_mem_mult(proxy);
dfb8e184
MT		 1341
1342 if (queue < VIRTIO_QUEUE_MAX) {
1343 virtio_queue_notify(vdev, queue);
1344 }
1345}
1346
9824d2a3
JW		 1347static void virtio_pci_notify_write_pio(void *opaque, hwaddr addr,
1348 uint64_t val, unsigned size)
1349{
1350 VirtIODevice *vdev = opaque;
1351 unsigned queue = val;
1352
1353 if (queue < VIRTIO_QUEUE_MAX) {
1354 virtio_queue_notify(vdev, queue);
1355 }
1356}
1357
dfb8e184
MT		 1358static uint64_t virtio_pci_isr_read(void *opaque, hwaddr addr,
1359 unsigned size)
1360{
1361 VirtIOPCIProxy *proxy = opaque;
1362 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
0687c37c 1363 uint64_t val = atomic_xchg(&vdev->isr, 0);
dfb8e184
MT		 1364 pci_irq_deassert(&proxy->pci_dev);
1365
1366 return val;
1367}
1368
1369static void virtio_pci_isr_write(void *opaque, hwaddr addr,
1370 uint64_t val, unsigned size)
1371{
1372}
1373
1374static uint64_t virtio_pci_device_read(void *opaque, hwaddr addr,
1375 unsigned size)
1376{
1377 VirtIODevice *vdev = opaque;
1378 uint64_t val = 0;
1379
1380 switch (size) {
1381 case 1:
54c720d4 1382 val = virtio_config_modern_readb(vdev, addr);
dfb8e184
MT		 1383 break;
1384 case 2:
54c720d4 1385 val = virtio_config_modern_readw(vdev, addr);
dfb8e184
MT		 1386 break;
1387 case 4:
54c720d4 1388 val = virtio_config_modern_readl(vdev, addr);
dfb8e184
MT		 1389 break;
1390 }
1391 return val;
1392}
1393
1394static void virtio_pci_device_write(void *opaque, hwaddr addr,
1395 uint64_t val, unsigned size)
1396{
1397 VirtIODevice *vdev = opaque;
1398 switch (size) {
1399 case 1:
54c720d4 1400 virtio_config_modern_writeb(vdev, addr, val);
dfb8e184
MT		 1401 break;
1402 case 2:
54c720d4 1403 virtio_config_modern_writew(vdev, addr, val);
dfb8e184
MT		 1404 break;
1405 case 4:
54c720d4 1406 virtio_config_modern_writel(vdev, addr, val);
dfb8e184
MT		 1407 break;
1408 }
1409}
1410
1141ce21
GH		 1411static void virtio_pci_modern_regions_init(VirtIOPCIProxy *proxy)
1412{
1413 static const MemoryRegionOps common_ops = {
1414 .read = virtio_pci_common_read,
1415 .write = virtio_pci_common_write,
1416 .impl = {
1417 .min_access_size = 1,
1418 .max_access_size = 4,
1419 },
1420 .endianness = DEVICE_LITTLE_ENDIAN,
1421 };
1422 static const MemoryRegionOps isr_ops = {
1423 .read = virtio_pci_isr_read,
1424 .write = virtio_pci_isr_write,
1425 .impl = {
1426 .min_access_size = 1,
1427 .max_access_size = 4,
1428 },
1429 .endianness = DEVICE_LITTLE_ENDIAN,
1430 };
1431 static const MemoryRegionOps device_ops = {
1432 .read = virtio_pci_device_read,
1433 .write = virtio_pci_device_write,
1434 .impl = {
1435 .min_access_size = 1,
1436 .max_access_size = 4,
1437 },
1438 .endianness = DEVICE_LITTLE_ENDIAN,
1439 };
1440 static const MemoryRegionOps notify_ops = {
1441 .read = virtio_pci_notify_read,
1442 .write = virtio_pci_notify_write,
1443 .impl = {
1444 .min_access_size = 1,
1445 .max_access_size = 4,
1446 },
1447 .endianness = DEVICE_LITTLE_ENDIAN,
1448 };
9824d2a3
JW		 1449 static const MemoryRegionOps notify_pio_ops = {
1450 .read = virtio_pci_notify_read,
1451 .write = virtio_pci_notify_write_pio,
1452 .impl = {
1453 .min_access_size = 1,
1454 .max_access_size = 4,
1455 },
1456 .endianness = DEVICE_LITTLE_ENDIAN,
1457 };
1458
1141ce21
GH		 1459
1460 memory_region_init_io(&proxy->common.mr, OBJECT(proxy),
1461 &common_ops,
1462 proxy,
b6ce27a5
GH		 1463 "virtio-pci-common",
1464 proxy->common.size);
a3cc2e81 1465
1141ce21
GH		 1466 memory_region_init_io(&proxy->isr.mr, OBJECT(proxy),
1467 &isr_ops,
1468 proxy,
b6ce27a5
GH		 1469 "virtio-pci-isr",
1470 proxy->isr.size);
a3cc2e81 1471
1141ce21
GH		 1472 memory_region_init_io(&proxy->device.mr, OBJECT(proxy),
1473 &device_ops,
1474 virtio_bus_get_device(&proxy->bus),
b6ce27a5
GH		 1475 "virtio-pci-device",
1476 proxy->device.size);
a3cc2e81 1477
1141ce21
GH		 1478 memory_region_init_io(&proxy->notify.mr, OBJECT(proxy),
1479 &notify_ops,
1480 virtio_bus_get_device(&proxy->bus),
1481 "virtio-pci-notify",
b6ce27a5 1482 proxy->notify.size);
9824d2a3
JW		 1483
1484 memory_region_init_io(&proxy->notify_pio.mr, OBJECT(proxy),
1485 &notify_pio_ops,
1486 virtio_bus_get_device(&proxy->bus),
1487 "virtio-pci-notify-pio",
e3aab6c7 1488 proxy->notify_pio.size);
a3cc2e81
GH		 1489}
1490
1491static void virtio_pci_modern_region_map(VirtIOPCIProxy *proxy,
54790d71 1492 VirtIOPCIRegion *region,
9824d2a3
JW		 1493 struct virtio_pci_cap *cap,
1494 MemoryRegion *mr,
1495 uint8_t bar)
a3cc2e81 1496{
9824d2a3 1497 memory_region_add_subregion(mr, region->offset, &region->mr);
54790d71 1498
fc004905 1499 cap->cfg_type = region->type;
9824d2a3 1500 cap->bar = bar;
54790d71 1501 cap->offset = cpu_to_le32(region->offset);
b6ce27a5 1502 cap->length = cpu_to_le32(region->size);
54790d71 1503 virtio_pci_add_mem_cap(proxy, cap);
9824d2a3
JW		 1504
1505}
1506
1507static void virtio_pci_modern_mem_region_map(VirtIOPCIProxy *proxy,
1508 VirtIOPCIRegion *region,
1509 struct virtio_pci_cap *cap)
1510{
1511 virtio_pci_modern_region_map(proxy, region, cap,
7a25126d 1512 &proxy->modern_bar, proxy->modern_mem_bar_idx);
1141ce21 1513}
dfb8e184 1514
9824d2a3
JW		 1515static void virtio_pci_modern_io_region_map(VirtIOPCIProxy *proxy,
1516 VirtIOPCIRegion *region,
1517 struct virtio_pci_cap *cap)
1518{
1519 virtio_pci_modern_region_map(proxy, region, cap,
7a25126d 1520 &proxy->io_bar, proxy->modern_io_bar_idx);
9824d2a3
JW		 1521}
1522
1523static void virtio_pci_modern_mem_region_unmap(VirtIOPCIProxy *proxy,
1524 VirtIOPCIRegion *region)
27462695
MT		 1525{
1526 memory_region_del_subregion(&proxy->modern_bar,
1527 &region->mr);
1528}
1529
9824d2a3
JW		 1530static void virtio_pci_modern_io_region_unmap(VirtIOPCIProxy *proxy,
1531 VirtIOPCIRegion *region)
1532{
1533 memory_region_del_subregion(&proxy->io_bar,
1534 &region->mr);
1535}
1536
d1b4259f
MC		 1537static void virtio_pci_pre_plugged(DeviceState *d, Error **errp)
1538{
1539 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1540 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
1541
1542 if (virtio_pci_modern(proxy)) {
1543 virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1);
1544 }
1545
1546 virtio_add_feature(&vdev->host_features, VIRTIO_F_BAD_FEATURE);
1547}
1548
085bccb7 1549/* This is called by virtio-bus just after the device is plugged. */
e8398045 1550static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
085bccb7
FK		 1551{
1552 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
1553 VirtioBusState *bus = &proxy->bus;
9a4c0e22 1554 bool legacy = virtio_pci_legacy(proxy);
d1b4259f 1555 bool modern;
9824d2a3 1556 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
085bccb7
FK		 1557 uint8_t *config;
1558 uint32_t size;
6b8f1020 1559 VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
085bccb7 1560
d1b4259f
MC		 1561 /*
1562 * Virtio capabilities present without
1563 * VIRTIO_F_VERSION_1 confuses guests
1564 */
66d1c4c1
MC		 1565 if (!proxy->ignore_backend_features &&
1566 !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) {
d1b4259f
MC		 1567 virtio_pci_disable_modern(proxy);
1568
1569 if (!legacy) {
1570 error_setg(errp, "Device doesn't support modern mode, and legacy"
1571 " mode is disabled");
1572 error_append_hint(errp, "Set disable-legacy to off\n");
1573
1574 return;
1575 }
1576 }
1577
1578 modern = virtio_pci_modern(proxy);
1579
085bccb7
FK		 1580 config = proxy->pci_dev.config;
1581 if (proxy->class_code) {
1582 pci_config_set_class(config, proxy->class_code);
1583 }
e266d421
GH		 1584
1585 if (legacy) {
8607f5c3
JW		 1586 if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
1587 error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by"
1588 "neither legacy nor transitional device.");
1589 return ;
1590 }
f2bc54de
LP		 1591 /*
1592 * Legacy and transitional devices use specific subsystem IDs.
1593 * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID)
1594 * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default.
1595 */
e266d421
GH		 1596 pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus));
1597 } else {
1598 /* pure virtio-1.0 */
1599 pci_set_word(config + PCI_VENDOR_ID,
1600 PCI_VENDOR_ID_REDHAT_QUMRANET);
1601 pci_set_word(config + PCI_DEVICE_ID,
1602 0x1040 + virtio_bus_get_vdev_id(bus));
1603 pci_config_set_revision(config, 1);
1604 }
085bccb7
FK		 1605 config[PCI_INTERRUPT_PIN] = 1;
1606
dfb8e184 1607
e266d421 1608 if (modern) {
cc52ea90
GH		 1609 struct virtio_pci_cap cap = {
1610 .cap_len = sizeof cap,
dfb8e184
MT		 1611 };
1612 struct virtio_pci_notify_cap notify = {
dfb8e184 1613 .cap.cap_len = sizeof notify,
dfb8e184 1614 .notify_off_multiplier =
d9997d89 1615 cpu_to_le32(virtio_pci_queue_mem_mult(proxy)),
dfb8e184 1616 };
ada434cd
MT		 1617 struct virtio_pci_cfg_cap cfg = {
1618 .cap.cap_len = sizeof cfg,
1619 .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
1620 };
9824d2a3
JW		 1621 struct virtio_pci_notify_cap notify_pio = {
1622 .cap.cap_len = sizeof notify,
1623 .notify_off_multiplier = cpu_to_le32(0x0),
1624 };
dfb8e184 1625
9824d2a3 1626 struct virtio_pci_cfg_cap *cfg_mask;
dfb8e184 1627
1141ce21 1628 virtio_pci_modern_regions_init(proxy);
9824d2a3
JW		 1629
1630 virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap);
1631 virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap);
1632 virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap);
1633 virtio_pci_modern_mem_region_map(proxy, &proxy->notify, &notify.cap);
1634
1635 if (modern_pio) {
1636 memory_region_init(&proxy->io_bar, OBJECT(proxy),
1637 "virtio-pci-io", 0x4);
1638
7a25126d 1639 pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx,
9824d2a3
JW		 1640 PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar);
1641
1642 virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio,
1643 &notify_pio.cap);
1644 }
ada434cd 1645
7a25126d 1646 pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
4e93a68e
GH		 1647 PCI_BASE_ADDRESS_SPACE_MEMORY |
1648 PCI_BASE_ADDRESS_MEM_PREFETCH |
1649 PCI_BASE_ADDRESS_MEM_TYPE_64,
dfb8e184 1650 &proxy->modern_bar);
ada434cd
MT		 1651
1652 proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
1653 cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
1654 pci_set_byte(&cfg_mask->cap.bar, ~0x0);
1655 pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
1656 pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
1657 pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
dfb8e184
MT		 1658 }
1659
0d583647
RH		 1660 if (proxy->nvectors) {
1661 int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
ee640c62 1662 proxy->msix_bar_idx, NULL);
0d583647 1663 if (err) {
ee640c62 1664 /* Notice when a system that supports MSIx can't initialize it */
0d583647
RH		 1665 if (err != -ENOTSUP) {
1666 error_report("unable to init msix vectors to %" PRIu32,
1667 proxy->nvectors);
1668 }
1669 proxy->nvectors = 0;
1670 }
085bccb7
FK		 1671 }
1672
1673 proxy->pci_dev.config_write = virtio_write_config;
ada434cd 1674 proxy->pci_dev.config_read = virtio_read_config;
085bccb7 1675
e266d421
GH		 1676 if (legacy) {
1677 size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
1678 + virtio_bus_get_vdev_config_len(bus);
1d0148fe 1679 size = pow2ceil(size);
085bccb7 1680
e266d421
GH		 1681 memory_region_init_io(&proxy->bar, OBJECT(proxy),
1682 &virtio_pci_config_ops,
1683 proxy, "virtio-pci", size);
dfb8e184 1684
7a25126d 1685 pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
23c5e397 1686 PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
e266d421 1687 }
085bccb7
FK		 1688}
1689
06a13073
PB		 1690static void virtio_pci_device_unplugged(DeviceState *d)
1691{
06a13073 1692 VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
9a4c0e22 1693 bool modern = virtio_pci_modern(proxy);
9824d2a3 1694 bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
06a13073
PB		 1695
1696 virtio_pci_stop_ioeventfd(proxy);
27462695
MT		 1697
1698 if (modern) {
9824d2a3
JW		 1699 virtio_pci_modern_mem_region_unmap(proxy, &proxy->common);
1700 virtio_pci_modern_mem_region_unmap(proxy, &proxy->isr);
1701 virtio_pci_modern_mem_region_unmap(proxy, &proxy->device);
1702 virtio_pci_modern_mem_region_unmap(proxy, &proxy->notify);
1703 if (modern_pio) {
1704 virtio_pci_modern_io_region_unmap(proxy, &proxy->notify_pio);
1705 }
27462695 1706 }
06a13073
PB		 1707}
1708
fc079951 1709static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
085bccb7 1710{
b6ce27a5 1711 VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
085bccb7 1712 VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev);
fd56e061
DG		 1713 bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
1714 !pci_bus_is_root(pci_get_bus(pci_dev));
fc079951 1715
c324fd0a 1716 if (kvm_enabled() && !kvm_has_many_ioeventfds()) {
ca2b413c
PB		 1717 proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;
1718 }
1719
b6ce27a5
GH		 1720 /*
1721 * virtio pci bar layout used by default.
1722 * subclasses can re-arrange things if needed.
1723 *
1724 * region 0 -- virtio legacy io bar
1725 * region 1 -- msi-x bar
1726 * region 4+5 -- virtio modern memory (64bit) bar
1727 *
1728 */
7a25126d
CF		 1729 proxy->legacy_io_bar_idx = 0;
1730 proxy->msix_bar_idx = 1;
1731 proxy->modern_io_bar_idx = 2;
1732 proxy->modern_mem_bar_idx = 4;
b6ce27a5
GH		 1733
1734 proxy->common.offset = 0x0;
1735 proxy->common.size = 0x1000;
1736 proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;
1737
1738 proxy->isr.offset = 0x1000;
1739 proxy->isr.size = 0x1000;
1740 proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;
1741
1742 proxy->device.offset = 0x2000;
1743 proxy->device.size = 0x1000;
1744 proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;
1745
1746 proxy->notify.offset = 0x3000;
d9997d89 1747 proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;
b6ce27a5
GH		 1748 proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
1749
9824d2a3
JW		 1750 proxy->notify_pio.offset = 0x0;
1751 proxy->notify_pio.size = 0x4;
1752 proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;
1753
b6ce27a5
GH		 1754 /* subclasses can enforce modern, so do this unconditionally */
1755 memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",
d9997d89
MA		 1756 /* PCI BAR regions must be powers of 2 */
1757 pow2ceil(proxy->notify.offset + proxy->notify.size));
b6ce27a5 1758
9a4c0e22
MA		 1759 if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {
1760 proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
1761 }
1762
71d19fc5 1763 if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {
3eff3769
GK		 1764 error_setg(errp, "device cannot work as neither modern nor legacy mode"
1765 " is enabled");
1766 error_append_hint(errp, "Set either disable-modern or disable-legacy"
1767 " to off\n");
1768 return;
1769 }
1770
9a4c0e22 1771 if (pcie_port && pci_is_express(pci_dev)) {
1811e64c
MA		 1772 int pos;
1773
1811e64c
MA		 1774 pos = pcie_endpoint_cap_init(pci_dev, 0);
1775 assert(pos > 0);
1776
9a7c2a59
MZ		 1777 pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,
1778 PCI_PM_SIZEOF, errp);
1779 if (pos < 0) {
1780 return;
1781 }
1782
27ce0f3a 1783 pci_dev->exp.pm_cap = pos;
1811e64c
MA		 1784
1785 /*
1786 * Indicates that this function complies with revision 1.2 of the
1787 * PCI Power Management Interface Specification.
1788 */
1789 pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
615c4ed2 1790
c2cabb34
MA		 1791 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
1792 /* Init error enabling flags */
1793 pcie_cap_deverr_init(pci_dev);
1794 }
1795
d584f1b9
MA		 1796 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {
1797 /* Init Link Control Register */
1798 pcie_cap_lnkctl_init(pci_dev);
1799 }
1800
27ce0f3a
MA		 1801 if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
1802 /* Init Power Management Control Register */
1803 pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
1804 PCI_PM_CTRL_STATE_MASK);
1805 }
1806
615c4ed2
JW		 1807 if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
1808 pcie_ats_init(pci_dev, 256);
1809 }
1810
0560b0e9
SL		 1811 } else {
1812 /*
1813 * make future invocations of pci_is_express() return false
1814 * and pci_config_size() return PCI_CONFIG_SPACE_SIZE.
1815 */
1816 pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;
1811e64c
MA		 1817 }
1818
b6ce27a5 1819 virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
fc079951 1820 if (k->realize) {
b6ce27a5 1821 k->realize(proxy, errp);
085bccb7 1822 }
085bccb7
FK		 1823}
1824
1825static void virtio_pci_exit(PCIDevice *pci_dev)
1826{
8b81bb3b 1827 msix_uninit_exclusive_bar(pci_dev);
085bccb7
FK		 1828}
1829
59ccd20a 1830static void virtio_pci_reset(DeviceState *qdev)
085bccb7
FK		 1831{
1832 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
1833 VirtioBusState *bus = VIRTIO_BUS(&proxy->bus);
c2cabb34 1834 PCIDevice *dev = PCI_DEVICE(qdev);
393f04d3
JW		 1835 int i;
1836
085bccb7
FK		 1837 virtio_pci_stop_ioeventfd(proxy);
1838 virtio_bus_reset(bus);
1839 msix_unuse_all_vectors(&proxy->pci_dev);
393f04d3
JW		 1840
1841 for (i = 0; i < VIRTIO_QUEUE_MAX; i++) {
1842 proxy->vqs[i].enabled = 0;
60a8d802
JW		 1843 proxy->vqs[i].num = 0;
1844 proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0;
1845 proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0;
1846 proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0;
393f04d3 1847 }
c2cabb34
MA		 1848
1849 if (pci_is_express(dev)) {
1850 pcie_cap_deverr_reset(dev);
d584f1b9 1851 pcie_cap_lnkctl_reset(dev);
27ce0f3a
MA		 1852
1853 pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
c2cabb34 1854 }
085bccb7
FK		 1855}
1856
85d1277e 1857static Property virtio_pci_properties[] = {
68a27b20
MT		 1858 DEFINE_PROP_BIT("virtio-pci-bus-master-bug-migration", VirtIOPCIProxy, flags,
1859 VIRTIO_PCI_FLAG_BUS_MASTER_BUG_MIGRATION_BIT, false),
9a4c0e22
MA		 1860 DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy,
1861 ON_OFF_AUTO_AUTO),
1862 DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false),
a6df8adf
JW		 1863 DEFINE_PROP_BIT("migrate-extra", VirtIOPCIProxy, flags,
1864 VIRTIO_PCI_FLAG_MIGRATE_EXTRA_BIT, true),
9824d2a3
JW		 1865 DEFINE_PROP_BIT("modern-pio-notify", VirtIOPCIProxy, flags,
1866 VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY_BIT, false),
1811e64c
MA		 1867 DEFINE_PROP_BIT("x-disable-pcie", VirtIOPCIProxy, flags,
1868 VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
d9997d89
MA		 1869 DEFINE_PROP_BIT("page-per-vq", VirtIOPCIProxy, flags,
1870 VIRTIO_PCI_FLAG_PAGE_PER_VQ_BIT, false),
66d1c4c1
MC		 1871 DEFINE_PROP_BOOL("x-ignore-backend-features", VirtIOPCIProxy,
1872 ignore_backend_features, false),
615c4ed2
JW		 1873 DEFINE_PROP_BIT("ats", VirtIOPCIProxy, flags,
1874 VIRTIO_PCI_FLAG_ATS_BIT, false),
c2cabb34
MA		 1875 DEFINE_PROP_BIT("x-pcie-deverr-init", VirtIOPCIProxy, flags,
1876 VIRTIO_PCI_FLAG_INIT_DEVERR_BIT, true),
d584f1b9
MA		 1877 DEFINE_PROP_BIT("x-pcie-lnkctl-init", VirtIOPCIProxy, flags,
1878 VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
27ce0f3a
MA		 1879 DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
1880 VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
85d1277e
ML		 1881 DEFINE_PROP_END_OF_LIST(),
1882};
1883
0560b0e9
SL		 1884static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
1885{
1886 VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev);
1887 VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);
1888 PCIDevice *pci_dev = &proxy->pci_dev;
1889
1890 if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&
9a4c0e22 1891 virtio_pci_modern(proxy)) {
0560b0e9
SL		 1892 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1893 }
1894
1895 vpciklass->parent_dc_realize(qdev, errp);
1896}
1897
085bccb7
FK		 1898static void virtio_pci_class_init(ObjectClass *klass, void *data)
1899{
1900 DeviceClass *dc = DEVICE_CLASS(klass);
1901 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
0560b0e9 1902 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
085bccb7 1903
85d1277e 1904 dc->props = virtio_pci_properties;
fc079951 1905 k->realize = virtio_pci_realize;
085bccb7
FK		 1906 k->exit = virtio_pci_exit;
1907 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1908 k->revision = VIRTIO_PCI_ABI_VERSION;
1909 k->class_id = PCI_CLASS_OTHERS;
bf853881
PMD		 1910 device_class_set_parent_realize(dc, virtio_pci_dc_realize,
1911 &vpciklass->parent_dc_realize);
59ccd20a 1912 dc->reset = virtio_pci_reset;
085bccb7
FK		 1913}
1914
1915static const TypeInfo virtio_pci_info = {
1916 .name = TYPE_VIRTIO_PCI,
1917 .parent = TYPE_PCI_DEVICE,
1918 .instance_size = sizeof(VirtIOPCIProxy),
1919 .class_init = virtio_pci_class_init,
1920 .class_size = sizeof(VirtioPCIClass),
1921 .abstract = true,
a5fa336f
EH		 1922 .interfaces = (InterfaceInfo[]) {
1923 { INTERFACE_PCIE_DEVICE },
1924 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1925 { }
1926 },
085bccb7
FK		 1927};
1928
653ced07
FK		 1929/* virtio-blk-pci */
1930
1931static Property virtio_blk_pci_properties[] = {
c7bcc85d 1932 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
653ced07
FK		 1933 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
1934 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
1935 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
653ced07
FK		 1936 DEFINE_PROP_END_OF_LIST(),
1937};
1938
fc079951 1939static void virtio_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
653ced07
FK		 1940{
1941 VirtIOBlkPCI *dev = VIRTIO_BLK_PCI(vpci_dev);
1942 DeviceState *vdev = DEVICE(&dev->vdev);
fc079951 1943
653ced07 1944 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 1945 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
653ced07
FK		 1946}
1947
1948static void virtio_blk_pci_class_init(ObjectClass *klass, void *data)
1949{
1950 DeviceClass *dc = DEVICE_CLASS(klass);
1951 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
1952 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
1953
125ee0ed 1954 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
653ced07 1955 dc->props = virtio_blk_pci_properties;
fc079951 1956 k->realize = virtio_blk_pci_realize;
653ced07
FK		 1957 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1958 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
1959 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
1960 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
1961}
1962
1963static void virtio_blk_pci_instance_init(Object *obj)
1964{
1965 VirtIOBlkPCI *dev = VIRTIO_BLK_PCI(obj);
c8075caf
GA		 1966
1967 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
1968 TYPE_VIRTIO_BLK);
aeb98ddc
GA		 1969 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
1970 "bootindex", &error_abort);
653ced07
FK		 1971}
1972
1973static const TypeInfo virtio_blk_pci_info = {
1974 .name = TYPE_VIRTIO_BLK_PCI,
1975 .parent = TYPE_VIRTIO_PCI,
1976 .instance_size = sizeof(VirtIOBlkPCI),
1977 .instance_init = virtio_blk_pci_instance_init,
1978 .class_init = virtio_blk_pci_class_init,
1979};
1980
00343e4b
CL		 1981#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
1982/* vhost-user-blk */
1983
1984static Property vhost_user_blk_pci_properties[] = {
1985 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
1986 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
1987 DEFINE_PROP_END_OF_LIST(),
1988};
1989
1990static void vhost_user_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
1991{
1992 VHostUserBlkPCI *dev = VHOST_USER_BLK_PCI(vpci_dev);
1993 DeviceState *vdev = DEVICE(&dev->vdev);
1994
1995 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
1996 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
1997}
1998
1999static void vhost_user_blk_pci_class_init(ObjectClass *klass, void *data)
2000{
2001 DeviceClass *dc = DEVICE_CLASS(klass);
2002 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2003 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2004
2005 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2006 dc->props = vhost_user_blk_pci_properties;
2007 k->realize = vhost_user_blk_pci_realize;
2008 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2009 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
2010 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2011 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2012}
2013
2014static void vhost_user_blk_pci_instance_init(Object *obj)
2015{
2016 VHostUserBlkPCI *dev = VHOST_USER_BLK_PCI(obj);
2017
2018 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2019 TYPE_VHOST_USER_BLK);
2020 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2021 "bootindex", &error_abort);
2022}
2023
2024static const TypeInfo vhost_user_blk_pci_info = {
2025 .name = TYPE_VHOST_USER_BLK_PCI,
2026 .parent = TYPE_VIRTIO_PCI,
2027 .instance_size = sizeof(VHostUserBlkPCI),
2028 .instance_init = vhost_user_blk_pci_instance_init,
2029 .class_init = vhost_user_blk_pci_class_init,
2030};
2031#endif
2032
bc7b90a0
FK		 2033/* virtio-scsi-pci */
2034
2035static Property virtio_scsi_pci_properties[] = {
2036 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
2037 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
2038 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2039 DEV_NVECTORS_UNSPECIFIED),
bc7b90a0
FK		 2040 DEFINE_PROP_END_OF_LIST(),
2041};
2042
fc079951 2043static void virtio_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
bc7b90a0
FK		 2044{
2045 VirtIOSCSIPCI *dev = VIRTIO_SCSI_PCI(vpci_dev);
2046 DeviceState *vdev = DEVICE(&dev->vdev);
292c8e50 2047 VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
6f32a6b4
FK		 2048 DeviceState *proxy = DEVICE(vpci_dev);
2049 char *bus_name;
bc7b90a0
FK		 2050
2051 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
292c8e50 2052 vpci_dev->nvectors = vs->conf.num_queues + 3;
bc7b90a0
FK		 2053 }
2054
6f32a6b4
FK		 2055 /*
2056 * For command line compatibility, this sets the virtio-scsi-device bus
2057 * name as before.
2058 */
2059 if (proxy->id) {
2060 bus_name = g_strdup_printf("%s.0", proxy->id);
2061 virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name);
2062 g_free(bus_name);
2063 }
2064
bc7b90a0 2065 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2066 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
bc7b90a0
FK		 2067}
2068
2069static void virtio_scsi_pci_class_init(ObjectClass *klass, void *data)
2070{
2071 DeviceClass *dc = DEVICE_CLASS(klass);
2072 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2073 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951
MA		 2074
2075 k->realize = virtio_scsi_pci_realize;
125ee0ed 2076 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
bc7b90a0
FK		 2077 dc->props = virtio_scsi_pci_properties;
2078 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2079 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
2080 pcidev_k->revision = 0x00;
2081 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2082}
2083
2084static void virtio_scsi_pci_instance_init(Object *obj)
2085{
2086 VirtIOSCSIPCI *dev = VIRTIO_SCSI_PCI(obj);
c8075caf
GA		 2087
2088 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2089 TYPE_VIRTIO_SCSI);
bc7b90a0
FK		 2090}
2091
2092static const TypeInfo virtio_scsi_pci_info = {
2093 .name = TYPE_VIRTIO_SCSI_PCI,
2094 .parent = TYPE_VIRTIO_PCI,
2095 .instance_size = sizeof(VirtIOSCSIPCI),
2096 .instance_init = virtio_scsi_pci_instance_init,
2097 .class_init = virtio_scsi_pci_class_init,
2098};
2099
50787628
NB		 2100/* vhost-scsi-pci */
2101
2102#ifdef CONFIG_VHOST_SCSI
2103static Property vhost_scsi_pci_properties[] = {
2104 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2105 DEV_NVECTORS_UNSPECIFIED),
50787628
NB		 2106 DEFINE_PROP_END_OF_LIST(),
2107};
2108
fc079951 2109static void vhost_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
50787628
NB		 2110{
2111 VHostSCSIPCI *dev = VHOST_SCSI_PCI(vpci_dev);
2112 DeviceState *vdev = DEVICE(&dev->vdev);
2113 VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
2114
2115 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2116 vpci_dev->nvectors = vs->conf.num_queues + 3;
2117 }
2118
2119 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2120 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
50787628
NB		 2121}
2122
2123static void vhost_scsi_pci_class_init(ObjectClass *klass, void *data)
2124{
2125 DeviceClass *dc = DEVICE_CLASS(klass);
2126 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2127 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951 2128 k->realize = vhost_scsi_pci_realize;
125ee0ed 2129 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
50787628
NB		 2130 dc->props = vhost_scsi_pci_properties;
2131 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2132 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
2133 pcidev_k->revision = 0x00;
2134 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2135}
2136
2137static void vhost_scsi_pci_instance_init(Object *obj)
2138{
2139 VHostSCSIPCI *dev = VHOST_SCSI_PCI(obj);
c8075caf
GA		 2140
2141 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2142 TYPE_VHOST_SCSI);
d4433f32
GA		 2143 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2144 "bootindex", &error_abort);
50787628
NB		 2145}
2146
2147static const TypeInfo vhost_scsi_pci_info = {
2148 .name = TYPE_VHOST_SCSI_PCI,
2149 .parent = TYPE_VIRTIO_PCI,
2150 .instance_size = sizeof(VHostSCSIPCI),
2151 .instance_init = vhost_scsi_pci_instance_init,
2152 .class_init = vhost_scsi_pci_class_init,
2153};
2154#endif
2155
e6a74868 2156#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
f12c1ebd
FF		 2157/* vhost-user-scsi-pci */
2158static Property vhost_user_scsi_pci_properties[] = {
2159 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors,
2160 DEV_NVECTORS_UNSPECIFIED),
2161 DEFINE_PROP_END_OF_LIST(),
2162};
2163
2164static void vhost_user_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2165{
2166 VHostUserSCSIPCI *dev = VHOST_USER_SCSI_PCI(vpci_dev);
2167 DeviceState *vdev = DEVICE(&dev->vdev);
2168 VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev);
2169
2170 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2171 vpci_dev->nvectors = vs->conf.num_queues + 3;
2172 }
2173
2174 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
2175 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2176}
2177
2178static void vhost_user_scsi_pci_class_init(ObjectClass *klass, void *data)
2179{
2180 DeviceClass *dc = DEVICE_CLASS(klass);
2181 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2182 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2183 k->realize = vhost_user_scsi_pci_realize;
2184 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2185 dc->props = vhost_user_scsi_pci_properties;
2186 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2187 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
2188 pcidev_k->revision = 0x00;
2189 pcidev_k->class_id = PCI_CLASS_STORAGE_SCSI;
2190}
2191
2192static void vhost_user_scsi_pci_instance_init(Object *obj)
2193{
2194 VHostUserSCSIPCI *dev = VHOST_USER_SCSI_PCI(obj);
2195
2196 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2197 TYPE_VHOST_USER_SCSI);
2198 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2199 "bootindex", &error_abort);
2200}
2201
2202static const TypeInfo vhost_user_scsi_pci_info = {
2203 .name = TYPE_VHOST_USER_SCSI_PCI,
2204 .parent = TYPE_VIRTIO_PCI,
2205 .instance_size = sizeof(VHostUserSCSIPCI),
2206 .instance_init = vhost_user_scsi_pci_instance_init,
2207 .class_init = vhost_user_scsi_pci_class_init,
2208};
2209#endif
2210
fc0b9b0e
SH		 2211/* vhost-vsock-pci */
2212
2213#ifdef CONFIG_VHOST_VSOCK
2214static Property vhost_vsock_pci_properties[] = {
2215 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
2216 DEFINE_PROP_END_OF_LIST(),
2217};
2218
2219static void vhost_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2220{
2221 VHostVSockPCI *dev = VHOST_VSOCK_PCI(vpci_dev);
2222 DeviceState *vdev = DEVICE(&dev->vdev);
2223
2224 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
2225 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2226}
2227
2228static void vhost_vsock_pci_class_init(ObjectClass *klass, void *data)
2229{
2230 DeviceClass *dc = DEVICE_CLASS(klass);
2231 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2232 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2233 k->realize = vhost_vsock_pci_realize;
2234 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
2235 dc->props = vhost_vsock_pci_properties;
2236 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2237 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_VSOCK;
2238 pcidev_k->revision = 0x00;
2239 pcidev_k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
2240}
2241
2242static void vhost_vsock_pci_instance_init(Object *obj)
2243{
2244 VHostVSockPCI *dev = VHOST_VSOCK_PCI(obj);
2245
2246 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2247 TYPE_VHOST_VSOCK);
2248}
2249
2250static const TypeInfo vhost_vsock_pci_info = {
2251 .name = TYPE_VHOST_VSOCK_PCI,
2252 .parent = TYPE_VIRTIO_PCI,
2253 .instance_size = sizeof(VHostVSockPCI),
2254 .instance_init = vhost_vsock_pci_instance_init,
2255 .class_init = vhost_vsock_pci_class_init,
2256};
2257#endif
2258
e378e88d
FK		 2259/* virtio-balloon-pci */
2260
2261static Property virtio_balloon_pci_properties[] = {
c7bcc85d 2262 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
e378e88d
FK		 2263 DEFINE_PROP_END_OF_LIST(),
2264};
2265
fc079951 2266static void virtio_balloon_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
e378e88d
FK		 2267{
2268 VirtIOBalloonPCI *dev = VIRTIO_BALLOON_PCI(vpci_dev);
2269 DeviceState *vdev = DEVICE(&dev->vdev);
2270
2271 if (vpci_dev->class_code != PCI_CLASS_OTHERS &&
2272 vpci_dev->class_code != PCI_CLASS_MEMORY_RAM) { /* qemu < 1.1 */
2273 vpci_dev->class_code = PCI_CLASS_OTHERS;
2274 }
2275
2276 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2277 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
e378e88d
FK		 2278}
2279
2280static void virtio_balloon_pci_class_init(ObjectClass *klass, void *data)
2281{
2282 DeviceClass *dc = DEVICE_CLASS(klass);
2283 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2284 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951 2285 k->realize = virtio_balloon_pci_realize;
125ee0ed 2286 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
e378e88d
FK		 2287 dc->props = virtio_balloon_pci_properties;
2288 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2289 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BALLOON;
2290 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2291 pcidev_k->class_id = PCI_CLASS_OTHERS;
2292}
2293
2294static void virtio_balloon_pci_instance_init(Object *obj)
2295{
2296 VirtIOBalloonPCI *dev = VIRTIO_BALLOON_PCI(obj);
39b87c7b 2297
a6027b0f
DL		 2298 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2299 TYPE_VIRTIO_BALLOON);
39b87c7b
SZ		 2300 object_property_add_alias(obj, "guest-stats", OBJECT(&dev->vdev),
2301 "guest-stats", &error_abort);
2302 object_property_add_alias(obj, "guest-stats-polling-interval",
2303 OBJECT(&dev->vdev),
2304 "guest-stats-polling-interval", &error_abort);
e378e88d
FK		 2305}
2306
2307static const TypeInfo virtio_balloon_pci_info = {
2308 .name = TYPE_VIRTIO_BALLOON_PCI,
2309 .parent = TYPE_VIRTIO_PCI,
2310 .instance_size = sizeof(VirtIOBalloonPCI),
2311 .instance_init = virtio_balloon_pci_instance_init,
2312 .class_init = virtio_balloon_pci_class_init,
2313};
2314
f7f7464a
FK		 2315/* virtio-serial-pci */
2316
fc079951 2317static void virtio_serial_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
f7f7464a
FK		 2318{
2319 VirtIOSerialPCI *dev = VIRTIO_SERIAL_PCI(vpci_dev);
2320 DeviceState *vdev = DEVICE(&dev->vdev);
80270a19
FK		 2321 DeviceState *proxy = DEVICE(vpci_dev);
2322 char *bus_name;
f7f7464a
FK		 2323
2324 if (vpci_dev->class_code != PCI_CLASS_COMMUNICATION_OTHER &&
2325 vpci_dev->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */
2326 vpci_dev->class_code != PCI_CLASS_OTHERS) { /* qemu-kvm */
2327 vpci_dev->class_code = PCI_CLASS_COMMUNICATION_OTHER;
2328 }
2329
2330 /* backwards-compatibility with machines that were created with
2331 DEV_NVECTORS_UNSPECIFIED */
2332 if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) {
2333 vpci_dev->nvectors = dev->vdev.serial.max_virtserial_ports + 1;
2334 }
2335
80270a19
FK		 2336 /*
2337 * For command line compatibility, this sets the virtio-serial-device bus
2338 * name as before.
2339 */
2340 if (proxy->id) {
2341 bus_name = g_strdup_printf("%s.0", proxy->id);
2342 virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name);
2343 g_free(bus_name);
2344 }
2345
f7f7464a 2346 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2347 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
f7f7464a
FK		 2348}
2349
2350static Property virtio_serial_pci_properties[] = {
2351 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
2352 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
2353 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
c7bcc85d 2354 DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
f7f7464a
FK		 2355 DEFINE_PROP_END_OF_LIST(),
2356};
2357
2358static void virtio_serial_pci_class_init(ObjectClass *klass, void *data)
2359{
2360 DeviceClass *dc = DEVICE_CLASS(klass);
2361 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2362 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
fc079951 2363 k->realize = virtio_serial_pci_realize;
125ee0ed 2364 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
f7f7464a
FK		 2365 dc->props = virtio_serial_pci_properties;
2366 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2367 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_CONSOLE;
2368 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2369 pcidev_k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
2370}
2371
2372static void virtio_serial_pci_instance_init(Object *obj)
2373{
2374 VirtIOSerialPCI *dev = VIRTIO_SERIAL_PCI(obj);
c8075caf
GA		 2375
2376 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2377 TYPE_VIRTIO_SERIAL);
f7f7464a
FK		 2378}
2379
2380static const TypeInfo virtio_serial_pci_info = {
2381 .name = TYPE_VIRTIO_SERIAL_PCI,
2382 .parent = TYPE_VIRTIO_PCI,
2383 .instance_size = sizeof(VirtIOSerialPCI),
2384 .instance_init = virtio_serial_pci_instance_init,
2385 .class_init = virtio_serial_pci_class_init,
2386};
2387
e37da394
FK		 2388/* virtio-net-pci */
2389
2390static Property virtio_net_properties[] = {
2391 DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
4a3f03ba 2392 VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
e37da394 2393 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
e37da394
FK		 2394 DEFINE_PROP_END_OF_LIST(),
2395};
2396
fc079951 2397static void virtio_net_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
e37da394 2398{
800ced8c 2399 DeviceState *qdev = DEVICE(vpci_dev);
e37da394
FK		 2400 VirtIONetPCI *dev = VIRTIO_NET_PCI(vpci_dev);
2401 DeviceState *vdev = DEVICE(&dev->vdev);
2402
800ced8c
FK		 2403 virtio_net_set_netclient_name(&dev->vdev, qdev->id,
2404 object_get_typename(OBJECT(qdev)));
e37da394 2405 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951 2406 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
e37da394
FK		 2407}
2408
2409static void virtio_net_pci_class_init(ObjectClass *klass, void *data)
2410{
2411 DeviceClass *dc = DEVICE_CLASS(klass);
2412 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2413 VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
2414
2415 k->romfile = "efi-virtio.rom";
2416 k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2417 k->device_id = PCI_DEVICE_ID_VIRTIO_NET;
2418 k->revision = VIRTIO_PCI_ABI_VERSION;
2419 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
125ee0ed 2420 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
e37da394 2421 dc->props = virtio_net_properties;
fc079951 2422 vpciklass->realize = virtio_net_pci_realize;
e37da394
FK		 2423}
2424
2425static void virtio_net_pci_instance_init(Object *obj)
2426{
2427 VirtIONetPCI *dev = VIRTIO_NET_PCI(obj);
c8075caf
GA		 2428
2429 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2430 TYPE_VIRTIO_NET);
0cf63c3e
GA		 2431 object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
2432 "bootindex", &error_abort);
e37da394
FK		 2433}
2434
2435static const TypeInfo virtio_net_pci_info = {
2436 .name = TYPE_VIRTIO_NET_PCI,
2437 .parent = TYPE_VIRTIO_PCI,
2438 .instance_size = sizeof(VirtIONetPCI),
2439 .instance_init = virtio_net_pci_instance_init,
2440 .class_init = virtio_net_pci_class_init,
2441};
2442
59ccd20a
FK		 2443/* virtio-rng-pci */
2444
fc079951 2445static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
59ccd20a
FK		 2446{
2447 VirtIORngPCI *vrng = VIRTIO_RNG_PCI(vpci_dev);
2448 DeviceState *vdev = DEVICE(&vrng->vdev);
fc079951 2449 Error *err = NULL;
59ccd20a
FK		 2450
2451 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
fc079951
MA		 2452 object_property_set_bool(OBJECT(vdev), true, "realized", &err);
2453 if (err) {
2454 error_propagate(errp, err);
2455 return;
59ccd20a
FK		 2456 }
2457
2458 object_property_set_link(OBJECT(vrng),
5b456438 2459 OBJECT(vrng->vdev.conf.rng), "rng",
59ccd20a 2460 NULL);
59ccd20a
FK		 2461}
2462
2463static void virtio_rng_pci_class_init(ObjectClass *klass, void *data)
2464{
2465 DeviceClass *dc = DEVICE_CLASS(klass);
2466 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2467 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2468
fc079951 2469 k->realize = virtio_rng_pci_realize;
125ee0ed 2470 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
59ccd20a
FK		 2471
2472 pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
2473 pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_RNG;
2474 pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
2475 pcidev_k->class_id = PCI_CLASS_OTHERS;
2476}
2477
2478static void virtio_rng_initfn(Object *obj)
2479{
2480 VirtIORngPCI *dev = VIRTIO_RNG_PCI(obj);
c8075caf
GA		 2481
2482 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2483 TYPE_VIRTIO_RNG);
59ccd20a
FK		 2484}
2485
2486static const TypeInfo virtio_rng_pci_info = {
2487 .name = TYPE_VIRTIO_RNG_PCI,
2488 .parent = TYPE_VIRTIO_PCI,
2489 .instance_size = sizeof(VirtIORngPCI),
2490 .instance_init = virtio_rng_initfn,
2491 .class_init = virtio_rng_pci_class_init,
2492};
2493
f958c8aa
GH		 2494/* virtio-input-pci */
2495
6f2b9a5b 2496static Property virtio_input_pci_properties[] = {
710e2d90
GH		 2497 DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
2498 DEFINE_PROP_END_OF_LIST(),
2499};
2500
f958c8aa
GH		 2501static void virtio_input_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
2502{
2503 VirtIOInputPCI *vinput = VIRTIO_INPUT_PCI(vpci_dev);
2504 DeviceState *vdev = DEVICE(&vinput->vdev);
2505
2506 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
9a4c0e22 2507 virtio_pci_force_virtio_1(vpci_dev);
f958c8aa
GH		 2508 object_property_set_bool(OBJECT(vdev), true, "realized", errp);
2509}
2510
2511static void virtio_input_pci_class_init(ObjectClass *klass, void *data)
2512{
2513 DeviceClass *dc = DEVICE_CLASS(klass);
2514 VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
2515 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2516
6f2b9a5b 2517 dc->props = virtio_input_pci_properties;
f958c8aa
GH		 2518 k->realize = virtio_input_pci_realize;
2519 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
2520
2521 pcidev_k->class_id = PCI_CLASS_INPUT_OTHER;
2522}
2523
710e2d90
GH		 2524static void virtio_input_hid_kbd_pci_class_init(ObjectClass *klass, void *data)
2525{
2526 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2527
2528 pcidev_k->class_id = PCI_CLASS_INPUT_KEYBOARD;
2529}
2530
2531static void virtio_input_hid_mouse_pci_class_init(ObjectClass *klass,
2532 void *data)
2533{
2534 PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
2535
2536 pcidev_k->class_id = PCI_CLASS_INPUT_MOUSE;
2537}
2538
2539static void virtio_keyboard_initfn(Object *obj)
2540{
2541 VirtIOInputHIDPCI *dev = VIRTIO_INPUT_HID_PCI(obj);
6f2b9a5b
GH		 2542
2543 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2544 TYPE_VIRTIO_KEYBOARD);
710e2d90
GH		 2545}
2546
2547static void virtio_mouse_initfn(Object *obj)
2548{
2549 VirtIOInputHIDPCI *dev = VIRTIO_INPUT_HID_PCI(obj);
6f2b9a5b
GH		 2550
2551 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2552 TYPE_VIRTIO_MOUSE);
710e2d90
GH		 2553}
2554
2555static void virtio_tablet_initfn(Object *obj)
2556{
2557 VirtIOInputHIDPCI *dev = VIRTIO_INPUT_HID_PCI(obj);
6f2b9a5b
GH		 2558
2559 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2560 TYPE_VIRTIO_TABLET);
710e2d90
GH		 2561}
2562
f958c8aa
GH		 2563static const TypeInfo virtio_input_pci_info = {
2564 .name = TYPE_VIRTIO_INPUT_PCI,
2565 .parent = TYPE_VIRTIO_PCI,
2566 .instance_size = sizeof(VirtIOInputPCI),
2567 .class_init = virtio_input_pci_class_init,
2568 .abstract = true,
2569};
2570
710e2d90
GH		 2571static const TypeInfo virtio_input_hid_pci_info = {
2572 .name = TYPE_VIRTIO_INPUT_HID_PCI,
2573 .parent = TYPE_VIRTIO_INPUT_PCI,
2574 .instance_size = sizeof(VirtIOInputHIDPCI),
710e2d90
GH		 2575 .abstract = true,
2576};
2577
2578static const TypeInfo virtio_keyboard_pci_info = {
2579 .name = TYPE_VIRTIO_KEYBOARD_PCI,
2580 .parent = TYPE_VIRTIO_INPUT_HID_PCI,
2581 .class_init = virtio_input_hid_kbd_pci_class_init,
2582 .instance_size = sizeof(VirtIOInputHIDPCI),
2583 .instance_init = virtio_keyboard_initfn,
2584};
2585
2586static const TypeInfo virtio_mouse_pci_info = {
2587 .name = TYPE_VIRTIO_MOUSE_PCI,
2588 .parent = TYPE_VIRTIO_INPUT_HID_PCI,
2589 .class_init = virtio_input_hid_mouse_pci_class_init,
2590 .instance_size = sizeof(VirtIOInputHIDPCI),
2591 .instance_init = virtio_mouse_initfn,
2592};
2593
2594static const TypeInfo virtio_tablet_pci_info = {
2595 .name = TYPE_VIRTIO_TABLET_PCI,
2596 .parent = TYPE_VIRTIO_INPUT_HID_PCI,
2597 .instance_size = sizeof(VirtIOInputHIDPCI),
2598 .instance_init = virtio_tablet_initfn,
2599};
2600
c6047e96
MA		 2601#ifdef CONFIG_LINUX
2602static void virtio_host_initfn(Object *obj)
2603{
2604 VirtIOInputHostPCI *dev = VIRTIO_INPUT_HOST_PCI(obj);
2605
2606 virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
2607 TYPE_VIRTIO_INPUT_HOST);
2608}
2609
006a5ede
GH		 2610static const TypeInfo virtio_host_pci_info = {
2611 .name = TYPE_VIRTIO_INPUT_HOST_PCI,
2612 .parent = TYPE_VIRTIO_INPUT_PCI,
2613 .instance_size = sizeof(VirtIOInputHostPCI),
2614 .instance_init = virtio_host_initfn,
2615};
c6047e96 2616#endif
006a5ede 2617
0a2acf5e
FK		 2618/* virtio-pci-bus */
2619
ac7af112
AF		 2620static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
2621 VirtIOPCIProxy *dev)
0a2acf5e
FK		 2622{
2623 DeviceState *qdev = DEVICE(dev);
f4dd69aa
FK		 2624 char virtio_bus_name[] = "virtio-bus";
2625
fb17dfe0 2626 qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
f4dd69aa 2627 virtio_bus_name);
0a2acf5e
FK		 2628}
2629
2630static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
2631{
2632 BusClass *bus_class = BUS_CLASS(klass);
2633 VirtioBusClass *k = VIRTIO_BUS_CLASS(klass);
2634 bus_class->max_dev = 1;
2635 k->notify = virtio_pci_notify;
2636 k->save_config = virtio_pci_save_config;
2637 k->load_config = virtio_pci_load_config;
2638 k->save_queue = virtio_pci_save_queue;
2639 k->load_queue = virtio_pci_load_queue;
a6df8adf
JW		 2640 k->save_extra_state = virtio_pci_save_extra_state;
2641 k->load_extra_state = virtio_pci_load_extra_state;
2642 k->has_extra_state = virtio_pci_has_extra_state;
0a2acf5e 2643 k->query_guest_notifiers = virtio_pci_query_guest_notifiers;
0a2acf5e
FK		 2644 k->set_guest_notifiers = virtio_pci_set_guest_notifiers;
2645 k->vmstate_change = virtio_pci_vmstate_change;
d1b4259f 2646 k->pre_plugged = virtio_pci_pre_plugged;
085bccb7 2647 k->device_plugged = virtio_pci_device_plugged;
06a13073 2648 k->device_unplugged = virtio_pci_device_unplugged;
e0d686bf 2649 k->query_nvectors = virtio_pci_query_nvectors;
8e93cef1 2650 k->ioeventfd_enabled = virtio_pci_ioeventfd_enabled;
9f06e71a 2651 k->ioeventfd_assign = virtio_pci_ioeventfd_assign;
8607f5c3 2652 k->get_dma_as = virtio_pci_get_dma_as;
0a2acf5e
FK		 2653}
2654
2655static const TypeInfo virtio_pci_bus_info = {
2656 .name = TYPE_VIRTIO_PCI_BUS,
2657 .parent = TYPE_VIRTIO_BUS,
2658 .instance_size = sizeof(VirtioPCIBusState),
2659 .class_init = virtio_pci_bus_class_init,
2660};
2661
83f7d43a 2662static void virtio_pci_register_types(void)
53c25cea 2663{
59ccd20a 2664 type_register_static(&virtio_rng_pci_info);
f958c8aa 2665 type_register_static(&virtio_input_pci_info);
710e2d90
GH		 2666 type_register_static(&virtio_input_hid_pci_info);
2667 type_register_static(&virtio_keyboard_pci_info);
2668 type_register_static(&virtio_mouse_pci_info);
2669 type_register_static(&virtio_tablet_pci_info);
c6047e96 2670#ifdef CONFIG_LINUX
006a5ede 2671 type_register_static(&virtio_host_pci_info);
c6047e96 2672#endif
0a2acf5e 2673 type_register_static(&virtio_pci_bus_info);
085bccb7 2674 type_register_static(&virtio_pci_info);
60653b28 2675#ifdef CONFIG_VIRTFS
234a336f 2676 type_register_static(&virtio_9p_pci_info);
60653b28 2677#endif
653ced07 2678 type_register_static(&virtio_blk_pci_info);
00343e4b
CL		 2679#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
2680 type_register_static(&vhost_user_blk_pci_info);
2681#endif
bc7b90a0 2682 type_register_static(&virtio_scsi_pci_info);
e378e88d 2683 type_register_static(&virtio_balloon_pci_info);
f7f7464a 2684 type_register_static(&virtio_serial_pci_info);
e37da394 2685 type_register_static(&virtio_net_pci_info);
50787628
NB		 2686#ifdef CONFIG_VHOST_SCSI
2687 type_register_static(&vhost_scsi_pci_info);
2688#endif
e6a74868 2689#if defined(CONFIG_VHOST_USER) && defined(CONFIG_LINUX)
f12c1ebd
FF		 2690 type_register_static(&vhost_user_scsi_pci_info);
2691#endif
fc0b9b0e
SH		 2692#ifdef CONFIG_VHOST_VSOCK
2693 type_register_static(&vhost_vsock_pci_info);
2694#endif
53c25cea
PB		 2695}
2696
83f7d43a 2697type_init(virtio_pci_register_types)
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