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Commit | Line | Data |
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53c25cea PB |
1 | /* |
2 | * Virtio PCI Bindings | |
3 | * | |
4 | * Copyright IBM, Corp. 2007 | |
5 | * Copyright (c) 2009 CodeSourcery | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * Paul Brook <paul@codesourcery.com> | |
10 | * | |
11 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
12 | * the COPYING file in the top-level directory. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <inttypes.h> | |
17 | ||
18 | #include "virtio.h" | |
8172539d MT |
19 | #include "virtio-blk.h" |
20 | #include "virtio-net.h" | |
53c25cea | 21 | #include "pci.h" |
d176c495 | 22 | #include "sysemu.h" |
aba800a3 | 23 | #include "msix.h" |
a1e0fea5 | 24 | #include "net.h" |
97b15621 | 25 | #include "loader.h" |
53c25cea PB |
26 | |
27 | /* from Linux's linux/virtio_pci.h */ | |
28 | ||
29 | /* A 32-bit r/o bitmask of the features supported by the host */ | |
30 | #define VIRTIO_PCI_HOST_FEATURES 0 | |
31 | ||
32 | /* A 32-bit r/w bitmask of features activated by the guest */ | |
33 | #define VIRTIO_PCI_GUEST_FEATURES 4 | |
34 | ||
35 | /* A 32-bit r/w PFN for the currently selected queue */ | |
36 | #define VIRTIO_PCI_QUEUE_PFN 8 | |
37 | ||
38 | /* A 16-bit r/o queue size for the currently selected queue */ | |
39 | #define VIRTIO_PCI_QUEUE_NUM 12 | |
40 | ||
41 | /* A 16-bit r/w queue selector */ | |
42 | #define VIRTIO_PCI_QUEUE_SEL 14 | |
43 | ||
44 | /* A 16-bit r/w queue notifier */ | |
45 | #define VIRTIO_PCI_QUEUE_NOTIFY 16 | |
46 | ||
47 | /* An 8-bit device status register. */ | |
48 | #define VIRTIO_PCI_STATUS 18 | |
49 | ||
50 | /* An 8-bit r/o interrupt status register. Reading the value will return the | |
51 | * current contents of the ISR and will also clear it. This is effectively | |
52 | * a read-and-acknowledge. */ | |
53 | #define VIRTIO_PCI_ISR 19 | |
54 | ||
aba800a3 MT |
55 | /* MSI-X registers: only enabled if MSI-X is enabled. */ |
56 | /* A 16-bit vector for configuration changes. */ | |
57 | #define VIRTIO_MSI_CONFIG_VECTOR 20 | |
58 | /* A 16-bit vector for selected queue notifications. */ | |
59 | #define VIRTIO_MSI_QUEUE_VECTOR 22 | |
60 | ||
61 | /* Config space size */ | |
62 | #define VIRTIO_PCI_CONFIG_NOMSI 20 | |
63 | #define VIRTIO_PCI_CONFIG_MSI 24 | |
64 | #define VIRTIO_PCI_REGION_SIZE(dev) (msix_present(dev) ? \ | |
65 | VIRTIO_PCI_CONFIG_MSI : \ | |
66 | VIRTIO_PCI_CONFIG_NOMSI) | |
67 | ||
68 | /* The remaining space is defined by each driver as the per-driver | |
69 | * configuration space */ | |
70 | #define VIRTIO_PCI_CONFIG(dev) (msix_enabled(dev) ? \ | |
71 | VIRTIO_PCI_CONFIG_MSI : \ | |
72 | VIRTIO_PCI_CONFIG_NOMSI) | |
53c25cea PB |
73 | |
74 | /* Virtio ABI version, if we increment this, we break the guest driver. */ | |
75 | #define VIRTIO_PCI_ABI_VERSION 0 | |
76 | ||
77 | /* How many bits to shift physical queue address written to QUEUE_PFN. | |
78 | * 12 is historical, and due to x86 page size. */ | |
79 | #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 | |
80 | ||
81 | /* QEMU doesn't strictly need write barriers since everything runs in | |
82 | * lock-step. We'll leave the calls to wmb() in though to make it obvious for | |
83 | * KVM or if kqemu gets SMP support. | |
84 | */ | |
85 | #define wmb() do { } while (0) | |
86 | ||
87 | /* PCI bindings. */ | |
88 | ||
89 | typedef struct { | |
90 | PCIDevice pci_dev; | |
91 | VirtIODevice *vdev; | |
92 | uint32_t addr; | |
ab73ff29 | 93 | uint32_t class_code; |
a1e0fea5 | 94 | uint32_t nvectors; |
d176c495 | 95 | DriveInfo *dinfo; |
97b15621 | 96 | NICConf nic; |
8172539d | 97 | uint32_t host_features; |
98b19252 AS |
98 | /* Max. number of ports we can have for a the virtio-serial device */ |
99 | uint32_t max_virtserial_ports; | |
53c25cea PB |
100 | } VirtIOPCIProxy; |
101 | ||
102 | /* virtio device */ | |
103 | ||
7055e687 | 104 | static void virtio_pci_notify(void *opaque, uint16_t vector) |
53c25cea PB |
105 | { |
106 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
107 | if (msix_enabled(&proxy->pci_dev)) |
108 | msix_notify(&proxy->pci_dev, vector); | |
109 | else | |
110 | qemu_set_irq(proxy->pci_dev.irq[0], proxy->vdev->isr & 1); | |
53c25cea PB |
111 | } |
112 | ||
ff24bd58 MT |
113 | static void virtio_pci_save_config(void * opaque, QEMUFile *f) |
114 | { | |
115 | VirtIOPCIProxy *proxy = opaque; | |
116 | pci_device_save(&proxy->pci_dev, f); | |
117 | msix_save(&proxy->pci_dev, f); | |
118 | if (msix_present(&proxy->pci_dev)) | |
119 | qemu_put_be16(f, proxy->vdev->config_vector); | |
120 | } | |
121 | ||
122 | static void virtio_pci_save_queue(void * opaque, int n, QEMUFile *f) | |
123 | { | |
124 | VirtIOPCIProxy *proxy = opaque; | |
125 | if (msix_present(&proxy->pci_dev)) | |
126 | qemu_put_be16(f, virtio_queue_vector(proxy->vdev, n)); | |
127 | } | |
128 | ||
129 | static int virtio_pci_load_config(void * opaque, QEMUFile *f) | |
130 | { | |
131 | VirtIOPCIProxy *proxy = opaque; | |
132 | int ret; | |
133 | ret = pci_device_load(&proxy->pci_dev, f); | |
e6da7680 | 134 | if (ret) { |
ff24bd58 | 135 | return ret; |
e6da7680 | 136 | } |
ff24bd58 | 137 | msix_load(&proxy->pci_dev, f); |
e6da7680 | 138 | if (msix_present(&proxy->pci_dev)) { |
ff24bd58 | 139 | qemu_get_be16s(f, &proxy->vdev->config_vector); |
e6da7680 MT |
140 | } else { |
141 | proxy->vdev->config_vector = VIRTIO_NO_VECTOR; | |
142 | } | |
143 | if (proxy->vdev->config_vector != VIRTIO_NO_VECTOR) { | |
144 | return msix_vector_use(&proxy->pci_dev, proxy->vdev->config_vector); | |
145 | } | |
ff24bd58 MT |
146 | return 0; |
147 | } | |
148 | ||
149 | static int virtio_pci_load_queue(void * opaque, int n, QEMUFile *f) | |
150 | { | |
151 | VirtIOPCIProxy *proxy = opaque; | |
152 | uint16_t vector; | |
e6da7680 MT |
153 | if (msix_present(&proxy->pci_dev)) { |
154 | qemu_get_be16s(f, &vector); | |
155 | } else { | |
156 | vector = VIRTIO_NO_VECTOR; | |
157 | } | |
ff24bd58 | 158 | virtio_queue_set_vector(proxy->vdev, n, vector); |
e6da7680 MT |
159 | if (vector != VIRTIO_NO_VECTOR) { |
160 | return msix_vector_use(&proxy->pci_dev, vector); | |
161 | } | |
ff24bd58 MT |
162 | return 0; |
163 | } | |
164 | ||
e489030d | 165 | static void virtio_pci_reset(DeviceState *d) |
7055e687 | 166 | { |
e489030d | 167 | VirtIOPCIProxy *proxy = container_of(d, VirtIOPCIProxy, pci_dev.qdev); |
7055e687 | 168 | virtio_reset(proxy->vdev); |
aba800a3 | 169 | msix_reset(&proxy->pci_dev); |
7055e687 MT |
170 | } |
171 | ||
53c25cea PB |
172 | static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
173 | { | |
174 | VirtIOPCIProxy *proxy = opaque; | |
175 | VirtIODevice *vdev = proxy->vdev; | |
c227f099 | 176 | target_phys_addr_t pa; |
53c25cea | 177 | |
53c25cea PB |
178 | switch (addr) { |
179 | case VIRTIO_PCI_GUEST_FEATURES: | |
180 | /* Guest does not negotiate properly? We have to assume nothing. */ | |
181 | if (val & (1 << VIRTIO_F_BAD_FEATURE)) { | |
182 | if (vdev->bad_features) | |
8172539d | 183 | val = proxy->host_features & vdev->bad_features(vdev); |
53c25cea PB |
184 | else |
185 | val = 0; | |
186 | } | |
187 | if (vdev->set_features) | |
188 | vdev->set_features(vdev, val); | |
704a76fc | 189 | vdev->guest_features = val; |
53c25cea PB |
190 | break; |
191 | case VIRTIO_PCI_QUEUE_PFN: | |
c227f099 | 192 | pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT; |
1b8e9b27 MT |
193 | if (pa == 0) { |
194 | virtio_reset(proxy->vdev); | |
195 | msix_unuse_all_vectors(&proxy->pci_dev); | |
196 | } | |
7055e687 MT |
197 | else |
198 | virtio_queue_set_addr(vdev, vdev->queue_sel, pa); | |
53c25cea PB |
199 | break; |
200 | case VIRTIO_PCI_QUEUE_SEL: | |
201 | if (val < VIRTIO_PCI_QUEUE_MAX) | |
202 | vdev->queue_sel = val; | |
203 | break; | |
204 | case VIRTIO_PCI_QUEUE_NOTIFY: | |
205 | virtio_queue_notify(vdev, val); | |
206 | break; | |
207 | case VIRTIO_PCI_STATUS: | |
208 | vdev->status = val & 0xFF; | |
1b8e9b27 MT |
209 | if (vdev->status == 0) { |
210 | virtio_reset(proxy->vdev); | |
211 | msix_unuse_all_vectors(&proxy->pci_dev); | |
212 | } | |
53c25cea | 213 | break; |
aba800a3 MT |
214 | case VIRTIO_MSI_CONFIG_VECTOR: |
215 | msix_vector_unuse(&proxy->pci_dev, vdev->config_vector); | |
216 | /* Make it possible for guest to discover an error took place. */ | |
217 | if (msix_vector_use(&proxy->pci_dev, val) < 0) | |
218 | val = VIRTIO_NO_VECTOR; | |
219 | vdev->config_vector = val; | |
220 | break; | |
221 | case VIRTIO_MSI_QUEUE_VECTOR: | |
222 | msix_vector_unuse(&proxy->pci_dev, | |
223 | virtio_queue_vector(vdev, vdev->queue_sel)); | |
224 | /* Make it possible for guest to discover an error took place. */ | |
225 | if (msix_vector_use(&proxy->pci_dev, val) < 0) | |
226 | val = VIRTIO_NO_VECTOR; | |
227 | virtio_queue_set_vector(vdev, vdev->queue_sel, val); | |
228 | break; | |
229 | default: | |
230 | fprintf(stderr, "%s: unexpected address 0x%x value 0x%x\n", | |
231 | __func__, addr, val); | |
232 | break; | |
53c25cea PB |
233 | } |
234 | } | |
235 | ||
aba800a3 | 236 | static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr) |
53c25cea | 237 | { |
53c25cea PB |
238 | VirtIODevice *vdev = proxy->vdev; |
239 | uint32_t ret = 0xFFFFFFFF; | |
240 | ||
53c25cea PB |
241 | switch (addr) { |
242 | case VIRTIO_PCI_HOST_FEATURES: | |
8172539d | 243 | ret = proxy->host_features; |
53c25cea PB |
244 | break; |
245 | case VIRTIO_PCI_GUEST_FEATURES: | |
704a76fc | 246 | ret = vdev->guest_features; |
53c25cea PB |
247 | break; |
248 | case VIRTIO_PCI_QUEUE_PFN: | |
249 | ret = virtio_queue_get_addr(vdev, vdev->queue_sel) | |
250 | >> VIRTIO_PCI_QUEUE_ADDR_SHIFT; | |
251 | break; | |
252 | case VIRTIO_PCI_QUEUE_NUM: | |
253 | ret = virtio_queue_get_num(vdev, vdev->queue_sel); | |
254 | break; | |
255 | case VIRTIO_PCI_QUEUE_SEL: | |
256 | ret = vdev->queue_sel; | |
257 | break; | |
258 | case VIRTIO_PCI_STATUS: | |
259 | ret = vdev->status; | |
260 | break; | |
261 | case VIRTIO_PCI_ISR: | |
262 | /* reading from the ISR also clears it. */ | |
263 | ret = vdev->isr; | |
264 | vdev->isr = 0; | |
7055e687 | 265 | qemu_set_irq(proxy->pci_dev.irq[0], 0); |
53c25cea | 266 | break; |
aba800a3 MT |
267 | case VIRTIO_MSI_CONFIG_VECTOR: |
268 | ret = vdev->config_vector; | |
269 | break; | |
270 | case VIRTIO_MSI_QUEUE_VECTOR: | |
271 | ret = virtio_queue_vector(vdev, vdev->queue_sel); | |
272 | break; | |
53c25cea PB |
273 | default: |
274 | break; | |
275 | } | |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
280 | static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr) | |
281 | { | |
282 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
283 | uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
284 | addr -= proxy->addr; | |
285 | if (addr < config) | |
286 | return virtio_ioport_read(proxy, addr); | |
287 | addr -= config; | |
53c25cea PB |
288 | return virtio_config_readb(proxy->vdev, addr); |
289 | } | |
290 | ||
291 | static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr) | |
292 | { | |
293 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
294 | uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
295 | addr -= proxy->addr; | |
296 | if (addr < config) | |
297 | return virtio_ioport_read(proxy, addr); | |
298 | addr -= config; | |
53c25cea PB |
299 | return virtio_config_readw(proxy->vdev, addr); |
300 | } | |
301 | ||
302 | static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr) | |
303 | { | |
304 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
305 | uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
306 | addr -= proxy->addr; | |
307 | if (addr < config) | |
308 | return virtio_ioport_read(proxy, addr); | |
309 | addr -= config; | |
53c25cea PB |
310 | return virtio_config_readl(proxy->vdev, addr); |
311 | } | |
312 | ||
313 | static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val) | |
314 | { | |
315 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
316 | uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
317 | addr -= proxy->addr; | |
318 | if (addr < config) { | |
319 | virtio_ioport_write(proxy, addr, val); | |
320 | return; | |
321 | } | |
322 | addr -= config; | |
53c25cea PB |
323 | virtio_config_writeb(proxy->vdev, addr, val); |
324 | } | |
325 | ||
326 | static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val) | |
327 | { | |
328 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
329 | uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
330 | addr -= proxy->addr; | |
331 | if (addr < config) { | |
332 | virtio_ioport_write(proxy, addr, val); | |
333 | return; | |
334 | } | |
335 | addr -= config; | |
53c25cea PB |
336 | virtio_config_writew(proxy->vdev, addr, val); |
337 | } | |
338 | ||
339 | static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val) | |
340 | { | |
341 | VirtIOPCIProxy *proxy = opaque; | |
aba800a3 MT |
342 | uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev); |
343 | addr -= proxy->addr; | |
344 | if (addr < config) { | |
345 | virtio_ioport_write(proxy, addr, val); | |
346 | return; | |
347 | } | |
348 | addr -= config; | |
53c25cea PB |
349 | virtio_config_writel(proxy->vdev, addr, val); |
350 | } | |
351 | ||
352 | static void virtio_map(PCIDevice *pci_dev, int region_num, | |
6e355d90 | 353 | pcibus_t addr, pcibus_t size, int type) |
53c25cea PB |
354 | { |
355 | VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev); | |
356 | VirtIODevice *vdev = proxy->vdev; | |
aba800a3 | 357 | unsigned config_len = VIRTIO_PCI_REGION_SIZE(pci_dev) + vdev->config_len; |
53c25cea PB |
358 | |
359 | proxy->addr = addr; | |
53c25cea | 360 | |
aba800a3 MT |
361 | register_ioport_write(addr, config_len, 1, virtio_pci_config_writeb, proxy); |
362 | register_ioport_write(addr, config_len, 2, virtio_pci_config_writew, proxy); | |
363 | register_ioport_write(addr, config_len, 4, virtio_pci_config_writel, proxy); | |
364 | register_ioport_read(addr, config_len, 1, virtio_pci_config_readb, proxy); | |
365 | register_ioport_read(addr, config_len, 2, virtio_pci_config_readw, proxy); | |
366 | register_ioport_read(addr, config_len, 4, virtio_pci_config_readl, proxy); | |
53c25cea | 367 | |
aba800a3 | 368 | if (vdev->config_len) |
53c25cea | 369 | vdev->get_config(vdev, vdev->config); |
aba800a3 MT |
370 | } |
371 | ||
372 | static void virtio_write_config(PCIDevice *pci_dev, uint32_t address, | |
373 | uint32_t val, int len) | |
374 | { | |
ed757e14 YV |
375 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); |
376 | ||
377 | if (PCI_COMMAND == address) { | |
378 | if (!(val & PCI_COMMAND_MASTER)) { | |
49e75cf3 | 379 | proxy->vdev->status &= ~VIRTIO_CONFIG_S_DRIVER_OK; |
ed757e14 YV |
380 | } |
381 | } | |
382 | ||
aba800a3 | 383 | pci_default_write_config(pci_dev, address, val, len); |
85352471 | 384 | msix_write_config(pci_dev, address, val, len); |
53c25cea PB |
385 | } |
386 | ||
6d74ca5a MT |
387 | static unsigned virtio_pci_get_features(void *opaque) |
388 | { | |
8172539d MT |
389 | VirtIOPCIProxy *proxy = opaque; |
390 | return proxy->host_features; | |
6d74ca5a MT |
391 | } |
392 | ||
53c25cea | 393 | static const VirtIOBindings virtio_pci_bindings = { |
ff24bd58 MT |
394 | .notify = virtio_pci_notify, |
395 | .save_config = virtio_pci_save_config, | |
396 | .load_config = virtio_pci_load_config, | |
397 | .save_queue = virtio_pci_save_queue, | |
398 | .load_queue = virtio_pci_load_queue, | |
6d74ca5a | 399 | .get_features = virtio_pci_get_features, |
53c25cea PB |
400 | }; |
401 | ||
402 | static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev, | |
403 | uint16_t vendor, uint16_t device, | |
404 | uint16_t class_code, uint8_t pif) | |
405 | { | |
406 | uint8_t *config; | |
407 | uint32_t size; | |
408 | ||
409 | proxy->vdev = vdev; | |
410 | ||
411 | config = proxy->pci_dev.config; | |
412 | pci_config_set_vendor_id(config, vendor); | |
413 | pci_config_set_device_id(config, device); | |
414 | ||
415 | config[0x08] = VIRTIO_PCI_ABI_VERSION; | |
416 | ||
417 | config[0x09] = pif; | |
418 | pci_config_set_class(config, class_code); | |
419 | config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; | |
420 | ||
421 | config[0x2c] = vendor & 0xFF; | |
422 | config[0x2d] = (vendor >> 8) & 0xFF; | |
423 | config[0x2e] = vdev->device_id & 0xFF; | |
424 | config[0x2f] = (vdev->device_id >> 8) & 0xFF; | |
425 | ||
426 | config[0x3d] = 1; | |
427 | ||
5a1fc5e8 | 428 | if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) { |
aba800a3 MT |
429 | pci_register_bar(&proxy->pci_dev, 1, |
430 | msix_bar_size(&proxy->pci_dev), | |
0392a017 | 431 | PCI_BASE_ADDRESS_SPACE_MEMORY, |
aba800a3 | 432 | msix_mmio_map); |
aba800a3 MT |
433 | } else |
434 | vdev->nvectors = 0; | |
435 | ||
ed757e14 YV |
436 | proxy->pci_dev.config_write = virtio_write_config; |
437 | ||
aba800a3 | 438 | size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev) + vdev->config_len; |
53c25cea PB |
439 | if (size & (size-1)) |
440 | size = 1 << qemu_fls(size); | |
441 | ||
0392a017 | 442 | pci_register_bar(&proxy->pci_dev, 0, size, PCI_BASE_ADDRESS_SPACE_IO, |
53c25cea PB |
443 | virtio_map); |
444 | ||
445 | virtio_bind_device(vdev, &virtio_pci_bindings, proxy); | |
8172539d MT |
446 | proxy->host_features |= 0x1 << VIRTIO_F_NOTIFY_ON_EMPTY; |
447 | proxy->host_features |= 0x1 << VIRTIO_F_BAD_FEATURE; | |
448 | proxy->host_features = vdev->get_features(vdev, proxy->host_features); | |
53c25cea PB |
449 | } |
450 | ||
81a322d4 | 451 | static int virtio_blk_init_pci(PCIDevice *pci_dev) |
53c25cea PB |
452 | { |
453 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); | |
454 | VirtIODevice *vdev; | |
455 | ||
ab73ff29 GH |
456 | if (proxy->class_code != PCI_CLASS_STORAGE_SCSI && |
457 | proxy->class_code != PCI_CLASS_STORAGE_OTHER) | |
458 | proxy->class_code = PCI_CLASS_STORAGE_SCSI; | |
53c25cea | 459 | |
d176c495 | 460 | if (!proxy->dinfo) { |
84fc5589 | 461 | qemu_error("virtio-blk-pci: drive property not set\n"); |
81a322d4 | 462 | return -1; |
d176c495 GH |
463 | } |
464 | vdev = virtio_blk_init(&pci_dev->qdev, proxy->dinfo); | |
177539e0 | 465 | vdev->nvectors = proxy->nvectors; |
53c25cea PB |
466 | virtio_init_pci(proxy, vdev, |
467 | PCI_VENDOR_ID_REDHAT_QUMRANET, | |
85c2c735 MM |
468 | PCI_DEVICE_ID_VIRTIO_BLOCK, |
469 | proxy->class_code, 0x00); | |
177539e0 GH |
470 | /* make the actual value visible */ |
471 | proxy->nvectors = vdev->nvectors; | |
81a322d4 | 472 | return 0; |
21d58b57 MM |
473 | } |
474 | ||
0f457d91 MT |
475 | static int virtio_exit_pci(PCIDevice *pci_dev) |
476 | { | |
477 | return msix_uninit(pci_dev); | |
478 | } | |
479 | ||
56a14938 GH |
480 | static int virtio_blk_exit_pci(PCIDevice *pci_dev) |
481 | { | |
482 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); | |
483 | ||
484 | drive_uninit(proxy->dinfo); | |
0f457d91 | 485 | return virtio_exit_pci(pci_dev); |
56a14938 GH |
486 | } |
487 | ||
98b19252 | 488 | static int virtio_serial_init_pci(PCIDevice *pci_dev) |
21d58b57 | 489 | { |
d6beee99 | 490 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); |
85c2c735 MM |
491 | VirtIODevice *vdev; |
492 | ||
d6beee99 GH |
493 | if (proxy->class_code != PCI_CLASS_COMMUNICATION_OTHER && |
494 | proxy->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */ | |
495 | proxy->class_code != PCI_CLASS_OTHERS) /* qemu-kvm */ | |
496 | proxy->class_code = PCI_CLASS_COMMUNICATION_OTHER; | |
497 | ||
98b19252 | 498 | vdev = virtio_serial_init(&pci_dev->qdev, proxy->max_virtserial_ports); |
25fe3654 AS |
499 | if (!vdev) { |
500 | return -1; | |
501 | } | |
85c2c735 MM |
502 | virtio_init_pci(proxy, vdev, |
503 | PCI_VENDOR_ID_REDHAT_QUMRANET, | |
504 | PCI_DEVICE_ID_VIRTIO_CONSOLE, | |
505 | proxy->class_code, 0x00); | |
81a322d4 | 506 | return 0; |
53c25cea PB |
507 | } |
508 | ||
81a322d4 | 509 | static int virtio_net_init_pci(PCIDevice *pci_dev) |
53c25cea PB |
510 | { |
511 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); | |
512 | VirtIODevice *vdev; | |
513 | ||
97b15621 | 514 | vdev = virtio_net_init(&pci_dev->qdev, &proxy->nic); |
a1e0fea5 | 515 | |
97b15621 | 516 | vdev->nvectors = proxy->nvectors; |
53c25cea PB |
517 | virtio_init_pci(proxy, vdev, |
518 | PCI_VENDOR_ID_REDHAT_QUMRANET, | |
519 | PCI_DEVICE_ID_VIRTIO_NET, | |
520 | PCI_CLASS_NETWORK_ETHERNET, | |
521 | 0x00); | |
a1e0fea5 GH |
522 | |
523 | /* make the actual value visible */ | |
524 | proxy->nvectors = vdev->nvectors; | |
81a322d4 | 525 | return 0; |
53c25cea PB |
526 | } |
527 | ||
97b15621 GH |
528 | static int virtio_net_exit_pci(PCIDevice *pci_dev) |
529 | { | |
530 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); | |
531 | ||
532 | virtio_net_exit(proxy->vdev); | |
533 | return virtio_exit_pci(pci_dev); | |
534 | } | |
535 | ||
81a322d4 | 536 | static int virtio_balloon_init_pci(PCIDevice *pci_dev) |
53c25cea PB |
537 | { |
538 | VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev); | |
539 | VirtIODevice *vdev; | |
540 | ||
541 | vdev = virtio_balloon_init(&pci_dev->qdev); | |
542 | virtio_init_pci(proxy, vdev, | |
543 | PCI_VENDOR_ID_REDHAT_QUMRANET, | |
544 | PCI_DEVICE_ID_VIRTIO_BALLOON, | |
545 | PCI_CLASS_MEMORY_RAM, | |
546 | 0x00); | |
81a322d4 | 547 | return 0; |
53c25cea PB |
548 | } |
549 | ||
0aab0d3a GH |
550 | static PCIDeviceInfo virtio_info[] = { |
551 | { | |
552 | .qdev.name = "virtio-blk-pci", | |
553 | .qdev.size = sizeof(VirtIOPCIProxy), | |
554 | .init = virtio_blk_init_pci, | |
56a14938 | 555 | .exit = virtio_blk_exit_pci, |
ab73ff29 | 556 | .qdev.props = (Property[]) { |
72c61d0b GH |
557 | DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0), |
558 | DEFINE_PROP_DRIVE("drive", VirtIOPCIProxy, dinfo), | |
177539e0 | 559 | DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2), |
8172539d | 560 | DEFINE_VIRTIO_BLK_FEATURES(VirtIOPCIProxy, host_features), |
72c61d0b | 561 | DEFINE_PROP_END_OF_LIST(), |
ab73ff29 | 562 | }, |
e489030d | 563 | .qdev.reset = virtio_pci_reset, |
0aab0d3a | 564 | },{ |
a1e0fea5 GH |
565 | .qdev.name = "virtio-net-pci", |
566 | .qdev.size = sizeof(VirtIOPCIProxy), | |
567 | .init = virtio_net_init_pci, | |
97b15621 | 568 | .exit = virtio_net_exit_pci, |
8c52c8f3 | 569 | .romfile = "pxe-virtio.bin", |
a1e0fea5 | 570 | .qdev.props = (Property[]) { |
97b15621 | 571 | DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3), |
8172539d | 572 | DEFINE_VIRTIO_NET_FEATURES(VirtIOPCIProxy, host_features), |
97b15621 | 573 | DEFINE_NIC_PROPERTIES(VirtIOPCIProxy, nic), |
72c61d0b | 574 | DEFINE_PROP_END_OF_LIST(), |
a1e0fea5 | 575 | }, |
e489030d | 576 | .qdev.reset = virtio_pci_reset, |
0aab0d3a | 577 | },{ |
98b19252 AS |
578 | .qdev.name = "virtio-serial-pci", |
579 | .qdev.alias = "virtio-serial", | |
0aab0d3a | 580 | .qdev.size = sizeof(VirtIOPCIProxy), |
98b19252 | 581 | .init = virtio_serial_init_pci, |
0f457d91 | 582 | .exit = virtio_exit_pci, |
d6beee99 | 583 | .qdev.props = (Property[]) { |
72c61d0b | 584 | DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0), |
8172539d | 585 | DEFINE_VIRTIO_COMMON_FEATURES(VirtIOPCIProxy, host_features), |
98b19252 AS |
586 | DEFINE_PROP_UINT32("max_ports", VirtIOPCIProxy, max_virtserial_ports, |
587 | 31), | |
72c61d0b | 588 | DEFINE_PROP_END_OF_LIST(), |
d6beee99 | 589 | }, |
e489030d | 590 | .qdev.reset = virtio_pci_reset, |
0aab0d3a GH |
591 | },{ |
592 | .qdev.name = "virtio-balloon-pci", | |
593 | .qdev.size = sizeof(VirtIOPCIProxy), | |
594 | .init = virtio_balloon_init_pci, | |
0f457d91 | 595 | .exit = virtio_exit_pci, |
8172539d MT |
596 | .qdev.props = (Property[]) { |
597 | DEFINE_VIRTIO_COMMON_FEATURES(VirtIOPCIProxy, host_features), | |
598 | DEFINE_PROP_END_OF_LIST(), | |
599 | }, | |
e489030d | 600 | .qdev.reset = virtio_pci_reset, |
0aab0d3a GH |
601 | },{ |
602 | /* end of list */ | |
603 | } | |
604 | }; | |
605 | ||
53c25cea PB |
606 | static void virtio_pci_register_devices(void) |
607 | { | |
0aab0d3a | 608 | pci_qdev_register_many(virtio_info); |
53c25cea PB |
609 | } |
610 | ||
611 | device_init(virtio_pci_register_devices) |