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savevm: Add DeviceState param
[mirror_qemu.git] / hw / vmware_vga.c
CommitLineData
d34cab9f
TS		 1/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b 24#include "hw.h"
b3c3f123 25#include "loader.h"
87ecb68b
PB		 26#include "console.h"
27#include "pci.h"
18e08a55 28#include "vmware_vga.h"
d34cab9f
TS		 29
30#define VERBOSE
d34cab9f
TS		 31#undef DIRECT_VRAM
32#define HW_RECT_ACCEL
33#define HW_FILL_ACCEL
34#define HW_MOUSE_ACCEL
35
d34cab9f 36# include "vga_int.h"
d34cab9f
TS		 37
38struct vmsvga_state_s {
4e12cd94 39 VGACommonState vga;
d34cab9f
TS		 40
41 int width;
42 int height;
43 int invalidated;
44 int depth;
45 int bypp;
46 int enable;
47 int config;
48 struct {
49 int id;
50 int x;
51 int y;
52 int on;
53 } cursor;
54
c227f099 55 target_phys_addr_t vram_base;
d34cab9f
TS		 56
57 int index;
58 int scratch_size;
59 uint32_t *scratch;
60 int new_width;
61 int new_height;
62 uint32_t guest;
63 uint32_t svgaid;
64 uint32_t wred;
65 uint32_t wgreen;
66 uint32_t wblue;
67 int syncing;
68 int fb_size;
69
f351d050
DA		 70 ram_addr_t fifo_offset;
71 uint8_t *fifo_ptr;
72 unsigned int fifo_size;
73 target_phys_addr_t fifo_base;
74
d34cab9f
TS		 75 union {
76 uint32_t *fifo;
77 struct __attribute__((__packed__)) {
78 uint32_t min;
79 uint32_t max;
80 uint32_t next_cmd;
81 uint32_t stop;
82 /* Add registers here when adding capabilities. */
83 uint32_t fifo[0];
84 } *cmd;
85 };
86
87#define REDRAW_FIFO_LEN 512
88 struct vmsvga_rect_s {
89 int x, y, w, h;
90 } redraw_fifo[REDRAW_FIFO_LEN];
91 int redraw_fifo_first, redraw_fifo_last;
92};
93
94struct pci_vmsvga_state_s {
95 PCIDevice card;
96 struct vmsvga_state_s chip;
97};
98
99#define SVGA_MAGIC 0x900000UL
100#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
101#define SVGA_ID_0 SVGA_MAKE_ID(0)
102#define SVGA_ID_1 SVGA_MAKE_ID(1)
103#define SVGA_ID_2 SVGA_MAKE_ID(2)
104
105#define SVGA_LEGACY_BASE_PORT 0x4560
106#define SVGA_INDEX_PORT 0x0
107#define SVGA_VALUE_PORT 0x1
108#define SVGA_BIOS_PORT 0x2
109
110#define SVGA_VERSION_2
111
112#ifdef SVGA_VERSION_2
113# define SVGA_ID SVGA_ID_2
114# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
115# define SVGA_IO_MUL 1
116# define SVGA_FIFO_SIZE 0x10000
1f72aae5 117# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 118# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
119#else
120# define SVGA_ID SVGA_ID_1
121# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
122# define SVGA_IO_MUL 4
123# define SVGA_FIFO_SIZE 0x10000
1f72aae5 124# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 125# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
126#endif
127
128enum {
129 /* ID 0, 1 and 2 registers */
130 SVGA_REG_ID = 0,
131 SVGA_REG_ENABLE = 1,
132 SVGA_REG_WIDTH = 2,
133 SVGA_REG_HEIGHT = 3,
134 SVGA_REG_MAX_WIDTH = 4,
135 SVGA_REG_MAX_HEIGHT = 5,
136 SVGA_REG_DEPTH = 6,
137 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
138 SVGA_REG_PSEUDOCOLOR = 8,
139 SVGA_REG_RED_MASK = 9,
140 SVGA_REG_GREEN_MASK = 10,
141 SVGA_REG_BLUE_MASK = 11,
142 SVGA_REG_BYTES_PER_LINE = 12,
143 SVGA_REG_FB_START = 13,
144 SVGA_REG_FB_OFFSET = 14,
145 SVGA_REG_VRAM_SIZE = 15,
146 SVGA_REG_FB_SIZE = 16,
147
148 /* ID 1 and 2 registers */
149 SVGA_REG_CAPABILITIES = 17,
150 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
151 SVGA_REG_MEM_SIZE = 19,
152 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
153 SVGA_REG_SYNC = 21, /* Write to force synchronization */
154 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
155 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
156 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
157 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
158 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
159 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
160 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
161 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
162 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
163 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
164 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
165
166 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
167 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
168 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
169};
170
171#define SVGA_CAP_NONE 0
172#define SVGA_CAP_RECT_FILL (1 << 0)
173#define SVGA_CAP_RECT_COPY (1 << 1)
174#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
175#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
176#define SVGA_CAP_RASTER_OP (1 << 4)
177#define SVGA_CAP_CURSOR (1 << 5)
178#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
179#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
180#define SVGA_CAP_8BIT_EMULATION (1 << 8)
181#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
182#define SVGA_CAP_GLYPH (1 << 10)
183#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
184#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
185#define SVGA_CAP_ALPHA_BLEND (1 << 13)
186#define SVGA_CAP_3D (1 << 14)
187#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
188#define SVGA_CAP_MULTIMON (1 << 16)
189#define SVGA_CAP_PITCHLOCK (1 << 17)
190
191/*
192 * FIFO offsets (seen as an array of 32-bit words)
193 */
194enum {
195 /*
196 * The original defined FIFO offsets
197 */
198 SVGA_FIFO_MIN = 0,
199 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
200 SVGA_FIFO_NEXT_CMD,
201 SVGA_FIFO_STOP,
202
203 /*
204 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
205 */
206 SVGA_FIFO_CAPABILITIES = 4,
207 SVGA_FIFO_FLAGS,
208 SVGA_FIFO_FENCE,
209 SVGA_FIFO_3D_HWVERSION,
210 SVGA_FIFO_PITCHLOCK,
211};
212
213#define SVGA_FIFO_CAP_NONE 0
214#define SVGA_FIFO_CAP_FENCE (1 << 0)
215#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
216#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
217
218#define SVGA_FIFO_FLAG_NONE 0
219#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
220
221/* These values can probably be changed arbitrarily. */
222#define SVGA_SCRATCH_SIZE 0x8000
223#define SVGA_MAX_WIDTH 2360
224#define SVGA_MAX_HEIGHT 1770
225
226#ifdef VERBOSE
227# define GUEST_OS_BASE 0x5001
228static const char *vmsvga_guest_id[] = {
f707cfba
AZ		 229 [0x00] = "Dos",
230 [0x01] = "Windows 3.1",
231 [0x02] = "Windows 95",
232 [0x03] = "Windows 98",
233 [0x04] = "Windows ME",
234 [0x05] = "Windows NT",
235 [0x06] = "Windows 2000",
236 [0x07] = "Linux",
237 [0x08] = "OS/2",
511d2b14 238 [0x09] = "an unknown OS",
f707cfba
AZ		 239 [0x0a] = "BSD",
240 [0x0b] = "Whistler",
511d2b14
BS		 241 [0x0c] = "an unknown OS",
242 [0x0d] = "an unknown OS",
243 [0x0e] = "an unknown OS",
244 [0x0f] = "an unknown OS",
245 [0x10] = "an unknown OS",
246 [0x11] = "an unknown OS",
247 [0x12] = "an unknown OS",
248 [0x13] = "an unknown OS",
249 [0x14] = "an unknown OS",
f707cfba 250 [0x15] = "Windows 2003",
d34cab9f
TS		 251};
252#endif
253
254enum {
255 SVGA_CMD_INVALID_CMD = 0,
256 SVGA_CMD_UPDATE = 1,
257 SVGA_CMD_RECT_FILL = 2,
258 SVGA_CMD_RECT_COPY = 3,
259 SVGA_CMD_DEFINE_BITMAP = 4,
260 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
261 SVGA_CMD_DEFINE_PIXMAP = 6,
262 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
263 SVGA_CMD_RECT_BITMAP_FILL = 8,
264 SVGA_CMD_RECT_PIXMAP_FILL = 9,
265 SVGA_CMD_RECT_BITMAP_COPY = 10,
266 SVGA_CMD_RECT_PIXMAP_COPY = 11,
267 SVGA_CMD_FREE_OBJECT = 12,
268 SVGA_CMD_RECT_ROP_FILL = 13,
269 SVGA_CMD_RECT_ROP_COPY = 14,
270 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
271 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
272 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
273 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
274 SVGA_CMD_DEFINE_CURSOR = 19,
275 SVGA_CMD_DISPLAY_CURSOR = 20,
276 SVGA_CMD_MOVE_CURSOR = 21,
277 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
278 SVGA_CMD_DRAW_GLYPH = 23,
279 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
280 SVGA_CMD_UPDATE_VERBOSE = 25,
281 SVGA_CMD_SURFACE_FILL = 26,
282 SVGA_CMD_SURFACE_COPY = 27,
283 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
284 SVGA_CMD_FRONT_ROP_FILL = 29,
285 SVGA_CMD_FENCE = 30,
286};
287
288/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
289enum {
290 SVGA_CURSOR_ON_HIDE = 0,
291 SVGA_CURSOR_ON_SHOW = 1,
292 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
293 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
294};
295
296static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
297 int x, int y, int w, int h)
298{
299#ifndef DIRECT_VRAM
a8fbaf96
AZ		 300 int line;
301 int bypl;
302 int width;
303 int start;
304 uint8_t *src;
305 uint8_t *dst;
306
307 if (x + w > s->width) {
308 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
309 __FUNCTION__, x, w);
310 x = MIN(x, s->width);
311 w = s->width - x;
312 }
313
314 if (y + h > s->height) {
315 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
316 __FUNCTION__, y, h);
317 y = MIN(y, s->height);
318 h = s->height - y;
319 }
320
321 line = h;
322 bypl = s->bypp * s->width;
323 width = s->bypp * w;
324 start = s->bypp * x + bypl * y;
4e12cd94
AK		 325 src = s->vga.vram_ptr + start;
326 dst = ds_get_data(s->vga.ds) + start;
d34cab9f
TS		 327
328 for (; line > 0; line --, src += bypl, dst += bypl)
329 memcpy(dst, src, width);
330#endif
331
4e12cd94 332 dpy_update(s->vga.ds, x, y, w, h);
d34cab9f
TS		 333}
334
335static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
336{
337#ifndef DIRECT_VRAM
4e12cd94 338 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
d34cab9f
TS		 339#endif
340
4e12cd94 341 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
d34cab9f
TS		 342}
343
344#ifdef DIRECT_VRAM
345# define vmsvga_update_rect_delayed vmsvga_update_rect
346#else
347static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
348 int x, int y, int w, int h)
349{
350 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
351 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
352 rect->x = x;
353 rect->y = y;
354 rect->w = w;
355 rect->h = h;
356}
357#endif
358
359static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
360{
361 struct vmsvga_rect_s *rect;
362 if (s->invalidated) {
363 s->redraw_fifo_first = s->redraw_fifo_last;
364 return;
365 }
366 /* Overlapping region updates can be optimised out here - if someone
367 * knows a smart algorithm to do that, please share. */
368 while (s->redraw_fifo_first != s->redraw_fifo_last) {
369 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
370 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
371 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
372 }
373}
374
375#ifdef HW_RECT_ACCEL
376static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
377 int x0, int y0, int x1, int y1, int w, int h)
378{
379# ifdef DIRECT_VRAM
0e1f5a0c 380 uint8_t *vram = ds_get_data(s->ds);
d34cab9f 381# else
4e12cd94 382 uint8_t *vram = s->vga.vram_ptr;
d34cab9f
TS		 383# endif
384 int bypl = s->bypp * s->width;
385 int width = s->bypp * w;
386 int line = h;
387 uint8_t *ptr[2];
388
389# ifdef DIRECT_VRAM
390 if (s->ds->dpy_copy)
3023f332 391 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
d34cab9f
TS		 392 else
393# endif
394 {
395 if (y1 > y0) {
396 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
397 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
398 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
399 memmove(ptr[1], ptr[0], width);
400 } else {
401 ptr[0] = vram + s->bypp * x0 + bypl * y0;
402 ptr[1] = vram + s->bypp * x1 + bypl * y1;
403 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
404 memmove(ptr[1], ptr[0], width);
405 }
406 }
407
408 vmsvga_update_rect_delayed(s, x1, y1, w, h);
409}
410#endif
411
412#ifdef HW_FILL_ACCEL
413static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
414 uint32_t c, int x, int y, int w, int h)
415{
416# ifdef DIRECT_VRAM
0e1f5a0c 417 uint8_t *vram = ds_get_data(s->ds);
d34cab9f 418# else
4e12cd94 419 uint8_t *vram = s->vga.vram_ptr;
d34cab9f
TS		 420# endif
421 int bypp = s->bypp;
422 int bypl = bypp * s->width;
423 int width = bypp * w;
424 int line = h;
425 int column;
426 uint8_t *fst = vram + bypp * x + bypl * y;
427 uint8_t *dst;
428 uint8_t *src;
429 uint8_t col[4];
430
431# ifdef DIRECT_VRAM
432 if (s->ds->dpy_fill)
433 s->ds->dpy_fill(s->ds, x, y, w, h, c);
434 else
435# endif
436 {
437 col[0] = c;
438 col[1] = c >> 8;
439 col[2] = c >> 16;
440 col[3] = c >> 24;
441
442 if (line --) {
443 dst = fst;
444 src = col;
445 for (column = width; column > 0; column --) {
446 *(dst ++) = *(src ++);
447 if (src - col == bypp)
448 src = col;
449 }
450 dst = fst;
451 for (; line > 0; line --) {
452 dst += bypl;
453 memcpy(dst, fst, width);
454 }
455 }
456 }
457
458 vmsvga_update_rect_delayed(s, x, y, w, h);
459}
460#endif
461
462struct vmsvga_cursor_definition_s {
463 int width;
464 int height;
465 int id;
466 int bpp;
467 int hot_x;
468 int hot_y;
469 uint32_t mask[1024];
8095cb3e 470 uint32_t image[4096];
d34cab9f
TS		 471};
472
473#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
474#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
475
476#ifdef HW_MOUSE_ACCEL
477static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
478 struct vmsvga_cursor_definition_s *c)
479{
fbe6d7a4
GH		 480 QEMUCursor *qc;
481 int i, pixels;
482
483 qc = cursor_alloc(c->width, c->height);
484 qc->hot_x = c->hot_x;
485 qc->hot_y = c->hot_y;
486 switch (c->bpp) {
487 case 1:
488 cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image,
489 1, (void*)c->mask);
490#ifdef DEBUG
491 cursor_print_ascii_art(qc, "vmware/mono");
492#endif
493 break;
494 case 32:
495 /* fill alpha channel from mask, set color to zero */
496 cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask,
497 1, (void*)c->mask);
498 /* add in rgb values */
499 pixels = c->width * c->height;
500 for (i = 0; i < pixels; i++) {
501 qc->data[i] |= c->image[i] & 0xffffff;
502 }
503#ifdef DEBUG
504 cursor_print_ascii_art(qc, "vmware/32bit");
505#endif
506 break;
507 default:
508 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
509 __FUNCTION__, c->bpp);
510 cursor_put(qc);
511 qc = cursor_builtin_left_ptr();
512 }
d34cab9f 513
4e12cd94 514 if (s->vga.ds->cursor_define)
fbe6d7a4
GH		 515 s->vga.ds->cursor_define(qc);
516 cursor_put(qc);
d34cab9f
TS		 517}
518#endif
519
ff9cf2cb
AZ		 520#define CMD(f) le32_to_cpu(s->cmd->f)
521
d34cab9f
TS		 522static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
523{
524 if (!s->config || !s->enable)
f707cfba 525 return 1;
d34cab9f
TS		 526 return (s->cmd->next_cmd == s->cmd->stop);
527}
528
ff9cf2cb 529static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
d34cab9f 530{
ff9cf2cb
AZ		 531 uint32_t cmd = s->fifo[CMD(stop) >> 2];
532 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
533 if (CMD(stop) >= CMD(max))
d34cab9f
TS		 534 s->cmd->stop = s->cmd->min;
535 return cmd;
536}
537
ff9cf2cb
AZ		 538static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
539{
540 return le32_to_cpu(vmsvga_fifo_read_raw(s));
541}
542
d34cab9f
TS		 543static void vmsvga_fifo_run(struct vmsvga_state_s *s)
544{
545 uint32_t cmd, colour;
546 int args = 0;
547 int x, y, dx, dy, width, height;
548 struct vmsvga_cursor_definition_s cursor;
549 while (!vmsvga_fifo_empty(s))
550 switch (cmd = vmsvga_fifo_read(s)) {
551 case SVGA_CMD_UPDATE:
552 case SVGA_CMD_UPDATE_VERBOSE:
553 x = vmsvga_fifo_read(s);
554 y = vmsvga_fifo_read(s);
555 width = vmsvga_fifo_read(s);
556 height = vmsvga_fifo_read(s);
557 vmsvga_update_rect_delayed(s, x, y, width, height);
558 break;
559
560 case SVGA_CMD_RECT_FILL:
561 colour = vmsvga_fifo_read(s);
562 x = vmsvga_fifo_read(s);
563 y = vmsvga_fifo_read(s);
564 width = vmsvga_fifo_read(s);
565 height = vmsvga_fifo_read(s);
566#ifdef HW_FILL_ACCEL
567 vmsvga_fill_rect(s, colour, x, y, width, height);
568 break;
569#else
570 goto badcmd;
571#endif
572
573 case SVGA_CMD_RECT_COPY:
574 x = vmsvga_fifo_read(s);
575 y = vmsvga_fifo_read(s);
576 dx = vmsvga_fifo_read(s);
577 dy = vmsvga_fifo_read(s);
578 width = vmsvga_fifo_read(s);
579 height = vmsvga_fifo_read(s);
580#ifdef HW_RECT_ACCEL
581 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
582 break;
583#else
584 goto badcmd;
585#endif
586
587 case SVGA_CMD_DEFINE_CURSOR:
588 cursor.id = vmsvga_fifo_read(s);
589 cursor.hot_x = vmsvga_fifo_read(s);
590 cursor.hot_y = vmsvga_fifo_read(s);
591 cursor.width = x = vmsvga_fifo_read(s);
592 cursor.height = y = vmsvga_fifo_read(s);
593 vmsvga_fifo_read(s);
594 cursor.bpp = vmsvga_fifo_read(s);
f2d928d4
RD		 595
596 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
597 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
598 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
599 goto badcmd;
600 }
601
d34cab9f 602 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
ff9cf2cb 603 cursor.mask[args] = vmsvga_fifo_read_raw(s);
d34cab9f 604 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
ff9cf2cb 605 cursor.image[args] = vmsvga_fifo_read_raw(s);
d34cab9f
TS		 606#ifdef HW_MOUSE_ACCEL
607 vmsvga_cursor_define(s, &cursor);
608 break;
609#else
610 args = 0;
611 goto badcmd;
612#endif
613
614 /*
615 * Other commands that we at least know the number of arguments
616 * for so we can avoid FIFO desync if driver uses them illegally.
617 */
618 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
619 vmsvga_fifo_read(s);
620 vmsvga_fifo_read(s);
621 vmsvga_fifo_read(s);
622 x = vmsvga_fifo_read(s);
623 y = vmsvga_fifo_read(s);
624 args = x * y;
625 goto badcmd;
626 case SVGA_CMD_RECT_ROP_FILL:
627 args = 6;
628 goto badcmd;
629 case SVGA_CMD_RECT_ROP_COPY:
630 args = 7;
631 goto badcmd;
632 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
633 vmsvga_fifo_read(s);
634 vmsvga_fifo_read(s);
635 args = 7 + (vmsvga_fifo_read(s) >> 2);
636 goto badcmd;
637 case SVGA_CMD_SURFACE_ALPHA_BLEND:
638 args = 12;
639 goto badcmd;
640
641 /*
642 * Other commands that are not listed as depending on any
643 * CAPABILITIES bits, but are not described in the README either.
644 */
645 case SVGA_CMD_SURFACE_FILL:
646 case SVGA_CMD_SURFACE_COPY:
647 case SVGA_CMD_FRONT_ROP_FILL:
648 case SVGA_CMD_FENCE:
649 case SVGA_CMD_INVALID_CMD:
650 break; /* Nop */
651
652 default:
653 badcmd:
654 while (args --)
655 vmsvga_fifo_read(s);
656 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
657 __FUNCTION__, cmd);
658 break;
659 }
660
661 s->syncing = 0;
662}
663
664static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
665{
467d44b2 666 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 667 return s->index;
668}
669
670static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
671{
467d44b2 672 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 673 s->index = index;
674}
675
676static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
677{
678 uint32_t caps;
467d44b2 679 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 680 switch (s->index) {
681 case SVGA_REG_ID:
682 return s->svgaid;
683
684 case SVGA_REG_ENABLE:
685 return s->enable;
686
687 case SVGA_REG_WIDTH:
688 return s->width;
689
690 case SVGA_REG_HEIGHT:
691 return s->height;
692
693 case SVGA_REG_MAX_WIDTH:
694 return SVGA_MAX_WIDTH;
695
696 case SVGA_REG_MAX_HEIGHT:
f707cfba 697 return SVGA_MAX_HEIGHT;
d34cab9f
TS		 698
699 case SVGA_REG_DEPTH:
700 return s->depth;
701
702 case SVGA_REG_BITS_PER_PIXEL:
703 return (s->depth + 7) & ~7;
704
705 case SVGA_REG_PSEUDOCOLOR:
706 return 0x0;
707
708 case SVGA_REG_RED_MASK:
709 return s->wred;
710 case SVGA_REG_GREEN_MASK:
711 return s->wgreen;
712 case SVGA_REG_BLUE_MASK:
713 return s->wblue;
714
715 case SVGA_REG_BYTES_PER_LINE:
716 return ((s->depth + 7) >> 3) * s->new_width;
717
718 case SVGA_REG_FB_START:
3016d80b 719 return s->vram_base;
d34cab9f
TS		 720
721 case SVGA_REG_FB_OFFSET:
722 return 0x0;
723
724 case SVGA_REG_VRAM_SIZE:
f351d050 725 return s->vga.vram_size;
d34cab9f
TS		 726
727 case SVGA_REG_FB_SIZE:
728 return s->fb_size;
729
730 case SVGA_REG_CAPABILITIES:
731 caps = SVGA_CAP_NONE;
732#ifdef HW_RECT_ACCEL
733 caps |= SVGA_CAP_RECT_COPY;
734#endif
735#ifdef HW_FILL_ACCEL
736 caps |= SVGA_CAP_RECT_FILL;
737#endif
738#ifdef HW_MOUSE_ACCEL
4e12cd94 739 if (s->vga.ds->mouse_set)
d34cab9f
TS		 740 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
741 SVGA_CAP_CURSOR_BYPASS;
742#endif
743 return caps;
744
745 case SVGA_REG_MEM_START:
f351d050 746 return s->fifo_base;
d34cab9f
TS		 747
748 case SVGA_REG_MEM_SIZE:
f351d050 749 return s->fifo_size;
d34cab9f
TS		 750
751 case SVGA_REG_CONFIG_DONE:
752 return s->config;
753
754 case SVGA_REG_SYNC:
755 case SVGA_REG_BUSY:
756 return s->syncing;
757
758 case SVGA_REG_GUEST_ID:
759 return s->guest;
760
761 case SVGA_REG_CURSOR_ID:
762 return s->cursor.id;
763
764 case SVGA_REG_CURSOR_X:
765 return s->cursor.x;
766
767 case SVGA_REG_CURSOR_Y:
768 return s->cursor.x;
769
770 case SVGA_REG_CURSOR_ON:
771 return s->cursor.on;
772
773 case SVGA_REG_HOST_BITS_PER_PIXEL:
774 return (s->depth + 7) & ~7;
775
776 case SVGA_REG_SCRATCH_SIZE:
777 return s->scratch_size;
778
779 case SVGA_REG_MEM_REGS:
780 case SVGA_REG_NUM_DISPLAYS:
781 case SVGA_REG_PITCHLOCK:
782 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
783 return 0;
784
785 default:
786 if (s->index >= SVGA_SCRATCH_BASE &&
787 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
788 return s->scratch[s->index - SVGA_SCRATCH_BASE];
789 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
790 }
791
792 return 0;
793}
794
795static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
796{
467d44b2 797 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 798 switch (s->index) {
799 case SVGA_REG_ID:
800 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
801 s->svgaid = value;
802 break;
803
804 case SVGA_REG_ENABLE:
f707cfba
AZ		 805 s->enable = value;
806 s->config &= !!value;
d34cab9f
TS		 807 s->width = -1;
808 s->height = -1;
809 s->invalidated = 1;
4e12cd94 810 s->vga.invalidate(&s->vga);
b5cc6e32
AL		 811 if (s->enable) {
812 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
813 vga_dirty_log_stop(&s->vga);
814 } else {
815 vga_dirty_log_start(&s->vga);
816 }
d34cab9f
TS		 817 break;
818
819 case SVGA_REG_WIDTH:
820 s->new_width = value;
821 s->invalidated = 1;
822 break;
823
824 case SVGA_REG_HEIGHT:
825 s->new_height = value;
826 s->invalidated = 1;
827 break;
828
829 case SVGA_REG_DEPTH:
830 case SVGA_REG_BITS_PER_PIXEL:
831 if (value != s->depth) {
832 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
833 s->config = 0;
834 }
835 break;
836
837 case SVGA_REG_CONFIG_DONE:
838 if (value) {
f351d050 839 s->fifo = (uint32_t *) s->fifo_ptr;
d34cab9f 840 /* Check range and alignment. */
ff9cf2cb
AZ		 841 if ((CMD(min) | CMD(max) |
842 CMD(next_cmd) | CMD(stop)) & 3)
d34cab9f 843 break;
ff9cf2cb 844 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
d34cab9f 845 break;
ff9cf2cb 846 if (CMD(max) > SVGA_FIFO_SIZE)
d34cab9f 847 break;
ff9cf2cb 848 if (CMD(max) < CMD(min) + 10 * 1024)
d34cab9f
TS		 849 break;
850 }
f707cfba 851 s->config = !!value;
d34cab9f
TS		 852 break;
853
854 case SVGA_REG_SYNC:
855 s->syncing = 1;
856 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
857 break;
858
859 case SVGA_REG_GUEST_ID:
860 s->guest = value;
861#ifdef VERBOSE
862 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
b1503cda 863 ARRAY_SIZE(vmsvga_guest_id))
d34cab9f
TS		 864 printf("%s: guest runs %s.\n", __FUNCTION__,
865 vmsvga_guest_id[value - GUEST_OS_BASE]);
866#endif
867 break;
868
869 case SVGA_REG_CURSOR_ID:
870 s->cursor.id = value;
871 break;
872
873 case SVGA_REG_CURSOR_X:
874 s->cursor.x = value;
875 break;
876
877 case SVGA_REG_CURSOR_Y:
878 s->cursor.y = value;
879 break;
880
881 case SVGA_REG_CURSOR_ON:
882 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
883 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
884#ifdef HW_MOUSE_ACCEL
4e12cd94
AK		 885 if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
886 s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
d34cab9f
TS		 887#endif
888 break;
889
890 case SVGA_REG_MEM_REGS:
891 case SVGA_REG_NUM_DISPLAYS:
892 case SVGA_REG_PITCHLOCK:
893 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
894 break;
895
896 default:
897 if (s->index >= SVGA_SCRATCH_BASE &&
898 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
899 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
900 break;
901 }
902 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
903 }
904}
905
906static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
907{
908 printf("%s: what are we supposed to return?\n", __FUNCTION__);
909 return 0xcafe;
910}
911
912static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
913{
914 printf("%s: what are we supposed to do with (%08x)?\n",
915 __FUNCTION__, data);
916}
917
918static inline void vmsvga_size(struct vmsvga_state_s *s)
919{
920 if (s->new_width != s->width || s->new_height != s->height) {
921 s->width = s->new_width;
922 s->height = s->new_height;
4e12cd94 923 qemu_console_resize(s->vga.ds, s->width, s->height);
d34cab9f
TS		 924 s->invalidated = 1;
925 }
926}
927
928static void vmsvga_update_display(void *opaque)
929{
467d44b2 930 struct vmsvga_state_s *s = opaque;
d34cab9f 931 if (!s->enable) {
4e12cd94 932 s->vga.update(&s->vga);
d34cab9f
TS		 933 return;
934 }
935
936 vmsvga_size(s);
937
938 vmsvga_fifo_run(s);
939 vmsvga_update_rect_flush(s);
940
941 /*
942 * Is it more efficient to look at vram VGA-dirty bits or wait
943 * for the driver to issue SVGA_CMD_UPDATE?
944 */
945 if (s->invalidated) {
946 s->invalidated = 0;
947 vmsvga_update_screen(s);
948 }
949}
950
951static void vmsvga_reset(struct vmsvga_state_s *s)
952{
953 s->index = 0;
954 s->enable = 0;
955 s->config = 0;
956 s->width = -1;
957 s->height = -1;
958 s->svgaid = SVGA_ID;
a6109ff1
AL		 959 s->depth = ds_get_bits_per_pixel(s->vga.ds);
960 s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
d34cab9f
TS		 961 s->cursor.on = 0;
962 s->redraw_fifo_first = 0;
963 s->redraw_fifo_last = 0;
964 switch (s->depth) {
965 case 8:
966 s->wred = 0x00000007;
967 s->wgreen = 0x00000038;
968 s->wblue = 0x000000c0;
969 break;
970 case 15:
971 s->wred = 0x0000001f;
972 s->wgreen = 0x000003e0;
973 s->wblue = 0x00007c00;
974 break;
975 case 16:
976 s->wred = 0x0000001f;
977 s->wgreen = 0x000007e0;
978 s->wblue = 0x0000f800;
979 break;
980 case 24:
f707cfba 981 s->wred = 0x00ff0000;
d34cab9f 982 s->wgreen = 0x0000ff00;
f707cfba 983 s->wblue = 0x000000ff;
d34cab9f
TS		 984 break;
985 case 32:
f707cfba 986 s->wred = 0x00ff0000;
d34cab9f 987 s->wgreen = 0x0000ff00;
f707cfba 988 s->wblue = 0x000000ff;
d34cab9f
TS		 989 break;
990 }
991 s->syncing = 0;
b5cc6e32
AL		 992
993 vga_dirty_log_start(&s->vga);
d34cab9f
TS		 994}
995
996static void vmsvga_invalidate_display(void *opaque)
997{
467d44b2 998 struct vmsvga_state_s *s = opaque;
d34cab9f 999 if (!s->enable) {
4e12cd94 1000 s->vga.invalidate(&s->vga);
d34cab9f
TS		 1001 return;
1002 }
1003
1004 s->invalidated = 1;
1005}
1006
f707cfba
AZ		 1007/* save the vga display in a PPM image even if no display is
1008 available */
d34cab9f
TS		 1009static void vmsvga_screen_dump(void *opaque, const char *filename)
1010{
467d44b2 1011 struct vmsvga_state_s *s = opaque;
d34cab9f 1012 if (!s->enable) {
4e12cd94 1013 s->vga.screen_dump(&s->vga, filename);
d34cab9f
TS		 1014 return;
1015 }
1016
f707cfba 1017 if (s->depth == 32) {
e07d630a 1018 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
4e12cd94 1019 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
e07d630a
AL		 1020 ppm_save(filename, ds);
1021 qemu_free(ds);
f707cfba 1022 }
d34cab9f
TS		 1023}
1024
c227f099 1025static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
4d3b6f6e 1026{
467d44b2 1027 struct vmsvga_state_s *s = opaque;
4d3b6f6e 1028
4e12cd94
AK		 1029 if (s->vga.text_update)
1030 s->vga.text_update(&s->vga, chardata);
4d3b6f6e
AZ		 1031}
1032
d34cab9f 1033#ifdef DIRECT_VRAM
c227f099 1034static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
d34cab9f 1035{
467d44b2 1036 struct vmsvga_state_s *s = opaque;
d34cab9f 1037 if (addr < s->fb_size)
0e1f5a0c 1038 return *(uint8_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1039 else
b584726d 1040 return *(uint8_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1041}
1042
c227f099 1043static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
d34cab9f 1044{
467d44b2 1045 struct vmsvga_state_s *s = opaque;
d34cab9f 1046 if (addr < s->fb_size)
0e1f5a0c 1047 return *(uint16_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1048 else
b584726d 1049 return *(uint16_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1050}
1051
c227f099 1052static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
d34cab9f 1053{
467d44b2 1054 struct vmsvga_state_s *s = opaque;
d34cab9f 1055 if (addr < s->fb_size)
0e1f5a0c 1056 return *(uint32_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1057 else
b584726d 1058 return *(uint32_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1059}
1060
c227f099 1061static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1062 uint32_t value)
1063{
467d44b2 1064 struct vmsvga_state_s *s = opaque;
d34cab9f 1065 if (addr < s->fb_size)
0e1f5a0c 1066 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1067 else
b584726d 1068 *(uint8_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1069}
1070
c227f099 1071static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1072 uint32_t value)
1073{
467d44b2 1074 struct vmsvga_state_s *s = opaque;
d34cab9f 1075 if (addr < s->fb_size)
0e1f5a0c 1076 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1077 else
b584726d 1078 *(uint16_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1079}
1080
c227f099 1081static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1082 uint32_t value)
1083{
467d44b2 1084 struct vmsvga_state_s *s = opaque;
d34cab9f 1085 if (addr < s->fb_size)
0e1f5a0c 1086 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1087 else
b584726d 1088 *(uint32_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1089}
1090
d60efc6b 1091static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
d34cab9f
TS		 1092 vmsvga_vram_readb,
1093 vmsvga_vram_readw,
1094 vmsvga_vram_readl,
1095};
1096
d60efc6b 1097static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
d34cab9f
TS		 1098 vmsvga_vram_writeb,
1099 vmsvga_vram_writew,
1100 vmsvga_vram_writel,
1101};
1102#endif
1103
bacbe284 1104static int vmsvga_post_load(void *opaque, int version_id)
d34cab9f 1105{
bacbe284 1106 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 1107
1108 s->invalidated = 1;
1109 if (s->config)
f351d050 1110 s->fifo = (uint32_t *) s->fifo_ptr;
d34cab9f
TS		 1111
1112 return 0;
1113}
1114
d05ac8fa 1115static const VMStateDescription vmstate_vmware_vga_internal = {
bacbe284
JQ		 1116 .name = "vmware_vga_internal",
1117 .version_id = 0,
1118 .minimum_version_id = 0,
1119 .minimum_version_id_old = 0,
1120 .post_load = vmsvga_post_load,
1121 .fields = (VMStateField []) {
1122 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1123 VMSTATE_INT32(enable, struct vmsvga_state_s),
1124 VMSTATE_INT32(config, struct vmsvga_state_s),
1125 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1126 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1127 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1128 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1129 VMSTATE_INT32(index, struct vmsvga_state_s),
1130 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1131 scratch_size, 0, vmstate_info_uint32, uint32_t),
1132 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1133 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1134 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1135 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1136 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1137 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1138 VMSTATE_END_OF_LIST()
1139 }
1140};
1141
d05ac8fa 1142static const VMStateDescription vmstate_vmware_vga = {
bacbe284
JQ		 1143 .name = "vmware_vga",
1144 .version_id = 0,
1145 .minimum_version_id = 0,
1146 .minimum_version_id_old = 0,
1147 .fields = (VMStateField []) {
1148 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1149 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1150 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1151 VMSTATE_END_OF_LIST()
1152 }
1153};
1154
b584726d 1155static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
d34cab9f 1156{
d34cab9f 1157 s->scratch_size = SVGA_SCRATCH_SIZE;
fe740c43 1158 s->scratch = qemu_malloc(s->scratch_size * 4);
d34cab9f 1159
a6109ff1
AL		 1160 s->vga.ds = graphic_console_init(vmsvga_update_display,
1161 vmsvga_invalidate_display,
1162 vmsvga_screen_dump,
1163 vmsvga_text_update, s);
1164
4445b0a6 1165
f351d050
DA		 1166 s->fifo_size = SVGA_FIFO_SIZE;
1167 s->fifo_offset = qemu_ram_alloc(s->fifo_size);
1168 s->fifo_ptr = qemu_get_ram_ptr(s->fifo_offset);
1169
a4a2f59c
JQ		 1170 vga_common_init(&s->vga, vga_ram_size);
1171 vga_init(&s->vga);
0be71e32 1172 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
e93a5f4f 1173
f0138a63 1174 vga_init_vbe(&s->vga);
b5cc6e32 1175
f0138a63 1176 rom_add_vga(VGABIOS_FILENAME);
b5cc6e32
AL		 1177
1178 vmsvga_reset(s);
d34cab9f
TS		 1179}
1180
1492a3c4 1181static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
6e355d90 1182 pcibus_t addr, pcibus_t size, int type)
1492a3c4
AZ		 1183{
1184 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1185 struct vmsvga_state_s *s = &d->chip;
1186
1187 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1188 1, 4, vmsvga_index_read, s);
1189 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1190 1, 4, vmsvga_index_write, s);
1191 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1192 1, 4, vmsvga_value_read, s);
1193 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1194 1, 4, vmsvga_value_write, s);
1195 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1196 1, 4, vmsvga_bios_read, s);
1197 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1198 1, 4, vmsvga_bios_write, s);
1199}
1200
3016d80b 1201static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
6e355d90 1202 pcibus_t addr, pcibus_t size, int type)
3016d80b
AZ		 1203{
1204 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1205 struct vmsvga_state_s *s = &d->chip;
c227f099 1206 ram_addr_t iomemtype;
3016d80b
AZ		 1207
1208 s->vram_base = addr;
1209#ifdef DIRECT_VRAM
1eed09cb 1210 iomemtype = cpu_register_io_memory(vmsvga_vram_read,
3016d80b
AZ		 1211 vmsvga_vram_write, s);
1212#else
4e12cd94 1213 iomemtype = s->vga.vram_offset | IO_MEM_RAM;
3016d80b 1214#endif
4e12cd94 1215 cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
3016d80b 1216 iomemtype);
ee3e41a9
AL		 1217
1218 s->vga.map_addr = addr;
1219 s->vga.map_end = addr + s->vga.vram_size;
b5cc6e32 1220 vga_dirty_log_restart(&s->vga);
3016d80b
AZ		 1221}
1222
f351d050
DA		 1223static void pci_vmsvga_map_fifo(PCIDevice *pci_dev, int region_num,
1224 pcibus_t addr, pcibus_t size, int type)
1225{
1226 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1227 struct vmsvga_state_s *s = &d->chip;
1228 ram_addr_t iomemtype;
1229
1230 s->fifo_base = addr;
1231 iomemtype = s->fifo_offset | IO_MEM_RAM;
1232 cpu_register_physical_memory(s->fifo_base, s->fifo_size,
1233 iomemtype);
1234}
1235
81a322d4 1236static int pci_vmsvga_initfn(PCIDevice *dev)
d34cab9f 1237{
a414c306
GH		 1238 struct pci_vmsvga_state_s *s =
1239 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
d34cab9f 1240
deb54399
AL		 1241 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1242 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
3fa0f955
MT		 1243 s->card.config[PCI_COMMAND] = PCI_COMMAND_IO |
1244 PCI_COMMAND_MEMORY |
1245 PCI_COMMAND_MASTER; /* I/O + Memory */
173a543b 1246 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
3fa0f955
MT		 1247 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
1248 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
1249 s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
1250 s->card.config[PCI_SUBSYSTEM_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1251 s->card.config[PCI_SUBSYSTEM_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1252 s->card.config[PCI_SUBSYSTEM_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1253 s->card.config[PCI_SUBSYSTEM_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1254 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
d34cab9f 1255
28c2c264 1256 pci_register_bar(&s->card, 0, 0x10,
0392a017 1257 PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
28c2c264 1258 pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
0392a017 1259 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem);
1492a3c4 1260
f351d050
DA		 1261 pci_register_bar(&s->card, 2, SVGA_FIFO_SIZE,
1262 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_fifo);
1263
fbe1b595 1264 vmsvga_init(&s->chip, VGA_RAM_SIZE);
d34cab9f 1265
81a322d4 1266 return 0;
d34cab9f 1267}
a414c306
GH		 1268
1269void pci_vmsvga_init(PCIBus *bus)
1270{
556cd098 1271 pci_create_simple(bus, -1, "vmware-svga");
a414c306
GH		 1272}
1273
1274static PCIDeviceInfo vmsvga_info = {
556cd098 1275 .qdev.name = "vmware-svga",
a414c306 1276 .qdev.size = sizeof(struct pci_vmsvga_state_s),
be73cfe2 1277 .qdev.vmsd = &vmstate_vmware_vga,
a414c306
GH		 1278 .init = pci_vmsvga_initfn,
1279};
1280
1281static void vmsvga_register(void)
1282{
1283 pci_qdev_register(&vmsvga_info);
1284}
1285device_init(vmsvga_register);
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