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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
13 | #include "hw.h" | |
14 | #include "pc.h" | |
15 | #include "vt82c686.h" | |
16 | #include "i2c.h" | |
17 | #include "smbus.h" | |
18 | #include "pci.h" | |
19 | #include "isa.h" | |
20 | #include "sysbus.h" | |
21 | #include "mips.h" | |
22 | #include "apm.h" | |
23 | #include "acpi.h" | |
24 | #include "pm_smbus.h" | |
25 | #include "sysemu.h" | |
26 | #include "qemu-timer.h" | |
a2902821 | 27 | #include "exec-memory.h" |
edf79e66 HC |
28 | |
29 | typedef uint32_t pci_addr_t; | |
30 | #include "pci_host.h" | |
31 | //#define DEBUG_VT82C686B | |
32 | ||
33 | #ifdef DEBUG_VT82C686B | |
34 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
35 | #else | |
36 | #define DPRINTF(fmt, ...) | |
37 | #endif | |
38 | ||
39 | typedef struct SuperIOConfig | |
40 | { | |
41 | uint8_t config[0xff]; | |
42 | uint8_t index; | |
43 | uint8_t data; | |
44 | } SuperIOConfig; | |
45 | ||
46 | typedef struct VT82C686BState { | |
47 | PCIDevice dev; | |
48 | SuperIOConfig superio_conf; | |
49 | } VT82C686BState; | |
50 | ||
51 | static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) | |
52 | { | |
53 | int can_write; | |
54 | SuperIOConfig *superio_conf = opaque; | |
55 | ||
b2bedb21 | 56 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
edf79e66 HC |
57 | if (addr == 0x3f0) { |
58 | superio_conf->index = data & 0xff; | |
59 | } else { | |
60 | /* 0x3f1 */ | |
61 | switch (superio_conf->index) { | |
62 | case 0x00 ... 0xdf: | |
63 | case 0xe4: | |
64 | case 0xe5: | |
65 | case 0xe9 ... 0xed: | |
66 | case 0xf3: | |
67 | case 0xf5: | |
68 | case 0xf7: | |
69 | case 0xf9 ... 0xfb: | |
70 | case 0xfd ... 0xff: | |
71 | can_write = 0; | |
72 | break; | |
73 | default: | |
74 | can_write = 1; | |
75 | ||
76 | if (can_write) { | |
77 | switch (superio_conf->index) { | |
78 | case 0xe7: | |
79 | if ((data & 0xff) != 0xfe) { | |
b2bedb21 | 80 | DPRINTF("chage uart 1 base. unsupported yet\n"); |
edf79e66 HC |
81 | } |
82 | break; | |
83 | case 0xe8: | |
84 | if ((data & 0xff) != 0xbe) { | |
b2bedb21 | 85 | DPRINTF("chage uart 2 base. unsupported yet\n"); |
edf79e66 HC |
86 | } |
87 | break; | |
88 | ||
89 | default: | |
90 | superio_conf->config[superio_conf->index] = data & 0xff; | |
91 | } | |
92 | } | |
93 | } | |
94 | superio_conf->config[superio_conf->index] = data & 0xff; | |
95 | } | |
96 | } | |
97 | ||
98 | static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) | |
99 | { | |
100 | SuperIOConfig *superio_conf = opaque; | |
101 | ||
b2bedb21 | 102 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
edf79e66 HC |
103 | return (superio_conf->config[superio_conf->index]); |
104 | } | |
105 | ||
106 | static void vt82c686b_reset(void * opaque) | |
107 | { | |
108 | PCIDevice *d = opaque; | |
109 | uint8_t *pci_conf = d->config; | |
110 | VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); | |
111 | ||
112 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
113 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
114 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
115 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
116 | ||
117 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
118 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
119 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
120 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
121 | pci_conf[0x59] = 0x04; | |
122 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
123 | pci_conf[0x5f] = 0x04; | |
124 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
125 | ||
126 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
127 | vt82c->superio_conf.config[0xe2] = 0x03; | |
128 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
129 | vt82c->superio_conf.config[0xe6] = 0xde; | |
130 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
131 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
132 | } | |
133 | ||
134 | /* write config pci function0 registers. PCI-ISA bridge */ | |
135 | static void vt82c686b_write_config(PCIDevice * d, uint32_t address, | |
136 | uint32_t val, int len) | |
137 | { | |
138 | VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); | |
139 | ||
b2bedb21 | 140 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
141 | address, val, len); |
142 | ||
143 | pci_default_write_config(d, address, val, len); | |
144 | if (address == 0x85) { /* enable or disable super IO configure */ | |
145 | if (val & 0x2) { | |
146 | /* floppy also uses 0x3f0 and 0x3f1. | |
147 | * But we do not emulate flopy,so just set it here. */ | |
148 | isa_unassign_ioport(0x3f0, 2); | |
149 | register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, | |
150 | &vt686->superio_conf); | |
151 | register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, | |
152 | &vt686->superio_conf); | |
153 | } else { | |
154 | isa_unassign_ioport(0x3f0, 2); | |
155 | } | |
156 | } | |
157 | } | |
158 | ||
159 | #define ACPI_DBG_IO_ADDR 0xb044 | |
160 | ||
161 | typedef struct VT686PMState { | |
162 | PCIDevice dev; | |
a2902821 | 163 | MemoryRegion io; |
355bf2e5 | 164 | ACPIREGS ar; |
edf79e66 | 165 | APMState apm; |
edf79e66 HC |
166 | PMSMBus smb; |
167 | uint32_t smb_io_base; | |
168 | } VT686PMState; | |
169 | ||
170 | typedef struct VT686AC97State { | |
171 | PCIDevice dev; | |
172 | } VT686AC97State; | |
173 | ||
174 | typedef struct VT686MC97State { | |
175 | PCIDevice dev; | |
176 | } VT686MC97State; | |
177 | ||
edf79e66 HC |
178 | static void pm_update_sci(VT686PMState *s) |
179 | { | |
180 | int sci_level, pmsts; | |
edf79e66 | 181 | |
2886be1b | 182 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 183 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
04dc308f IY |
184 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
185 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
186 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
187 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
edf79e66 HC |
188 | qemu_set_irq(s->dev.irq[0], sci_level); |
189 | /* schedule a timer interruption if needed */ | |
355bf2e5 | 190 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 191 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
192 | } |
193 | ||
355bf2e5 | 194 | static void pm_tmr_timer(ACPIREGS *ar) |
edf79e66 | 195 | { |
355bf2e5 | 196 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
edf79e66 HC |
197 | pm_update_sci(s); |
198 | } | |
199 | ||
200 | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
201 | { | |
202 | VT686PMState *s = opaque; | |
203 | ||
204 | addr &= 0x0f; | |
205 | switch (addr) { | |
206 | case 0x00: | |
355bf2e5 | 207 | acpi_pm1_evt_write_sts(&s->ar, val); |
04dc308f | 208 | pm_update_sci(s); |
edf79e66 HC |
209 | break; |
210 | case 0x02: | |
8283c4f5 | 211 | acpi_pm1_evt_write_en(&s->ar, val); |
edf79e66 HC |
212 | pm_update_sci(s); |
213 | break; | |
edf79e66 HC |
214 | default: |
215 | break; | |
216 | } | |
217 | DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val); | |
218 | } | |
219 | ||
220 | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) | |
221 | { | |
222 | VT686PMState *s = opaque; | |
223 | uint32_t val; | |
224 | ||
225 | addr &= 0x0f; | |
226 | switch (addr) { | |
227 | case 0x00: | |
2886be1b | 228 | val = acpi_pm1_evt_get_sts(&s->ar); |
edf79e66 HC |
229 | break; |
230 | case 0x02: | |
355bf2e5 | 231 | val = s->ar.pm1.evt.en; |
edf79e66 | 232 | break; |
edf79e66 HC |
233 | default: |
234 | val = 0; | |
235 | break; | |
236 | } | |
237 | DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val); | |
238 | return val; | |
239 | } | |
240 | ||
241 | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
242 | { | |
243 | addr &= 0x0f; | |
244 | DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val); | |
245 | } | |
246 | ||
247 | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) | |
248 | { | |
edf79e66 HC |
249 | uint32_t val; |
250 | ||
251 | addr &= 0x0f; | |
252 | switch (addr) { | |
edf79e66 HC |
253 | default: |
254 | val = 0; | |
255 | break; | |
256 | } | |
257 | DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val); | |
258 | return val; | |
259 | } | |
260 | ||
a2902821 GH |
261 | static const MemoryRegionOps pm_io_ops = { |
262 | .old_portio = (MemoryRegionPortio[]) { | |
263 | { .offset = 0, .len = 64, .size = 2, | |
264 | .read = pm_ioport_readw, .write = pm_ioport_writew }, | |
265 | { .offset = 0, .len = 64, .size = 4, | |
266 | .read = pm_ioport_readl, .write = pm_ioport_writel }, | |
267 | PORTIO_END_OF_LIST(), | |
268 | }, | |
269 | .valid.min_access_size = 1, | |
270 | .valid.max_access_size = 4, | |
271 | .impl.min_access_size = 1, | |
272 | .impl.max_access_size = 4, | |
273 | .endianness = DEVICE_LITTLE_ENDIAN, | |
274 | }; | |
275 | ||
edf79e66 HC |
276 | static void pm_io_space_update(VT686PMState *s) |
277 | { | |
278 | uint32_t pm_io_base; | |
279 | ||
a2902821 GH |
280 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
281 | pm_io_base &= 0xffc0; | |
edf79e66 | 282 | |
a2902821 GH |
283 | memory_region_transaction_begin(); |
284 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
285 | memory_region_set_address(&s->io, pm_io_base); | |
286 | memory_region_transaction_commit(); | |
edf79e66 HC |
287 | } |
288 | ||
289 | static void pm_write_config(PCIDevice *d, | |
290 | uint32_t address, uint32_t val, int len) | |
291 | { | |
b2bedb21 | 292 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
293 | address, val, len); |
294 | pci_default_write_config(d, address, val, len); | |
295 | } | |
296 | ||
297 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
298 | { | |
299 | VT686PMState *s = opaque; | |
300 | ||
301 | pm_io_space_update(s); | |
302 | return 0; | |
303 | } | |
304 | ||
305 | static const VMStateDescription vmstate_acpi = { | |
306 | .name = "vt82c686b_pm", | |
307 | .version_id = 1, | |
308 | .minimum_version_id = 1, | |
309 | .minimum_version_id_old = 1, | |
310 | .post_load = vmstate_acpi_post_load, | |
311 | .fields = (VMStateField []) { | |
312 | VMSTATE_PCI_DEVICE(dev, VT686PMState), | |
355bf2e5 GH |
313 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
314 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
315 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 316 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
317 | VMSTATE_TIMER(ar.tmr.timer, VT686PMState), |
318 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), | |
edf79e66 HC |
319 | VMSTATE_END_OF_LIST() |
320 | } | |
321 | }; | |
322 | ||
323 | /* | |
324 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() | |
325 | * just register a PCI device now, functionalities will be implemented later. | |
326 | */ | |
327 | ||
328 | static int vt82c686b_ac97_initfn(PCIDevice *dev) | |
329 | { | |
330 | VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); | |
331 | uint8_t *pci_conf = s->dev.config; | |
332 | ||
edf79e66 HC |
333 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
334 | PCI_COMMAND_PARITY); | |
335 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
336 | PCI_STATUS_DEVSEL_MEDIUM); | |
337 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) | |
343 | { | |
344 | PCIDevice *dev; | |
345 | ||
346 | dev = pci_create(bus, devfn, "VT82C686B_AC97"); | |
347 | qdev_init_nofail(&dev->qdev); | |
348 | } | |
349 | ||
40021f08 AL |
350 | static void via_ac97_class_init(ObjectClass *klass, void *data) |
351 | { | |
39bffca2 | 352 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
353 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
354 | ||
355 | k->init = vt82c686b_ac97_initfn; | |
356 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
357 | k->device_id = PCI_DEVICE_ID_VIA_AC97; | |
358 | k->revision = 0x50; | |
359 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; | |
39bffca2 | 360 | dc->desc = "AC97"; |
40021f08 AL |
361 | } |
362 | ||
39bffca2 AL |
363 | static TypeInfo via_ac97_info = { |
364 | .name = "VT82C686B_AC97", | |
365 | .parent = TYPE_PCI_DEVICE, | |
366 | .instance_size = sizeof(VT686AC97State), | |
367 | .class_init = via_ac97_class_init, | |
edf79e66 HC |
368 | }; |
369 | ||
edf79e66 HC |
370 | static int vt82c686b_mc97_initfn(PCIDevice *dev) |
371 | { | |
372 | VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); | |
373 | uint8_t *pci_conf = s->dev.config; | |
374 | ||
edf79e66 HC |
375 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
376 | PCI_COMMAND_VGA_PALETTE); | |
377 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
378 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) | |
384 | { | |
385 | PCIDevice *dev; | |
386 | ||
387 | dev = pci_create(bus, devfn, "VT82C686B_MC97"); | |
388 | qdev_init_nofail(&dev->qdev); | |
389 | } | |
390 | ||
40021f08 AL |
391 | static void via_mc97_class_init(ObjectClass *klass, void *data) |
392 | { | |
39bffca2 | 393 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
394 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
395 | ||
396 | k->init = vt82c686b_mc97_initfn; | |
397 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
398 | k->device_id = PCI_DEVICE_ID_VIA_MC97; | |
399 | k->class_id = PCI_CLASS_COMMUNICATION_OTHER; | |
400 | k->revision = 0x30; | |
39bffca2 | 401 | dc->desc = "MC97"; |
40021f08 AL |
402 | } |
403 | ||
39bffca2 AL |
404 | static TypeInfo via_mc97_info = { |
405 | .name = "VT82C686B_MC97", | |
406 | .parent = TYPE_PCI_DEVICE, | |
407 | .instance_size = sizeof(VT686MC97State), | |
408 | .class_init = via_mc97_class_init, | |
edf79e66 HC |
409 | }; |
410 | ||
edf79e66 HC |
411 | /* vt82c686 pm init */ |
412 | static int vt82c686b_pm_initfn(PCIDevice *dev) | |
413 | { | |
414 | VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); | |
415 | uint8_t *pci_conf; | |
416 | ||
417 | pci_conf = s->dev.config; | |
edf79e66 HC |
418 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
419 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
420 | PCI_STATUS_DEVSEL_MEDIUM); | |
421 | ||
422 | /* 0x48-0x4B is Power Management I/O Base */ | |
423 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
424 | ||
425 | /* SMB ports:0xeee0~0xeeef */ | |
426 | s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); | |
427 | pci_conf[0x90] = s->smb_io_base | 1; | |
428 | pci_conf[0x91] = s->smb_io_base >> 8; | |
429 | pci_conf[0xd2] = 0x90; | |
430 | register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb); | |
431 | register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb); | |
432 | ||
433 | apm_init(&s->apm, NULL, s); | |
434 | ||
a2902821 GH |
435 | memory_region_init_io(&s->io, &pm_io_ops, s, "vt82c686-pm", 64); |
436 | memory_region_set_enabled(&s->io, false); | |
437 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
438 | ||
77d58b1e | 439 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
afafe4bb | 440 | acpi_pm1_cnt_init(&s->ar, &s->io); |
edf79e66 HC |
441 | |
442 | pm_smbus_init(&s->dev.qdev, &s->smb); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
448 | qemu_irq sci_irq) | |
449 | { | |
450 | PCIDevice *dev; | |
451 | VT686PMState *s; | |
452 | ||
453 | dev = pci_create(bus, devfn, "VT82C686B_PM"); | |
454 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
455 | ||
456 | s = DO_UPCAST(VT686PMState, dev, dev); | |
457 | ||
458 | qdev_init_nofail(&dev->qdev); | |
459 | ||
460 | return s->smb.smbus; | |
461 | } | |
462 | ||
40021f08 AL |
463 | static Property via_pm_properties[] = { |
464 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
465 | DEFINE_PROP_END_OF_LIST(), | |
466 | }; | |
467 | ||
468 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
469 | { | |
39bffca2 | 470 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
471 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
472 | ||
473 | k->init = vt82c686b_pm_initfn; | |
474 | k->config_write = pm_write_config; | |
475 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
476 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
477 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
478 | k->revision = 0x40; | |
39bffca2 AL |
479 | dc->desc = "PM"; |
480 | dc->vmsd = &vmstate_acpi; | |
481 | dc->props = via_pm_properties; | |
40021f08 AL |
482 | } |
483 | ||
39bffca2 AL |
484 | static TypeInfo via_pm_info = { |
485 | .name = "VT82C686B_PM", | |
486 | .parent = TYPE_PCI_DEVICE, | |
487 | .instance_size = sizeof(VT686PMState), | |
488 | .class_init = via_pm_class_init, | |
edf79e66 HC |
489 | }; |
490 | ||
edf79e66 HC |
491 | static const VMStateDescription vmstate_via = { |
492 | .name = "vt82c686b", | |
493 | .version_id = 1, | |
494 | .minimum_version_id = 1, | |
495 | .minimum_version_id_old = 1, | |
496 | .fields = (VMStateField []) { | |
497 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), | |
498 | VMSTATE_END_OF_LIST() | |
499 | } | |
500 | }; | |
501 | ||
502 | /* init the PCI-to-ISA bridge */ | |
503 | static int vt82c686b_initfn(PCIDevice *d) | |
504 | { | |
505 | uint8_t *pci_conf; | |
506 | uint8_t *wmask; | |
507 | int i; | |
508 | ||
c2d0d012 | 509 | isa_bus_new(&d->qdev, pci_address_space_io(d)); |
edf79e66 HC |
510 | |
511 | pci_conf = d->config; | |
edf79e66 | 512 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
513 | |
514 | wmask = d->wmask; | |
515 | for (i = 0x00; i < 0xff; i++) { | |
516 | if (i<=0x03 || (i>=0x08 && i<=0x3f)) { | |
517 | wmask[i] = 0x00; | |
518 | } | |
519 | } | |
520 | ||
521 | qemu_register_reset(vt82c686b_reset, d); | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
c9940edb | 526 | ISABus *vt82c686b_init(PCIBus *bus, int devfn) |
edf79e66 HC |
527 | { |
528 | PCIDevice *d; | |
529 | ||
aa5fb7b3 | 530 | d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); |
edf79e66 | 531 | |
c9940edb | 532 | return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0")); |
edf79e66 HC |
533 | } |
534 | ||
40021f08 AL |
535 | static void via_class_init(ObjectClass *klass, void *data) |
536 | { | |
39bffca2 | 537 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
538 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
539 | ||
540 | k->init = vt82c686b_initfn; | |
541 | k->config_write = vt82c686b_write_config; | |
542 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
543 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
544 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
545 | k->revision = 0x40; | |
39bffca2 AL |
546 | dc->desc = "ISA bridge"; |
547 | dc->no_user = 1; | |
548 | dc->vmsd = &vmstate_via; | |
40021f08 AL |
549 | } |
550 | ||
39bffca2 AL |
551 | static TypeInfo via_info = { |
552 | .name = "VT82C686B", | |
553 | .parent = TYPE_PCI_DEVICE, | |
554 | .instance_size = sizeof(VT82C686BState), | |
555 | .class_init = via_class_init, | |
edf79e66 HC |
556 | }; |
557 | ||
83f7d43a | 558 | static void vt82c686b_register_types(void) |
edf79e66 | 559 | { |
83f7d43a AF |
560 | type_register_static(&via_ac97_info); |
561 | type_register_static(&via_mc97_info); | |
562 | type_register_static(&via_pm_info); | |
39bffca2 | 563 | type_register_static(&via_info); |
edf79e66 | 564 | } |
83f7d43a AF |
565 | |
566 | type_init(vt82c686b_register_types) |