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050c2ea0 PM |
1 | /* |
2 | * ARM CMSDK APB watchdog emulation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * This is a model of the "APB watchdog" which is part of the Cortex-M | |
14 | * System Design Kit (CMSDK) and documented in the Cortex-M System | |
15 | * Design Kit Technical Reference Manual (ARM DDI0479C): | |
16 | * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit | |
566528f8 MH |
17 | * |
18 | * We also support the variant of this device found in the TI | |
19 | * Stellaris/Luminary boards and documented in: | |
20 | * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf | |
050c2ea0 PM |
21 | */ |
22 | ||
23 | #include "qemu/osdep.h" | |
24 | #include "qemu/log.h" | |
25 | #include "trace.h" | |
26 | #include "qapi/error.h" | |
27 | #include "qemu/main-loop.h" | |
0b8fa32f | 28 | #include "qemu/module.h" |
050c2ea0 PM |
29 | #include "sysemu/watchdog.h" |
30 | #include "hw/sysbus.h" | |
64552b6b | 31 | #include "hw/irq.h" |
050c2ea0 PM |
32 | #include "hw/registerfields.h" |
33 | #include "hw/watchdog/cmsdk-apb-watchdog.h" | |
d6454270 | 34 | #include "migration/vmstate.h" |
050c2ea0 PM |
35 | |
36 | REG32(WDOGLOAD, 0x0) | |
37 | REG32(WDOGVALUE, 0x4) | |
38 | REG32(WDOGCONTROL, 0x8) | |
39 | FIELD(WDOGCONTROL, INTEN, 0, 1) | |
40 | FIELD(WDOGCONTROL, RESEN, 1, 1) | |
41 | #define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \ | |
42 | R_WDOGCONTROL_RESEN_MASK) | |
43 | REG32(WDOGINTCLR, 0xc) | |
44 | REG32(WDOGRIS, 0x10) | |
45 | FIELD(WDOGRIS, INT, 0, 1) | |
46 | REG32(WDOGMIS, 0x14) | |
566528f8 | 47 | REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */ |
050c2ea0 PM |
48 | REG32(WDOGLOCK, 0xc00) |
49 | #define WDOG_UNLOCK_VALUE 0x1ACCE551 | |
50 | REG32(WDOGITCR, 0xf00) | |
51 | FIELD(WDOGITCR, ENABLE, 0, 1) | |
52 | #define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK | |
53 | REG32(WDOGITOP, 0xf04) | |
54 | FIELD(WDOGITOP, WDOGRES, 0, 1) | |
55 | FIELD(WDOGITOP, WDOGINT, 1, 1) | |
56 | #define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \ | |
57 | R_WDOGITOP_WDOGINT_MASK) | |
58 | REG32(PID4, 0xfd0) | |
59 | REG32(PID5, 0xfd4) | |
60 | REG32(PID6, 0xfd8) | |
61 | REG32(PID7, 0xfdc) | |
62 | REG32(PID0, 0xfe0) | |
63 | REG32(PID1, 0xfe4) | |
64 | REG32(PID2, 0xfe8) | |
65 | REG32(PID3, 0xfec) | |
66 | REG32(CID0, 0xff0) | |
67 | REG32(CID1, 0xff4) | |
68 | REG32(CID2, 0xff8) | |
69 | REG32(CID3, 0xffc) | |
70 | ||
71 | /* PID/CID values */ | |
566528f8 | 72 | static const uint32_t cmsdk_apb_watchdog_id[] = { |
050c2ea0 PM |
73 | 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ |
74 | 0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ | |
75 | 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ | |
76 | }; | |
77 | ||
566528f8 MH |
78 | static const uint32_t luminary_watchdog_id[] = { |
79 | 0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */ | |
80 | 0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */ | |
81 | 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ | |
82 | }; | |
83 | ||
050c2ea0 PM |
84 | static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s) |
85 | { | |
86 | /* Return masked interrupt status */ | |
87 | return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK); | |
88 | } | |
89 | ||
90 | static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s) | |
91 | { | |
92 | /* Return masked reset status */ | |
93 | return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK); | |
94 | } | |
95 | ||
96 | static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s) | |
97 | { | |
98 | bool wdogint; | |
99 | bool wdogres; | |
100 | ||
101 | if (s->itcr) { | |
566528f8 MH |
102 | /* |
103 | * Not checking that !s->is_luminary since s->itcr can't be written | |
104 | * when s->is_luminary in the first place. | |
105 | */ | |
050c2ea0 PM |
106 | wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK; |
107 | wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK; | |
108 | } else { | |
109 | wdogint = cmsdk_apb_watchdog_intstatus(s); | |
110 | wdogres = cmsdk_apb_watchdog_resetstatus(s); | |
111 | } | |
112 | ||
113 | qemu_set_irq(s->wdogint, wdogint); | |
114 | if (wdogres) { | |
115 | watchdog_perform_action(); | |
116 | } | |
117 | } | |
118 | ||
119 | static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset, | |
120 | unsigned size) | |
121 | { | |
122 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); | |
123 | uint64_t r; | |
124 | ||
125 | switch (offset) { | |
126 | case A_WDOGLOAD: | |
127 | r = ptimer_get_limit(s->timer); | |
128 | break; | |
129 | case A_WDOGVALUE: | |
130 | r = ptimer_get_count(s->timer); | |
131 | break; | |
132 | case A_WDOGCONTROL: | |
133 | r = s->control; | |
134 | break; | |
135 | case A_WDOGRIS: | |
136 | r = s->intstatus; | |
137 | break; | |
138 | case A_WDOGMIS: | |
139 | r = cmsdk_apb_watchdog_intstatus(s); | |
140 | break; | |
141 | case A_WDOGLOCK: | |
142 | r = s->lock; | |
143 | break; | |
144 | case A_WDOGITCR: | |
566528f8 MH |
145 | if (s->is_luminary) { |
146 | goto bad_offset; | |
147 | } | |
050c2ea0 PM |
148 | r = s->itcr; |
149 | break; | |
150 | case A_PID4 ... A_CID3: | |
566528f8 | 151 | r = s->id[(offset - A_PID4) / 4]; |
050c2ea0 PM |
152 | break; |
153 | case A_WDOGINTCLR: | |
154 | case A_WDOGITOP: | |
566528f8 MH |
155 | if (s->is_luminary) { |
156 | goto bad_offset; | |
157 | } | |
050c2ea0 PM |
158 | qemu_log_mask(LOG_GUEST_ERROR, |
159 | "CMSDK APB watchdog read: read of WO offset %x\n", | |
160 | (int)offset); | |
161 | r = 0; | |
162 | break; | |
566528f8 MH |
163 | case A_WDOGTEST: |
164 | if (!s->is_luminary) { | |
165 | goto bad_offset; | |
166 | } | |
167 | qemu_log_mask(LOG_UNIMP, | |
168 | "Luminary watchdog read: stall not implemented\n"); | |
169 | r = 0; | |
170 | break; | |
050c2ea0 | 171 | default: |
566528f8 | 172 | bad_offset: |
050c2ea0 PM |
173 | qemu_log_mask(LOG_GUEST_ERROR, |
174 | "CMSDK APB watchdog read: bad offset %x\n", (int)offset); | |
175 | r = 0; | |
176 | break; | |
177 | } | |
178 | trace_cmsdk_apb_watchdog_read(offset, r, size); | |
179 | return r; | |
180 | } | |
181 | ||
182 | static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | |
183 | uint64_t value, unsigned size) | |
184 | { | |
185 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); | |
186 | ||
187 | trace_cmsdk_apb_watchdog_write(offset, value, size); | |
188 | ||
189 | if (s->lock && offset != A_WDOGLOCK) { | |
190 | /* Write access is disabled via WDOGLOCK */ | |
191 | qemu_log_mask(LOG_GUEST_ERROR, | |
192 | "CMSDK APB watchdog write: write to locked watchdog\n"); | |
193 | return; | |
194 | } | |
195 | ||
196 | switch (offset) { | |
197 | case A_WDOGLOAD: | |
198 | /* | |
199 | * Reset the load value and the current count, and make sure | |
200 | * we're counting. | |
201 | */ | |
202 | ptimer_set_limit(s->timer, value, 1); | |
203 | ptimer_run(s->timer, 0); | |
204 | break; | |
205 | case A_WDOGCONTROL: | |
566528f8 MH |
206 | if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) { |
207 | /* | |
208 | * The Luminary version of this device ignores writes to | |
209 | * this register after the guest has enabled interrupts | |
210 | * (so they can only be disabled again via reset). | |
211 | */ | |
212 | break; | |
213 | } | |
050c2ea0 PM |
214 | s->control = value & R_WDOGCONTROL_VALID_MASK; |
215 | cmsdk_apb_watchdog_update(s); | |
216 | break; | |
217 | case A_WDOGINTCLR: | |
218 | s->intstatus = 0; | |
219 | ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); | |
220 | cmsdk_apb_watchdog_update(s); | |
221 | break; | |
222 | case A_WDOGLOCK: | |
223 | s->lock = (value != WDOG_UNLOCK_VALUE); | |
224 | break; | |
225 | case A_WDOGITCR: | |
566528f8 MH |
226 | if (s->is_luminary) { |
227 | goto bad_offset; | |
228 | } | |
050c2ea0 PM |
229 | s->itcr = value & R_WDOGITCR_VALID_MASK; |
230 | cmsdk_apb_watchdog_update(s); | |
231 | break; | |
232 | case A_WDOGITOP: | |
566528f8 MH |
233 | if (s->is_luminary) { |
234 | goto bad_offset; | |
235 | } | |
050c2ea0 PM |
236 | s->itop = value & R_WDOGITOP_VALID_MASK; |
237 | cmsdk_apb_watchdog_update(s); | |
238 | break; | |
239 | case A_WDOGVALUE: | |
240 | case A_WDOGRIS: | |
241 | case A_WDOGMIS: | |
242 | case A_PID4 ... A_CID3: | |
243 | qemu_log_mask(LOG_GUEST_ERROR, | |
244 | "CMSDK APB watchdog write: write to RO offset 0x%x\n", | |
245 | (int)offset); | |
246 | break; | |
566528f8 MH |
247 | case A_WDOGTEST: |
248 | if (!s->is_luminary) { | |
249 | goto bad_offset; | |
250 | } | |
251 | qemu_log_mask(LOG_UNIMP, | |
252 | "Luminary watchdog write: stall not implemented\n"); | |
253 | break; | |
050c2ea0 | 254 | default: |
566528f8 | 255 | bad_offset: |
050c2ea0 PM |
256 | qemu_log_mask(LOG_GUEST_ERROR, |
257 | "CMSDK APB watchdog write: bad offset 0x%x\n", | |
258 | (int)offset); | |
259 | break; | |
260 | } | |
261 | } | |
262 | ||
263 | static const MemoryRegionOps cmsdk_apb_watchdog_ops = { | |
264 | .read = cmsdk_apb_watchdog_read, | |
265 | .write = cmsdk_apb_watchdog_write, | |
266 | .endianness = DEVICE_LITTLE_ENDIAN, | |
267 | /* byte/halfword accesses are just zero-padded on reads and writes */ | |
268 | .impl.min_access_size = 4, | |
269 | .impl.max_access_size = 4, | |
270 | .valid.min_access_size = 1, | |
271 | .valid.max_access_size = 4, | |
272 | }; | |
273 | ||
274 | static void cmsdk_apb_watchdog_tick(void *opaque) | |
275 | { | |
276 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); | |
277 | ||
278 | if (!s->intstatus) { | |
279 | /* Count expired for the first time: raise interrupt */ | |
280 | s->intstatus = R_WDOGRIS_INT_MASK; | |
281 | } else { | |
282 | /* Count expired for the second time: raise reset and stop clock */ | |
283 | s->resetstatus = 1; | |
284 | ptimer_stop(s->timer); | |
285 | } | |
286 | cmsdk_apb_watchdog_update(s); | |
287 | } | |
288 | ||
289 | static void cmsdk_apb_watchdog_reset(DeviceState *dev) | |
290 | { | |
291 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); | |
292 | ||
293 | trace_cmsdk_apb_watchdog_reset(); | |
294 | s->control = 0; | |
295 | s->intstatus = 0; | |
296 | s->lock = 0; | |
297 | s->itcr = 0; | |
298 | s->itop = 0; | |
299 | s->resetstatus = 0; | |
300 | /* Set the limit and the count */ | |
301 | ptimer_set_limit(s->timer, 0xffffffff, 1); | |
302 | ptimer_run(s->timer, 0); | |
303 | } | |
304 | ||
305 | static void cmsdk_apb_watchdog_init(Object *obj) | |
306 | { | |
307 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
308 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj); | |
309 | ||
310 | memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops, | |
311 | s, "cmsdk-apb-watchdog", 0x1000); | |
312 | sysbus_init_mmio(sbd, &s->iomem); | |
313 | sysbus_init_irq(sbd, &s->wdogint); | |
566528f8 MH |
314 | |
315 | s->is_luminary = false; | |
316 | s->id = cmsdk_apb_watchdog_id; | |
050c2ea0 PM |
317 | } |
318 | ||
319 | static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | |
320 | { | |
321 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); | |
322 | QEMUBH *bh; | |
323 | ||
324 | if (s->wdogclk_frq == 0) { | |
325 | error_setg(errp, | |
326 | "CMSDK APB watchdog: wdogclk-frq property must be set"); | |
327 | return; | |
328 | } | |
329 | ||
330 | bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s); | |
331 | s->timer = ptimer_init(bh, | |
332 | PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | |
333 | PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | |
334 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | |
335 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | |
336 | ||
337 | ptimer_set_freq(s->timer, s->wdogclk_frq); | |
338 | } | |
339 | ||
340 | static const VMStateDescription cmsdk_apb_watchdog_vmstate = { | |
341 | .name = "cmsdk-apb-watchdog", | |
342 | .version_id = 1, | |
343 | .minimum_version_id = 1, | |
344 | .fields = (VMStateField[]) { | |
345 | VMSTATE_PTIMER(timer, CMSDKAPBWatchdog), | |
346 | VMSTATE_UINT32(control, CMSDKAPBWatchdog), | |
347 | VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog), | |
348 | VMSTATE_UINT32(lock, CMSDKAPBWatchdog), | |
349 | VMSTATE_UINT32(itcr, CMSDKAPBWatchdog), | |
350 | VMSTATE_UINT32(itop, CMSDKAPBWatchdog), | |
351 | VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog), | |
352 | VMSTATE_END_OF_LIST() | |
353 | } | |
354 | }; | |
355 | ||
356 | static Property cmsdk_apb_watchdog_properties[] = { | |
357 | DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0), | |
358 | DEFINE_PROP_END_OF_LIST(), | |
359 | }; | |
360 | ||
361 | static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) | |
362 | { | |
363 | DeviceClass *dc = DEVICE_CLASS(klass); | |
364 | ||
365 | dc->realize = cmsdk_apb_watchdog_realize; | |
366 | dc->vmsd = &cmsdk_apb_watchdog_vmstate; | |
367 | dc->reset = cmsdk_apb_watchdog_reset; | |
368 | dc->props = cmsdk_apb_watchdog_properties; | |
369 | } | |
370 | ||
371 | static const TypeInfo cmsdk_apb_watchdog_info = { | |
372 | .name = TYPE_CMSDK_APB_WATCHDOG, | |
373 | .parent = TYPE_SYS_BUS_DEVICE, | |
374 | .instance_size = sizeof(CMSDKAPBWatchdog), | |
375 | .instance_init = cmsdk_apb_watchdog_init, | |
376 | .class_init = cmsdk_apb_watchdog_class_init, | |
377 | }; | |
378 | ||
566528f8 MH |
379 | static void luminary_watchdog_init(Object *obj) |
380 | { | |
381 | CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj); | |
382 | ||
383 | s->is_luminary = true; | |
384 | s->id = luminary_watchdog_id; | |
385 | } | |
386 | ||
387 | static const TypeInfo luminary_watchdog_info = { | |
388 | .name = TYPE_LUMINARY_WATCHDOG, | |
389 | .parent = TYPE_CMSDK_APB_WATCHDOG, | |
390 | .instance_init = luminary_watchdog_init | |
391 | }; | |
392 | ||
050c2ea0 PM |
393 | static void cmsdk_apb_watchdog_register_types(void) |
394 | { | |
395 | type_register_static(&cmsdk_apb_watchdog_info); | |
566528f8 | 396 | type_register_static(&luminary_watchdog_info); |
050c2ea0 PM |
397 | } |
398 | ||
399 | type_init(cmsdk_apb_watchdog_register_types); |