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854123bf CLG |
1 | /* |
2 | * ASPEED Watchdog Controller | |
3 | * | |
4 | * Copyright (C) 2016-2017 IBM Corp. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
f55d613b AJ |
11 | |
12 | #include "qapi/error.h" | |
854123bf | 13 | #include "qemu/log.h" |
0b8fa32f | 14 | #include "qemu/module.h" |
f55d613b | 15 | #include "qemu/timer.h" |
854123bf | 16 | #include "sysemu/watchdog.h" |
f55d613b | 17 | #include "hw/misc/aspeed_scu.h" |
a27bd6c7 | 18 | #include "hw/qdev-properties.h" |
854123bf | 19 | #include "hw/sysbus.h" |
854123bf | 20 | #include "hw/watchdog/wdt_aspeed.h" |
d6454270 | 21 | #include "migration/vmstate.h" |
a8eb9a43 | 22 | #include "trace.h" |
854123bf | 23 | |
f55d613b AJ |
24 | #define WDT_STATUS (0x00 / 4) |
25 | #define WDT_RELOAD_VALUE (0x04 / 4) | |
26 | #define WDT_RESTART (0x08 / 4) | |
27 | #define WDT_CTRL (0x0C / 4) | |
854123bf CLG |
28 | #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) |
29 | #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) | |
30 | #define WDT_CTRL_1MHZ_CLK BIT(4) | |
31 | #define WDT_CTRL_WDT_EXT BIT(3) | |
32 | #define WDT_CTRL_WDT_INTR BIT(2) | |
33 | #define WDT_CTRL_RESET_SYSTEM BIT(1) | |
34 | #define WDT_CTRL_ENABLE BIT(0) | |
f55d613b AJ |
35 | #define WDT_RESET_WIDTH (0x18 / 4) |
36 | #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) | |
37 | #define WDT_POLARITY_MASK (0xFF << 24) | |
38 | #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) | |
39 | #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) | |
40 | #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) | |
41 | #define WDT_DRIVE_TYPE_MASK (0xFF << 24) | |
42 | #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) | |
43 | #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) | |
6b2b2a70 | 44 | #define WDT_RESET_MASK1 (0x1c / 4) |
f8ad8958 PMD |
45 | #define WDT_RESET_MASK2 (0x20 / 4) |
46 | ||
47 | #define WDT_SW_RESET_CTRL (0x24 / 4) | |
48 | #define WDT_SW_RESET_MASK1 (0x28 / 4) | |
49 | #define WDT_SW_RESET_MASK2 (0x2c / 4) | |
854123bf | 50 | |
f55d613b AJ |
51 | #define WDT_TIMEOUT_STATUS (0x10 / 4) |
52 | #define WDT_TIMEOUT_CLEAR (0x14 / 4) | |
854123bf | 53 | |
f55d613b | 54 | #define WDT_RESTART_MAGIC 0x4755 |
854123bf | 55 | |
6b2b2a70 | 56 | #define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) |
3059c2f5 JS |
57 | #define SCU_RESET_CONTROL1 (0x04 / 4) |
58 | #define SCU_RESET_SDRAM BIT(0) | |
59 | ||
854123bf CLG |
60 | static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) |
61 | { | |
62 | return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; | |
63 | } | |
64 | ||
65 | static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | |
66 | { | |
67 | AspeedWDTState *s = ASPEED_WDT(opaque); | |
68 | ||
a8eb9a43 CLG |
69 | trace_aspeed_wdt_read(offset, size); |
70 | ||
854123bf CLG |
71 | offset >>= 2; |
72 | ||
73 | switch (offset) { | |
74 | case WDT_STATUS: | |
75 | return s->regs[WDT_STATUS]; | |
76 | case WDT_RELOAD_VALUE: | |
77 | return s->regs[WDT_RELOAD_VALUE]; | |
78 | case WDT_RESTART: | |
79 | qemu_log_mask(LOG_GUEST_ERROR, | |
80 | "%s: read from write-only reg at offset 0x%" | |
81 | HWADDR_PRIx "\n", __func__, offset); | |
82 | return 0; | |
83 | case WDT_CTRL: | |
84 | return s->regs[WDT_CTRL]; | |
f55d613b AJ |
85 | case WDT_RESET_WIDTH: |
86 | return s->regs[WDT_RESET_WIDTH]; | |
6b2b2a70 JS |
87 | case WDT_RESET_MASK1: |
88 | return s->regs[WDT_RESET_MASK1]; | |
854123bf CLG |
89 | case WDT_TIMEOUT_STATUS: |
90 | case WDT_TIMEOUT_CLEAR: | |
f8ad8958 PMD |
91 | case WDT_RESET_MASK2: |
92 | case WDT_SW_RESET_CTRL: | |
93 | case WDT_SW_RESET_MASK1: | |
94 | case WDT_SW_RESET_MASK2: | |
854123bf CLG |
95 | qemu_log_mask(LOG_UNIMP, |
96 | "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", | |
97 | __func__, offset); | |
98 | return 0; | |
99 | default: | |
100 | qemu_log_mask(LOG_GUEST_ERROR, | |
101 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | |
102 | __func__, offset); | |
103 | return 0; | |
104 | } | |
105 | ||
106 | } | |
107 | ||
28c80f15 | 108 | static void aspeed_wdt_reload(AspeedWDTState *s) |
854123bf | 109 | { |
f958537a | 110 | uint64_t reload; |
854123bf | 111 | |
28c80f15 | 112 | if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) { |
854123bf CLG |
113 | reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, |
114 | s->pclk_freq); | |
115 | } else { | |
f958537a | 116 | reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; |
854123bf CLG |
117 | } |
118 | ||
119 | if (aspeed_wdt_is_enabled(s)) { | |
120 | timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); | |
121 | } | |
122 | } | |
123 | ||
28c80f15 JS |
124 | static void aspeed_wdt_reload_1mhz(AspeedWDTState *s) |
125 | { | |
126 | uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; | |
127 | ||
128 | if (aspeed_wdt_is_enabled(s)) { | |
129 | timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); | |
130 | } | |
131 | } | |
132 | ||
709098fd AJ |
133 | static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data) |
134 | { | |
135 | return data & 0xffff; | |
136 | } | |
137 | ||
138 | static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data) | |
139 | { | |
140 | return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK; | |
141 | } | |
142 | ||
143 | static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data) | |
144 | { | |
145 | return data & ~(0x7UL << 7); | |
146 | } | |
28c80f15 | 147 | |
854123bf CLG |
148 | static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, |
149 | unsigned size) | |
150 | { | |
151 | AspeedWDTState *s = ASPEED_WDT(opaque); | |
6112bd6d | 152 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); |
709098fd | 153 | bool enable; |
854123bf | 154 | |
a8eb9a43 CLG |
155 | trace_aspeed_wdt_write(offset, size, data); |
156 | ||
854123bf CLG |
157 | offset >>= 2; |
158 | ||
159 | switch (offset) { | |
160 | case WDT_STATUS: | |
161 | qemu_log_mask(LOG_GUEST_ERROR, | |
162 | "%s: write to read-only reg at offset 0x%" | |
163 | HWADDR_PRIx "\n", __func__, offset); | |
164 | break; | |
165 | case WDT_RELOAD_VALUE: | |
166 | s->regs[WDT_RELOAD_VALUE] = data; | |
167 | break; | |
168 | case WDT_RESTART: | |
169 | if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { | |
170 | s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; | |
28c80f15 | 171 | awc->wdt_reload(s); |
854123bf CLG |
172 | } |
173 | break; | |
174 | case WDT_CTRL: | |
709098fd AJ |
175 | data = awc->sanitize_ctrl(data); |
176 | enable = data & WDT_CTRL_ENABLE; | |
854123bf CLG |
177 | if (enable && !aspeed_wdt_is_enabled(s)) { |
178 | s->regs[WDT_CTRL] = data; | |
28c80f15 | 179 | awc->wdt_reload(s); |
854123bf CLG |
180 | } else if (!enable && aspeed_wdt_is_enabled(s)) { |
181 | s->regs[WDT_CTRL] = data; | |
182 | timer_del(s->timer); | |
74b67e1f AJ |
183 | } else { |
184 | s->regs[WDT_CTRL] = data; | |
854123bf CLG |
185 | } |
186 | break; | |
f55d613b | 187 | case WDT_RESET_WIDTH: |
6112bd6d CLG |
188 | if (awc->reset_pulse) { |
189 | awc->reset_pulse(s, data & WDT_POLARITY_MASK); | |
f55d613b | 190 | } |
6112bd6d CLG |
191 | s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; |
192 | s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; | |
f55d613b | 193 | break; |
6112bd6d | 194 | |
6b2b2a70 JS |
195 | case WDT_RESET_MASK1: |
196 | /* TODO: implement */ | |
197 | s->regs[WDT_RESET_MASK1] = data; | |
198 | break; | |
199 | ||
854123bf CLG |
200 | case WDT_TIMEOUT_STATUS: |
201 | case WDT_TIMEOUT_CLEAR: | |
f8ad8958 PMD |
202 | case WDT_RESET_MASK2: |
203 | case WDT_SW_RESET_CTRL: | |
204 | case WDT_SW_RESET_MASK1: | |
205 | case WDT_SW_RESET_MASK2: | |
854123bf CLG |
206 | qemu_log_mask(LOG_UNIMP, |
207 | "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", | |
208 | __func__, offset); | |
209 | break; | |
210 | default: | |
211 | qemu_log_mask(LOG_GUEST_ERROR, | |
212 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | |
213 | __func__, offset); | |
214 | } | |
215 | return; | |
216 | } | |
217 | ||
854123bf CLG |
218 | static const VMStateDescription vmstate_aspeed_wdt = { |
219 | .name = "vmstate_aspeed_wdt", | |
220 | .version_id = 0, | |
221 | .minimum_version_id = 0, | |
222 | .fields = (VMStateField[]) { | |
223 | VMSTATE_TIMER_PTR(timer, AspeedWDTState), | |
224 | VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), | |
225 | VMSTATE_END_OF_LIST() | |
226 | } | |
227 | }; | |
228 | ||
229 | static const MemoryRegionOps aspeed_wdt_ops = { | |
230 | .read = aspeed_wdt_read, | |
231 | .write = aspeed_wdt_write, | |
232 | .endianness = DEVICE_LITTLE_ENDIAN, | |
233 | .valid.min_access_size = 4, | |
234 | .valid.max_access_size = 4, | |
235 | .valid.unaligned = false, | |
236 | }; | |
237 | ||
238 | static void aspeed_wdt_reset(DeviceState *dev) | |
239 | { | |
240 | AspeedWDTState *s = ASPEED_WDT(dev); | |
709098fd | 241 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); |
854123bf | 242 | |
018134ab SL |
243 | s->regs[WDT_STATUS] = awc->default_status; |
244 | s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value; | |
854123bf | 245 | s->regs[WDT_RESTART] = 0; |
709098fd | 246 | s->regs[WDT_CTRL] = awc->sanitize_ctrl(0); |
f55d613b | 247 | s->regs[WDT_RESET_WIDTH] = 0xFF; |
854123bf CLG |
248 | |
249 | timer_del(s->timer); | |
250 | } | |
251 | ||
252 | static void aspeed_wdt_timer_expired(void *dev) | |
253 | { | |
254 | AspeedWDTState *s = ASPEED_WDT(dev); | |
6112bd6d | 255 | uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; |
854123bf | 256 | |
3059c2f5 | 257 | /* Do not reset on SDRAM controller reset */ |
6112bd6d | 258 | if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { |
3059c2f5 JS |
259 | timer_del(s->timer); |
260 | s->regs[WDT_CTRL] = 0; | |
261 | return; | |
262 | } | |
263 | ||
aabf1de4 JS |
264 | qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n", |
265 | s->iomem.addr); | |
854123bf CLG |
266 | watchdog_perform_action(); |
267 | timer_del(s->timer); | |
268 | } | |
269 | ||
270 | #define PCLK_HZ 24000000 | |
271 | ||
272 | static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | |
273 | { | |
274 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
275 | AspeedWDTState *s = ASPEED_WDT(dev); | |
4ef24766 | 276 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev); |
3059c2f5 | 277 | |
2ec11f23 | 278 | assert(s->scu); |
854123bf CLG |
279 | |
280 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); | |
281 | ||
282 | /* FIXME: This setting should be derived from the SCU hw strapping | |
283 | * register SCU70 | |
284 | */ | |
285 | s->pclk_freq = PCLK_HZ; | |
286 | ||
287 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, | |
4ef24766 | 288 | TYPE_ASPEED_WDT, awc->iosize); |
854123bf CLG |
289 | sysbus_init_mmio(sbd, &s->iomem); |
290 | } | |
291 | ||
2ec11f23 CLG |
292 | static Property aspeed_wdt_properties[] = { |
293 | DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU, | |
294 | AspeedSCUState *), | |
295 | DEFINE_PROP_END_OF_LIST(), | |
296 | }; | |
297 | ||
854123bf CLG |
298 | static void aspeed_wdt_class_init(ObjectClass *klass, void *data) |
299 | { | |
300 | DeviceClass *dc = DEVICE_CLASS(klass); | |
301 | ||
6112bd6d | 302 | dc->desc = "ASPEED Watchdog Controller"; |
854123bf CLG |
303 | dc->realize = aspeed_wdt_realize; |
304 | dc->reset = aspeed_wdt_reset; | |
b10cb627 | 305 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); |
854123bf | 306 | dc->vmsd = &vmstate_aspeed_wdt; |
4f67d30b | 307 | device_class_set_props(dc, aspeed_wdt_properties); |
b10cb627 | 308 | dc->desc = "Aspeed watchdog device"; |
854123bf CLG |
309 | } |
310 | ||
311 | static const TypeInfo aspeed_wdt_info = { | |
312 | .parent = TYPE_SYS_BUS_DEVICE, | |
313 | .name = TYPE_ASPEED_WDT, | |
314 | .instance_size = sizeof(AspeedWDTState), | |
315 | .class_init = aspeed_wdt_class_init, | |
6112bd6d CLG |
316 | .class_size = sizeof(AspeedWDTClass), |
317 | .abstract = true, | |
318 | }; | |
319 | ||
320 | static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) | |
321 | { | |
322 | DeviceClass *dc = DEVICE_CLASS(klass); | |
323 | AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | |
324 | ||
325 | dc->desc = "ASPEED 2400 Watchdog Controller"; | |
6fdb4381 | 326 | awc->iosize = 0x20; |
6112bd6d CLG |
327 | awc->ext_pulse_width_mask = 0xff; |
328 | awc->reset_ctrl_reg = SCU_RESET_CONTROL1; | |
28c80f15 | 329 | awc->wdt_reload = aspeed_wdt_reload; |
709098fd | 330 | awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl; |
018134ab SL |
331 | awc->default_status = 0x03EF1480; |
332 | awc->default_reload_value = 0x03EF1480; | |
6112bd6d CLG |
333 | } |
334 | ||
335 | static const TypeInfo aspeed_2400_wdt_info = { | |
336 | .name = TYPE_ASPEED_2400_WDT, | |
337 | .parent = TYPE_ASPEED_WDT, | |
338 | .instance_size = sizeof(AspeedWDTState), | |
339 | .class_init = aspeed_2400_wdt_class_init, | |
340 | }; | |
341 | ||
342 | static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) | |
343 | { | |
344 | if (property) { | |
345 | if (property == WDT_ACTIVE_HIGH_MAGIC) { | |
346 | s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; | |
347 | } else if (property == WDT_ACTIVE_LOW_MAGIC) { | |
348 | s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; | |
349 | } else if (property == WDT_PUSH_PULL_MAGIC) { | |
350 | s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; | |
351 | } else if (property == WDT_OPEN_DRAIN_MAGIC) { | |
352 | s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; | |
353 | } | |
354 | } | |
355 | } | |
356 | ||
357 | static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) | |
358 | { | |
359 | DeviceClass *dc = DEVICE_CLASS(klass); | |
360 | AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | |
361 | ||
362 | dc->desc = "ASPEED 2500 Watchdog Controller"; | |
6fdb4381 | 363 | awc->iosize = 0x20; |
6112bd6d CLG |
364 | awc->ext_pulse_width_mask = 0xfffff; |
365 | awc->reset_ctrl_reg = SCU_RESET_CONTROL1; | |
366 | awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | |
28c80f15 | 367 | awc->wdt_reload = aspeed_wdt_reload_1mhz; |
709098fd | 368 | awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl; |
018134ab SL |
369 | awc->default_status = 0x014FB180; |
370 | awc->default_reload_value = 0x014FB180; | |
6112bd6d CLG |
371 | } |
372 | ||
373 | static const TypeInfo aspeed_2500_wdt_info = { | |
374 | .name = TYPE_ASPEED_2500_WDT, | |
375 | .parent = TYPE_ASPEED_WDT, | |
376 | .instance_size = sizeof(AspeedWDTState), | |
377 | .class_init = aspeed_2500_wdt_class_init, | |
854123bf CLG |
378 | }; |
379 | ||
6b2b2a70 JS |
380 | static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) |
381 | { | |
382 | DeviceClass *dc = DEVICE_CLASS(klass); | |
383 | AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | |
384 | ||
385 | dc->desc = "ASPEED 2600 Watchdog Controller"; | |
6fdb4381 | 386 | awc->iosize = 0x40; |
6b2b2a70 JS |
387 | awc->ext_pulse_width_mask = 0xfffff; /* TODO */ |
388 | awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; | |
389 | awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | |
28c80f15 | 390 | awc->wdt_reload = aspeed_wdt_reload_1mhz; |
709098fd | 391 | awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl; |
018134ab SL |
392 | awc->default_status = 0x014FB180; |
393 | awc->default_reload_value = 0x014FB180; | |
6b2b2a70 JS |
394 | } |
395 | ||
396 | static const TypeInfo aspeed_2600_wdt_info = { | |
397 | .name = TYPE_ASPEED_2600_WDT, | |
398 | .parent = TYPE_ASPEED_WDT, | |
399 | .instance_size = sizeof(AspeedWDTState), | |
400 | .class_init = aspeed_2600_wdt_class_init, | |
401 | }; | |
402 | ||
e259e01e SL |
403 | static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data) |
404 | { | |
405 | DeviceClass *dc = DEVICE_CLASS(klass); | |
406 | AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); | |
407 | ||
408 | dc->desc = "ASPEED 1030 Watchdog Controller"; | |
6fdb4381 | 409 | awc->iosize = 0x80; |
e259e01e SL |
410 | awc->ext_pulse_width_mask = 0xfffff; /* TODO */ |
411 | awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; | |
412 | awc->reset_pulse = aspeed_2500_wdt_reset_pulse; | |
413 | awc->wdt_reload = aspeed_wdt_reload_1mhz; | |
414 | awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl; | |
415 | awc->default_status = 0x014FB180; | |
416 | awc->default_reload_value = 0x014FB180; | |
417 | } | |
418 | ||
419 | static const TypeInfo aspeed_1030_wdt_info = { | |
420 | .name = TYPE_ASPEED_1030_WDT, | |
421 | .parent = TYPE_ASPEED_WDT, | |
422 | .instance_size = sizeof(AspeedWDTState), | |
423 | .class_init = aspeed_1030_wdt_class_init, | |
424 | }; | |
425 | ||
854123bf CLG |
426 | static void wdt_aspeed_register_types(void) |
427 | { | |
854123bf | 428 | type_register_static(&aspeed_wdt_info); |
6112bd6d CLG |
429 | type_register_static(&aspeed_2400_wdt_info); |
430 | type_register_static(&aspeed_2500_wdt_info); | |
6b2b2a70 | 431 | type_register_static(&aspeed_2600_wdt_info); |
e259e01e | 432 | type_register_static(&aspeed_1030_wdt_info); |
854123bf CLG |
433 | } |
434 | ||
435 | type_init(wdt_aspeed_register_types) |