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854123bf CLG |
1 | /* |
2 | * ASPEED Watchdog Controller | |
3 | * | |
4 | * Copyright (C) 2016-2017 IBM Corp. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qemu/log.h" | |
12 | #include "sysemu/watchdog.h" | |
13 | #include "hw/sysbus.h" | |
14 | #include "qemu/timer.h" | |
15 | #include "hw/watchdog/wdt_aspeed.h" | |
16 | ||
17 | #define WDT_STATUS (0x00 / 4) | |
18 | #define WDT_RELOAD_VALUE (0x04 / 4) | |
19 | #define WDT_RESTART (0x08 / 4) | |
20 | #define WDT_CTRL (0x0C / 4) | |
21 | #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) | |
22 | #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) | |
23 | #define WDT_CTRL_1MHZ_CLK BIT(4) | |
24 | #define WDT_CTRL_WDT_EXT BIT(3) | |
25 | #define WDT_CTRL_WDT_INTR BIT(2) | |
26 | #define WDT_CTRL_RESET_SYSTEM BIT(1) | |
27 | #define WDT_CTRL_ENABLE BIT(0) | |
28 | ||
29 | #define WDT_TIMEOUT_STATUS (0x10 / 4) | |
30 | #define WDT_TIMEOUT_CLEAR (0x14 / 4) | |
31 | #define WDT_RESET_WDITH (0x18 / 4) | |
32 | ||
33 | #define WDT_RESTART_MAGIC 0x4755 | |
34 | ||
35 | static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) | |
36 | { | |
37 | return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; | |
38 | } | |
39 | ||
40 | static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | |
41 | { | |
42 | AspeedWDTState *s = ASPEED_WDT(opaque); | |
43 | ||
44 | offset >>= 2; | |
45 | ||
46 | switch (offset) { | |
47 | case WDT_STATUS: | |
48 | return s->regs[WDT_STATUS]; | |
49 | case WDT_RELOAD_VALUE: | |
50 | return s->regs[WDT_RELOAD_VALUE]; | |
51 | case WDT_RESTART: | |
52 | qemu_log_mask(LOG_GUEST_ERROR, | |
53 | "%s: read from write-only reg at offset 0x%" | |
54 | HWADDR_PRIx "\n", __func__, offset); | |
55 | return 0; | |
56 | case WDT_CTRL: | |
57 | return s->regs[WDT_CTRL]; | |
58 | case WDT_TIMEOUT_STATUS: | |
59 | case WDT_TIMEOUT_CLEAR: | |
60 | case WDT_RESET_WDITH: | |
61 | qemu_log_mask(LOG_UNIMP, | |
62 | "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", | |
63 | __func__, offset); | |
64 | return 0; | |
65 | default: | |
66 | qemu_log_mask(LOG_GUEST_ERROR, | |
67 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | |
68 | __func__, offset); | |
69 | return 0; | |
70 | } | |
71 | ||
72 | } | |
73 | ||
74 | static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) | |
75 | { | |
76 | uint32_t reload; | |
77 | ||
78 | if (pclk) { | |
79 | reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, | |
80 | s->pclk_freq); | |
81 | } else { | |
82 | reload = s->regs[WDT_RELOAD_VALUE] * 1000; | |
83 | } | |
84 | ||
85 | if (aspeed_wdt_is_enabled(s)) { | |
86 | timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); | |
87 | } | |
88 | } | |
89 | ||
90 | static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | |
91 | unsigned size) | |
92 | { | |
93 | AspeedWDTState *s = ASPEED_WDT(opaque); | |
94 | bool enable = data & WDT_CTRL_ENABLE; | |
95 | ||
96 | offset >>= 2; | |
97 | ||
98 | switch (offset) { | |
99 | case WDT_STATUS: | |
100 | qemu_log_mask(LOG_GUEST_ERROR, | |
101 | "%s: write to read-only reg at offset 0x%" | |
102 | HWADDR_PRIx "\n", __func__, offset); | |
103 | break; | |
104 | case WDT_RELOAD_VALUE: | |
105 | s->regs[WDT_RELOAD_VALUE] = data; | |
106 | break; | |
107 | case WDT_RESTART: | |
108 | if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { | |
109 | s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; | |
110 | aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | |
111 | } | |
112 | break; | |
113 | case WDT_CTRL: | |
114 | if (enable && !aspeed_wdt_is_enabled(s)) { | |
115 | s->regs[WDT_CTRL] = data; | |
116 | aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | |
117 | } else if (!enable && aspeed_wdt_is_enabled(s)) { | |
118 | s->regs[WDT_CTRL] = data; | |
119 | timer_del(s->timer); | |
120 | } | |
121 | break; | |
122 | case WDT_TIMEOUT_STATUS: | |
123 | case WDT_TIMEOUT_CLEAR: | |
124 | case WDT_RESET_WDITH: | |
125 | qemu_log_mask(LOG_UNIMP, | |
126 | "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", | |
127 | __func__, offset); | |
128 | break; | |
129 | default: | |
130 | qemu_log_mask(LOG_GUEST_ERROR, | |
131 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | |
132 | __func__, offset); | |
133 | } | |
134 | return; | |
135 | } | |
136 | ||
137 | static WatchdogTimerModel model = { | |
138 | .wdt_name = TYPE_ASPEED_WDT, | |
139 | .wdt_description = "Aspeed watchdog device", | |
140 | }; | |
141 | ||
142 | static const VMStateDescription vmstate_aspeed_wdt = { | |
143 | .name = "vmstate_aspeed_wdt", | |
144 | .version_id = 0, | |
145 | .minimum_version_id = 0, | |
146 | .fields = (VMStateField[]) { | |
147 | VMSTATE_TIMER_PTR(timer, AspeedWDTState), | |
148 | VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), | |
149 | VMSTATE_END_OF_LIST() | |
150 | } | |
151 | }; | |
152 | ||
153 | static const MemoryRegionOps aspeed_wdt_ops = { | |
154 | .read = aspeed_wdt_read, | |
155 | .write = aspeed_wdt_write, | |
156 | .endianness = DEVICE_LITTLE_ENDIAN, | |
157 | .valid.min_access_size = 4, | |
158 | .valid.max_access_size = 4, | |
159 | .valid.unaligned = false, | |
160 | }; | |
161 | ||
162 | static void aspeed_wdt_reset(DeviceState *dev) | |
163 | { | |
164 | AspeedWDTState *s = ASPEED_WDT(dev); | |
165 | ||
166 | s->regs[WDT_STATUS] = 0x3EF1480; | |
167 | s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; | |
168 | s->regs[WDT_RESTART] = 0; | |
169 | s->regs[WDT_CTRL] = 0; | |
170 | ||
171 | timer_del(s->timer); | |
172 | } | |
173 | ||
174 | static void aspeed_wdt_timer_expired(void *dev) | |
175 | { | |
176 | AspeedWDTState *s = ASPEED_WDT(dev); | |
177 | ||
178 | qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); | |
179 | watchdog_perform_action(); | |
180 | timer_del(s->timer); | |
181 | } | |
182 | ||
183 | #define PCLK_HZ 24000000 | |
184 | ||
185 | static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | |
186 | { | |
187 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
188 | AspeedWDTState *s = ASPEED_WDT(dev); | |
189 | ||
190 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); | |
191 | ||
192 | /* FIXME: This setting should be derived from the SCU hw strapping | |
193 | * register SCU70 | |
194 | */ | |
195 | s->pclk_freq = PCLK_HZ; | |
196 | ||
197 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, | |
198 | TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); | |
199 | sysbus_init_mmio(sbd, &s->iomem); | |
200 | } | |
201 | ||
202 | static void aspeed_wdt_class_init(ObjectClass *klass, void *data) | |
203 | { | |
204 | DeviceClass *dc = DEVICE_CLASS(klass); | |
205 | ||
206 | dc->realize = aspeed_wdt_realize; | |
207 | dc->reset = aspeed_wdt_reset; | |
208 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | |
209 | dc->vmsd = &vmstate_aspeed_wdt; | |
210 | } | |
211 | ||
212 | static const TypeInfo aspeed_wdt_info = { | |
213 | .parent = TYPE_SYS_BUS_DEVICE, | |
214 | .name = TYPE_ASPEED_WDT, | |
215 | .instance_size = sizeof(AspeedWDTState), | |
216 | .class_init = aspeed_wdt_class_init, | |
217 | }; | |
218 | ||
219 | static void wdt_aspeed_register_types(void) | |
220 | { | |
221 | watchdog_add_model(&model); | |
222 | type_register_static(&aspeed_wdt_info); | |
223 | } | |
224 | ||
225 | type_init(wdt_aspeed_register_types) |