[mirror_qemu.git] / hw / watchdog / wdt_aspeed.c

/*
 * ASPEED Watchdog Controller
 *
 * Copyright (C) 2016-2017 IBM Corp.
 *
 * This code is licensed under the GPL version 2 or later. See the
 * COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"

#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "sysemu/watchdog.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "migration/vmstate.h"
#include "trace.h"

#define WDT_STATUS                      (0x00 / 4)
#define WDT_RELOAD_VALUE                (0x04 / 4)
#define WDT_RESTART                     (0x08 / 4)
#define WDT_CTRL                        (0x0C / 4)
#define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
#define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
#define   WDT_CTRL_1MHZ_CLK             BIT(4)
#define   WDT_CTRL_WDT_EXT              BIT(3)
#define   WDT_CTRL_WDT_INTR             BIT(2)
#define   WDT_CTRL_RESET_SYSTEM         BIT(1)
#define   WDT_CTRL_ENABLE               BIT(0)
#define WDT_RESET_WIDTH                 (0x18 / 4)
#define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
#define     WDT_POLARITY_MASK           (0xFF << 24)
#define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
#define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
#define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
#define     WDT_DRIVE_TYPE_MASK         (0xFF << 24)
#define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
#define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
#define WDT_RESET_MASK1                 (0x1c / 4)
#define WDT_RESET_MASK2                 (0x20 / 4)

#define WDT_SW_RESET_CTRL               (0x24 / 4)
#define WDT_SW_RESET_MASK1              (0x28 / 4)
#define WDT_SW_RESET_MASK2              (0x2c / 4)

#define WDT_TIMEOUT_STATUS              (0x10 / 4)
#define WDT_TIMEOUT_CLEAR               (0x14 / 4)

#define WDT_RESTART_MAGIC               0x4755

#define AST2600_SCU_RESET_CONTROL1      (0x40 / 4)
#define SCU_RESET_CONTROL1              (0x04 / 4)
#define    SCU_RESET_SDRAM              BIT(0)

static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
{
    return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
}

static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
{
    AspeedWDTState *s = ASPEED_WDT(opaque);

    trace_aspeed_wdt_read(offset, size);

    offset >>= 2;

    switch (offset) {
    case WDT_STATUS:
        return s->regs[WDT_STATUS];
    case WDT_RELOAD_VALUE:
        return s->regs[WDT_RELOAD_VALUE];
    case WDT_RESTART:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: read from write-only reg at offset 0x%"
                      HWADDR_PRIx "\n", __func__, offset);
        return 0;
    case WDT_CTRL:
        return s->regs[WDT_CTRL];
    case WDT_RESET_WIDTH:
        return s->regs[WDT_RESET_WIDTH];
    case WDT_RESET_MASK1:
        return s->regs[WDT_RESET_MASK1];
    case WDT_TIMEOUT_STATUS:
    case WDT_TIMEOUT_CLEAR:
    case WDT_RESET_MASK2:
    case WDT_SW_RESET_CTRL:
    case WDT_SW_RESET_MASK1:
    case WDT_SW_RESET_MASK2:
        qemu_log_mask(LOG_UNIMP,
                      "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return 0;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        return 0;
    }

}

static void aspeed_wdt_reload(AspeedWDTState *s)
{
    uint64_t reload;

    if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) {
        reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
                          s->pclk_freq);
    } else {
        reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
    }

    if (aspeed_wdt_is_enabled(s)) {
        timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
    }
}

static void aspeed_wdt_reload_1mhz(AspeedWDTState *s)
{
    uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;

    if (aspeed_wdt_is_enabled(s)) {
        timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
    }
}

static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data)
{
    return data & 0xffff;
}

static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data)
{
    return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK;
}

static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data)
{
    return data & ~(0x7UL << 7);
}

static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
                             unsigned size)
{
    AspeedWDTState *s = ASPEED_WDT(opaque);
    AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
    bool enable;

    trace_aspeed_wdt_write(offset, size, data);

    offset >>= 2;

    switch (offset) {
    case WDT_STATUS:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: write to read-only reg at offset 0x%"
                      HWADDR_PRIx "\n", __func__, offset);
        break;
    case WDT_RELOAD_VALUE:
        s->regs[WDT_RELOAD_VALUE] = data;
        break;
    case WDT_RESTART:
        if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
            s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
            awc->wdt_reload(s);
        }
        break;
    case WDT_CTRL:
        data = awc->sanitize_ctrl(data);
        enable = data & WDT_CTRL_ENABLE;
        if (enable && !aspeed_wdt_is_enabled(s)) {
            s->regs[WDT_CTRL] = data;
            awc->wdt_reload(s);
        } else if (!enable && aspeed_wdt_is_enabled(s)) {
            s->regs[WDT_CTRL] = data;
            timer_del(s->timer);
        } else {
            s->regs[WDT_CTRL] = data;
        }
        break;
    case WDT_RESET_WIDTH:
        if (awc->reset_pulse) {
            awc->reset_pulse(s, data & WDT_POLARITY_MASK);
        }
        s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask;
        s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask;
        break;

    case WDT_RESET_MASK1:
        /* TODO: implement */
        s->regs[WDT_RESET_MASK1] = data;
        break;

    case WDT_TIMEOUT_STATUS:
    case WDT_TIMEOUT_CLEAR:
    case WDT_RESET_MASK2:
    case WDT_SW_RESET_CTRL:
    case WDT_SW_RESET_MASK1:
    case WDT_SW_RESET_MASK2:
        qemu_log_mask(LOG_UNIMP,
                      "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
                      __func__, offset);
    }
    return;
}

static const VMStateDescription vmstate_aspeed_wdt = {
    .name = "vmstate_aspeed_wdt",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_TIMER_PTR(timer, AspeedWDTState),
        VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static const MemoryRegionOps aspeed_wdt_ops = {
    .read = aspeed_wdt_read,
    .write = aspeed_wdt_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
    .valid.unaligned = false,
};

static void aspeed_wdt_reset(DeviceState *dev)
{
    AspeedWDTState *s = ASPEED_WDT(dev);
    AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);

    s->regs[WDT_STATUS] = awc->default_status;
    s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value;
    s->regs[WDT_RESTART] = 0;
    s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
    s->regs[WDT_RESET_WIDTH] = 0xFF;

    timer_del(s->timer);
}

static void aspeed_wdt_timer_expired(void *dev)
{
    AspeedWDTState *s = ASPEED_WDT(dev);
    uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg;

    /* Do not reset on SDRAM controller reset */
    if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) {
        timer_del(s->timer);
        s->regs[WDT_CTRL] = 0;
        return;
    }

    qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n",
                  s->iomem.addr);
    watchdog_perform_action();
    timer_del(s->timer);
}

#define PCLK_HZ 24000000

static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    AspeedWDTState *s = ASPEED_WDT(dev);
    AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);

    assert(s->scu);

    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);

    /* FIXME: This setting should be derived from the SCU hw strapping
     * register SCU70
     */
    s->pclk_freq = PCLK_HZ;

    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
                          TYPE_ASPEED_WDT, awc->iosize);
    sysbus_init_mmio(sbd, &s->iomem);
}

static Property aspeed_wdt_properties[] = {
    DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU,
                     AspeedSCUState *),
    DEFINE_PROP_END_OF_LIST(),
};

static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "ASPEED Watchdog Controller";
    dc->realize = aspeed_wdt_realize;
    dc->reset = aspeed_wdt_reset;
    set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
    dc->vmsd = &vmstate_aspeed_wdt;
    device_class_set_props(dc, aspeed_wdt_properties);
    dc->desc = "Aspeed watchdog device";
}

static const TypeInfo aspeed_wdt_info = {
    .parent = TYPE_SYS_BUS_DEVICE,
    .name  = TYPE_ASPEED_WDT,
    .instance_size  = sizeof(AspeedWDTState),
    .class_init = aspeed_wdt_class_init,
    .class_size    = sizeof(AspeedWDTClass),
    .abstract      = true,
};

static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);

    dc->desc = "ASPEED 2400 Watchdog Controller";
    awc->iosize = 0x20;
    awc->ext_pulse_width_mask = 0xff;
    awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
    awc->wdt_reload = aspeed_wdt_reload;
    awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
    awc->default_status = 0x03EF1480;
    awc->default_reload_value = 0x03EF1480;
}

static const TypeInfo aspeed_2400_wdt_info = {
    .name = TYPE_ASPEED_2400_WDT,
    .parent = TYPE_ASPEED_WDT,
    .instance_size = sizeof(AspeedWDTState),
    .class_init = aspeed_2400_wdt_class_init,
};

static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property)
{
    if (property) {
        if (property == WDT_ACTIVE_HIGH_MAGIC) {
            s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
        } else if (property == WDT_ACTIVE_LOW_MAGIC) {
            s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
        } else if (property == WDT_PUSH_PULL_MAGIC) {
            s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
        } else if (property == WDT_OPEN_DRAIN_MAGIC) {
            s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
        }
    }
}

static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);

    dc->desc = "ASPEED 2500 Watchdog Controller";
    awc->iosize = 0x20;
    awc->ext_pulse_width_mask = 0xfffff;
    awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
    awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
    awc->wdt_reload = aspeed_wdt_reload_1mhz;
    awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
    awc->default_status = 0x014FB180;
    awc->default_reload_value = 0x014FB180;
}

static const TypeInfo aspeed_2500_wdt_info = {
    .name = TYPE_ASPEED_2500_WDT,
    .parent = TYPE_ASPEED_WDT,
    .instance_size = sizeof(AspeedWDTState),
    .class_init = aspeed_2500_wdt_class_init,
};

static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);

    dc->desc = "ASPEED 2600 Watchdog Controller";
    awc->iosize = 0x40;
    awc->ext_pulse_width_mask = 0xfffff; /* TODO */
    awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
    awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
    awc->wdt_reload = aspeed_wdt_reload_1mhz;
    awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
    awc->default_status = 0x014FB180;
    awc->default_reload_value = 0x014FB180;
}

static const TypeInfo aspeed_2600_wdt_info = {
    .name = TYPE_ASPEED_2600_WDT,
    .parent = TYPE_ASPEED_WDT,
    .instance_size = sizeof(AspeedWDTState),
    .class_init = aspeed_2600_wdt_class_init,
};

static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);

    dc->desc = "ASPEED 1030 Watchdog Controller";
    awc->iosize = 0x80;
    awc->ext_pulse_width_mask = 0xfffff; /* TODO */
    awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
    awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
    awc->wdt_reload = aspeed_wdt_reload_1mhz;
    awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
    awc->default_status = 0x014FB180;
    awc->default_reload_value = 0x014FB180;
}

static const TypeInfo aspeed_1030_wdt_info = {
    .name = TYPE_ASPEED_1030_WDT,
    .parent = TYPE_ASPEED_WDT,
    .instance_size = sizeof(AspeedWDTState),
    .class_init = aspeed_1030_wdt_class_init,
};

static void wdt_aspeed_register_types(void)
{
    type_register_static(&aspeed_wdt_info);
    type_register_static(&aspeed_2400_wdt_info);
    type_register_static(&aspeed_2500_wdt_info);
    type_register_static(&aspeed_2600_wdt_info);
    type_register_static(&aspeed_1030_wdt_info);
}

type_init(wdt_aspeed_register_types)
Commit	Line	Data
854123bf CLG	1	/*
	2	* ASPEED Watchdog Controller
	3	*
	4	* Copyright (C) 2016-2017 IBM Corp.
	5	*
	6	* This code is licensed under the GPL version 2 or later. See the
	7	* COPYING file in the top-level directory.
	8	*/
	9
	10	#include "qemu/osdep.h"
f55d613b AJ	11
f55d613b AJ	12	#include "qapi/error.h"
854123bf	13	#include "qemu/log.h"
0b8fa32f	14	#include "qemu/module.h"
f55d613b	15	#include "qemu/timer.h"
854123bf	16	#include "sysemu/watchdog.h"
a27bd6c7	17	#include "hw/qdev-properties.h"
854123bf	18	#include "hw/sysbus.h"
854123bf	19	#include "hw/watchdog/wdt_aspeed.h"
d6454270	20	#include "migration/vmstate.h"
a8eb9a43	21	#include "trace.h"
854123bf	22
f55d613b AJ	23	#define WDT_STATUS (0x00 / 4)
	24	#define WDT_RELOAD_VALUE (0x04 / 4)
	25	#define WDT_RESTART (0x08 / 4)
	26	#define WDT_CTRL (0x0C / 4)
854123bf CLG	27	#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
	28	#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
	29	#define WDT_CTRL_1MHZ_CLK BIT(4)
	30	#define WDT_CTRL_WDT_EXT BIT(3)
	31	#define WDT_CTRL_WDT_INTR BIT(2)
	32	#define WDT_CTRL_RESET_SYSTEM BIT(1)
	33	#define WDT_CTRL_ENABLE BIT(0)
f55d613b AJ	34	#define WDT_RESET_WIDTH (0x18 / 4)
	35	#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
	36	#define WDT_POLARITY_MASK (0xFF << 24)
	37	#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
	38	#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
	39	#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
	40	#define WDT_DRIVE_TYPE_MASK (0xFF << 24)
	41	#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
	42	#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
6b2b2a70	43	#define WDT_RESET_MASK1 (0x1c / 4)
f8ad8958 PMD	44	#define WDT_RESET_MASK2 (0x20 / 4)
	45
	46	#define WDT_SW_RESET_CTRL (0x24 / 4)
	47	#define WDT_SW_RESET_MASK1 (0x28 / 4)
	48	#define WDT_SW_RESET_MASK2 (0x2c / 4)
854123bf	49
f55d613b AJ	50	#define WDT_TIMEOUT_STATUS (0x10 / 4)
f55d613b AJ	51	#define WDT_TIMEOUT_CLEAR (0x14 / 4)
854123bf	52
f55d613b	53	#define WDT_RESTART_MAGIC 0x4755
854123bf	54
6b2b2a70	55	#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4)
3059c2f5 JS	56	#define SCU_RESET_CONTROL1 (0x04 / 4)
	57	#define SCU_RESET_SDRAM BIT(0)
	58
854123bf CLG	59	static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
	60	{
	61	return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
	62	}
	63
	64	static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
	65	{
	66	AspeedWDTState *s = ASPEED_WDT(opaque);
	67
a8eb9a43 CLG	68	trace_aspeed_wdt_read(offset, size);
a8eb9a43 CLG	69
854123bf CLG	70	offset >>= 2;
	71
	72	switch (offset) {
	73	case WDT_STATUS:
	74	return s->regs[WDT_STATUS];
	75	case WDT_RELOAD_VALUE:
	76	return s->regs[WDT_RELOAD_VALUE];
	77	case WDT_RESTART:
	78	qemu_log_mask(LOG_GUEST_ERROR,
	79	"%s: read from write-only reg at offset 0x%"
	80	HWADDR_PRIx "\n", __func__, offset);
	81	return 0;
	82	case WDT_CTRL:
	83	return s->regs[WDT_CTRL];
f55d613b AJ	84	case WDT_RESET_WIDTH:
f55d613b AJ	85	return s->regs[WDT_RESET_WIDTH];
6b2b2a70 JS	86	case WDT_RESET_MASK1:
6b2b2a70 JS	87	return s->regs[WDT_RESET_MASK1];
854123bf CLG	88	case WDT_TIMEOUT_STATUS:
854123bf CLG	89	case WDT_TIMEOUT_CLEAR:
f8ad8958 PMD	90	case WDT_RESET_MASK2:
	91	case WDT_SW_RESET_CTRL:
	92	case WDT_SW_RESET_MASK1:
	93	case WDT_SW_RESET_MASK2:
854123bf CLG	94	qemu_log_mask(LOG_UNIMP,
	95	"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
	96	__func__, offset);
	97	return 0;
	98	default:
	99	qemu_log_mask(LOG_GUEST_ERROR,
	100	"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
	101	__func__, offset);
	102	return 0;
	103	}
	104
	105	}
	106
28c80f15	107	static void aspeed_wdt_reload(AspeedWDTState *s)
854123bf	108	{
f958537a	109	uint64_t reload;
854123bf	110
28c80f15	111	if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) {
854123bf CLG	112	reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
	113	s->pclk_freq);
	114	} else {
f958537a	115	reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
854123bf CLG	116	}
	117
	118	if (aspeed_wdt_is_enabled(s)) {
	119	timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
	120	}
	121	}
	122
28c80f15 JS	123	static void aspeed_wdt_reload_1mhz(AspeedWDTState *s)
	124	{
	125	uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
	126
	127	if (aspeed_wdt_is_enabled(s)) {
	128	timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
	129	}
	130	}
	131
709098fd AJ	132	static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data)
	133	{
	134	return data & 0xffff;
	135	}
	136
	137	static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data)
	138	{
	139	return (data & ~(0xfUL << 8)) \| WDT_CTRL_1MHZ_CLK;
	140	}
	141
	142	static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data)
	143	{
	144	return data & ~(0x7UL << 7);
	145	}
28c80f15	146
854123bf CLG	147	static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
	148	unsigned size)
	149	{
	150	AspeedWDTState *s = ASPEED_WDT(opaque);
6112bd6d	151	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
709098fd	152	bool enable;
854123bf	153
a8eb9a43 CLG	154	trace_aspeed_wdt_write(offset, size, data);
a8eb9a43 CLG	155
854123bf CLG	156	offset >>= 2;
	157
	158	switch (offset) {
	159	case WDT_STATUS:
	160	qemu_log_mask(LOG_GUEST_ERROR,
	161	"%s: write to read-only reg at offset 0x%"
	162	HWADDR_PRIx "\n", __func__, offset);
	163	break;
	164	case WDT_RELOAD_VALUE:
	165	s->regs[WDT_RELOAD_VALUE] = data;
	166	break;
	167	case WDT_RESTART:
	168	if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
	169	s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
28c80f15	170	awc->wdt_reload(s);
854123bf CLG	171	}
	172	break;
	173	case WDT_CTRL:
709098fd AJ	174	data = awc->sanitize_ctrl(data);
709098fd AJ	175	enable = data & WDT_CTRL_ENABLE;
854123bf CLG	176	if (enable && !aspeed_wdt_is_enabled(s)) {
854123bf CLG	177	s->regs[WDT_CTRL] = data;
28c80f15	178	awc->wdt_reload(s);
854123bf CLG	179	} else if (!enable && aspeed_wdt_is_enabled(s)) {
	180	s->regs[WDT_CTRL] = data;
	181	timer_del(s->timer);
74b67e1f AJ	182	} else {
74b67e1f AJ	183	s->regs[WDT_CTRL] = data;
854123bf CLG	184	}
854123bf CLG	185	break;
f55d613b	186	case WDT_RESET_WIDTH:
6112bd6d CLG	187	if (awc->reset_pulse) {
6112bd6d CLG	188	awc->reset_pulse(s, data & WDT_POLARITY_MASK);
f55d613b	189	}
6112bd6d CLG	190	s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask;
6112bd6d CLG	191	s->regs[WDT_RESET_WIDTH] \|= data & awc->ext_pulse_width_mask;
f55d613b	192	break;
6112bd6d	193
6b2b2a70 JS	194	case WDT_RESET_MASK1:
	195	/* TODO: implement */
	196	s->regs[WDT_RESET_MASK1] = data;
	197	break;
	198
854123bf CLG	199	case WDT_TIMEOUT_STATUS:
854123bf CLG	200	case WDT_TIMEOUT_CLEAR:
f8ad8958 PMD	201	case WDT_RESET_MASK2:
	202	case WDT_SW_RESET_CTRL:
	203	case WDT_SW_RESET_MASK1:
	204	case WDT_SW_RESET_MASK2:
854123bf CLG	205	qemu_log_mask(LOG_UNIMP,
	206	"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
	207	__func__, offset);
	208	break;
	209	default:
	210	qemu_log_mask(LOG_GUEST_ERROR,
	211	"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
	212	__func__, offset);
	213	}
	214	return;
	215	}
	216
854123bf CLG	217	static const VMStateDescription vmstate_aspeed_wdt = {
	218	.name = "vmstate_aspeed_wdt",
	219	.version_id = 0,
	220	.minimum_version_id = 0,
	221	.fields = (VMStateField[]) {
	222	VMSTATE_TIMER_PTR(timer, AspeedWDTState),
	223	VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
	224	VMSTATE_END_OF_LIST()
	225	}
	226	};
	227
	228	static const MemoryRegionOps aspeed_wdt_ops = {
	229	.read = aspeed_wdt_read,
	230	.write = aspeed_wdt_write,
	231	.endianness = DEVICE_LITTLE_ENDIAN,
	232	.valid.min_access_size = 4,
	233	.valid.max_access_size = 4,
	234	.valid.unaligned = false,
	235	};
	236
	237	static void aspeed_wdt_reset(DeviceState *dev)
	238	{
	239	AspeedWDTState *s = ASPEED_WDT(dev);
709098fd	240	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
854123bf	241
018134ab SL	242	s->regs[WDT_STATUS] = awc->default_status;
018134ab SL	243	s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value;
854123bf	244	s->regs[WDT_RESTART] = 0;
709098fd	245	s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
f55d613b	246	s->regs[WDT_RESET_WIDTH] = 0xFF;
854123bf CLG	247
	248	timer_del(s->timer);
	249	}
	250
	251	static void aspeed_wdt_timer_expired(void *dev)
	252	{
	253	AspeedWDTState *s = ASPEED_WDT(dev);
6112bd6d	254	uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg;
854123bf	255
3059c2f5	256	/* Do not reset on SDRAM controller reset */
6112bd6d	257	if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) {
3059c2f5 JS	258	timer_del(s->timer);
	259	s->regs[WDT_CTRL] = 0;
	260	return;
	261	}
	262
aabf1de4 JS	263	qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n",
aabf1de4 JS	264	s->iomem.addr);
854123bf CLG	265	watchdog_perform_action();
	266	timer_del(s->timer);
	267	}
	268
	269	#define PCLK_HZ 24000000
	270
	271	static void aspeed_wdt_realize(DeviceState dev, Error *errp)
	272	{
	273	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	274	AspeedWDTState *s = ASPEED_WDT(dev);
4ef24766	275	AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
3059c2f5	276
2ec11f23	277	assert(s->scu);
854123bf CLG	278
	279	s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
	280
	281	/* FIXME: This setting should be derived from the SCU hw strapping
	282	* register SCU70
	283	*/
	284	s->pclk_freq = PCLK_HZ;
	285
	286	memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
4ef24766	287	TYPE_ASPEED_WDT, awc->iosize);
854123bf CLG	288	sysbus_init_mmio(sbd, &s->iomem);
	289	}
	290
2ec11f23 CLG	291	static Property aspeed_wdt_properties[] = {
	292	DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU,
	293	AspeedSCUState *),
	294	DEFINE_PROP_END_OF_LIST(),
	295	};
	296
854123bf CLG	297	static void aspeed_wdt_class_init(ObjectClass klass, void data)
	298	{
	299	DeviceClass *dc = DEVICE_CLASS(klass);
	300
6112bd6d	301	dc->desc = "ASPEED Watchdog Controller";
854123bf CLG	302	dc->realize = aspeed_wdt_realize;
854123bf CLG	303	dc->reset = aspeed_wdt_reset;
b10cb627	304	set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
854123bf	305	dc->vmsd = &vmstate_aspeed_wdt;
4f67d30b	306	device_class_set_props(dc, aspeed_wdt_properties);
b10cb627	307	dc->desc = "Aspeed watchdog device";
854123bf CLG	308	}
	309
	310	static const TypeInfo aspeed_wdt_info = {
	311	.parent = TYPE_SYS_BUS_DEVICE,
	312	.name = TYPE_ASPEED_WDT,
	313	.instance_size = sizeof(AspeedWDTState),
	314	.class_init = aspeed_wdt_class_init,
6112bd6d CLG	315	.class_size = sizeof(AspeedWDTClass),
	316	.abstract = true,
	317	};
	318
	319	static void aspeed_2400_wdt_class_init(ObjectClass klass, void data)
	320	{
	321	DeviceClass *dc = DEVICE_CLASS(klass);
	322	AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
	323
	324	dc->desc = "ASPEED 2400 Watchdog Controller";
6fdb4381	325	awc->iosize = 0x20;
6112bd6d CLG	326	awc->ext_pulse_width_mask = 0xff;
6112bd6d CLG	327	awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
28c80f15	328	awc->wdt_reload = aspeed_wdt_reload;
709098fd	329	awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
018134ab SL	330	awc->default_status = 0x03EF1480;
018134ab SL	331	awc->default_reload_value = 0x03EF1480;
6112bd6d CLG	332	}
	333
	334	static const TypeInfo aspeed_2400_wdt_info = {
	335	.name = TYPE_ASPEED_2400_WDT,
	336	.parent = TYPE_ASPEED_WDT,
	337	.instance_size = sizeof(AspeedWDTState),
	338	.class_init = aspeed_2400_wdt_class_init,
	339	};
	340
	341	static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property)
	342	{
	343	if (property) {
	344	if (property == WDT_ACTIVE_HIGH_MAGIC) {
	345	s->regs[WDT_RESET_WIDTH] \|= WDT_RESET_WIDTH_ACTIVE_HIGH;
	346	} else if (property == WDT_ACTIVE_LOW_MAGIC) {
	347	s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
	348	} else if (property == WDT_PUSH_PULL_MAGIC) {
	349	s->regs[WDT_RESET_WIDTH] \|= WDT_RESET_WIDTH_PUSH_PULL;
	350	} else if (property == WDT_OPEN_DRAIN_MAGIC) {
	351	s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
	352	}
	353	}
	354	}
	355
	356	static void aspeed_2500_wdt_class_init(ObjectClass klass, void data)
	357	{
	358	DeviceClass *dc = DEVICE_CLASS(klass);
	359	AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
	360
	361	dc->desc = "ASPEED 2500 Watchdog Controller";
6fdb4381	362	awc->iosize = 0x20;
6112bd6d CLG	363	awc->ext_pulse_width_mask = 0xfffff;
	364	awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
	365	awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
28c80f15	366	awc->wdt_reload = aspeed_wdt_reload_1mhz;
709098fd	367	awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
018134ab SL	368	awc->default_status = 0x014FB180;
018134ab SL	369	awc->default_reload_value = 0x014FB180;
6112bd6d CLG	370	}
	371
	372	static const TypeInfo aspeed_2500_wdt_info = {
	373	.name = TYPE_ASPEED_2500_WDT,
	374	.parent = TYPE_ASPEED_WDT,
	375	.instance_size = sizeof(AspeedWDTState),
	376	.class_init = aspeed_2500_wdt_class_init,
854123bf CLG	377	};
854123bf CLG	378
6b2b2a70 JS	379	static void aspeed_2600_wdt_class_init(ObjectClass klass, void data)
	380	{
	381	DeviceClass *dc = DEVICE_CLASS(klass);
	382	AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
	383
	384	dc->desc = "ASPEED 2600 Watchdog Controller";
6fdb4381	385	awc->iosize = 0x40;
6b2b2a70 JS	386	awc->ext_pulse_width_mask = 0xfffff; /* TODO */
	387	awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
	388	awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
28c80f15	389	awc->wdt_reload = aspeed_wdt_reload_1mhz;
709098fd	390	awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
018134ab SL	391	awc->default_status = 0x014FB180;
018134ab SL	392	awc->default_reload_value = 0x014FB180;
6b2b2a70 JS	393	}
	394
	395	static const TypeInfo aspeed_2600_wdt_info = {
	396	.name = TYPE_ASPEED_2600_WDT,
	397	.parent = TYPE_ASPEED_WDT,
	398	.instance_size = sizeof(AspeedWDTState),
	399	.class_init = aspeed_2600_wdt_class_init,
	400	};
	401
e259e01e SL	402	static void aspeed_1030_wdt_class_init(ObjectClass klass, void data)
	403	{
	404	DeviceClass *dc = DEVICE_CLASS(klass);
	405	AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
	406
	407	dc->desc = "ASPEED 1030 Watchdog Controller";
6fdb4381	408	awc->iosize = 0x80;
e259e01e SL	409	awc->ext_pulse_width_mask = 0xfffff; /* TODO */
	410	awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
	411	awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
	412	awc->wdt_reload = aspeed_wdt_reload_1mhz;
	413	awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
	414	awc->default_status = 0x014FB180;
	415	awc->default_reload_value = 0x014FB180;
	416	}
	417
	418	static const TypeInfo aspeed_1030_wdt_info = {
	419	.name = TYPE_ASPEED_1030_WDT,
	420	.parent = TYPE_ASPEED_WDT,
	421	.instance_size = sizeof(AspeedWDTState),
	422	.class_init = aspeed_1030_wdt_class_init,
	423	};
	424
854123bf CLG	425	static void wdt_aspeed_register_types(void)
854123bf CLG	426	{
854123bf	427	type_register_static(&aspeed_wdt_info);
6112bd6d CLG	428	type_register_static(&aspeed_2400_wdt_info);
6112bd6d CLG	429	type_register_static(&aspeed_2500_wdt_info);
6b2b2a70	430	type_register_static(&aspeed_2600_wdt_info);
e259e01e	431	type_register_static(&aspeed_1030_wdt_info);
854123bf CLG	432	}
	433
	434	type_init(wdt_aspeed_register_types)