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854123bf CLG |
1 | /* |
2 | * ASPEED Watchdog Controller | |
3 | * | |
4 | * Copyright (C) 2016-2017 IBM Corp. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See the | |
7 | * COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
f55d613b AJ |
11 | |
12 | #include "qapi/error.h" | |
854123bf | 13 | #include "qemu/log.h" |
0b8fa32f | 14 | #include "qemu/module.h" |
f55d613b | 15 | #include "qemu/timer.h" |
854123bf | 16 | #include "sysemu/watchdog.h" |
f55d613b | 17 | #include "hw/misc/aspeed_scu.h" |
854123bf | 18 | #include "hw/sysbus.h" |
854123bf CLG |
19 | #include "hw/watchdog/wdt_aspeed.h" |
20 | ||
f55d613b AJ |
21 | #define WDT_STATUS (0x00 / 4) |
22 | #define WDT_RELOAD_VALUE (0x04 / 4) | |
23 | #define WDT_RESTART (0x08 / 4) | |
24 | #define WDT_CTRL (0x0C / 4) | |
854123bf CLG |
25 | #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) |
26 | #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) | |
27 | #define WDT_CTRL_1MHZ_CLK BIT(4) | |
28 | #define WDT_CTRL_WDT_EXT BIT(3) | |
29 | #define WDT_CTRL_WDT_INTR BIT(2) | |
30 | #define WDT_CTRL_RESET_SYSTEM BIT(1) | |
31 | #define WDT_CTRL_ENABLE BIT(0) | |
f55d613b AJ |
32 | #define WDT_RESET_WIDTH (0x18 / 4) |
33 | #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) | |
34 | #define WDT_POLARITY_MASK (0xFF << 24) | |
35 | #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) | |
36 | #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) | |
37 | #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) | |
38 | #define WDT_DRIVE_TYPE_MASK (0xFF << 24) | |
39 | #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) | |
40 | #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) | |
854123bf | 41 | |
f55d613b AJ |
42 | #define WDT_TIMEOUT_STATUS (0x10 / 4) |
43 | #define WDT_TIMEOUT_CLEAR (0x14 / 4) | |
854123bf | 44 | |
f55d613b | 45 | #define WDT_RESTART_MAGIC 0x4755 |
854123bf CLG |
46 | |
47 | static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) | |
48 | { | |
49 | return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; | |
50 | } | |
51 | ||
f55d613b AJ |
52 | static bool is_ast2500(const AspeedWDTState *s) |
53 | { | |
54 | switch (s->silicon_rev) { | |
55 | case AST2500_A0_SILICON_REV: | |
56 | case AST2500_A1_SILICON_REV: | |
57 | return true; | |
58 | case AST2400_A0_SILICON_REV: | |
59 | case AST2400_A1_SILICON_REV: | |
60 | default: | |
61 | break; | |
62 | } | |
63 | ||
64 | return false; | |
65 | } | |
66 | ||
854123bf CLG |
67 | static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) |
68 | { | |
69 | AspeedWDTState *s = ASPEED_WDT(opaque); | |
70 | ||
71 | offset >>= 2; | |
72 | ||
73 | switch (offset) { | |
74 | case WDT_STATUS: | |
75 | return s->regs[WDT_STATUS]; | |
76 | case WDT_RELOAD_VALUE: | |
77 | return s->regs[WDT_RELOAD_VALUE]; | |
78 | case WDT_RESTART: | |
79 | qemu_log_mask(LOG_GUEST_ERROR, | |
80 | "%s: read from write-only reg at offset 0x%" | |
81 | HWADDR_PRIx "\n", __func__, offset); | |
82 | return 0; | |
83 | case WDT_CTRL: | |
84 | return s->regs[WDT_CTRL]; | |
f55d613b AJ |
85 | case WDT_RESET_WIDTH: |
86 | return s->regs[WDT_RESET_WIDTH]; | |
854123bf CLG |
87 | case WDT_TIMEOUT_STATUS: |
88 | case WDT_TIMEOUT_CLEAR: | |
854123bf CLG |
89 | qemu_log_mask(LOG_UNIMP, |
90 | "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", | |
91 | __func__, offset); | |
92 | return 0; | |
93 | default: | |
94 | qemu_log_mask(LOG_GUEST_ERROR, | |
95 | "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | |
96 | __func__, offset); | |
97 | return 0; | |
98 | } | |
99 | ||
100 | } | |
101 | ||
102 | static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) | |
103 | { | |
f958537a | 104 | uint64_t reload; |
854123bf CLG |
105 | |
106 | if (pclk) { | |
107 | reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, | |
108 | s->pclk_freq); | |
109 | } else { | |
f958537a | 110 | reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; |
854123bf CLG |
111 | } |
112 | ||
113 | if (aspeed_wdt_is_enabled(s)) { | |
114 | timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); | |
115 | } | |
116 | } | |
117 | ||
118 | static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | |
119 | unsigned size) | |
120 | { | |
121 | AspeedWDTState *s = ASPEED_WDT(opaque); | |
122 | bool enable = data & WDT_CTRL_ENABLE; | |
123 | ||
124 | offset >>= 2; | |
125 | ||
126 | switch (offset) { | |
127 | case WDT_STATUS: | |
128 | qemu_log_mask(LOG_GUEST_ERROR, | |
129 | "%s: write to read-only reg at offset 0x%" | |
130 | HWADDR_PRIx "\n", __func__, offset); | |
131 | break; | |
132 | case WDT_RELOAD_VALUE: | |
133 | s->regs[WDT_RELOAD_VALUE] = data; | |
134 | break; | |
135 | case WDT_RESTART: | |
136 | if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { | |
137 | s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; | |
138 | aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | |
139 | } | |
140 | break; | |
141 | case WDT_CTRL: | |
142 | if (enable && !aspeed_wdt_is_enabled(s)) { | |
143 | s->regs[WDT_CTRL] = data; | |
144 | aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | |
145 | } else if (!enable && aspeed_wdt_is_enabled(s)) { | |
146 | s->regs[WDT_CTRL] = data; | |
147 | timer_del(s->timer); | |
148 | } | |
149 | break; | |
f55d613b AJ |
150 | case WDT_RESET_WIDTH: |
151 | { | |
152 | uint32_t property = data & WDT_POLARITY_MASK; | |
153 | ||
154 | if (property && is_ast2500(s)) { | |
155 | if (property == WDT_ACTIVE_HIGH_MAGIC) { | |
156 | s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; | |
157 | } else if (property == WDT_ACTIVE_LOW_MAGIC) { | |
158 | s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; | |
159 | } else if (property == WDT_PUSH_PULL_MAGIC) { | |
160 | s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; | |
161 | } else if (property == WDT_OPEN_DRAIN_MAGIC) { | |
162 | s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; | |
163 | } | |
164 | } | |
165 | s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask; | |
166 | s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask; | |
167 | break; | |
168 | } | |
854123bf CLG |
169 | case WDT_TIMEOUT_STATUS: |
170 | case WDT_TIMEOUT_CLEAR: | |
854123bf CLG |
171 | qemu_log_mask(LOG_UNIMP, |
172 | "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", | |
173 | __func__, offset); | |
174 | break; | |
175 | default: | |
176 | qemu_log_mask(LOG_GUEST_ERROR, | |
177 | "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | |
178 | __func__, offset); | |
179 | } | |
180 | return; | |
181 | } | |
182 | ||
183 | static WatchdogTimerModel model = { | |
184 | .wdt_name = TYPE_ASPEED_WDT, | |
185 | .wdt_description = "Aspeed watchdog device", | |
186 | }; | |
187 | ||
188 | static const VMStateDescription vmstate_aspeed_wdt = { | |
189 | .name = "vmstate_aspeed_wdt", | |
190 | .version_id = 0, | |
191 | .minimum_version_id = 0, | |
192 | .fields = (VMStateField[]) { | |
193 | VMSTATE_TIMER_PTR(timer, AspeedWDTState), | |
194 | VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), | |
195 | VMSTATE_END_OF_LIST() | |
196 | } | |
197 | }; | |
198 | ||
199 | static const MemoryRegionOps aspeed_wdt_ops = { | |
200 | .read = aspeed_wdt_read, | |
201 | .write = aspeed_wdt_write, | |
202 | .endianness = DEVICE_LITTLE_ENDIAN, | |
203 | .valid.min_access_size = 4, | |
204 | .valid.max_access_size = 4, | |
205 | .valid.unaligned = false, | |
206 | }; | |
207 | ||
208 | static void aspeed_wdt_reset(DeviceState *dev) | |
209 | { | |
210 | AspeedWDTState *s = ASPEED_WDT(dev); | |
211 | ||
212 | s->regs[WDT_STATUS] = 0x3EF1480; | |
213 | s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; | |
214 | s->regs[WDT_RESTART] = 0; | |
215 | s->regs[WDT_CTRL] = 0; | |
f55d613b | 216 | s->regs[WDT_RESET_WIDTH] = 0xFF; |
854123bf CLG |
217 | |
218 | timer_del(s->timer); | |
219 | } | |
220 | ||
221 | static void aspeed_wdt_timer_expired(void *dev) | |
222 | { | |
223 | AspeedWDTState *s = ASPEED_WDT(dev); | |
224 | ||
225 | qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); | |
226 | watchdog_perform_action(); | |
227 | timer_del(s->timer); | |
228 | } | |
229 | ||
230 | #define PCLK_HZ 24000000 | |
231 | ||
232 | static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | |
233 | { | |
234 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
235 | AspeedWDTState *s = ASPEED_WDT(dev); | |
236 | ||
f55d613b AJ |
237 | if (!is_supported_silicon_rev(s->silicon_rev)) { |
238 | error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, | |
239 | s->silicon_rev); | |
240 | return; | |
241 | } | |
242 | ||
243 | switch (s->silicon_rev) { | |
244 | case AST2400_A0_SILICON_REV: | |
245 | case AST2400_A1_SILICON_REV: | |
246 | s->ext_pulse_width_mask = 0xff; | |
247 | break; | |
248 | case AST2500_A0_SILICON_REV: | |
249 | case AST2500_A1_SILICON_REV: | |
250 | s->ext_pulse_width_mask = 0xfffff; | |
251 | break; | |
252 | default: | |
253 | g_assert_not_reached(); | |
254 | } | |
255 | ||
854123bf CLG |
256 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); |
257 | ||
258 | /* FIXME: This setting should be derived from the SCU hw strapping | |
259 | * register SCU70 | |
260 | */ | |
261 | s->pclk_freq = PCLK_HZ; | |
262 | ||
263 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, | |
264 | TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); | |
265 | sysbus_init_mmio(sbd, &s->iomem); | |
266 | } | |
267 | ||
f55d613b AJ |
268 | static Property aspeed_wdt_properties[] = { |
269 | DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0), | |
270 | DEFINE_PROP_END_OF_LIST(), | |
271 | }; | |
272 | ||
854123bf CLG |
273 | static void aspeed_wdt_class_init(ObjectClass *klass, void *data) |
274 | { | |
275 | DeviceClass *dc = DEVICE_CLASS(klass); | |
276 | ||
277 | dc->realize = aspeed_wdt_realize; | |
278 | dc->reset = aspeed_wdt_reset; | |
279 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); | |
280 | dc->vmsd = &vmstate_aspeed_wdt; | |
f55d613b | 281 | dc->props = aspeed_wdt_properties; |
854123bf CLG |
282 | } |
283 | ||
284 | static const TypeInfo aspeed_wdt_info = { | |
285 | .parent = TYPE_SYS_BUS_DEVICE, | |
286 | .name = TYPE_ASPEED_WDT, | |
287 | .instance_size = sizeof(AspeedWDTState), | |
288 | .class_init = aspeed_wdt_class_init, | |
289 | }; | |
290 | ||
291 | static void wdt_aspeed_register_types(void) | |
292 | { | |
293 | watchdog_add_model(&model); | |
294 | type_register_static(&aspeed_wdt_info); | |
295 | } | |
296 | ||
297 | type_init(wdt_aspeed_register_types) |