[mirror_qemu.git] / hw / watchdog / wdt_i6300esb.c

/*
 * Virtual hardware watchdog.
 *
 * Copyright (C) 2009 Red Hat Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * By Richard W.M. Jones (rjones@redhat.com).
 */

#include "qemu/osdep.h"

#include "qemu/module.h"
#include "qemu/timer.h"
#include "sysemu/watchdog.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qom/object.h"

/*#define I6300ESB_DEBUG 1*/

#ifdef I6300ESB_DEBUG
#define i6300esb_debug(fs,...) \
    fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
#else
#define i6300esb_debug(fs,...)
#endif

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers (offset from base address) */
#define ESB_TIMER1_REG  0x00            /* Timer1 value after each reset     */
#define ESB_TIMER2_REG  0x04            /* Timer2 value after each reset     */
#define ESB_GINTSR_REG  0x08            /* General Interrupt Status Register */
#define ESB_RELOAD_REG  0x0c            /* Reload register                   */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* Device state. */
struct I6300State {
    PCIDevice dev;
    MemoryRegion io_mem;

    int reboot_enabled;         /* "Reboot" on timer expiry.  The real action
                                 * performed depends on the -watchdog-action
                                 * param passed on QEMU command line.
                                 */
    int clock_scale;            /* Clock scale. */
#define CLOCK_SCALE_1KHZ 0
#define CLOCK_SCALE_1MHZ 1

    int int_type;               /* Interrupt type generated. */
#define INT_TYPE_IRQ 0          /* APIC 1, INT 10 */
#define INT_TYPE_SMI 2
#define INT_TYPE_DISABLED 3

    int free_run;               /* If true, reload timer on expiry. */
    int locked;                 /* If true, enabled field cannot be changed. */
    int enabled;                /* If true, watchdog is enabled. */

    QEMUTimer *timer;           /* The actual watchdog timer. */

    uint32_t timer1_preload;    /* Values preloaded into timer1, timer2. */
    uint32_t timer2_preload;
    int stage;                  /* Stage (1 or 2). */

    int unlock_state;           /* Guest writes 0x80, 0x86 to unlock the
                                 * registers, and we transition through
                                 * states 0 -> 1 -> 2 when this happens.
                                 */

    int previous_reboot_flag;   /* If the watchdog caused the previous
                                 * reboot, this flag will be set.
                                 */
};


#define TYPE_WATCHDOG_I6300ESB_DEVICE "i6300esb"
OBJECT_DECLARE_SIMPLE_TYPE(I6300State, WATCHDOG_I6300ESB_DEVICE)

/* This function is called when the watchdog has either been enabled
 * (hence it starts counting down) or has been keep-alived.
 */
static void i6300esb_restart_timer(I6300State *d, int stage)
{
    int64_t timeout;

    if (!d->enabled)
        return;

    d->stage = stage;

    if (d->stage <= 1)
        timeout = d->timer1_preload;
    else
        timeout = d->timer2_preload;

    if (d->clock_scale == CLOCK_SCALE_1KHZ)
        timeout <<= 15;
    else
        timeout <<= 5;

    /* Get the timeout in nanoseconds. */

    timeout = timeout * 30; /* on a PCI bus, 1 tick is 30 ns*/

    i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);

    timer_mod(d->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
}

/* This is called when the guest disables the watchdog. */
static void i6300esb_disable_timer(I6300State *d)
{
    i6300esb_debug("timer disabled\n");

    timer_del(d->timer);
}

static void i6300esb_reset(DeviceState *dev)
{
    PCIDevice *pdev = PCI_DEVICE(dev);
    I6300State *d = WATCHDOG_I6300ESB_DEVICE(pdev);

    i6300esb_debug("I6300State = %p\n", d);

    i6300esb_disable_timer(d);

    /* NB: Don't change d->previous_reboot_flag in this function. */

    d->reboot_enabled = 1;
    d->clock_scale = CLOCK_SCALE_1KHZ;
    d->int_type = INT_TYPE_IRQ;
    d->free_run = 0;
    d->locked = 0;
    d->enabled = 0;
    d->timer1_preload = 0xfffff;
    d->timer2_preload = 0xfffff;
    d->stage = 1;
    d->unlock_state = 0;
}

/* This function is called when the watchdog expires.  Note that
 * the hardware has two timers, and so expiry happens in two stages.
 * If d->stage == 1 then we perform the first stage action (usually,
 * sending an interrupt) and then restart the timer again for the
 * second stage.  If the second stage expires then the watchdog
 * really has run out.
 */
static void i6300esb_timer_expired(void *vp)
{
    I6300State *d = vp;

    i6300esb_debug("stage %d\n", d->stage);

    if (d->stage == 1) {
        /* What to do at the end of stage 1? */
        switch (d->int_type) {
        case INT_TYPE_IRQ:
            fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
            break;
        case INT_TYPE_SMI:
            fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
            break;
        }

        /* Start the second stage. */
        i6300esb_restart_timer(d, 2);
    } else {
        /* Second stage expired, reboot for real. */
        if (d->reboot_enabled) {
            d->previous_reboot_flag = 1;
            watchdog_perform_action(); /* This reboots, exits, etc */
            i6300esb_reset(DEVICE(d));
        }

        /* In "free running mode" we start stage 1 again. */
        if (d->free_run)
            i6300esb_restart_timer(d, 1);
    }
}

static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
                                  uint32_t data, int len)
{
    I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
    int old;

    i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
        d->clock_scale =
            (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
        d->int_type = (data & ESB_WDT_INTTYPE);
    } else if (addr == ESB_LOCK_REG && len == 1) {
        if (!d->locked) {
            d->locked = (data & ESB_WDT_LOCK) != 0;
            d->free_run = (data & ESB_WDT_FUNC) != 0;
            old = d->enabled;
            d->enabled = (data & ESB_WDT_ENABLE) != 0;
            if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
                i6300esb_restart_timer(d, 1);
            else if (!d->enabled)
                i6300esb_disable_timer(d);
        }
    } else {
        pci_default_write_config(dev, addr, data, len);
    }
}

static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
{
    I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
    uint32_t data;

    i6300esb_debug ("addr = %x, len = %d\n", addr, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        data =
            (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
            (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
            d->int_type;
        return data;
    } else if (addr == ESB_LOCK_REG && len == 1) {
        data =
            (d->free_run ? ESB_WDT_FUNC : 0) |
            (d->locked ? ESB_WDT_LOCK : 0) |
            (d->enabled ? ESB_WDT_ENABLE : 0);
        return data;
    } else {
        return pci_default_read_config(dev, addr, len);
    }
}

static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
{
    i6300esb_debug ("addr = %x\n", (int) addr);

    return 0;
}

static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
{
    uint32_t data = 0;
    I6300State *d = vp;

    i6300esb_debug("addr = %x\n", (int) addr);

    if (addr == 0xc) {
        /* The previous reboot flag is really bit 9, but there is
         * a bug in the Linux driver where it thinks it's bit 12.
         * Set both.
         */
        data = d->previous_reboot_flag ? 0x1200 : 0;
    }

    return data;
}

static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
{
    i6300esb_debug("addr = %x\n", (int) addr);

    return 0;
}

static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
}

static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0xc) {
                if ((val & 0x100) != 0)
                    /* This is the "ping" from the userspace watchdog in
                     * the guest ...
                     */
                    i6300esb_restart_timer(d, 1);

                /* Setting bit 9 resets the previous reboot flag.
                 * There's a bug in the Linux driver where it sets
                 * bit 12 instead.
                 */
                if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
                    d->previous_reboot_flag = 0;
                }
            }

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0)
                d->timer1_preload = val & 0xfffff;
            else if (addr == 4)
                d->timer2_preload = val & 0xfffff;

            d->unlock_state = 0;
        }
    }
}

static uint64_t i6300esb_mem_readfn(void *opaque, hwaddr addr, unsigned size)
{
    switch (size) {
    case 1:
        return i6300esb_mem_readb(opaque, addr);
    case 2:
        return i6300esb_mem_readw(opaque, addr);
    case 4:
        return i6300esb_mem_readl(opaque, addr);
    default:
        g_assert_not_reached();
    }
}

static void i6300esb_mem_writefn(void *opaque, hwaddr addr,
                                 uint64_t value, unsigned size)
{
    switch (size) {
    case 1:
        i6300esb_mem_writeb(opaque, addr, value);
        break;
    case 2:
        i6300esb_mem_writew(opaque, addr, value);
        break;
    case 4:
        i6300esb_mem_writel(opaque, addr, value);
        break;
    default:
        g_assert_not_reached();
    }
}

static const MemoryRegionOps i6300esb_ops = {
    .read = i6300esb_mem_readfn,
    .write = i6300esb_mem_writefn,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static const VMStateDescription vmstate_i6300esb = {
    .name = "i6300esb_wdt",
    /* With this VMSD's introduction, version_id/minimum_version_id were
     * erroneously set to sizeof(I6300State), causing a somewhat random
     * version_id to be set for every build. This eventually broke
     * migration.
     *
     * To correct this without breaking old->new migration for older
     * versions of QEMU, we've set version_id to a value high enough
     * to exceed all past values of sizeof(I6300State) across various
     * build environments, and have reset minimum_version_id to 1,
     * since this VMSD has never changed and thus can accept all past
     * versions.
     *
     * For future changes we can treat these values as we normally would.
     */
    .version_id = 10000,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, I6300State),
        VMSTATE_INT32(reboot_enabled, I6300State),
        VMSTATE_INT32(clock_scale, I6300State),
        VMSTATE_INT32(int_type, I6300State),
        VMSTATE_INT32(free_run, I6300State),
        VMSTATE_INT32(locked, I6300State),
        VMSTATE_INT32(enabled, I6300State),
        VMSTATE_TIMER_PTR(timer, I6300State),
        VMSTATE_UINT32(timer1_preload, I6300State),
        VMSTATE_UINT32(timer2_preload, I6300State),
        VMSTATE_INT32(stage, I6300State),
        VMSTATE_INT32(unlock_state, I6300State),
        VMSTATE_INT32(previous_reboot_flag, I6300State),
        VMSTATE_END_OF_LIST()
    }
};

static void i6300esb_realize(PCIDevice *dev, Error **errp)
{
    I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);

    i6300esb_debug("I6300State = %p\n", d);

    d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
    d->previous_reboot_flag = 0;

    memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
                          "i6300esb", 0x10);
    pci_register_bar(&d->dev, 0, 0, &d->io_mem);
}

static void i6300esb_exit(PCIDevice *dev)
{
    I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);

    timer_free(d->timer);
}

static void i6300esb_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->config_read = i6300esb_config_read;
    k->config_write = i6300esb_config_write;
    k->realize = i6300esb_realize;
    k->exit = i6300esb_exit;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
    k->class_id = PCI_CLASS_SYSTEM_OTHER;
    dc->reset = i6300esb_reset;
    dc->vmsd = &vmstate_i6300esb;
    set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
    dc->desc = "Intel 6300ESB";
}

static const TypeInfo i6300esb_info = {
    .name          = TYPE_WATCHDOG_I6300ESB_DEVICE,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(I6300State),
    .class_init    = i6300esb_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void i6300esb_register_types(void)
{
    type_register_static(&i6300esb_info);
}

type_init(i6300esb_register_types)
Commit	Line	Data
9dd986cc RJ	1	/*
	2	* Virtual hardware watchdog.
	3	*
	4	* Copyright (C) 2009 Red Hat Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
9dd986cc RJ	18	*
	19	* By Richard W.M. Jones (rjones@redhat.com).
	20	*/
	21
0430891c	22	#include "qemu/osdep.h"
9dd986cc	23
0b8fa32f	24	#include "qemu/module.h"
1de7afc9	25	#include "qemu/timer.h"
0d09e41a	26	#include "sysemu/watchdog.h"
83c9f4ca	27	#include "hw/pci/pci.h"
d6454270	28	#include "migration/vmstate.h"
db1015e9	29	#include "qom/object.h"
9dd986cc RJ	30
	31	/#define I6300ESB_DEBUG 1/
	32
	33	#ifdef I6300ESB_DEBUG
	34	#define i6300esb_debug(fs,...) \
	35	fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
	36	#else
	37	#define i6300esb_debug(fs,...)
	38	#endif
	39
9dd986cc RJ	40	/* PCI configuration registers */
	41	#define ESB_CONFIG_REG 0x60 /* Config register */
	42	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	43
	44	/* Memory mapped registers (offset from base address) */
	45	#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
	46	#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
	47	#define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
	48	#define ESB_RELOAD_REG 0x0c /* Reload register */
	49
	50	/* Lock register bits */
	51	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	52	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	53	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
	54
	55	/* Config register bits */
	56	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
	57	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
	58	#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
	59
	60	/* Reload register bits */
	61	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
	62
	63	/* Magic constants */
	64	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	65	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	66
	67	/* Device state. */
	68	struct I6300State {
9d472d51	69	PCIDevice dev;
d9c6ebd1	70	MemoryRegion io_mem;
9dd986cc RJ	71
	72	int reboot_enabled; /* "Reboot" on timer expiry. The real action
	73	* performed depends on the -watchdog-action
	74	* param passed on QEMU command line.
	75	*/
	76	int clock_scale; /* Clock scale. */
	77	#define CLOCK_SCALE_1KHZ 0
	78	#define CLOCK_SCALE_1MHZ 1
	79
	80	int int_type; /* Interrupt type generated. */
	81	#define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
	82	#define INT_TYPE_SMI 2
	83	#define INT_TYPE_DISABLED 3
	84
	85	int free_run; /* If true, reload timer on expiry. */
	86	int locked; /* If true, enabled field cannot be changed. */
	87	int enabled; /* If true, watchdog is enabled. */
	88
	89	QEMUTimer timer; / The actual watchdog timer. */
	90
	91	uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
	92	uint32_t timer2_preload;
	93	int stage; /* Stage (1 or 2). */
	94
	95	int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
	96	* registers, and we transition through
	97	* states 0 -> 1 -> 2 when this happens.
	98	*/
	99
	100	int previous_reboot_flag; /* If the watchdog caused the previous
	101	* reboot, this flag will be set.
	102	*/
	103	};
	104
9dd986cc	105
41fc9050	106	#define TYPE_WATCHDOG_I6300ESB_DEVICE "i6300esb"
8063396b	107	OBJECT_DECLARE_SIMPLE_TYPE(I6300State, WATCHDOG_I6300ESB_DEVICE)
41fc9050	108
9dd986cc RJ	109	/* This function is called when the watchdog has either been enabled
	110	* (hence it starts counting down) or has been keep-alived.
	111	*/
	112	static void i6300esb_restart_timer(I6300State *d, int stage)
	113	{
	114	int64_t timeout;
	115
	116	if (!d->enabled)
	117	return;
	118
	119	d->stage = stage;
	120
	121	if (d->stage <= 1)
	122	timeout = d->timer1_preload;
	123	else
	124	timeout = d->timer2_preload;
	125
	126	if (d->clock_scale == CLOCK_SCALE_1KHZ)
	127	timeout <<= 15;
	128	else
	129	timeout <<= 5;
	130
9491e9bc LV	131	/* Get the timeout in nanoseconds. */
	132
	133	timeout = timeout * 30; /* on a PCI bus, 1 tick is 30 ns*/
9dd986cc RJ	134
	135	i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
	136
bc72ad67	137	timer_mod(d->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
9dd986cc RJ	138	}
	139
	140	/* This is called when the guest disables the watchdog. */
	141	static void i6300esb_disable_timer(I6300State *d)
	142	{
	143	i6300esb_debug("timer disabled\n");
	144
bc72ad67	145	timer_del(d->timer);
9dd986cc RJ	146	}
9dd986cc RJ	147
fa82e9c3	148	static void i6300esb_reset(DeviceState *dev)
9dd986cc	149	{
40021f08	150	PCIDevice *pdev = PCI_DEVICE(dev);
41fc9050	151	I6300State *d = WATCHDOG_I6300ESB_DEVICE(pdev);
fa82e9c3 BK	152
	153	i6300esb_debug("I6300State = %p\n", d);
	154
9dd986cc	155	i6300esb_disable_timer(d);
fa82e9c3	156
36888c63 RJ	157	/* NB: Don't change d->previous_reboot_flag in this function. */
36888c63 RJ	158
fa82e9c3 BK	159	d->reboot_enabled = 1;
	160	d->clock_scale = CLOCK_SCALE_1KHZ;
	161	d->int_type = INT_TYPE_IRQ;
	162	d->free_run = 0;
	163	d->locked = 0;
	164	d->enabled = 0;
	165	d->timer1_preload = 0xfffff;
	166	d->timer2_preload = 0xfffff;
	167	d->stage = 1;
	168	d->unlock_state = 0;
9dd986cc RJ	169	}
	170
	171	/* This function is called when the watchdog expires. Note that
	172	* the hardware has two timers, and so expiry happens in two stages.
	173	* If d->stage == 1 then we perform the first stage action (usually,
	174	* sending an interrupt) and then restart the timer again for the
	175	* second stage. If the second stage expires then the watchdog
	176	* really has run out.
	177	*/
	178	static void i6300esb_timer_expired(void *vp)
	179	{
4f423e81	180	I6300State *d = vp;
9dd986cc RJ	181
	182	i6300esb_debug("stage %d\n", d->stage);
	183
	184	if (d->stage == 1) {
	185	/* What to do at the end of stage 1? */
	186	switch (d->int_type) {
	187	case INT_TYPE_IRQ:
	188	fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
	189	break;
	190	case INT_TYPE_SMI:
	191	fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
	192	break;
	193	}
	194
	195	/* Start the second stage. */
	196	i6300esb_restart_timer(d, 2);
	197	} else {
	198	/* Second stage expired, reboot for real. */
	199	if (d->reboot_enabled) {
	200	d->previous_reboot_flag = 1;
	201	watchdog_perform_action(); /* This reboots, exits, etc */
f1114d32	202	i6300esb_reset(DEVICE(d));
9dd986cc RJ	203	}
	204
	205	/* In "free running mode" we start stage 1 again. */
	206	if (d->free_run)
	207	i6300esb_restart_timer(d, 1);
	208	}
	209	}
	210
	211	static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
	212	uint32_t data, int len)
	213	{
41fc9050	214	I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
9dd986cc RJ	215	int old;
	216
	217	i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
	218
	219	if (addr == ESB_CONFIG_REG && len == 2) {
	220	d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
	221	d->clock_scale =
	222	(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
	223	d->int_type = (data & ESB_WDT_INTTYPE);
	224	} else if (addr == ESB_LOCK_REG && len == 1) {
	225	if (!d->locked) {
	226	d->locked = (data & ESB_WDT_LOCK) != 0;
	227	d->free_run = (data & ESB_WDT_FUNC) != 0;
	228	old = d->enabled;
	229	d->enabled = (data & ESB_WDT_ENABLE) != 0;
	230	if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
	231	i6300esb_restart_timer(d, 1);
	232	else if (!d->enabled)
	233	i6300esb_disable_timer(d);
	234	}
	235	} else {
	236	pci_default_write_config(dev, addr, data, len);
	237	}
	238	}
	239
	240	static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
	241	{
41fc9050	242	I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
9dd986cc RJ	243	uint32_t data;
	244
	245	i6300esb_debug ("addr = %x, len = %d\n", addr, len);
	246
	247	if (addr == ESB_CONFIG_REG && len == 2) {
	248	data =
	249	(d->reboot_enabled ? 0 : ESB_WDT_REBOOT) \|
	250	(d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) \|
	251	d->int_type;
	252	return data;
	253	} else if (addr == ESB_LOCK_REG && len == 1) {
	254	data =
	255	(d->free_run ? ESB_WDT_FUNC : 0) \|
	256	(d->locked ? ESB_WDT_LOCK : 0) \|
	257	(d->enabled ? ESB_WDT_ENABLE : 0);
	258	return data;
	259	} else {
	260	return pci_default_read_config(dev, addr, len);
	261	}
	262	}
	263
a8170e5e	264	static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
9dd986cc RJ	265	{
	266	i6300esb_debug ("addr = %x\n", (int) addr);
	267
	268	return 0;
	269	}
	270
a8170e5e	271	static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
9dd986cc RJ	272	{
9dd986cc RJ	273	uint32_t data = 0;
4f423e81	274	I6300State *d = vp;
9dd986cc RJ	275
	276	i6300esb_debug("addr = %x\n", (int) addr);
	277
	278	if (addr == 0xc) {
	279	/* The previous reboot flag is really bit 9, but there is
	280	* a bug in the Linux driver where it thinks it's bit 12.
	281	* Set both.
	282	*/
	283	data = d->previous_reboot_flag ? 0x1200 : 0;
	284	}
	285
	286	return data;
	287	}
	288
a8170e5e	289	static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
9dd986cc RJ	290	{
	291	i6300esb_debug("addr = %x\n", (int) addr);
	292
	293	return 0;
	294	}
	295
a8170e5e	296	static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
9dd986cc	297	{
4f423e81	298	I6300State *d = vp;
9dd986cc RJ	299
	300	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	301
	302	if (addr == 0xc && val == 0x80)
	303	d->unlock_state = 1;
	304	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	305	d->unlock_state = 2;
	306	}
	307
a8170e5e	308	static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
9dd986cc	309	{
4f423e81	310	I6300State *d = vp;
9dd986cc RJ	311
	312	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	313
	314	if (addr == 0xc && val == 0x80)
	315	d->unlock_state = 1;
	316	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	317	d->unlock_state = 2;
	318	else {
	319	if (d->unlock_state == 2) {
	320	if (addr == 0xc) {
	321	if ((val & 0x100) != 0)
	322	/* This is the "ping" from the userspace watchdog in
	323	* the guest ...
	324	*/
	325	i6300esb_restart_timer(d, 1);
	326
	327	/* Setting bit 9 resets the previous reboot flag.
	328	* There's a bug in the Linux driver where it sets
	329	* bit 12 instead.
	330	*/
	331	if ((val & 0x200) != 0 \|\| (val & 0x1000) != 0) {
	332	d->previous_reboot_flag = 0;
	333	}
	334	}
	335
	336	d->unlock_state = 0;
	337	}
	338	}
	339	}
	340
a8170e5e	341	static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
9dd986cc	342	{
4f423e81	343	I6300State *d = vp;
9dd986cc RJ	344
	345	i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
	346
	347	if (addr == 0xc && val == 0x80)
	348	d->unlock_state = 1;
	349	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	350	d->unlock_state = 2;
	351	else {
	352	if (d->unlock_state == 2) {
	353	if (addr == 0)
	354	d->timer1_preload = val & 0xfffff;
	355	else if (addr == 4)
	356	d->timer2_preload = val & 0xfffff;
	357
	358	d->unlock_state = 0;
	359	}
	360	}
	361	}
	362
a821541e PM	363	static uint64_t i6300esb_mem_readfn(void *opaque, hwaddr addr, unsigned size)
	364	{
	365	switch (size) {
	366	case 1:
	367	return i6300esb_mem_readb(opaque, addr);
	368	case 2:
	369	return i6300esb_mem_readw(opaque, addr);
	370	case 4:
	371	return i6300esb_mem_readl(opaque, addr);
	372	default:
	373	g_assert_not_reached();
	374	}
	375	}
	376
	377	static void i6300esb_mem_writefn(void *opaque, hwaddr addr,
	378	uint64_t value, unsigned size)
	379	{
	380	switch (size) {
	381	case 1:
	382	i6300esb_mem_writeb(opaque, addr, value);
	383	break;
	384	case 2:
	385	i6300esb_mem_writew(opaque, addr, value);
	386	break;
	387	case 4:
	388	i6300esb_mem_writel(opaque, addr, value);
	389	break;
	390	default:
	391	g_assert_not_reached();
	392	}
	393	}
	394
d9c6ebd1	395	static const MemoryRegionOps i6300esb_ops = {
a821541e PM	396	.read = i6300esb_mem_readfn,
	397	.write = i6300esb_mem_writefn,
	398	.valid.min_access_size = 1,
	399	.valid.max_access_size = 4,
06b82e2d	400	.endianness = DEVICE_LITTLE_ENDIAN,
d9c6ebd1 AK	401	};
d9c6ebd1 AK	402
95c90a0e JQ	403	static const VMStateDescription vmstate_i6300esb = {
95c90a0e JQ	404	.name = "i6300esb_wdt",
c1990468 MR	405	/* With this VMSD's introduction, version_id/minimum_version_id were
	406	* erroneously set to sizeof(I6300State), causing a somewhat random
	407	* version_id to be set for every build. This eventually broke
	408	* migration.
	409	*
d49805ae JQ	410	* To correct this without breaking old->new migration for older
	411	* versions of QEMU, we've set version_id to a value high enough
	412	* to exceed all past values of sizeof(I6300State) across various
	413	* build environments, and have reset minimum_version_id to 1,
	414	* since this VMSD has never changed and thus can accept all past
	415	* versions.
c1990468 MR	416	*
	417	* For future changes we can treat these values as we normally would.
	418	*/
	419	.version_id = 10000,
	420	.minimum_version_id = 1,
d49805ae	421	.fields = (VMStateField[]) {
95c90a0e JQ	422	VMSTATE_PCI_DEVICE(dev, I6300State),
	423	VMSTATE_INT32(reboot_enabled, I6300State),
	424	VMSTATE_INT32(clock_scale, I6300State),
	425	VMSTATE_INT32(int_type, I6300State),
	426	VMSTATE_INT32(free_run, I6300State),
	427	VMSTATE_INT32(locked, I6300State),
	428	VMSTATE_INT32(enabled, I6300State),
e720677e	429	VMSTATE_TIMER_PTR(timer, I6300State),
95c90a0e JQ	430	VMSTATE_UINT32(timer1_preload, I6300State),
	431	VMSTATE_UINT32(timer2_preload, I6300State),
	432	VMSTATE_INT32(stage, I6300State),
	433	VMSTATE_INT32(unlock_state, I6300State),
	434	VMSTATE_INT32(previous_reboot_flag, I6300State),
	435	VMSTATE_END_OF_LIST()
	436	}
	437	};
9dd986cc	438
9af21dbe	439	static void i6300esb_realize(PCIDevice dev, Error *errp)
9dd986cc	440	{
41fc9050	441	I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
9dd986cc	442
fa82e9c3 BK	443	i6300esb_debug("I6300State = %p\n", d);
fa82e9c3 BK	444
bc72ad67	445	d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
36888c63	446	d->previous_reboot_flag = 0;
9dd986cc	447
22fc860b PB	448	memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
22fc860b PB	449	"i6300esb", 0x10);
e824b2cc	450	pci_register_bar(&d->dev, 0, 0, &d->io_mem);
9dd986cc RJ	451	}
9dd986cc RJ	452
eb7a20a3 LQ	453	static void i6300esb_exit(PCIDevice *dev)
	454	{
	455	I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
	456
eb7a20a3 LQ	457	timer_free(d->timer);
	458	}
	459
40021f08 AL	460	static void i6300esb_class_init(ObjectClass klass, void data)
40021f08 AL	461	{
39bffca2	462	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	463	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	464
	465	k->config_read = i6300esb_config_read;
	466	k->config_write = i6300esb_config_write;
9af21dbe	467	k->realize = i6300esb_realize;
eb7a20a3	468	k->exit = i6300esb_exit;
40021f08 AL	469	k->vendor_id = PCI_VENDOR_ID_INTEL;
	470	k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
	471	k->class_id = PCI_CLASS_SYSTEM_OTHER;
39bffca2 AL	472	dc->reset = i6300esb_reset;
39bffca2 AL	473	dc->vmsd = &vmstate_i6300esb;
b10cb627 PB	474	set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
b10cb627 PB	475	dc->desc = "Intel 6300ESB";
40021f08 AL	476	}
40021f08 AL	477
8c43a6f0	478	static const TypeInfo i6300esb_info = {
41fc9050	479	.name = TYPE_WATCHDOG_I6300ESB_DEVICE,
39bffca2 AL	480	.parent = TYPE_PCI_DEVICE,
	481	.instance_size = sizeof(I6300State),
	482	.class_init = i6300esb_class_init,
fd3b02c8 EH	483	.interfaces = (InterfaceInfo[]) {
	484	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	485	{ },
	486	},
09aaa160 MA	487	};
09aaa160 MA	488
83f7d43a	489	static void i6300esb_register_types(void)
9dd986cc	490	{
39bffca2	491	type_register_static(&i6300esb_info);
9dd986cc	492	}
09aaa160	493
83f7d43a	494	type_init(i6300esb_register_types)