[mirror_qemu.git] / hw / xen_platform.c

/*
 * XEN platform pci device, formerly known as the event channel device
 *
 * Copyright (c) 2003-2004 Intel Corp.
 * Copyright (c) 2006 XenSource
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <assert.h>

#include "hw.h"
#include "pc.h"
#include "pci/pci.h"
#include "irq.h"
#include "xen_common.h"
#include "xen_backend.h"
#include "trace.h"
#include "exec/address-spaces.h"

#include <xenguest.h>

//#define DEBUG_PLATFORM

#ifdef DEBUG_PLATFORM
#define DPRINTF(fmt, ...) do { \
    fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
} while (0)
#else
#define DPRINTF(fmt, ...) do { } while (0)
#endif

#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */

typedef struct PCIXenPlatformState {
    PCIDevice  pci_dev;
    MemoryRegion fixed_io;
    MemoryRegion bar;
    MemoryRegion mmio_bar;
    uint8_t flags; /* used only for version_id == 2 */
    int drivers_blacklisted;
    uint16_t driver_product_version;

    /* Log from guest drivers */
    char log_buffer[4096];
    int log_buffer_off;
} PCIXenPlatformState;

#define XEN_PLATFORM_IOPORT 0x10

/* Send bytes to syslog */
static void log_writeb(PCIXenPlatformState *s, char val)
{
    if (val == '\n' || s->log_buffer_off == sizeof(s->log_buffer) - 1) {
        /* Flush buffer */
        s->log_buffer[s->log_buffer_off] = 0;
        trace_xen_platform_log(s->log_buffer);
        s->log_buffer_off = 0;
    } else {
        s->log_buffer[s->log_buffer_off++] = val;
    }
}

/* Xen Platform, Fixed IOPort */
#define UNPLUG_ALL_IDE_DISKS 1
#define UNPLUG_ALL_NICS 2
#define UNPLUG_AUX_IDE_DISKS 4

static void unplug_nic(PCIBus *b, PCIDevice *d, void *o)
{
    /* We have to ignore passthrough devices */
    if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
            PCI_CLASS_NETWORK_ETHERNET
            && strcmp(d->name, "xen-pci-passthrough") != 0) {
        qdev_free(&d->qdev);
    }
}

static void pci_unplug_nics(PCIBus *bus)
{
    pci_for_each_device(bus, 0, unplug_nic, NULL);
}

static void unplug_disks(PCIBus *b, PCIDevice *d, void *o)
{
    /* We have to ignore passthrough devices */
    if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
            PCI_CLASS_STORAGE_IDE
            && strcmp(d->name, "xen-pci-passthrough") != 0) {
        qdev_unplug(&(d->qdev), NULL);
    }
}

static void pci_unplug_disks(PCIBus *bus)
{
    pci_for_each_device(bus, 0, unplug_disks, NULL);
}

static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0:
        /* Unplug devices.  Value is a bitmask of which devices to
           unplug, with bit 0 the IDE devices, bit 1 the network
           devices, and bit 2 the non-primary-master IDE devices. */
        if (val & UNPLUG_ALL_IDE_DISKS) {
            DPRINTF("unplug disks\n");
            bdrv_drain_all();
            bdrv_flush_all();
            pci_unplug_disks(s->pci_dev.bus);
        }
        if (val & UNPLUG_ALL_NICS) {
            DPRINTF("unplug nics\n");
            pci_unplug_nics(s->pci_dev.bus);
        }
        if (val & UNPLUG_AUX_IDE_DISKS) {
            DPRINTF("unplug auxiliary disks not supported\n");
        }
        break;
    case 2:
        switch (val) {
        case 1:
            DPRINTF("Citrix Windows PV drivers loaded in guest\n");
            break;
        case 0:
            DPRINTF("Guest claimed to be running PV product 0?\n");
            break;
        default:
            DPRINTF("Unknown PV product %d loaded in guest\n", val);
            break;
        }
        s->driver_product_version = val;
        break;
    }
}

static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
                                         uint32_t val)
{
    switch (addr) {
    case 0:
        /* PV driver version */
        break;
    }
}

static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0: /* Platform flags */ {
        hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
            HVMMEM_ram_ro : HVMMEM_ram_rw;
        if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
            DPRINTF("unable to change ro/rw state of ROM memory area!\n");
        } else {
            s->flags = val & PFFLAG_ROM_LOCK;
            DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
                    (mem_type == HVMMEM_ram_ro ? "ro":"rw"));
        }
        break;
    }
    case 2:
        log_writeb(s, val);
        break;
    }
}

static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0:
        if (s->drivers_blacklisted) {
            /* The drivers will recognise this magic number and refuse
             * to do anything. */
            return 0xd249;
        } else {
            /* Magic value so that you can identify the interface. */
            return 0x49d2;
        }
    default:
        return 0xffff;
    }
}

static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0:
        /* Platform flags */
        return s->flags;
    case 2:
        /* Version number */
        return 1;
    default:
        return 0xff;
    }
}

static void platform_fixed_ioport_reset(void *opaque)
{
    PCIXenPlatformState *s = opaque;

    platform_fixed_ioport_writeb(s, 0, 0);
}

static uint64_t platform_fixed_ioport_read(void *opaque,
                                           hwaddr addr,
                                           unsigned size)
{
    switch (size) {
    case 1:
        return platform_fixed_ioport_readb(opaque, addr);
    case 2:
        return platform_fixed_ioport_readw(opaque, addr);
    default:
        return -1;
    }
}

static void platform_fixed_ioport_write(void *opaque, hwaddr addr,

                                        uint64_t val, unsigned size)
{
    switch (size) {
    case 1:
        platform_fixed_ioport_writeb(opaque, addr, val);
        break;
    case 2:
        platform_fixed_ioport_writew(opaque, addr, val);
        break;
    case 4:
        platform_fixed_ioport_writel(opaque, addr, val);
        break;
    }
}


static const MemoryRegionOps platform_fixed_io_ops = {
    .read = platform_fixed_ioport_read,
    .write = platform_fixed_ioport_write,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 4,
    },
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void platform_fixed_ioport_init(PCIXenPlatformState* s)
{
    memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
                          "xen-fixed", 16);
    memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
                                &s->fixed_io);
}

/* Xen Platform PCI Device */

static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
{
    if (addr == 0) {
        return platform_fixed_ioport_readb(opaque, 0);
    } else {
        return ~0u;
    }
}

static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0: /* Platform flags */
        platform_fixed_ioport_writeb(opaque, 0, val);
        break;
    case 8:
        log_writeb(s, val);
        break;
    default:
        break;
    }
}

static MemoryRegionPortio xen_pci_portio[] = {
    { 0, 0x100, 1, .read = xen_platform_ioport_readb, },
    { 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
    PORTIO_END_OF_LIST()
};

static const MemoryRegionOps xen_pci_io_ops = {
    .old_portio = xen_pci_portio,
};

static void platform_ioport_bar_setup(PCIXenPlatformState *d)
{
    memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
}

static uint64_t platform_mmio_read(void *opaque, hwaddr addr,
                                   unsigned size)
{
    DPRINTF("Warning: attempted read from physical address "
            "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);

    return 0;
}

static void platform_mmio_write(void *opaque, hwaddr addr,
                                uint64_t val, unsigned size)
{
    DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
            "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
            val, addr);
}

static const MemoryRegionOps platform_mmio_handler = {
    .read = &platform_mmio_read,
    .write = &platform_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void platform_mmio_setup(PCIXenPlatformState *d)
{
    memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
                          "xen-mmio", 0x1000000);
}

static int xen_platform_post_load(void *opaque, int version_id)
{
    PCIXenPlatformState *s = opaque;

    platform_fixed_ioport_writeb(s, 0, s->flags);

    return 0;
}

static const VMStateDescription vmstate_xen_platform = {
    .name = "platform",
    .version_id = 4,
    .minimum_version_id = 4,
    .minimum_version_id_old = 4,
    .post_load = xen_platform_post_load,
    .fields = (VMStateField []) {
        VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
        VMSTATE_UINT8(flags, PCIXenPlatformState),
        VMSTATE_END_OF_LIST()
    }
};

static int xen_platform_initfn(PCIDevice *dev)
{
    PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
    uint8_t *pci_conf;

    pci_conf = d->pci_dev.config;

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);

    pci_config_set_prog_interface(pci_conf, 0);

    pci_conf[PCI_INTERRUPT_PIN] = 1;

    platform_ioport_bar_setup(d);
    pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);

    /* reserve 16MB mmio address for share memory*/
    platform_mmio_setup(d);
    pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
                     &d->mmio_bar);

    platform_fixed_ioport_init(d);

    return 0;
}

static void platform_reset(DeviceState *dev)
{
    PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev, dev);

    platform_fixed_ioport_reset(s);
}

static void xen_platform_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = xen_platform_initfn;
    k->vendor_id = PCI_VENDOR_ID_XEN;
    k->device_id = PCI_DEVICE_ID_XEN_PLATFORM;
    k->class_id = PCI_CLASS_OTHERS << 8 | 0x80;
    k->subsystem_vendor_id = PCI_VENDOR_ID_XEN;
    k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM;
    k->revision = 1;
    dc->desc = "XEN platform pci device";
    dc->reset = platform_reset;
    dc->vmsd = &vmstate_xen_platform;
}

static TypeInfo xen_platform_info = {
    .name          = "xen-platform",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIXenPlatformState),
    .class_init    = xen_platform_class_init,
};

static void xen_platform_register_types(void)
{
    type_register_static(&xen_platform_info);
}

type_init(xen_platform_register_types)
Commit	Line	Data
01195b73 SS	1	/*
	2	* XEN platform pci device, formerly known as the event channel device
	3	*
	4	* Copyright (c) 2003-2004 Intel Corp.
	5	* Copyright (c) 2006 XenSource
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
	26	#include <assert.h>
	27
	28	#include "hw.h"
	29	#include "pc.h"
a2cb15b0	30	#include "pci/pci.h"
01195b73 SS	31	#include "irq.h"
01195b73 SS	32	#include "xen_common.h"
01195b73	33	#include "xen_backend.h"
01195b73	34	#include "trace.h"
022c62cb	35	#include "exec/address-spaces.h"
01195b73 SS	36
	37	#include <xenguest.h>
	38
	39	//#define DEBUG_PLATFORM
	40
	41	#ifdef DEBUG_PLATFORM
	42	#define DPRINTF(fmt, ...) do { \
	43	fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
	44	} while (0)
	45	#else
	46	#define DPRINTF(fmt, ...) do { } while (0)
	47	#endif
	48
	49	#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
	50
	51	typedef struct PCIXenPlatformState {
	52	PCIDevice pci_dev;
de00982e AK	53	MemoryRegion fixed_io;
	54	MemoryRegion bar;
	55	MemoryRegion mmio_bar;
01195b73 SS	56	uint8_t flags; /* used only for version_id == 2 */
	57	int drivers_blacklisted;
	58	uint16_t driver_product_version;
	59
	60	/* Log from guest drivers */
	61	char log_buffer[4096];
	62	int log_buffer_off;
	63	} PCIXenPlatformState;
	64
	65	#define XEN_PLATFORM_IOPORT 0x10
	66
	67	/* Send bytes to syslog */
	68	static void log_writeb(PCIXenPlatformState *s, char val)
	69	{
	70	if (val == '\n' \|\| s->log_buffer_off == sizeof(s->log_buffer) - 1) {
	71	/* Flush buffer */
	72	s->log_buffer[s->log_buffer_off] = 0;
	73	trace_xen_platform_log(s->log_buffer);
	74	s->log_buffer_off = 0;
	75	} else {
	76	s->log_buffer[s->log_buffer_off++] = val;
	77	}
	78	}
	79
	80	/* Xen Platform, Fixed IOPort */
679f4f8b SS	81	#define UNPLUG_ALL_IDE_DISKS 1
	82	#define UNPLUG_ALL_NICS 2
	83	#define UNPLUG_AUX_IDE_DISKS 4
	84
7aa8cbb9	85	static void unplug_nic(PCIBus b, PCIDevice d, void *o)
679f4f8b	86	{
bd4982a6	87	/* We have to ignore passthrough devices */
679f4f8b	88	if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
bd4982a6 AP	89	PCI_CLASS_NETWORK_ETHERNET
bd4982a6 AP	90	&& strcmp(d->name, "xen-pci-passthrough") != 0) {
4accd107	91	qdev_free(&d->qdev);
679f4f8b SS	92	}
	93	}
	94
	95	static void pci_unplug_nics(PCIBus *bus)
	96	{
7aa8cbb9	97	pci_for_each_device(bus, 0, unplug_nic, NULL);
679f4f8b SS	98	}
679f4f8b SS	99
7aa8cbb9	100	static void unplug_disks(PCIBus b, PCIDevice d, void *o)
679f4f8b	101	{
bd4982a6	102	/* We have to ignore passthrough devices */
679f4f8b	103	if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
bd4982a6 AP	104	PCI_CLASS_STORAGE_IDE
bd4982a6 AP	105	&& strcmp(d->name, "xen-pci-passthrough") != 0) {
56f9107e	106	qdev_unplug(&(d->qdev), NULL);
679f4f8b SS	107	}
	108	}
	109
	110	static void pci_unplug_disks(PCIBus *bus)
	111	{
7aa8cbb9	112	pci_for_each_device(bus, 0, unplug_disks, NULL);
679f4f8b	113	}
01195b73 SS	114
	115	static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	116	{
	117	PCIXenPlatformState *s = opaque;
	118
e7b48c97	119	switch (addr) {
01195b73	120	case 0:
01195b73 SS	121	/* Unplug devices. Value is a bitmask of which devices to
	122	unplug, with bit 0 the IDE devices, bit 1 the network
	123	devices, and bit 2 the non-primary-master IDE devices. */
679f4f8b SS	124	if (val & UNPLUG_ALL_IDE_DISKS) {
679f4f8b SS	125	DPRINTF("unplug disks\n");
922453bc	126	bdrv_drain_all();
679f4f8b SS	127	bdrv_flush_all();
	128	pci_unplug_disks(s->pci_dev.bus);
	129	}
	130	if (val & UNPLUG_ALL_NICS) {
	131	DPRINTF("unplug nics\n");
	132	pci_unplug_nics(s->pci_dev.bus);
	133	}
	134	if (val & UNPLUG_AUX_IDE_DISKS) {
	135	DPRINTF("unplug auxiliary disks not supported\n");
	136	}
01195b73 SS	137	break;
	138	case 2:
	139	switch (val) {
	140	case 1:
	141	DPRINTF("Citrix Windows PV drivers loaded in guest\n");
	142	break;
	143	case 0:
	144	DPRINTF("Guest claimed to be running PV product 0?\n");
	145	break;
	146	default:
	147	DPRINTF("Unknown PV product %d loaded in guest\n", val);
	148	break;
	149	}
	150	s->driver_product_version = val;
	151	break;
	152	}
	153	}
	154
	155	static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
	156	uint32_t val)
	157	{
e7b48c97	158	switch (addr) {
01195b73 SS	159	case 0:
	160	/* PV driver version */
	161	break;
	162	}
	163	}
	164
	165	static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	166	{
	167	PCIXenPlatformState *s = opaque;
	168
e7b48c97	169	switch (addr) {
01195b73 SS	170	case 0: /* Platform flags */ {
	171	hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
	172	HVMMEM_ram_ro : HVMMEM_ram_rw;
	173	if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
	174	DPRINTF("unable to change ro/rw state of ROM memory area!\n");
	175	} else {
	176	s->flags = val & PFFLAG_ROM_LOCK;
	177	DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
	178	(mem_type == HVMMEM_ram_ro ? "ro":"rw"));
	179	}
	180	break;
	181	}
	182	case 2:
	183	log_writeb(s, val);
	184	break;
	185	}
	186	}
	187
	188	static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
	189	{
	190	PCIXenPlatformState *s = opaque;
	191
e7b48c97	192	switch (addr) {
01195b73 SS	193	case 0:
	194	if (s->drivers_blacklisted) {
	195	/* The drivers will recognise this magic number and refuse
	196	* to do anything. */
	197	return 0xd249;
	198	} else {
	199	/* Magic value so that you can identify the interface. */
	200	return 0x49d2;
	201	}
	202	default:
	203	return 0xffff;
	204	}
	205	}
	206
	207	static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
	208	{
	209	PCIXenPlatformState *s = opaque;
	210
e7b48c97	211	switch (addr) {
01195b73 SS	212	case 0:
	213	/* Platform flags */
	214	return s->flags;
	215	case 2:
	216	/* Version number */
	217	return 1;
	218	default:
	219	return 0xff;
	220	}
	221	}
	222
	223	static void platform_fixed_ioport_reset(void *opaque)
	224	{
	225	PCIXenPlatformState *s = opaque;
	226
e7b48c97	227	platform_fixed_ioport_writeb(s, 0, 0);
01195b73 SS	228	}
01195b73 SS	229
626c7a17 AG	230	static uint64_t platform_fixed_ioport_read(void *opaque,
	231	hwaddr addr,
	232	unsigned size)
	233	{
	234	switch (size) {
	235	case 1:
	236	return platform_fixed_ioport_readb(opaque, addr);
	237	case 2:
	238	return platform_fixed_ioport_readw(opaque, addr);
	239	default:
	240	return -1;
	241	}
	242	}
	243
	244	static void platform_fixed_ioport_write(void *opaque, hwaddr addr,
	245
	246	uint64_t val, unsigned size)
	247	{
	248	switch (size) {
	249	case 1:
	250	platform_fixed_ioport_writeb(opaque, addr, val);
	251	break;
	252	case 2:
	253	platform_fixed_ioport_writew(opaque, addr, val);
	254	break;
	255	case 4:
	256	platform_fixed_ioport_writel(opaque, addr, val);
	257	break;
	258	}
	259	}
	260
de00982e AK	261
de00982e AK	262	static const MemoryRegionOps platform_fixed_io_ops = {
626c7a17 AG	263	.read = platform_fixed_ioport_read,
	264	.write = platform_fixed_ioport_write,
	265	.impl = {
	266	.min_access_size = 1,
	267	.max_access_size = 4,
	268	},
	269	.endianness = DEVICE_LITTLE_ENDIAN,
de00982e AK	270	};
de00982e AK	271
01195b73 SS	272	static void platform_fixed_ioport_init(PCIXenPlatformState* s)
01195b73 SS	273	{
de00982e AK	274	memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
	275	"xen-fixed", 16);
	276	memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
	277	&s->fixed_io);
01195b73 SS	278	}
	279
	280	/* Xen Platform PCI Device */
	281
	282	static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
	283	{
01195b73	284	if (addr == 0) {
e7b48c97	285	return platform_fixed_ioport_readb(opaque, 0);
01195b73 SS	286	} else {
	287	return ~0u;
	288	}
	289	}
	290
	291	static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	292	{
	293	PCIXenPlatformState *s = opaque;
	294
01195b73 SS	295	switch (addr) {
01195b73 SS	296	case 0: /* Platform flags */
e7b48c97	297	platform_fixed_ioport_writeb(opaque, 0, val);
01195b73 SS	298	break;
	299	case 8:
	300	log_writeb(s, val);
	301	break;
	302	default:
	303	break;
	304	}
	305	}
	306
de00982e AK	307	static MemoryRegionPortio xen_pci_portio[] = {
	308	{ 0, 0x100, 1, .read = xen_platform_ioport_readb, },
	309	{ 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
	310	PORTIO_END_OF_LIST()
	311	};
	312
	313	static const MemoryRegionOps xen_pci_io_ops = {
	314	.old_portio = xen_pci_portio,
	315	};
01195b73	316
de00982e AK	317	static void platform_ioport_bar_setup(PCIXenPlatformState *d)
	318	{
	319	memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
01195b73 SS	320	}
01195b73 SS	321
a8170e5e	322	static uint64_t platform_mmio_read(void *opaque, hwaddr addr,
de00982e	323	unsigned size)
01195b73 SS	324	{
	325	DPRINTF("Warning: attempted read from physical address "
	326	"0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
	327
	328	return 0;
	329	}
	330
a8170e5e	331	static void platform_mmio_write(void *opaque, hwaddr addr,
de00982e	332	uint64_t val, unsigned size)
01195b73	333	{
de00982e	334	DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
01195b73 SS	335	"address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
	336	val, addr);
	337	}
	338
de00982e	339	static const MemoryRegionOps platform_mmio_handler = {
01195b73 SS	340	.read = &platform_mmio_read,
01195b73 SS	341	.write = &platform_mmio_write,
de00982e	342	.endianness = DEVICE_NATIVE_ENDIAN,
01195b73 SS	343	};
01195b73 SS	344
de00982e	345	static void platform_mmio_setup(PCIXenPlatformState *d)
01195b73	346	{
de00982e AK	347	memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
de00982e AK	348	"xen-mmio", 0x1000000);
01195b73 SS	349	}
	350
	351	static int xen_platform_post_load(void *opaque, int version_id)
	352	{
	353	PCIXenPlatformState *s = opaque;
	354
e7b48c97	355	platform_fixed_ioport_writeb(s, 0, s->flags);
01195b73 SS	356
	357	return 0;
	358	}
	359
	360	static const VMStateDescription vmstate_xen_platform = {
	361	.name = "platform",
	362	.version_id = 4,
	363	.minimum_version_id = 4,
	364	.minimum_version_id_old = 4,
	365	.post_load = xen_platform_post_load,
	366	.fields = (VMStateField []) {
	367	VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
	368	VMSTATE_UINT8(flags, PCIXenPlatformState),
	369	VMSTATE_END_OF_LIST()
	370	}
	371	};
	372
	373	static int xen_platform_initfn(PCIDevice *dev)
	374	{
	375	PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
	376	uint8_t *pci_conf;
	377
	378	pci_conf = d->pci_dev.config;
	379
01195b73 SS	380	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);
01195b73 SS	381
01195b73 SS	382	pci_config_set_prog_interface(pci_conf, 0);
01195b73 SS	383
01195b73 SS	384	pci_conf[PCI_INTERRUPT_PIN] = 1;
01195b73 SS	385
de00982e	386	platform_ioport_bar_setup(d);
e824b2cc	387	pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
01195b73 SS	388
01195b73 SS	389	/* reserve 16MB mmio address for share memory*/
de00982e	390	platform_mmio_setup(d);
e824b2cc AK	391	pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
e824b2cc AK	392	&d->mmio_bar);
01195b73 SS	393
	394	platform_fixed_ioport_init(d);
	395
	396	return 0;
	397	}
	398
	399	static void platform_reset(DeviceState *dev)
	400	{
	401	PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev, dev);
	402
	403	platform_fixed_ioport_reset(s);
	404	}
	405
40021f08 AL	406	static void xen_platform_class_init(ObjectClass klass, void data)
40021f08 AL	407	{
39bffca2	408	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	409	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	410
	411	k->init = xen_platform_initfn;
	412	k->vendor_id = PCI_VENDOR_ID_XEN;
	413	k->device_id = PCI_DEVICE_ID_XEN_PLATFORM;
	414	k->class_id = PCI_CLASS_OTHERS << 8 \| 0x80;
	415	k->subsystem_vendor_id = PCI_VENDOR_ID_XEN;
	416	k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM;
	417	k->revision = 1;
39bffca2 AL	418	dc->desc = "XEN platform pci device";
	419	dc->reset = platform_reset;
	420	dc->vmsd = &vmstate_xen_platform;
40021f08 AL	421	}
40021f08 AL	422
39bffca2 AL	423	static TypeInfo xen_platform_info = {
	424	.name = "xen-platform",
	425	.parent = TYPE_PCI_DEVICE,
	426	.instance_size = sizeof(PCIXenPlatformState),
	427	.class_init = xen_platform_class_init,
01195b73 SS	428	};
01195b73 SS	429
83f7d43a	430	static void xen_platform_register_types(void)
01195b73	431	{
39bffca2	432	type_register_static(&xen_platform_info);
01195b73 SS	433	}
01195b73 SS	434
83f7d43a	435	type_init(xen_platform_register_types)